drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dc_bios_types.h"
  28 #include "dcn10_stream_encoder.h"
  29 #include "reg_helper.h"
  30 #include "hw_shared.h"
  31
  32 #define DC_LOGGER \
  33                 enc1->base.ctx->logger
  34
  35
  36 #define REG(reg)\
  37         (enc1->regs->reg)
  38
  39 #undef FN
  40 #define FN(reg_name, field_name) \
  41         enc1->se_shift->field_name, enc1->se_mask->field_name
  42
  43 #define VBI_LINE_0 0
  44 #define DP_BLANK_MAX_RETRY 20
  45 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  46
  47
  48 enum {
  49         DP_MST_UPDATE_MAX_RETRY = 50
  50 };
  51
  52 #define CTX \
  53         enc1->base.ctx
  54
  55 void enc1_update_generic_info_packet(
  56         struct dcn10_stream_encoder *enc1,
  57         uint32_t packet_index,
  58         const struct dc_info_packet *info_packet)
  59 {
  60         uint32_t regval;
  61         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  62          * use 50 for now.
  63          */
  64         uint32_t max_retries = 50;
  65
  66         /*we need turn on clock before programming AFMT block*/
  67         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  68
  69         if (packet_index >= 8)
  70                 ASSERT(0);
  71
  72         /* poll dig_update_lock is not locked -> asic internal signal
  73          * assume otg master lock will unlock it
  74          */
  75 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  76                         0, 10, max_retries);*/
  77
  78         /* check if HW reading GSP memory */
  79         REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  80                         0, 10, max_retries);
  81
  82         /* HW does is not reading GSP memory not reading too long ->
  83          * something wrong. clear GPS memory access and notify?
  84          * hw SW is writing to GSP memory
  85          */
  86         REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  87
  88         /* choose which generic packet to use */
  89         regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
  90         REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
  91                         AFMT_GENERIC_INDEX, packet_index);
  92
  93         /* write generic packet header
  94          * (4th byte is for GENERIC0 only)
  95          */
  96         REG_SET_4(AFMT_GENERIC_HDR, 0,
  97                         AFMT_GENERIC_HB0, info_packet->hb0,
  98                         AFMT_GENERIC_HB1, info_packet->hb1,
  99                         AFMT_GENERIC_HB2, info_packet->hb2,
 100                         AFMT_GENERIC_HB3, info_packet->hb3);
 101
 102         /* write generic packet contents
 103          * (we never use last 4 bytes)
 104          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
 105          */
 106         {
 107                 const uint32_t *content =
 108                         (const uint32_t *) &info_packet->sb[0];
 109
 110                 REG_WRITE(AFMT_GENERIC_0, *content++);
 111                 REG_WRITE(AFMT_GENERIC_1, *content++);
 112                 REG_WRITE(AFMT_GENERIC_2, *content++);
 113                 REG_WRITE(AFMT_GENERIC_3, *content++);
 114                 REG_WRITE(AFMT_GENERIC_4, *content++);
 115                 REG_WRITE(AFMT_GENERIC_5, *content++);
 116                 REG_WRITE(AFMT_GENERIC_6, *content++);
 117                 REG_WRITE(AFMT_GENERIC_7, *content);
 118         }
 119
 120         switch (packet_index) {
 121         case 0:
 122                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 123                                 AFMT_GENERIC0_FRAME_UPDATE, 1);
 124                 break;
 125         case 1:
 126                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 127                                 AFMT_GENERIC1_FRAME_UPDATE, 1);
 128                 break;
 129         case 2:
 130                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 131                                 AFMT_GENERIC2_FRAME_UPDATE, 1);
 132                 break;
 133         case 3:
 134                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 135                                 AFMT_GENERIC3_FRAME_UPDATE, 1);
 136                 break;
 137         case 4:
 138                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 139                                 AFMT_GENERIC4_FRAME_UPDATE, 1);
 140                 break;
 141         case 5:
 142                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 143                                 AFMT_GENERIC5_FRAME_UPDATE, 1);
 144                 break;
 145         case 6:
 146                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 147                                 AFMT_GENERIC6_FRAME_UPDATE, 1);
 148                 break;
 149         case 7:
 150                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 151                                 AFMT_GENERIC7_FRAME_UPDATE, 1);
 152                 break;
 153         default:
 154                 break;
 155         }
 156 }
 157
 158 static void enc1_update_hdmi_info_packet(
 159         struct dcn10_stream_encoder *enc1,
 160         uint32_t packet_index,
 161         const struct dc_info_packet *info_packet)
 162 {
 163         uint32_t cont, send, line;
 164
 165         if (info_packet->valid) {
 166                 enc1_update_generic_info_packet(
 167                         enc1,
 168                         packet_index,
 169                         info_packet);
 170
 171                 /* enable transmission of packet(s) -
 172                  * packet transmission begins on the next frame
 173                  */
 174                 cont = 1;
 175                 /* send packet(s) every frame */
 176                 send = 1;
 177                 /* select line number to send packets on */
 178                 line = 2;
 179         } else {
 180                 cont = 0;
 181                 send = 0;
 182                 line = 0;
 183         }
 184
 185         /* choose which generic packet control to use */
 186         switch (packet_index) {
 187         case 0:
 188                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 189                                 HDMI_GENERIC0_CONT, cont,
 190                                 HDMI_GENERIC0_SEND, send,
 191                                 HDMI_GENERIC0_LINE, line);
 192                 break;
 193         case 1:
 194                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 195                                 HDMI_GENERIC1_CONT, cont,
 196                                 HDMI_GENERIC1_SEND, send,
 197                                 HDMI_GENERIC1_LINE, line);
 198                 break;
 199         case 2:
 200                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 201                                 HDMI_GENERIC0_CONT, cont,
 202                                 HDMI_GENERIC0_SEND, send,
 203                                 HDMI_GENERIC0_LINE, line);
 204                 break;
 205         case 3:
 206                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 207                                 HDMI_GENERIC1_CONT, cont,
 208                                 HDMI_GENERIC1_SEND, send,
 209                                 HDMI_GENERIC1_LINE, line);
 210                 break;
 211         case 4:
 212                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 213                                 HDMI_GENERIC0_CONT, cont,
 214                                 HDMI_GENERIC0_SEND, send,
 215                                 HDMI_GENERIC0_LINE, line);
 216                 break;
 217         case 5:
 218                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 219                                 HDMI_GENERIC1_CONT, cont,
 220                                 HDMI_GENERIC1_SEND, send,
 221                                 HDMI_GENERIC1_LINE, line);
 222                 break;
 223         case 6:
 224                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 225                                 HDMI_GENERIC0_CONT, cont,
 226                                 HDMI_GENERIC0_SEND, send,
 227                                 HDMI_GENERIC0_LINE, line);
 228                 break;
 229         case 7:
 230                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 231                                 HDMI_GENERIC1_CONT, cont,
 232                                 HDMI_GENERIC1_SEND, send,
 233                                 HDMI_GENERIC1_LINE, line);
 234                 break;
 235         default:
 236                 /* invalid HW packet index */
 237                 DC_LOG_WARNING(
 238                         "Invalid HW packet index: %s()\n",
 239                         __func__);
 240                 return;
 241         }
 242 }
 243
 244 /* setup stream encoder in dp mode */
 245 void enc1_stream_encoder_dp_set_stream_attribute(
 246         struct stream_encoder *enc,
 247         struct dc_crtc_timing *crtc_timing,
 248         enum dc_color_space output_color_space)
 249 {
 250         uint32_t h_active_start;
 251         uint32_t v_active_start;
 252         uint32_t misc0 = 0;
 253         uint32_t misc1 = 0;
 254         uint32_t h_blank;
 255         uint32_t h_back_porch;
 256         uint8_t synchronous_clock = 0; /* asynchronous mode */
 257         uint8_t colorimetry_bpc;
 258         uint8_t dynamic_range_rgb = 0; /*full range*/
 259         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 260         uint8_t dp_pixel_encoding = 0;
 261         uint8_t dp_component_depth = 0;
 262
 263         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 264         struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 265
 266         if (hw_crtc_timing.flags.INTERLACE) {
 267                 /*the input timing is in VESA spec format with Interlace flag =1*/
 268                 hw_crtc_timing.v_total /= 2;
 269                 hw_crtc_timing.v_border_top /= 2;
 270                 hw_crtc_timing.v_addressable /= 2;
 271                 hw_crtc_timing.v_border_bottom /= 2;
 272                 hw_crtc_timing.v_front_porch /= 2;
 273                 hw_crtc_timing.v_sync_width /= 2;
 274         }
 275
 276
 277         /* set pixel encoding */
 278         switch (hw_crtc_timing.pixel_encoding) {
 279         case PIXEL_ENCODING_YCBCR422:
 280                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
 281                 break;
 282         case PIXEL_ENCODING_YCBCR444:
 283                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
 284
 285                 if (hw_crtc_timing.flags.Y_ONLY)
 286                         if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 287                                 /* HW testing only, no use case yet.
 288                                  * Color depth of Y-only could be
 289                                  * 8, 10, 12, 16 bits
 290                                  */
 291                                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
 292
 293                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 294                  * of Y-only mode.
 295                  * This bit is set in HW if register
 296                  * DP_PIXEL_ENCODING is programmed to 0x4
 297                  */
 298                 break;
 299         case PIXEL_ENCODING_YCBCR420:
 300                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
 301                 break;
 302         default:
 303                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
 304                 break;
 305         }
 306
 307         misc1 = REG_READ(DP_MSA_MISC);
 308         /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
 309          * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
 310          * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
 311          * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
 312          */
 313         if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
 314                         (output_color_space == COLOR_SPACE_2020_YCBCR) ||
 315                         (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
 316                         (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
 317                 misc1 = misc1 | 0x40;
 318         else
 319                 misc1 = misc1 & ~0x40;
 320
 321         /* set color depth */
 322         switch (hw_crtc_timing.display_color_depth) {
 323         case COLOR_DEPTH_666:
 324                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
 325                 break;
 326         case COLOR_DEPTH_888:
 327                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
 328                 break;
 329         case COLOR_DEPTH_101010:
 330                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
 331                 break;
 332         case COLOR_DEPTH_121212:
 333                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
 334                 break;
 335         case COLOR_DEPTH_161616:
 336                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
 337                 break;
 338         default:
 339                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
 340                 break;
 341         }
 342
 343         /* Set DP pixel encoding and component depth */
 344         REG_UPDATE_2(DP_PIXEL_FORMAT,
 345                         DP_PIXEL_ENCODING, dp_pixel_encoding,
 346                         DP_COMPONENT_DEPTH, dp_component_depth);
 347
 348         /* set dynamic range and YCbCr range */
 349
 350         switch (hw_crtc_timing.display_color_depth) {
 351         case COLOR_DEPTH_666:
 352                 colorimetry_bpc = 0;
 353                 break;
 354         case COLOR_DEPTH_888:
 355                 colorimetry_bpc = 1;
 356                 break;
 357         case COLOR_DEPTH_101010:
 358                 colorimetry_bpc = 2;
 359                 break;
 360         case COLOR_DEPTH_121212:
 361                 colorimetry_bpc = 3;
 362                 break;
 363         default:
 364                 colorimetry_bpc = 0;
 365                 break;
 366         }
 367
 368         misc0 = misc0 | synchronous_clock;
 369         misc0 = colorimetry_bpc << 5;
 370
 371         switch (output_color_space) {
 372         case COLOR_SPACE_SRGB:
 373                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 374                 dynamic_range_rgb = 0; /*full range*/
 375                 break;
 376         case COLOR_SPACE_SRGB_LIMITED:
 377                 misc0 = misc0 | 0x8; /* bit3=1 */
 378                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 379                 dynamic_range_rgb = 1; /*limited range*/
 380                 break;
 381         case COLOR_SPACE_YCBCR601:
 382         case COLOR_SPACE_YCBCR601_LIMITED:
 383                 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 384                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 385                 dynamic_range_ycbcr = 0; /*bt601*/
 386                 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 387                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 388                 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 389                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 390                 break;
 391         case COLOR_SPACE_YCBCR709:
 392         case COLOR_SPACE_YCBCR709_LIMITED:
 393                 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 394                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
 395                 dynamic_range_ycbcr = 1; /*bt709*/
 396                 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 397                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 398                 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 399                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 400                 break;
 401         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 402                 dynamic_range_rgb = 1; /*limited range*/
 403                 break;
 404         case COLOR_SPACE_2020_RGB_FULLRANGE:
 405         case COLOR_SPACE_2020_YCBCR:
 406         case COLOR_SPACE_XR_RGB:
 407         case COLOR_SPACE_MSREF_SCRGB:
 408         case COLOR_SPACE_ADOBERGB:
 409         case COLOR_SPACE_DCIP3:
 410         case COLOR_SPACE_XV_YCC_709:
 411         case COLOR_SPACE_XV_YCC_601:
 412         case COLOR_SPACE_DISPLAYNATIVE:
 413         case COLOR_SPACE_DOLBYVISION:
 414         case COLOR_SPACE_APPCTRL:
 415         case COLOR_SPACE_CUSTOMPOINTS:
 416         case COLOR_SPACE_UNKNOWN:
 417                 /* do nothing */
 418                 break;
 419         }
 420
 421         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 422         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 423
 424         /* dcn new register
 425          * dc_crtc_timing is vesa dmt struct. data from edid
 426          */
 427         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 428                         DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 429                         DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 430
 431         /* calculate from vesa timing parameters
 432          * h_active_start related to leading edge of sync
 433          */
 434
 435         h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 436                         hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 437
 438         h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 439                         hw_crtc_timing.h_sync_width;
 440
 441         /* start at beginning of left border */
 442         h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 443
 444
 445         v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 446                         hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 447                         hw_crtc_timing.v_front_porch;
 448
 449
 450         /* start at beginning of left border */
 451         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 452                 DP_MSA_HSTART, h_active_start,
 453                 DP_MSA_VSTART, v_active_start);
 454
 455         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 456                         DP_MSA_HSYNCWIDTH,
 457                         hw_crtc_timing.h_sync_width,
 458                         DP_MSA_HSYNCPOLARITY,
 459                         !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 460                         DP_MSA_VSYNCWIDTH,
 461                         hw_crtc_timing.v_sync_width,
 462                         DP_MSA_VSYNCPOLARITY,
 463                         !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 464
 465         /* HWDITH include border or overscan */
 466         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 467                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 468                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 469                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 470                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 471 }
 472
 473 static void enc1_stream_encoder_set_stream_attribute_helper(
 474                 struct dcn10_stream_encoder *enc1,
 475                 struct dc_crtc_timing *crtc_timing)
 476 {
 477         switch (crtc_timing->pixel_encoding) {
 478         case PIXEL_ENCODING_YCBCR422:
 479                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 480                 break;
 481         default:
 482                 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 483                 break;
 484         }
 485         REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 486 }
 487
 488 /* setup stream encoder in hdmi mode */
 489 void enc1_stream_encoder_hdmi_set_stream_attribute(
 490         struct stream_encoder *enc,
 491         struct dc_crtc_timing *crtc_timing,
 492         int actual_pix_clk_khz,
 493         bool enable_audio)
 494 {
 495         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 496         struct bp_encoder_control cntl = {0};
 497
 498         cntl.action = ENCODER_CONTROL_SETUP;
 499         cntl.engine_id = enc1->base.id;
 500         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 501         cntl.enable_dp_audio = enable_audio;
 502         cntl.pixel_clock = actual_pix_clk_khz;
 503         cntl.lanes_number = LANE_COUNT_FOUR;
 504
 505         if (enc1->base.bp->funcs->encoder_control(
 506                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 507                 return;
 508
 509         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 510
 511         /* setup HDMI engine */
 512         REG_UPDATE_5(HDMI_CONTROL,
 513                 HDMI_PACKET_GEN_VERSION, 1,
 514                 HDMI_KEEPOUT_MODE, 1,
 515                 HDMI_DEEP_COLOR_ENABLE, 0,
 516                 HDMI_DATA_SCRAMBLE_EN, 0,
 517                 HDMI_CLOCK_CHANNEL_RATE, 0);
 518
 519
 520         switch (crtc_timing->display_color_depth) {
 521         case COLOR_DEPTH_888:
 522                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 523                 break;
 524         case COLOR_DEPTH_101010:
 525                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 526                         REG_UPDATE_2(HDMI_CONTROL,
 527                                         HDMI_DEEP_COLOR_DEPTH, 1,
 528                                         HDMI_DEEP_COLOR_ENABLE, 0);
 529                 } else {
 530                         REG_UPDATE_2(HDMI_CONTROL,
 531                                         HDMI_DEEP_COLOR_DEPTH, 1,
 532                                         HDMI_DEEP_COLOR_ENABLE, 1);
 533                         }
 534                 break;
 535         case COLOR_DEPTH_121212:
 536                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 537                         REG_UPDATE_2(HDMI_CONTROL,
 538                                         HDMI_DEEP_COLOR_DEPTH, 2,
 539                                         HDMI_DEEP_COLOR_ENABLE, 0);
 540                 } else {
 541                         REG_UPDATE_2(HDMI_CONTROL,
 542                                         HDMI_DEEP_COLOR_DEPTH, 2,
 543                                         HDMI_DEEP_COLOR_ENABLE, 1);
 544                         }
 545                 break;
 546         case COLOR_DEPTH_161616:
 547                 REG_UPDATE_2(HDMI_CONTROL,
 548                                 HDMI_DEEP_COLOR_DEPTH, 3,
 549                                 HDMI_DEEP_COLOR_ENABLE, 1);
 550                 break;
 551         default:
 552                 break;
 553         }
 554
 555         if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 556                 /* enable HDMI data scrambler
 557                  * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 558                  * Clock channel frequency is 1/4 of character rate.
 559                  */
 560                 REG_UPDATE_2(HDMI_CONTROL,
 561                         HDMI_DATA_SCRAMBLE_EN, 1,
 562                         HDMI_CLOCK_CHANNEL_RATE, 1);
 563         } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 564
 565                 /* TODO: New feature for DCE11, still need to implement */
 566
 567                 /* enable HDMI data scrambler
 568                  * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 569                  * Clock channel frequency is the same
 570                  * as character rate
 571                  */
 572                 REG_UPDATE_2(HDMI_CONTROL,
 573                         HDMI_DATA_SCRAMBLE_EN, 1,
 574                         HDMI_CLOCK_CHANNEL_RATE, 0);
 575         }
 576
 577
 578         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 579                 HDMI_GC_CONT, 1,
 580                 HDMI_GC_SEND, 1,
 581                 HDMI_NULL_SEND, 1);
 582
 583         /* following belongs to audio */
 584         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 585
 586         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 587
 588         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 589                                 VBI_LINE_0 + 2);
 590
 591         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 592 }
 593
 594 /* setup stream encoder in dvi mode */
 595 void enc1_stream_encoder_dvi_set_stream_attribute(
 596         struct stream_encoder *enc,
 597         struct dc_crtc_timing *crtc_timing,
 598         bool is_dual_link)
 599 {
 600         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 601         struct bp_encoder_control cntl = {0};
 602
 603         cntl.action = ENCODER_CONTROL_SETUP;
 604         cntl.engine_id = enc1->base.id;
 605         cntl.signal = is_dual_link ?
 606                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 607         cntl.enable_dp_audio = false;
 608         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 609         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 610
 611         if (enc1->base.bp->funcs->encoder_control(
 612                         enc1->base.bp, &cntl) != BP_RESULT_OK)
 613                 return;
 614
 615         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 616         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 617         enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
 618 }
 619
 620 void enc1_stream_encoder_set_mst_bandwidth(
 621         struct stream_encoder *enc,
 622         struct fixed31_32 avg_time_slots_per_mtp)
 623 {
 624         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 625         uint32_t x = dc_fixpt_floor(
 626                 avg_time_slots_per_mtp);
 627         uint32_t y = dc_fixpt_ceil(
 628                 dc_fixpt_shl(
 629                         dc_fixpt_sub_int(
 630                                 avg_time_slots_per_mtp,
 631                                 x),
 632                         26));
 633
 634         REG_SET_2(DP_MSE_RATE_CNTL, 0,
 635                 DP_MSE_RATE_X, x,
 636                 DP_MSE_RATE_Y, y);
 637
 638         /* wait for update to be completed on the link */
 639         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 640         /* is reset to 0 (not pending) */
 641         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 642                         0,
 643                         10, DP_MST_UPDATE_MAX_RETRY);
 644 }
 645
 646 static void enc1_stream_encoder_update_hdmi_info_packets(
 647         struct stream_encoder *enc,
 648         const struct encoder_info_frame *info_frame)
 649 {
 650         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 651
 652         /* for bring up, disable dp double  TODO */
 653         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 654
 655         enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
 656         enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
 657         enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
 658         enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
 659         enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
 660 }
 661
 662 static void enc1_stream_encoder_stop_hdmi_info_packets(
 663         struct stream_encoder *enc)
 664 {
 665         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 666
 667         /* stop generic packets 0 & 1 on HDMI */
 668         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 669                 HDMI_GENERIC1_CONT, 0,
 670                 HDMI_GENERIC1_LINE, 0,
 671                 HDMI_GENERIC1_SEND, 0,
 672                 HDMI_GENERIC0_CONT, 0,
 673                 HDMI_GENERIC0_LINE, 0,
 674                 HDMI_GENERIC0_SEND, 0);
 675
 676         /* stop generic packets 2 & 3 on HDMI */
 677         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 678                 HDMI_GENERIC0_CONT, 0,
 679                 HDMI_GENERIC0_LINE, 0,
 680                 HDMI_GENERIC0_SEND, 0,
 681                 HDMI_GENERIC1_CONT, 0,
 682                 HDMI_GENERIC1_LINE, 0,
 683                 HDMI_GENERIC1_SEND, 0);
 684
 685         /* stop generic packets 2 & 3 on HDMI */
 686         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 687                 HDMI_GENERIC0_CONT, 0,
 688                 HDMI_GENERIC0_LINE, 0,
 689                 HDMI_GENERIC0_SEND, 0,
 690                 HDMI_GENERIC1_CONT, 0,
 691                 HDMI_GENERIC1_LINE, 0,
 692                 HDMI_GENERIC1_SEND, 0);
 693
 694         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 695                 HDMI_GENERIC0_CONT, 0,
 696                 HDMI_GENERIC0_LINE, 0,
 697                 HDMI_GENERIC0_SEND, 0,
 698                 HDMI_GENERIC1_CONT, 0,
 699                 HDMI_GENERIC1_LINE, 0,
 700                 HDMI_GENERIC1_SEND, 0);
 701 }
 702
 703 void enc1_stream_encoder_update_dp_info_packets(
 704         struct stream_encoder *enc,
 705         const struct encoder_info_frame *info_frame)
 706 {
 707         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 708         uint32_t value = 0;
 709
 710         if (info_frame->vsc.valid)
 711                 enc1_update_generic_info_packet(
 712                                         enc1,
 713                                         0,  /* packetIndex */
 714                                         &info_frame->vsc);
 715
 716         if (info_frame->spd.valid)
 717                 enc1_update_generic_info_packet(
 718                                 enc1,
 719                                 2,  /* packetIndex */
 720                                 &info_frame->spd);
 721
 722         if (info_frame->hdrsmd.valid)
 723                 enc1_update_generic_info_packet(
 724                                 enc1,
 725                                 3,  /* packetIndex */
 726                                 &info_frame->hdrsmd);
 727
 728         if (info_frame->dpsdp.valid)
 729                 enc1_update_generic_info_packet(
 730                                 enc1,
 731                                 4,/* packetIndex */
 732                                 &info_frame->dpsdp);
 733
 734         /* enable/disable transmission of packet(s).
 735          * If enabled, packet transmission begins on the next frame
 736          */
 737         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 738         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 739         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 740         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, info_frame->dpsdp.valid);
 741
 742         /* This bit is the master enable bit.
 743          * When enabling secondary stream engine,
 744          * this master bit must also be set.
 745          * This register shared with audio info frame.
 746          * Therefore we need to enable master bit
 747          * if at least on of the fields is not 0
 748          */
 749         value = REG_READ(DP_SEC_CNTL);
 750         if (value)
 751                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 752 }
 753
 754 void enc1_stream_encoder_stop_dp_info_packets(
 755         struct stream_encoder *enc)
 756 {
 757         /* stop generic packets on DP */
 758         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 759         uint32_t value = 0;
 760
 761         REG_SET_10(DP_SEC_CNTL, 0,
 762                 DP_SEC_GSP0_ENABLE, 0,
 763                 DP_SEC_GSP1_ENABLE, 0,
 764                 DP_SEC_GSP2_ENABLE, 0,
 765                 DP_SEC_GSP3_ENABLE, 0,
 766                 DP_SEC_GSP4_ENABLE, 0,
 767                 DP_SEC_GSP5_ENABLE, 0,
 768                 DP_SEC_GSP6_ENABLE, 0,
 769                 DP_SEC_GSP7_ENABLE, 0,
 770                 DP_SEC_MPG_ENABLE, 0,
 771                 DP_SEC_STREAM_ENABLE, 0);
 772
 773         /* this register shared with audio info frame.
 774          * therefore we need to keep master enabled
 775          * if at least one of the fields is not 0 */
 776         value = REG_READ(DP_SEC_CNTL);
 777         if (value)
 778                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 779
 780 }
 781
 782 void enc1_stream_encoder_dp_blank(
 783         struct stream_encoder *enc)
 784 {
 785         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 786         uint32_t  reg1 = 0;
 787         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 788
 789         /* Note: For CZ, we are changing driver default to disable
 790          * stream deferred to next VBLANK. If results are positive, we
 791          * will make the same change to all DCE versions. There are a
 792          * handful of panels that cannot handle disable stream at
 793          * HBLANK and will result in a white line flash across the
 794          * screen on stream disable.
 795          */
 796         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 797         if ((reg1 & 0x1) == 0)
 798                 /*stream not enabled*/
 799                 return;
 800         /* Specify the video stream disable point
 801          * (2 = start of the next vertical blank)
 802          */
 803         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 804         /* Larger delay to wait until VBLANK - use max retry of
 805          * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
 806          * a little more because we may not trust delay accuracy.
 807          */
 808         max_retries = DP_BLANK_MAX_RETRY * 250;
 809
 810         /* disable DP stream */
 811         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 812
 813         /* the encoder stops sending the video stream
 814          * at the start of the vertical blanking.
 815          * Poll for DP_VID_STREAM_STATUS == 0
 816          */
 817
 818         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 819                         0,
 820                         10, max_retries);
 821
 822         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 823          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 824          * complete, stream status will be stuck in video stream enabled state,
 825          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 826          */
 827
 828         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 829 }
 830
 831 /* output video stream to link encoder */
 832 void enc1_stream_encoder_dp_unblank(
 833         struct stream_encoder *enc,
 834         const struct encoder_unblank_param *param)
 835 {
 836         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 837
 838         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 839                 uint32_t n_vid = 0x8000;
 840                 uint32_t m_vid;
 841                 uint32_t n_multiply = 0;
 842                 uint64_t m_vid_l = n_vid;
 843
 844                 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
 845                 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 846                         /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
 847                         n_multiply = 1;
 848                 }
 849                 /* M / N = Fstream / Flink
 850                  * m_vid / n_vid = pixel rate / link rate
 851                  */
 852
 853                 m_vid_l *= param->timing.pix_clk_100hz / 10;
 854                 m_vid_l = div_u64(m_vid_l,
 855                         param->link_settings.link_rate
 856                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 857
 858                 m_vid = (uint32_t) m_vid_l;
 859
 860                 /* enable auto measurement */
 861
 862                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 863
 864                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 865                  * therefore program initial value for Mvid and Nvid
 866                  */
 867
 868                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 869
 870                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 871
 872                 REG_UPDATE_2(DP_VID_TIMING,
 873                                 DP_VID_M_N_GEN_EN, 1,
 874                                 DP_VID_N_MUL, n_multiply);
 875         }
 876
 877         /* set DIG_START to 0x1 to resync FIFO */
 878
 879         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
 880
 881         /* switch DP encoder to CRTC data */
 882
 883         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 884
 885         /* wait 100us for DIG/DP logic to prime
 886          * (i.e. a few video lines)
 887          */
 888         udelay(100);
 889
 890         /* the hardware would start sending video at the start of the next DP
 891          * frame (i.e. rising edge of the vblank).
 892          * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
 893          * register has no effect on enable transition! HW always guarantees
 894          * VID_STREAM enable at start of next frame, and this is not
 895          * programmable
 896          */
 897
 898         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
 899 }
 900
 901 void enc1_stream_encoder_set_avmute(
 902         struct stream_encoder *enc,
 903         bool enable)
 904 {
 905         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 906         unsigned int value = enable ? 1 : 0;
 907
 908         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
 909 }
 910
 911
 912 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
 913 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
 914
 915 #include "include/audio_types.h"
 916
 917 /**
 918 * speakersToChannels
 919 *
 920 * @brief
 921 *  translate speakers to channels
 922 *
 923 *  FL  - Front Left
 924 *  FR  - Front Right
 925 *  RL  - Rear Left
 926 *  RR  - Rear Right
 927 *  RC  - Rear Center
 928 *  FC  - Front Center
 929 *  FLC - Front Left Center
 930 *  FRC - Front Right Center
 931 *  RLC - Rear Left Center
 932 *  RRC - Rear Right Center
 933 *  LFE - Low Freq Effect
 934 *
 935 *               FC
 936 *          FLC      FRC
 937 *    FL                    FR
 938 *
 939 *                    LFE
 940 *              ()
 941 *
 942 *
 943 *    RL                    RR
 944 *          RLC      RRC
 945 *               RC
 946 *
 947 *             ch  8   7   6   5   4   3   2   1
 948 * 0b00000011      -   -   -   -   -   -   FR  FL
 949 * 0b00000111      -   -   -   -   -   LFE FR  FL
 950 * 0b00001011      -   -   -   -   FC  -   FR  FL
 951 * 0b00001111      -   -   -   -   FC  LFE FR  FL
 952 * 0b00010011      -   -   -   RC  -   -   FR  FL
 953 * 0b00010111      -   -   -   RC  -   LFE FR  FL
 954 * 0b00011011      -   -   -   RC  FC  -   FR  FL
 955 * 0b00011111      -   -   -   RC  FC  LFE FR  FL
 956 * 0b00110011      -   -   RR  RL  -   -   FR  FL
 957 * 0b00110111      -   -   RR  RL  -   LFE FR  FL
 958 * 0b00111011      -   -   RR  RL  FC  -   FR  FL
 959 * 0b00111111      -   -   RR  RL  FC  LFE FR  FL
 960 * 0b01110011      -   RC  RR  RL  -   -   FR  FL
 961 * 0b01110111      -   RC  RR  RL  -   LFE FR  FL
 962 * 0b01111011      -   RC  RR  RL  FC  -   FR  FL
 963 * 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
 964 * 0b11110011      RRC RLC RR  RL  -   -   FR  FL
 965 * 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
 966 * 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
 967 * 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
 968 * 0b11000011      FRC FLC -   -   -   -   FR  FL
 969 * 0b11000111      FRC FLC -   -   -   LFE FR  FL
 970 * 0b11001011      FRC FLC -   -   FC  -   FR  FL
 971 * 0b11001111      FRC FLC -   -   FC  LFE FR  FL
 972 * 0b11010011      FRC FLC -   RC  -   -   FR  FL
 973 * 0b11010111      FRC FLC -   RC  -   LFE FR  FL
 974 * 0b11011011      FRC FLC -   RC  FC  -   FR  FL
 975 * 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
 976 * 0b11110011      FRC FLC RR  RL  -   -   FR  FL
 977 * 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
 978 * 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
 979 * 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
 980 *
 981 * @param
 982 *  speakers - speaker information as it comes from CEA audio block
 983 */
 984 /* translate speakers to channels */
 985
 986 union audio_cea_channels {
 987         uint8_t all;
 988         struct audio_cea_channels_bits {
 989                 uint32_t FL:1;
 990                 uint32_t FR:1;
 991                 uint32_t LFE:1;
 992                 uint32_t FC:1;
 993                 uint32_t RL_RC:1;
 994                 uint32_t RR:1;
 995                 uint32_t RC_RLC_FLC:1;
 996                 uint32_t RRC_FRC:1;
 997         } channels;
 998 };
 999
1000 struct audio_clock_info {
1001         /* pixel clock frequency*/
1002         uint32_t pixel_clock_in_10khz;
1003         /* N - 32KHz audio */
1004         uint32_t n_32khz;
1005         /* CTS - 32KHz audio*/
1006         uint32_t cts_32khz;
1007         uint32_t n_44khz;
1008         uint32_t cts_44khz;
1009         uint32_t n_48khz;
1010         uint32_t cts_48khz;
1011 };
1012
1013 /* 25.2MHz/1.001*/
1014 /* 25.2MHz/1.001*/
1015 /* 25.2MHz*/
1016 /* 27MHz */
1017 /* 27MHz*1.001*/
1018 /* 27MHz*1.001*/
1019 /* 54MHz*/
1020 /* 54MHz*1.001*/
1021 /* 74.25MHz/1.001*/
1022 /* 74.25MHz*/
1023 /* 148.5MHz/1.001*/
1024 /* 148.5MHz*/
1025
1026 static const struct audio_clock_info audio_clock_info_table[16] = {
1027         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1028         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1029         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1030         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1031         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1032         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1033         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1034         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1035         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1036         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1037         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1038         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1039         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1040         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1041         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1042         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1043 };
1044
1045 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1046         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1047         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1048         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1049         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1050         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1051         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1052         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1053         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1054         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1055         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1056         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1057         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1058         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1059         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1060 };
1061
1062 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1063         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1064         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1065         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1066         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1067         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1068         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1069         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1070         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1071         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1072         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1073         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1074         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1075         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1076         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1077
1078
1079 };
1080
1081 static union audio_cea_channels speakers_to_channels(
1082         struct audio_speaker_flags speaker_flags)
1083 {
1084         union audio_cea_channels cea_channels = {0};
1085
1086         /* these are one to one */
1087         cea_channels.channels.FL = speaker_flags.FL_FR;
1088         cea_channels.channels.FR = speaker_flags.FL_FR;
1089         cea_channels.channels.LFE = speaker_flags.LFE;
1090         cea_channels.channels.FC = speaker_flags.FC;
1091
1092         /* if Rear Left and Right exist move RC speaker to channel 7
1093          * otherwise to channel 5
1094          */
1095         if (speaker_flags.RL_RR) {
1096                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1097                 cea_channels.channels.RR = speaker_flags.RL_RR;
1098                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1099         } else {
1100                 cea_channels.channels.RL_RC = speaker_flags.RC;
1101         }
1102
1103         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1104         if (speaker_flags.FLC_FRC) {
1105                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1106                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1107         } else {
1108                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1109                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1110         }
1111
1112         return cea_channels;
1113 }
1114
1115 static void get_audio_clock_info(
1116         enum dc_color_depth color_depth,
1117         uint32_t crtc_pixel_clock_in_khz,
1118         uint32_t actual_pixel_clock_in_khz,
1119         struct audio_clock_info *audio_clock_info)
1120 {
1121         const struct audio_clock_info *clock_info;
1122         uint32_t index;
1123         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1124         uint32_t audio_array_size;
1125
1126         switch (color_depth) {
1127         case COLOR_DEPTH_161616:
1128                 clock_info = audio_clock_info_table_48bpc;
1129                 audio_array_size = ARRAY_SIZE(
1130                                 audio_clock_info_table_48bpc);
1131                 break;
1132         case COLOR_DEPTH_121212:
1133                 clock_info = audio_clock_info_table_36bpc;
1134                 audio_array_size = ARRAY_SIZE(
1135                                 audio_clock_info_table_36bpc);
1136                 break;
1137         default:
1138                 clock_info = audio_clock_info_table;
1139                 audio_array_size = ARRAY_SIZE(
1140                                 audio_clock_info_table);
1141                 break;
1142         }
1143
1144         if (clock_info != NULL) {
1145                 /* search for exact pixel clock in table */
1146                 for (index = 0; index < audio_array_size; index++) {
1147                         if (clock_info[index].pixel_clock_in_10khz >
1148                                 crtc_pixel_clock_in_10khz)
1149                                 break;  /* not match */
1150                         else if (clock_info[index].pixel_clock_in_10khz ==
1151                                         crtc_pixel_clock_in_10khz) {
1152                                 /* match found */
1153                                 *audio_clock_info = clock_info[index];
1154                                 return;
1155                         }
1156                 }
1157         }
1158
1159         /* not found */
1160         if (actual_pixel_clock_in_khz == 0)
1161                 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1162
1163         /* See HDMI spec  the table entry under
1164          *  pixel clock of "Other". */
1165         audio_clock_info->pixel_clock_in_10khz =
1166                         actual_pixel_clock_in_khz / 10;
1167         audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1168         audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1169         audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1170
1171         audio_clock_info->n_32khz = 4096;
1172         audio_clock_info->n_44khz = 6272;
1173         audio_clock_info->n_48khz = 6144;
1174 }
1175
1176 static void enc1_se_audio_setup(
1177         struct stream_encoder *enc,
1178         unsigned int az_inst,
1179         struct audio_info *audio_info)
1180 {
1181         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1182
1183         uint32_t speakers = 0;
1184         uint32_t channels = 0;
1185
1186         ASSERT(audio_info);
1187         if (audio_info == NULL)
1188                 /* This should not happen.it does so we don't get BSOD*/
1189                 return;
1190
1191         speakers = audio_info->flags.info.ALLSPEAKERS;
1192         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1193
1194         /* setup the audio stream source select (audio -> dig mapping) */
1195         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1196
1197         /* Channel allocation */
1198         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1199 }
1200
1201 static void enc1_se_setup_hdmi_audio(
1202         struct stream_encoder *enc,
1203         const struct audio_crtc_info *crtc_info)
1204 {
1205         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1206
1207         struct audio_clock_info audio_clock_info = {0};
1208
1209         /* HDMI_AUDIO_PACKET_CONTROL */
1210         REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1211                         HDMI_AUDIO_DELAY_EN, 1);
1212
1213         /* AFMT_AUDIO_PACKET_CONTROL */
1214         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1215
1216         /* AFMT_AUDIO_PACKET_CONTROL2 */
1217         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1218                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1219                         AFMT_60958_OSF_OVRD, 0);
1220
1221         /* HDMI_ACR_PACKET_CONTROL */
1222         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1223                         HDMI_ACR_AUTO_SEND, 1,
1224                         HDMI_ACR_SOURCE, 0,
1225                         HDMI_ACR_AUDIO_PRIORITY, 0);
1226
1227         /* Program audio clock sample/regeneration parameters */
1228         get_audio_clock_info(crtc_info->color_depth,
1229                              crtc_info->requested_pixel_clock,
1230                              crtc_info->calculated_pixel_clock,
1231                              &audio_clock_info);
1232         DC_LOG_HW_AUDIO(
1233                         "\n%s:Input::requested_pixel_clock = %d"        \
1234                         "calculated_pixel_clock = %d \n", __func__,     \
1235                         crtc_info->requested_pixel_clock,               \
1236                         crtc_info->calculated_pixel_clock);
1237
1238         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1239         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1240
1241         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1242         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1243
1244         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1245         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1246
1247         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1248         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1249
1250         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1251         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1252
1253         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1254         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1255
1256         /* Video driver cannot know in advance which sample rate will
1257          * be used by HD Audio driver
1258          * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1259          * programmed below in interruppt callback
1260          */
1261
1262         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1263          * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1264          */
1265         REG_UPDATE_2(AFMT_60958_0,
1266                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1267                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1268
1269         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1270         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1271
1272         /* AFMT_60958_2 now keep this settings until
1273          * Programming guide comes out
1274          */
1275         REG_UPDATE_6(AFMT_60958_2,
1276                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1277                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1278                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1279                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1280                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1281                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1282 }
1283
1284 static void enc1_se_setup_dp_audio(
1285         struct stream_encoder *enc)
1286 {
1287         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1288
1289         /* --- DP Audio packet configurations --- */
1290
1291         /* ATP Configuration */
1292         REG_SET(DP_SEC_AUD_N, 0,
1293                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1294
1295         /* Async/auto-calc timestamp mode */
1296         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1297                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1298
1299         /* --- The following are the registers
1300          *  copied from the SetupHDMI ---
1301          */
1302
1303         /* AFMT_AUDIO_PACKET_CONTROL */
1304         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1305
1306         /* AFMT_AUDIO_PACKET_CONTROL2 */
1307         /* Program the ATP and AIP next */
1308         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1309                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1310                         AFMT_60958_OSF_OVRD, 0);
1311
1312         /* AFMT_INFOFRAME_CONTROL0 */
1313         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1314
1315         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1316         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1317 }
1318
1319 static void enc1_se_enable_audio_clock(
1320         struct stream_encoder *enc,
1321         bool enable)
1322 {
1323         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1324
1325         if (REG(AFMT_CNTL) == 0)
1326                 return;   /* DCE8/10 does not have this register */
1327
1328         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1329
1330         /* wait for AFMT clock to turn on,
1331          * expectation: this should complete in 1-2 reads
1332          *
1333          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1334          *
1335          * TODO: wait for clock_on does not work well. May need HW
1336          * program sequence. But audio seems work normally even without wait
1337          * for clock_on status change
1338          */
1339 }
1340
1341 static void enc1_se_enable_dp_audio(
1342         struct stream_encoder *enc)
1343 {
1344         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1345
1346         /* Enable Audio packets */
1347         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1348
1349         /* Program the ATP and AIP next */
1350         REG_UPDATE_2(DP_SEC_CNTL,
1351                         DP_SEC_ATP_ENABLE, 1,
1352                         DP_SEC_AIP_ENABLE, 1);
1353
1354         /* Program STREAM_ENABLE after all the other enables. */
1355         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1356 }
1357
1358 static void enc1_se_disable_dp_audio(
1359         struct stream_encoder *enc)
1360 {
1361         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1362         uint32_t value = 0;
1363
1364         /* Disable Audio packets */
1365         REG_UPDATE_5(DP_SEC_CNTL,
1366                         DP_SEC_ASP_ENABLE, 0,
1367                         DP_SEC_ATP_ENABLE, 0,
1368                         DP_SEC_AIP_ENABLE, 0,
1369                         DP_SEC_ACM_ENABLE, 0,
1370                         DP_SEC_STREAM_ENABLE, 0);
1371
1372         /* This register shared with encoder info frame. Therefore we need to
1373          * keep master enabled if at least on of the fields is not 0
1374          */
1375         value = REG_READ(DP_SEC_CNTL);
1376         if (value != 0)
1377                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1378
1379 }
1380
1381 void enc1_se_audio_mute_control(
1382         struct stream_encoder *enc,
1383         bool mute)
1384 {
1385         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1386
1387         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1388 }
1389
1390 void enc1_se_dp_audio_setup(
1391         struct stream_encoder *enc,
1392         unsigned int az_inst,
1393         struct audio_info *info)
1394 {
1395         enc1_se_audio_setup(enc, az_inst, info);
1396 }
1397
1398 void enc1_se_dp_audio_enable(
1399         struct stream_encoder *enc)
1400 {
1401         enc1_se_enable_audio_clock(enc, true);
1402         enc1_se_setup_dp_audio(enc);
1403         enc1_se_enable_dp_audio(enc);
1404 }
1405
1406 void enc1_se_dp_audio_disable(
1407         struct stream_encoder *enc)
1408 {
1409         enc1_se_disable_dp_audio(enc);
1410         enc1_se_enable_audio_clock(enc, false);
1411 }
1412
1413 void enc1_se_hdmi_audio_setup(
1414         struct stream_encoder *enc,
1415         unsigned int az_inst,
1416         struct audio_info *info,
1417         struct audio_crtc_info *audio_crtc_info)
1418 {
1419         enc1_se_enable_audio_clock(enc, true);
1420         enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1421         enc1_se_audio_setup(enc, az_inst, info);
1422 }
1423
1424 void enc1_se_hdmi_audio_disable(
1425         struct stream_encoder *enc)
1426 {
1427         enc1_se_enable_audio_clock(enc, false);
1428 }
1429
1430
1431 void enc1_setup_stereo_sync(
1432         struct stream_encoder *enc,
1433         int tg_inst, bool enable)
1434 {
1435         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1436         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1437         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1438 }
1439
1440 void enc1_dig_connect_to_otg(
1441         struct stream_encoder *enc,
1442         int tg_inst)
1443 {
1444         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1445
1446         REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1447 }
1448
1449 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1450         .dp_set_stream_attribute =
1451                 enc1_stream_encoder_dp_set_stream_attribute,
1452         .hdmi_set_stream_attribute =
1453                 enc1_stream_encoder_hdmi_set_stream_attribute,
1454         .dvi_set_stream_attribute =
1455                 enc1_stream_encoder_dvi_set_stream_attribute,
1456         .set_mst_bandwidth =
1457                 enc1_stream_encoder_set_mst_bandwidth,
1458         .update_hdmi_info_packets =
1459                 enc1_stream_encoder_update_hdmi_info_packets,
1460         .stop_hdmi_info_packets =
1461                 enc1_stream_encoder_stop_hdmi_info_packets,
1462         .update_dp_info_packets =
1463                 enc1_stream_encoder_update_dp_info_packets,
1464         .stop_dp_info_packets =
1465                 enc1_stream_encoder_stop_dp_info_packets,
1466         .dp_blank =
1467                 enc1_stream_encoder_dp_blank,
1468         .dp_unblank =
1469                 enc1_stream_encoder_dp_unblank,
1470         .audio_mute_control = enc1_se_audio_mute_control,
1471
1472         .dp_audio_setup = enc1_se_dp_audio_setup,
1473         .dp_audio_enable = enc1_se_dp_audio_enable,
1474         .dp_audio_disable = enc1_se_dp_audio_disable,
1475
1476         .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1477         .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1478         .setup_stereo_sync  = enc1_setup_stereo_sync,
1479         .set_avmute = enc1_stream_encoder_set_avmute,
1480         .dig_connect_to_otg  = enc1_dig_connect_to_otg,
1481 };
1482
1483 void dcn10_stream_encoder_construct(
1484         struct dcn10_stream_encoder *enc1,
1485         struct dc_context *ctx,
1486         struct dc_bios *bp,
1487         enum engine_id eng_id,
1488         const struct dcn10_stream_enc_registers *regs,
1489         const struct dcn10_stream_encoder_shift *se_shift,
1490         const struct dcn10_stream_encoder_mask *se_mask)
1491 {
1492         enc1->base.funcs = &dcn10_str_enc_funcs;
1493         enc1->base.ctx = ctx;
1494         enc1->base.id = eng_id;
1495         enc1->base.bp = bp;
1496         enc1->regs = regs;
1497         enc1->se_shift = se_shift;
1498         enc1->se_mask = se_mask;
1499 }
1500