drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "resource.h"
  30 #include "include/irq_service_interface.h"
  31 #include "dcn20/dcn20_resource.h"
  32
  33 #include "dcn10/dcn10_hubp.h"
  34 #include "dcn10/dcn10_ipp.h"
  35 #include "dcn20_hubbub.h"
  36 #include "dcn20_mpc.h"
  37 #include "dcn20_hubp.h"
  38 #include "irq/dcn20/irq_service_dcn20.h"
  39 #include "dcn20_dpp.h"
  40 #include "dcn20_optc.h"
  41 #include "dcn20_hwseq.h"
  42 #include "dce110/dce110_hw_sequencer.h"
  43 #include "dcn20_opp.h"
  44
  45 #include "dcn20_link_encoder.h"
  46 #include "dcn20_stream_encoder.h"
  47 #include "dce/dce_clock_source.h"
  48 #include "dce/dce_audio.h"
  49 #include "dce/dce_hwseq.h"
  50 #include "virtual/virtual_stream_encoder.h"
  51 #include "dce110/dce110_resource.h"
  52 #include "dml/display_mode_vba.h"
  53 #include "dcn20_dccg.h"
  54 #include "dcn20_vmid.h"
  55
  56 #include "navi10_ip_offset.h"
  57
  58 #include "dcn/dcn_2_0_0_offset.h"
  59 #include "dcn/dcn_2_0_0_sh_mask.h"
  60
  61 #include "nbio/nbio_2_3_offset.h"
  62
  63 #include "mmhub/mmhub_2_0_0_offset.h"
  64 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  65
  66 #include "reg_helper.h"
  67 #include "dce/dce_abm.h"
  68 #include "dce/dce_dmcu.h"
  69 #include "dce/dce_aux.h"
  70 #include "dce/dce_i2c.h"
  71 #include "vm_helper.h"
  72
  73 #include "amdgpu_socbb.h"
  74
  75 #define SOC_BOUNDING_BOX_VALID false
  76 #define DC_LOGGER_INIT(logger)
  77
  78 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  79         .odm_capable = 1,
  80         .gpuvm_enable = 0,
  81         .hostvm_enable = 0,
  82         .gpuvm_max_page_table_levels = 4,
  83         .hostvm_max_page_table_levels = 4,
  84         .hostvm_cached_page_table_levels = 0,
  85         .pte_group_size_bytes = 2048,
  86         .num_dsc = 0,
  87         .rob_buffer_size_kbytes = 168,
  88         .det_buffer_size_kbytes = 164,
  89         .dpte_buffer_size_in_pte_reqs_luma = 84,
  90         .pde_proc_buffer_size_64k_reqs = 48,
  91         .dpp_output_buffer_pixels = 2560,
  92         .opp_output_buffer_lines = 1,
  93         .pixel_chunk_size_kbytes = 8,
  94         .pte_chunk_size_kbytes = 2,
  95         .meta_chunk_size_kbytes = 2,
  96         .writeback_chunk_size_kbytes = 2,
  97         .line_buffer_size_bits = 789504,
  98         .is_line_buffer_bpp_fixed = 0,
  99         .line_buffer_fixed_bpp = 0,
 100         .dcc_supported = true,
 101         .max_line_buffer_lines = 12,
 102         .writeback_luma_buffer_size_kbytes = 12,
 103         .writeback_chroma_buffer_size_kbytes = 8,
 104         .writeback_chroma_line_buffer_width_pixels = 4,
 105         .writeback_max_hscl_ratio = 1,
 106         .writeback_max_vscl_ratio = 1,
 107         .writeback_min_hscl_ratio = 1,
 108         .writeback_min_vscl_ratio = 1,
 109         .writeback_max_hscl_taps = 12,
 110         .writeback_max_vscl_taps = 12,
 111         .writeback_line_buffer_luma_buffer_size = 0,
 112         .writeback_line_buffer_chroma_buffer_size = 14643,
 113         .cursor_buffer_size = 8,
 114         .cursor_chunk_size = 2,
 115         .max_num_otg = 6,
 116         .max_num_dpp = 6,
 117         .max_num_wb = 1,
 118         .max_dchub_pscl_bw_pix_per_clk = 4,
 119         .max_pscl_lb_bw_pix_per_clk = 2,
 120         .max_lb_vscl_bw_pix_per_clk = 4,
 121         .max_vscl_hscl_bw_pix_per_clk = 4,
 122         .max_hscl_ratio = 8,
 123         .max_vscl_ratio = 8,
 124         .hscl_mults = 4,
 125         .vscl_mults = 4,
 126         .max_hscl_taps = 8,
 127         .max_vscl_taps = 8,
 128         .dispclk_ramp_margin_percent = 1,
 129         .underscan_factor = 1.10,
 130         .min_vblank_lines = 32, //
 131         .dppclk_delay_subtotal = 77, //
 132         .dppclk_delay_scl_lb_only = 16,
 133         .dppclk_delay_scl = 50,
 134         .dppclk_delay_cnvc_formatter = 8,
 135         .dppclk_delay_cnvc_cursor = 6,
 136         .dispclk_delay_subtotal = 87, //
 137         .dcfclk_cstate_latency = 10, // SRExitTime
 138         .max_inter_dcn_tile_repeaters = 8,
 139
 140         .xfc_supported = true,
 141         .xfc_fill_bw_overhead_percent = 10.0,
 142         .xfc_fill_constant_bytes = 0,
 143 };
 144
 145 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
 146
 147
 148 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 149         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 150         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 151         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 152         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 153         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 154         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 155         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 156         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 157         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 158         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 159         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 160         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 161         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 162         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 163 #endif
 164
 165
 166 enum dcn20_clk_src_array_id {
 167         DCN20_CLK_SRC_PLL0,
 168         DCN20_CLK_SRC_PLL1,
 169         DCN20_CLK_SRC_PLL2,
 170         DCN20_CLK_SRC_PLL3,
 171         DCN20_CLK_SRC_PLL4,
 172         DCN20_CLK_SRC_PLL5,
 173         DCN20_CLK_SRC_TOTAL
 174 };
 175
 176 /* begin *********************
 177  * macros to expend register list macro defined in HW object header file */
 178
 179 /* DCN */
 180 /* TODO awful hack. fixup dcn20_dwb.h */
 181 #undef BASE_INNER
 182 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 183
 184 #define BASE(seg) BASE_INNER(seg)
 185
 186 #define SR(reg_name)\
 187                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 188                                         mm ## reg_name
 189
 190 #define SRI(reg_name, block, id)\
 191         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 192                                         mm ## block ## id ## _ ## reg_name
 193
 194 #define SRIR(var_name, reg_name, block, id)\
 195         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 196                                         mm ## block ## id ## _ ## reg_name
 197
 198 #define SRII(reg_name, block, id)\
 199         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 200                                         mm ## block ## id ## _ ## reg_name
 201
 202 #define DCCG_SRII(reg_name, block, id)\
 203         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 204                                         mm ## block ## id ## _ ## reg_name
 205
 206 /* NBIO */
 207 #define NBIO_BASE_INNER(seg) \
 208         NBIO_BASE__INST0_SEG ## seg
 209
 210 #define NBIO_BASE(seg) \
 211         NBIO_BASE_INNER(seg)
 212
 213 #define NBIO_SR(reg_name)\
 214                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 215                                         mm ## reg_name
 216
 217 /* MMHUB */
 218 #define MMHUB_BASE_INNER(seg) \
 219         MMHUB_BASE__INST0_SEG ## seg
 220
 221 #define MMHUB_BASE(seg) \
 222         MMHUB_BASE_INNER(seg)
 223
 224 #define MMHUB_SR(reg_name)\
 225                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 226                                         mmMM ## reg_name
 227
 228 static const struct bios_registers bios_regs = {
 229                 NBIO_SR(BIOS_SCRATCH_3),
 230                 NBIO_SR(BIOS_SCRATCH_6)
 231 };
 232
 233 #define clk_src_regs(index, pllid)\
 234 [index] = {\
 235         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 236 }
 237
 238 static const struct dce110_clk_src_regs clk_src_regs[] = {
 239         clk_src_regs(0, A),
 240         clk_src_regs(1, B),
 241         clk_src_regs(2, C),
 242         clk_src_regs(3, D),
 243         clk_src_regs(4, E),
 244         clk_src_regs(5, F)
 245 };
 246
 247 static const struct dce110_clk_src_shift cs_shift = {
 248                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 249 };
 250
 251 static const struct dce110_clk_src_mask cs_mask = {
 252                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 253 };
 254
 255 static const struct dce_dmcu_registers dmcu_regs = {
 256                 DMCU_DCN10_REG_LIST()
 257 };
 258
 259 static const struct dce_dmcu_shift dmcu_shift = {
 260                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 261 };
 262
 263 static const struct dce_dmcu_mask dmcu_mask = {
 264                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 265 };
 266 /*
 267 static const struct dce_abm_registers abm_regs = {
 268                 ABM_DCN10_REG_LIST(0)
 269 };
 270
 271 static const struct dce_abm_shift abm_shift = {
 272                 ABM_MASK_SH_LIST_DCN10(__SHIFT)
 273 };
 274
 275 static const struct dce_abm_mask abm_mask = {
 276                 ABM_MASK_SH_LIST_DCN10(_MASK)
 277 };
 278 */
 279 #define audio_regs(id)\
 280 [id] = {\
 281                 AUD_COMMON_REG_LIST(id)\
 282 }
 283
 284 static const struct dce_audio_registers audio_regs[] = {
 285         audio_regs(0),
 286         audio_regs(1),
 287         audio_regs(2),
 288         audio_regs(3),
 289         audio_regs(4),
 290         audio_regs(5),
 291         audio_regs(6),
 292 };
 293
 294 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 295                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 296                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 297                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 298
 299 static const struct dce_audio_shift audio_shift = {
 300                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 301 };
 302
 303 static const struct dce_aduio_mask audio_mask = {
 304                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 305 };
 306
 307 #define stream_enc_regs(id)\
 308 [id] = {\
 309         SE_DCN2_REG_LIST(id)\
 310 }
 311
 312 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 313         stream_enc_regs(0),
 314         stream_enc_regs(1),
 315         stream_enc_regs(2),
 316         stream_enc_regs(3),
 317         stream_enc_regs(4),
 318         stream_enc_regs(5),
 319 };
 320
 321 static const struct dcn10_stream_encoder_shift se_shift = {
 322                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 323 };
 324
 325 static const struct dcn10_stream_encoder_mask se_mask = {
 326                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 327 };
 328
 329
 330 #define aux_regs(id)\
 331 [id] = {\
 332         DCN2_AUX_REG_LIST(id)\
 333 }
 334
 335 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 336                 aux_regs(0),
 337                 aux_regs(1),
 338                 aux_regs(2),
 339                 aux_regs(3),
 340                 aux_regs(4),
 341                 aux_regs(5)
 342 };
 343
 344 #define hpd_regs(id)\
 345 [id] = {\
 346         HPD_REG_LIST(id)\
 347 }
 348
 349 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 350                 hpd_regs(0),
 351                 hpd_regs(1),
 352                 hpd_regs(2),
 353                 hpd_regs(3),
 354                 hpd_regs(4),
 355                 hpd_regs(5)
 356 };
 357
 358 #define link_regs(id, phyid)\
 359 [id] = {\
 360         LE_DCN10_REG_LIST(id), \
 361         UNIPHY_DCN2_REG_LIST(phyid), \
 362         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 363 }
 364
 365 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 366         link_regs(0, A),
 367         link_regs(1, B),
 368         link_regs(2, C),
 369         link_regs(3, D),
 370         link_regs(4, E),
 371         link_regs(5, F)
 372 };
 373
 374 static const struct dcn10_link_enc_shift le_shift = {
 375         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
 376 };
 377
 378 static const struct dcn10_link_enc_mask le_mask = {
 379         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
 380 };
 381
 382 #define ipp_regs(id)\
 383 [id] = {\
 384         IPP_REG_LIST_DCN20(id),\
 385 }
 386
 387 static const struct dcn10_ipp_registers ipp_regs[] = {
 388         ipp_regs(0),
 389         ipp_regs(1),
 390         ipp_regs(2),
 391         ipp_regs(3),
 392         ipp_regs(4),
 393         ipp_regs(5),
 394 };
 395
 396 static const struct dcn10_ipp_shift ipp_shift = {
 397                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 398 };
 399
 400 static const struct dcn10_ipp_mask ipp_mask = {
 401                 IPP_MASK_SH_LIST_DCN20(_MASK),
 402 };
 403
 404 #define opp_regs(id)\
 405 [id] = {\
 406         OPP_REG_LIST_DCN20(id),\
 407 }
 408
 409 static const struct dcn20_opp_registers opp_regs[] = {
 410         opp_regs(0),
 411         opp_regs(1),
 412         opp_regs(2),
 413         opp_regs(3),
 414         opp_regs(4),
 415         opp_regs(5),
 416 };
 417
 418 static const struct dcn20_opp_shift opp_shift = {
 419                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 420 };
 421
 422 static const struct dcn20_opp_mask opp_mask = {
 423                 OPP_MASK_SH_LIST_DCN20(_MASK)
 424 };
 425
 426 #define aux_engine_regs(id)\
 427 [id] = {\
 428         AUX_COMMON_REG_LIST0(id), \
 429         .AUXN_IMPCAL = 0, \
 430         .AUXP_IMPCAL = 0, \
 431         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 432 }
 433
 434 static const struct dce110_aux_registers aux_engine_regs[] = {
 435                 aux_engine_regs(0),
 436                 aux_engine_regs(1),
 437                 aux_engine_regs(2),
 438                 aux_engine_regs(3),
 439                 aux_engine_regs(4),
 440                 aux_engine_regs(5)
 441 };
 442
 443 #define tf_regs(id)\
 444 [id] = {\
 445         TF_REG_LIST_DCN20(id),\
 446 }
 447
 448 static const struct dcn2_dpp_registers tf_regs[] = {
 449         tf_regs(0),
 450         tf_regs(1),
 451         tf_regs(2),
 452         tf_regs(3),
 453         tf_regs(4),
 454         tf_regs(5),
 455 };
 456
 457 static const struct dcn2_dpp_shift tf_shift = {
 458                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
 459 };
 460
 461 static const struct dcn2_dpp_mask tf_mask = {
 462                 TF_REG_LIST_SH_MASK_DCN20(_MASK)
 463 };
 464
 465 static const struct dcn20_mpc_registers mpc_regs = {
 466                 MPC_REG_LIST_DCN2_0(0),
 467                 MPC_REG_LIST_DCN2_0(1),
 468                 MPC_REG_LIST_DCN2_0(2),
 469                 MPC_REG_LIST_DCN2_0(3),
 470                 MPC_REG_LIST_DCN2_0(4),
 471                 MPC_REG_LIST_DCN2_0(5),
 472                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 473                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 474                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 475                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 476                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 477                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 478 };
 479
 480 static const struct dcn20_mpc_shift mpc_shift = {
 481         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 482 };
 483
 484 static const struct dcn20_mpc_mask mpc_mask = {
 485         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 486 };
 487
 488 #define tg_regs(id)\
 489 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 490
 491
 492 static const struct dcn_optc_registers tg_regs[] = {
 493         tg_regs(0),
 494         tg_regs(1),
 495         tg_regs(2),
 496         tg_regs(3),
 497         tg_regs(4),
 498         tg_regs(5)
 499 };
 500
 501 static const struct dcn_optc_shift tg_shift = {
 502         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 503 };
 504
 505 static const struct dcn_optc_mask tg_mask = {
 506         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 507 };
 508
 509 #define hubp_regs(id)\
 510 [id] = {\
 511         HUBP_REG_LIST_DCN20(id)\
 512 }
 513
 514 static const struct dcn_hubp2_registers hubp_regs[] = {
 515                 hubp_regs(0),
 516                 hubp_regs(1),
 517                 hubp_regs(2),
 518                 hubp_regs(3),
 519                 hubp_regs(4),
 520                 hubp_regs(5)
 521 };
 522
 523 static const struct dcn_hubp2_shift hubp_shift = {
 524                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 525 };
 526
 527 static const struct dcn_hubp2_mask hubp_mask = {
 528                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 529 };
 530
 531 static const struct dcn_hubbub_registers hubbub_reg = {
 532                 HUBBUB_REG_LIST_DCN20(0)
 533 };
 534
 535 static const struct dcn_hubbub_shift hubbub_shift = {
 536                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 537 };
 538
 539 static const struct dcn_hubbub_mask hubbub_mask = {
 540                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 541 };
 542
 543 #define vmid_regs(id)\
 544 [id] = {\
 545                 DCN20_VMID_REG_LIST(id)\
 546 }
 547
 548 static const struct dcn_vmid_registers vmid_regs[] = {
 549         vmid_regs(0),
 550         vmid_regs(1),
 551         vmid_regs(2),
 552         vmid_regs(3),
 553         vmid_regs(4),
 554         vmid_regs(5),
 555         vmid_regs(6),
 556         vmid_regs(7),
 557         vmid_regs(8),
 558         vmid_regs(9),
 559         vmid_regs(10),
 560         vmid_regs(11),
 561         vmid_regs(12),
 562         vmid_regs(13),
 563         vmid_regs(14),
 564         vmid_regs(15)
 565 };
 566
 567 static const struct dcn20_vmid_shift vmid_shifts = {
 568                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 569 };
 570
 571 static const struct dcn20_vmid_mask vmid_masks = {
 572                 DCN20_VMID_MASK_SH_LIST(_MASK)
 573 };
 574
 575
 576 static const struct dccg_registers dccg_regs = {
 577                 DCCG_REG_LIST_DCN2()
 578 };
 579
 580 static const struct dccg_shift dccg_shift = {
 581                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 582 };
 583
 584 static const struct dccg_mask dccg_mask = {
 585                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 586 };
 587
 588 static const struct resource_caps res_cap_nv10 = {
 589                 .num_timing_generator = 6,
 590                 .num_opp = 6,
 591                 .num_video_plane = 6,
 592                 .num_audio = 7,
 593                 .num_stream_encoder = 6,
 594                 .num_pll = 6,
 595                 .num_dwb = 1,
 596                 .num_ddc = 6,
 597                 .num_vmid = 16,
 598 };
 599
 600 static const struct dc_plane_cap plane_cap = {
 601         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 602         .blends_with_above = true,
 603         .blends_with_below = true,
 604         .supports_argb8888 = true,
 605         .per_pixel_alpha = true,
 606         .supports_argb8888 = true,
 607         .supports_nv12 = true
 608 };
 609
 610 static const struct dc_debug_options debug_defaults_drv = {
 611                 .disable_dmcu = true,
 612                 .force_abm_enable = false,
 613                 .timing_trace = false,
 614                 .clock_trace = true,
 615                 .disable_pplib_clock_request = true,
 616                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 617                 .force_single_disp_pipe_split = true,
 618                 .disable_dcc = DCC_ENABLE,
 619                 .vsr_support = true,
 620                 .performance_trace = false,
 621                 .max_downscale_src_width = 5120,/*upto 5K*/
 622                 .disable_pplib_wm_range = false,
 623                 .scl_reset_length10 = true,
 624                 .sanity_checks = true,
 625                 .disable_tri_buf = true,
 626 };
 627
 628 static const struct dc_debug_options debug_defaults_diags = {
 629                 .disable_dmcu = true,
 630                 .force_abm_enable = false,
 631                 .timing_trace = true,
 632                 .clock_trace = true,
 633                 .disable_dpp_power_gate = true,
 634                 .disable_hubp_power_gate = true,
 635                 .disable_clock_gate = true,
 636                 .disable_pplib_clock_request = true,
 637                 .disable_pplib_wm_range = true,
 638                 .disable_stutter = true,
 639                 .scl_reset_length10 = true,
 640 };
 641
 642 void dcn20_dpp_destroy(struct dpp **dpp)
 643 {
 644         kfree(TO_DCN20_DPP(*dpp));
 645         *dpp = NULL;
 646 }
 647
 648 struct dpp *dcn20_dpp_create(
 649         struct dc_context *ctx,
 650         uint32_t inst)
 651 {
 652         struct dcn20_dpp *dpp =
 653                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 654
 655         if (!dpp)
 656                 return NULL;
 657
 658         if (dpp2_construct(dpp, ctx, inst,
 659                         &tf_regs[inst], &tf_shift, &tf_mask))
 660                 return &dpp->base;
 661
 662         BREAK_TO_DEBUGGER();
 663         kfree(dpp);
 664         return NULL;
 665 }
 666
 667 struct input_pixel_processor *dcn20_ipp_create(
 668         struct dc_context *ctx, uint32_t inst)
 669 {
 670         struct dcn10_ipp *ipp =
 671                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 672
 673         if (!ipp) {
 674                 BREAK_TO_DEBUGGER();
 675                 return NULL;
 676         }
 677
 678         dcn20_ipp_construct(ipp, ctx, inst,
 679                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 680         return &ipp->base;
 681 }
 682
 683
 684 struct output_pixel_processor *dcn20_opp_create(
 685         struct dc_context *ctx, uint32_t inst)
 686 {
 687         struct dcn20_opp *opp =
 688                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 689
 690         if (!opp) {
 691                 BREAK_TO_DEBUGGER();
 692                 return NULL;
 693         }
 694
 695         dcn20_opp_construct(opp, ctx, inst,
 696                         &opp_regs[inst], &opp_shift, &opp_mask);
 697         return &opp->base;
 698 }
 699
 700 struct dce_aux *dcn20_aux_engine_create(
 701         struct dc_context *ctx,
 702         uint32_t inst)
 703 {
 704         struct aux_engine_dce110 *aux_engine =
 705                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 706
 707         if (!aux_engine)
 708                 return NULL;
 709
 710         dce110_aux_engine_construct(aux_engine, ctx, inst,
 711                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 712                                     &aux_engine_regs[inst]);
 713
 714         return &aux_engine->base;
 715 }
 716 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 717
 718 static const struct dce_i2c_registers i2c_hw_regs[] = {
 719                 i2c_inst_regs(1),
 720                 i2c_inst_regs(2),
 721                 i2c_inst_regs(3),
 722                 i2c_inst_regs(4),
 723                 i2c_inst_regs(5),
 724                 i2c_inst_regs(6),
 725 };
 726
 727 static const struct dce_i2c_shift i2c_shifts = {
 728                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 729 };
 730
 731 static const struct dce_i2c_mask i2c_masks = {
 732                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 733 };
 734
 735 struct dce_i2c_hw *dcn20_i2c_hw_create(
 736         struct dc_context *ctx,
 737         uint32_t inst)
 738 {
 739         struct dce_i2c_hw *dce_i2c_hw =
 740                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 741
 742         if (!dce_i2c_hw)
 743                 return NULL;
 744
 745         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 746                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 747
 748         return dce_i2c_hw;
 749 }
 750 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
 751 {
 752         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
 753                                           GFP_KERNEL);
 754
 755         if (!mpc20)
 756                 return NULL;
 757
 758         dcn20_mpc_construct(mpc20, ctx,
 759                         &mpc_regs,
 760                         &mpc_shift,
 761                         &mpc_mask,
 762                         6);
 763
 764         return &mpc20->base;
 765 }
 766
 767 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
 768 {
 769         int i;
 770         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
 771                                           GFP_KERNEL);
 772
 773         if (!hubbub)
 774                 return NULL;
 775
 776         hubbub2_construct(hubbub, ctx,
 777                         &hubbub_reg,
 778                         &hubbub_shift,
 779                         &hubbub_mask);
 780
 781         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
 782                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
 783
 784                 vmid->ctx = ctx;
 785
 786                 vmid->regs = &vmid_regs[i];
 787                 vmid->shifts = &vmid_shifts;
 788                 vmid->masks = &vmid_masks;
 789         }
 790
 791         return &hubbub->base;
 792 }
 793
 794 struct timing_generator *dcn20_timing_generator_create(
 795                 struct dc_context *ctx,
 796                 uint32_t instance)
 797 {
 798         struct optc *tgn10 =
 799                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 800
 801         if (!tgn10)
 802                 return NULL;
 803
 804         tgn10->base.inst = instance;
 805         tgn10->base.ctx = ctx;
 806
 807         tgn10->tg_regs = &tg_regs[instance];
 808         tgn10->tg_shift = &tg_shift;
 809         tgn10->tg_mask = &tg_mask;
 810
 811         dcn20_timing_generator_init(tgn10);
 812
 813         return &tgn10->base;
 814 }
 815
 816 static const struct encoder_feature_support link_enc_feature = {
 817                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 818                 .max_hdmi_pixel_clock = 600000,
 819                 .hdmi_ycbcr420_supported = true,
 820                 .dp_ycbcr420_supported = true,
 821                 .flags.bits.IS_HBR2_CAPABLE = true,
 822                 .flags.bits.IS_HBR3_CAPABLE = true,
 823                 .flags.bits.IS_TPS3_CAPABLE = true,
 824                 .flags.bits.IS_TPS4_CAPABLE = true
 825 };
 826
 827 struct link_encoder *dcn20_link_encoder_create(
 828         const struct encoder_init_data *enc_init_data)
 829 {
 830         struct dcn20_link_encoder *enc20 =
 831                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
 832
 833         if (!enc20)
 834                 return NULL;
 835
 836         dcn20_link_encoder_construct(enc20,
 837                                       enc_init_data,
 838                                       &link_enc_feature,
 839                                       &link_enc_regs[enc_init_data->transmitter],
 840                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 841                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
 842                                       &le_shift,
 843                                       &le_mask);
 844
 845         return &enc20->enc10.base;
 846 }
 847
 848 struct clock_source *dcn20_clock_source_create(
 849         struct dc_context *ctx,
 850         struct dc_bios *bios,
 851         enum clock_source_id id,
 852         const struct dce110_clk_src_regs *regs,
 853         bool dp_clk_src)
 854 {
 855         struct dce110_clk_src *clk_src =
 856                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 857
 858         if (!clk_src)
 859                 return NULL;
 860
 861         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
 862                         regs, &cs_shift, &cs_mask)) {
 863                 clk_src->base.dp_clk_src = dp_clk_src;
 864                 return &clk_src->base;
 865         }
 866
 867         BREAK_TO_DEBUGGER();
 868         return NULL;
 869 }
 870
 871 static void read_dce_straps(
 872         struct dc_context *ctx,
 873         struct resource_straps *straps)
 874 {
 875         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 876                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 877 }
 878
 879 static struct audio *dcn20_create_audio(
 880                 struct dc_context *ctx, unsigned int inst)
 881 {
 882         return dce_audio_create(ctx, inst,
 883                         &audio_regs[inst], &audio_shift, &audio_mask);
 884 }
 885
 886 struct stream_encoder *dcn20_stream_encoder_create(
 887         enum engine_id eng_id,
 888         struct dc_context *ctx)
 889 {
 890         struct dcn10_stream_encoder *enc1 =
 891                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 892
 893         if (!enc1)
 894                 return NULL;
 895
 896         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 897                                         &stream_enc_regs[eng_id],
 898                                         &se_shift, &se_mask);
 899
 900         return &enc1->base;
 901 }
 902
 903 static const struct dce_hwseq_registers hwseq_reg = {
 904                 HWSEQ_DCN2_REG_LIST()
 905 };
 906
 907 static const struct dce_hwseq_shift hwseq_shift = {
 908                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
 909 };
 910
 911 static const struct dce_hwseq_mask hwseq_mask = {
 912                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
 913 };
 914
 915 struct dce_hwseq *dcn20_hwseq_create(
 916         struct dc_context *ctx)
 917 {
 918         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 919
 920         if (hws) {
 921                 hws->ctx = ctx;
 922                 hws->regs = &hwseq_reg;
 923                 hws->shifts = &hwseq_shift;
 924                 hws->masks = &hwseq_mask;
 925         }
 926         return hws;
 927 }
 928
 929 static const struct resource_create_funcs res_create_funcs = {
 930         .read_dce_straps = read_dce_straps,
 931         .create_audio = dcn20_create_audio,
 932         .create_stream_encoder = dcn20_stream_encoder_create,
 933         .create_hwseq = dcn20_hwseq_create,
 934 };
 935
 936 static const struct resource_create_funcs res_create_maximus_funcs = {
 937         .read_dce_straps = NULL,
 938         .create_audio = NULL,
 939         .create_stream_encoder = NULL,
 940         .create_hwseq = dcn20_hwseq_create,
 941 };
 942
 943 void dcn20_clock_source_destroy(struct clock_source **clk_src)
 944 {
 945         kfree(TO_DCE110_CLK_SRC(*clk_src));
 946         *clk_src = NULL;
 947 }
 948
 949
 950 static void destruct(struct dcn20_resource_pool *pool)
 951 {
 952         unsigned int i;
 953
 954         for (i = 0; i < pool->base.stream_enc_count; i++) {
 955                 if (pool->base.stream_enc[i] != NULL) {
 956                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 957                         pool->base.stream_enc[i] = NULL;
 958                 }
 959         }
 960
 961
 962         if (pool->base.mpc != NULL) {
 963                 kfree(TO_DCN20_MPC(pool->base.mpc));
 964                 pool->base.mpc = NULL;
 965         }
 966         if (pool->base.hubbub != NULL) {
 967                 kfree(pool->base.hubbub);
 968                 pool->base.hubbub = NULL;
 969         }
 970         for (i = 0; i < pool->base.pipe_count; i++) {
 971                 if (pool->base.dpps[i] != NULL)
 972                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 973
 974                 if (pool->base.ipps[i] != NULL)
 975                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 976
 977                 if (pool->base.hubps[i] != NULL) {
 978                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 979                         pool->base.hubps[i] = NULL;
 980                 }
 981
 982                 if (pool->base.irqs != NULL) {
 983                         dal_irq_service_destroy(&pool->base.irqs);
 984                 }
 985         }
 986
 987         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 988                 if (pool->base.engines[i] != NULL)
 989                         dce110_engine_destroy(&pool->base.engines[i]);
 990                 if (pool->base.hw_i2cs[i] != NULL) {
 991                         kfree(pool->base.hw_i2cs[i]);
 992                         pool->base.hw_i2cs[i] = NULL;
 993                 }
 994                 if (pool->base.sw_i2cs[i] != NULL) {
 995                         kfree(pool->base.sw_i2cs[i]);
 996                         pool->base.sw_i2cs[i] = NULL;
 997                 }
 998         }
 999
1000         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1001                 if (pool->base.opps[i] != NULL)
1002                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1003         }
1004
1005         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1006                 if (pool->base.timing_generators[i] != NULL)    {
1007                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1008                         pool->base.timing_generators[i] = NULL;
1009                 }
1010         }
1011
1012         for (i = 0; i < pool->base.audio_count; i++) {
1013                 if (pool->base.audios[i])
1014                         dce_aud_destroy(&pool->base.audios[i]);
1015         }
1016
1017         for (i = 0; i < pool->base.clk_src_count; i++) {
1018                 if (pool->base.clock_sources[i] != NULL) {
1019                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1020                         pool->base.clock_sources[i] = NULL;
1021                 }
1022         }
1023
1024         if (pool->base.dp_clock_source != NULL) {
1025                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1026                 pool->base.dp_clock_source = NULL;
1027         }
1028
1029
1030         if (pool->base.abm != NULL)
1031                 dce_abm_destroy(&pool->base.abm);
1032
1033         if (pool->base.dmcu != NULL)
1034                 dce_dmcu_destroy(&pool->base.dmcu);
1035
1036         if (pool->base.dccg != NULL)
1037                 dcn_dccg_destroy(&pool->base.dccg);
1038
1039         if (pool->base.pp_smu != NULL)
1040                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1041
1042 }
1043
1044 struct hubp *dcn20_hubp_create(
1045         struct dc_context *ctx,
1046         uint32_t inst)
1047 {
1048         struct dcn20_hubp *hubp2 =
1049                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1050
1051         if (!hubp2)
1052                 return NULL;
1053
1054         if (hubp2_construct(hubp2, ctx, inst,
1055                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1056                 return &hubp2->base;
1057
1058         BREAK_TO_DEBUGGER();
1059         kfree(hubp2);
1060         return NULL;
1061 }
1062
1063 static void get_pixel_clock_parameters(
1064         struct pipe_ctx *pipe_ctx,
1065         struct pixel_clk_params *pixel_clk_params)
1066 {
1067         const struct dc_stream_state *stream = pipe_ctx->stream;
1068         bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
1069
1070         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1071         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1072         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1073         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1074         /* TODO: un-hardcode*/
1075         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1076                 LINK_RATE_REF_FREQ_IN_KHZ;
1077         pixel_clk_params->flags.ENABLE_SS = 0;
1078         pixel_clk_params->color_depth =
1079                 stream->timing.display_color_depth;
1080         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1081         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1082
1083         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1084                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1085
1086         if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
1087                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1088
1089         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1090                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1091
1092 }
1093
1094 static void build_clamping_params(struct dc_stream_state *stream)
1095 {
1096         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1097         stream->clamping.c_depth = stream->timing.display_color_depth;
1098         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1099 }
1100
1101 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1102 {
1103
1104         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1105
1106         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1107                 pipe_ctx->clock_source,
1108                 &pipe_ctx->stream_res.pix_clk_params,
1109                 &pipe_ctx->pll_settings);
1110
1111         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1112
1113         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1114                                         &pipe_ctx->stream->bit_depth_params);
1115         build_clamping_params(pipe_ctx->stream);
1116
1117         return DC_OK;
1118 }
1119
1120 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1121 {
1122         enum dc_status status = DC_OK;
1123         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1124
1125         /*TODO Seems unneeded anymore */
1126         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1127                         if (stream != NULL && old_context->streams[i] != NULL) {
1128                                  todo: shouldn't have to copy missing parameter here
1129                                 resource_build_bit_depth_reduction_params(stream,
1130                                                 &stream->bit_depth_params);
1131                                 stream->clamping.pixel_encoding =
1132                                                 stream->timing.pixel_encoding;
1133
1134                                 resource_build_bit_depth_reduction_params(stream,
1135                                                                 &stream->bit_depth_params);
1136                                 build_clamping_params(stream);
1137
1138                                 continue;
1139                         }
1140                 }
1141         */
1142
1143         if (!pipe_ctx)
1144                 return DC_ERROR_UNEXPECTED;
1145
1146
1147         status = build_pipe_hw_param(pipe_ctx);
1148
1149         return status;
1150 }
1151
1152
1153 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1154 {
1155         enum dc_status result = DC_ERROR_UNEXPECTED;
1156
1157         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1158
1159         if (result == DC_OK)
1160                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1161
1162
1163         if (result == DC_OK)
1164                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1165
1166         return result;
1167 }
1168
1169
1170 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1171 {
1172         struct pipe_ctx *pipe_ctx = NULL;
1173         int i;
1174
1175         /* Remove DSC */
1176         for (i = 0; i < MAX_PIPES; i++) {
1177                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1178                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1179                         break;
1180                 }
1181         }
1182
1183         if (!pipe_ctx)
1184                 return DC_ERROR_UNEXPECTED;
1185
1186
1187         return DC_OK;
1188 }
1189
1190
1191 static void swizzle_to_dml_params(
1192                 enum swizzle_mode_values swizzle,
1193                 unsigned int *sw_mode)
1194 {
1195         switch (swizzle) {
1196         case DC_SW_LINEAR:
1197                 *sw_mode = dm_sw_linear;
1198                 break;
1199         case DC_SW_4KB_S:
1200                 *sw_mode = dm_sw_4kb_s;
1201                 break;
1202         case DC_SW_4KB_S_X:
1203                 *sw_mode = dm_sw_4kb_s_x;
1204                 break;
1205         case DC_SW_4KB_D:
1206                 *sw_mode = dm_sw_4kb_d;
1207                 break;
1208         case DC_SW_4KB_D_X:
1209                 *sw_mode = dm_sw_4kb_d_x;
1210                 break;
1211         case DC_SW_64KB_S:
1212                 *sw_mode = dm_sw_64kb_s;
1213                 break;
1214         case DC_SW_64KB_S_X:
1215                 *sw_mode = dm_sw_64kb_s_x;
1216                 break;
1217         case DC_SW_64KB_S_T:
1218                 *sw_mode = dm_sw_64kb_s_t;
1219                 break;
1220         case DC_SW_64KB_D:
1221                 *sw_mode = dm_sw_64kb_d;
1222                 break;
1223         case DC_SW_64KB_D_X:
1224                 *sw_mode = dm_sw_64kb_d_x;
1225                 break;
1226         case DC_SW_64KB_D_T:
1227                 *sw_mode = dm_sw_64kb_d_t;
1228                 break;
1229         case DC_SW_64KB_R_X:
1230                 *sw_mode = dm_sw_64kb_r_x;
1231                 break;
1232         case DC_SW_VAR_S:
1233                 *sw_mode = dm_sw_var_s;
1234                 break;
1235         case DC_SW_VAR_S_X:
1236                 *sw_mode = dm_sw_var_s_x;
1237                 break;
1238         case DC_SW_VAR_D:
1239                 *sw_mode = dm_sw_var_d;
1240                 break;
1241         case DC_SW_VAR_D_X:
1242                 *sw_mode = dm_sw_var_d_x;
1243                 break;
1244
1245         default:
1246                 ASSERT(0); /* Not supported */
1247                 break;
1248         }
1249 }
1250
1251 static bool dcn20_split_stream_for_combine(
1252                 struct resource_context *res_ctx,
1253                 const struct resource_pool *pool,
1254                 struct pipe_ctx *primary_pipe,
1255                 struct pipe_ctx *secondary_pipe,
1256                 bool is_odm_combine)
1257 {
1258         int pipe_idx = secondary_pipe->pipe_idx;
1259         struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
1260         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1261         int new_width;
1262
1263         *secondary_pipe = *primary_pipe;
1264         secondary_pipe->bottom_pipe = sec_bot_pipe;
1265
1266         secondary_pipe->pipe_idx = pipe_idx;
1267         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1268         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1269         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1270         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1271         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1272         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1273         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1274                 ASSERT(!secondary_pipe->bottom_pipe);
1275                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1276                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1277         }
1278         primary_pipe->bottom_pipe = secondary_pipe;
1279         secondary_pipe->top_pipe = primary_pipe;
1280
1281         if (is_odm_combine) {
1282                 bool is_add_dsc = true;
1283
1284                 if (primary_pipe->plane_state) {
1285                         /* HACTIVE halved for odm combine */
1286                         sd->h_active /= 2;
1287                         /* Copy scl_data to secondary pipe */
1288                         secondary_pipe->plane_res.scl_data = *sd;
1289
1290                         /* Calculate new vp and recout for left pipe */
1291                         /* Need at least 16 pixels width per side */
1292                         if (sd->recout.x + 16 >= sd->h_active)
1293                                 return false;
1294                         new_width = sd->h_active - sd->recout.x;
1295                         sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1296                                         sd->ratios.horz, sd->recout.width - new_width));
1297                         sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1298                                         sd->ratios.horz_c, sd->recout.width - new_width));
1299                         sd->recout.width = new_width;
1300
1301                         /* Calculate new vp and recout for right pipe */
1302                         sd = &secondary_pipe->plane_res.scl_data;
1303                         new_width = sd->recout.width + sd->recout.x - sd->h_active;
1304                         /* Need at least 16 pixels width per side */
1305                         if (new_width <= 16)
1306                                 return false;
1307                         sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1308                                         sd->ratios.horz, sd->recout.width - new_width));
1309                         sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1310                                         sd->ratios.horz_c, sd->recout.width - new_width));
1311                         sd->recout.width = new_width;
1312                         sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1313                                         sd->ratios.horz, sd->h_active - sd->recout.x));
1314                         sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1315                                         sd->ratios.horz_c, sd->h_active - sd->recout.x));
1316                         sd->recout.x = 0;
1317                 }
1318                 secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
1319         } else {
1320                 ASSERT(primary_pipe->plane_state);
1321                 resource_build_scaling_params(primary_pipe);
1322                 resource_build_scaling_params(secondary_pipe);
1323         }
1324
1325         return true;
1326 }
1327
1328 void dcn20_populate_dml_writeback_from_context(
1329                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1330 {
1331         int pipe_cnt, i;
1332
1333         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1334                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1335
1336                 if (!res_ctx->pipe_ctx[i].stream)
1337                         continue;
1338
1339                 /* Set writeback information */
1340                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1341                 pipes[pipe_cnt].dout.num_active_wb++;
1342                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1343                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1344                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1345                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1346                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1347                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1348                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1349                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1350                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1351                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1352                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1353                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1354                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1355                         else
1356                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1357                 } else
1358                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1359
1360                 pipe_cnt++;
1361         }
1362
1363 }
1364
1365 int dcn20_populate_dml_pipes_from_context(
1366                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1367 {
1368         int pipe_cnt, i;
1369         bool synchronized_vblank = true;
1370
1371         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1372                 if (!res_ctx->pipe_ctx[i].stream)
1373                         continue;
1374
1375                 if (pipe_cnt < 0) {
1376                         pipe_cnt = i;
1377                         continue;
1378                 }
1379                 if (!resource_are_streams_timing_synchronizable(
1380                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1381                                 res_ctx->pipe_ctx[i].stream)) {
1382                         synchronized_vblank = false;
1383                         break;
1384                 }
1385         }
1386
1387         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1388                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1389                 struct dc_link *link;
1390
1391                 if (!res_ctx->pipe_ctx[i].stream)
1392                         continue;
1393                 /* todo:
1394                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1395                 pipes[pipe_cnt].pipe.src.dcc = 0;
1396                 pipes[pipe_cnt].pipe.src.vm = 0;*/
1397
1398                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1399                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1400                         /* 1/2 vblank */
1401                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1402                                 (timing->v_total - timing->v_addressable
1403                                         - timing->v_border_top - timing->v_border_bottom) / 2;
1404                         /* 36 bytes dp, 32 hdmi */
1405                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1406                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1407                 }
1408                 pipes[pipe_cnt].pipe.src.dcc = false;
1409                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1410                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1411                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1412                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1413                                 - timing->h_addressable
1414                                 - timing->h_border_left
1415                                 - timing->h_border_right;
1416                 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1417                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1418                                 - timing->v_addressable
1419                                 - timing->v_border_top
1420                                 - timing->v_border_bottom;
1421                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1422                 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1423                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1424                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1425                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1426                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1427                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1428                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1429                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1430
1431                 link = res_ctx->pipe_ctx[i].stream->link;
1432                 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) {
1433                         pipes[pipe_cnt].dout.dp_lanes = link->cur_link_settings.lane_count;
1434                 } else if (link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) {
1435                         pipes[pipe_cnt].dout.dp_lanes = link->verified_link_cap.lane_count;
1436                 } else {
1437                         /* Unknown link capabilities, so assume max */
1438                         pipes[pipe_cnt].dout.dp_lanes = 4;
1439                 }
1440
1441                 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth;
1442                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1443                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1444                 case SIGNAL_TYPE_DISPLAY_PORT:
1445                         pipes[pipe_cnt].dout.output_type = dm_dp;
1446                         break;
1447                 case SIGNAL_TYPE_EDP:
1448                         pipes[pipe_cnt].dout.output_type = dm_edp;
1449                         break;
1450                 case SIGNAL_TYPE_HDMI_TYPE_A:
1451                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1452                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1453                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1454                         break;
1455                 default:
1456                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1457                         pipes[pipe_cnt].dout.output_type = dm_dp;
1458                         pipes[pipe_cnt].dout.dp_lanes = 4;
1459                 }
1460                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1461                 case PIXEL_ENCODING_RGB:
1462                 case PIXEL_ENCODING_YCBCR444:
1463                         pipes[pipe_cnt].dout.output_format = dm_444;
1464                         break;
1465                 case PIXEL_ENCODING_YCBCR420:
1466                         pipes[pipe_cnt].dout.output_format = dm_420;
1467                         break;
1468                 case PIXEL_ENCODING_YCBCR422:
1469                         if (true) /* todo */
1470                                 pipes[pipe_cnt].dout.output_format = dm_s422;
1471                         else
1472                                 pipes[pipe_cnt].dout.output_format = dm_n422;
1473                         break;
1474                 default:
1475                         pipes[pipe_cnt].dout.output_format = dm_444;
1476                 }
1477                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1478                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1479                                 == res_ctx->pipe_ctx[i].plane_state)
1480                         pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1481
1482                 /* todo: default max for now, until there is logic reflecting this in dc*/
1483                 pipes[pipe_cnt].dout.output_bpc = 12;
1484                 /*
1485                  * Use max cursor settings for calculations to minimize
1486                  * bw calculations due to cursor on/off
1487                  */
1488                 pipes[pipe_cnt].pipe.src.num_cursors = 2;
1489                 pipes[pipe_cnt].pipe.src.cur0_src_width = 128;
1490                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_64bit;
1491                 pipes[pipe_cnt].pipe.src.cur1_src_width = 128;
1492                 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_64bit;
1493
1494                 if (!res_ctx->pipe_ctx[i].plane_state) {
1495                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
1496                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
1497                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
1498                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
1499                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
1500                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
1501                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
1502                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
1503                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
1504                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
1505                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1506                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
1507                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
1508                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
1509                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
1510                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
1511                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
1512                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
1513                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
1514                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
1515                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
1516                         pipes[pipe_cnt].pipe.src.is_hsplit = 0;
1517                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1518                 } else {
1519                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
1520                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
1521
1522                         pipes[pipe_cnt].pipe.src.macro_tile_size =
1523                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
1524                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
1525                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
1526                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
1527                                         || (res_ctx->pipe_ctx[i].top_pipe
1528                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
1529                         pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
1530                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
1531                                         && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
1532                                                 != res_ctx->pipe_ctx[i].stream_res.opp)
1533                                 || (res_ctx->pipe_ctx[i].top_pipe
1534                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
1535                                         && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
1536                                                 != res_ctx->pipe_ctx[i].stream_res.opp);
1537                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
1538                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
1539                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
1540                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
1541                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
1542                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
1543                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
1544                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
1545                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1546                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
1547                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
1548                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
1549                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
1550                         } else {
1551                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
1552                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
1553                         }
1554                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
1555                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
1556                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
1557                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
1558                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
1559                         if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
1560                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1561                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
1562                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1563                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
1564                         } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
1565                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
1566                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
1567                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
1568                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
1569                         }
1570
1571                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_10;
1572                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
1573                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
1574                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
1575                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
1576                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
1577                                         scl->ratios.vert.value != dc_fixpt_one.value
1578                                         || scl->ratios.horz.value != dc_fixpt_one.value
1579                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
1580                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
1581                                         || dc->debug.always_scale; /*support always scale*/
1582                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
1583                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
1584                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
1585                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
1586
1587                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
1588                                         &pipes[pipe_cnt].pipe.src.sw_mode);
1589
1590                         switch (pln->format) {
1591                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1592                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1593                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
1594                                 break;
1595                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1596                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1597                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
1598                                 break;
1599                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1600                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1601                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1602                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
1603                                 break;
1604                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1605                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1606                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
1607                                 break;
1608                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
1609                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
1610                                 break;
1611                         default:
1612                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
1613                                 break;
1614                         }
1615                 }
1616
1617                 pipe_cnt++;
1618         }
1619
1620         /* populate writeback information */
1621         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
1622
1623         return pipe_cnt;
1624 }
1625
1626 unsigned int dcn20_calc_max_scaled_time(
1627                 unsigned int time_per_pixel,
1628                 enum mmhubbub_wbif_mode mode,
1629                 unsigned int urgent_watermark)
1630 {
1631         unsigned int time_per_byte = 0;
1632         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1633         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1634         unsigned int small_free_entry, max_free_entry;
1635         unsigned int buf_lh_capability;
1636         unsigned int max_scaled_time;
1637
1638         if (mode == PACKED_444) /* packed mode */
1639                 time_per_byte = time_per_pixel/4;
1640         else if (mode == PLANAR_420_8BPC)
1641                 time_per_byte  = time_per_pixel;
1642         else if (mode == PLANAR_420_10BPC) /* p010 */
1643                 time_per_byte  = time_per_pixel * 819/1024;
1644
1645         if (time_per_byte == 0)
1646                 time_per_byte = 1;
1647
1648         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1649         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1650         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1651         max_scaled_time   = buf_lh_capability - urgent_watermark;
1652         return max_scaled_time;
1653 }
1654
1655 void dcn20_set_mcif_arb_params(
1656                 struct dc *dc,
1657                 struct dc_state *context,
1658                 display_e2e_pipe_params_st *pipes,
1659                 int pipe_cnt)
1660 {
1661         enum mmhubbub_wbif_mode wbif_mode;
1662         struct mcif_arb_params *wb_arb_params;
1663         int i, j, k, dwb_pipe;
1664
1665         /* Writeback MCIF_WB arbitration parameters */
1666         dwb_pipe = 0;
1667         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1668
1669                 if (!context->res_ctx.pipe_ctx[i].stream)
1670                         continue;
1671
1672                 for (j = 0; j < MAX_DWB_PIPES; j++) {
1673                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1674                                 continue;
1675
1676                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1677                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1678
1679                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1680                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1681                                         wbif_mode = PLANAR_420_8BPC;
1682                                 else
1683                                         wbif_mode = PLANAR_420_10BPC;
1684                         } else
1685                                 wbif_mode = PACKED_444;
1686
1687                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1688                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1689                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1690                         }
1691                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
1692                         wb_arb_params->slice_lines = 32;
1693                         wb_arb_params->arbitration_slice = 2;
1694                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1695                                 wbif_mode,
1696                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1697
1698                         dwb_pipe++;
1699
1700                         if (dwb_pipe >= MAX_DWB_PIPES)
1701                                 return;
1702                 }
1703                 if (dwb_pipe >= MAX_DWB_PIPES)
1704                         return;
1705         }
1706 }
1707
1708 bool dcn20_validate_bandwidth(struct dc *dc,
1709                               struct dc_state *context,
1710                               bool fast_validate)
1711 {
1712         int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
1713         int pipe_split_from[MAX_PIPES];
1714         bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
1715         bool force_split = false;
1716         int split_threshold = dc->res_pool->pipe_count / 2;
1717         bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
1718         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1719
1720         ASSERT(pipes);
1721         if (!pipes)
1722                 return false;
1723
1724         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1725                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1726                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1727
1728                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
1729                         continue;
1730
1731                 /* merge previously split pipe since mode support needs to make the decision */
1732                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1733                 if (hsplit_pipe->bottom_pipe)
1734                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
1735                 hsplit_pipe->plane_state = NULL;
1736                 hsplit_pipe->stream = NULL;
1737                 hsplit_pipe->top_pipe = NULL;
1738                 hsplit_pipe->bottom_pipe = NULL;
1739                 /* Clear plane_res and stream_res */
1740                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1741                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1742                 if (pipe->plane_state)
1743                         resource_build_scaling_params(pipe);
1744         }
1745
1746         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
1747         if (!pipe_cnt)
1748                 goto validate_pass;
1749
1750         context->bw_ctx.dml.ip.odm_capable = 0;
1751         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1752         context->bw_ctx.dml.ip.odm_capable = odm_capable;
1753
1754         if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
1755                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1756
1757         if (vlevel > context->bw_ctx.dml.soc.num_states)
1758                 goto validate_fail;
1759
1760         if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
1761                 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
1762                 context->commit_hints.full_update_needed = true;
1763
1764         /*initialize pipe_just_split_from to invalid idx*/
1765         for (i = 0; i < MAX_PIPES; i++)
1766                 pipe_split_from[i] = -1;
1767
1768         /* Single display only conditionals get set here */
1769         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1770                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1771                 bool exit_loop = false;
1772
1773                 if (!pipe->stream || pipe->top_pipe)
1774                         continue;
1775
1776                 if (dc->debug.force_single_disp_pipe_split) {
1777                         if (!force_split)
1778                                 force_split = true;
1779                         else {
1780                                 force_split = false;
1781                                 exit_loop = true;
1782                         }
1783                 }
1784                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
1785                         if (avoid_split)
1786                                 avoid_split = false;
1787                         else {
1788                                 avoid_split = true;
1789                                 exit_loop = true;
1790                         }
1791                 }
1792                 if (exit_loop)
1793                         break;
1794         }
1795
1796         if (context->stream_count > split_threshold)
1797                 avoid_split = true;
1798
1799         vlevel_unsplit = vlevel;
1800         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1801                 if (!context->res_ctx.pipe_ctx[i].stream)
1802                         continue;
1803                 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
1804                         if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
1805                                 break;
1806                 pipe_idx++;
1807         }
1808
1809         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1810                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1811                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1812                 bool need_split = true;
1813                 bool need_split3d;
1814
1815                 if (!pipe->stream || pipe_split_from[i] >= 0)
1816                         continue;
1817
1818                 pipe_idx++;
1819
1820                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1821                         force_split = true;
1822                         context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
1823                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
1824                 }
1825                 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
1826                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
1827
1828                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1829                         hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
1830                         ASSERT(hsplit_pipe);
1831                         if (!dcn20_split_stream_for_combine(
1832                                         &context->res_ctx, dc->res_pool,
1833                                         pipe, hsplit_pipe,
1834                                         true))
1835                                 goto validate_fail;
1836                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1837                         dcn20_build_mapped_resource(dc, context, pipe->stream);
1838                 }
1839
1840                 if (!pipe->plane_state)
1841                         continue;
1842                 /* Skip 2nd half of already split pipe */
1843                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
1844                         continue;
1845
1846                 need_split3d = ((pipe->stream->view_format ==
1847                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1848                                 pipe->stream->view_format ==
1849                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1850                                 (pipe->stream->timing.timing_3d_format ==
1851                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1852                                  pipe->stream->timing.timing_3d_format ==
1853                                 TIMING_3D_FORMAT_SIDE_BY_SIDE));
1854
1855                 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
1856                         need_split = false;
1857                         vlevel = vlevel_unsplit;
1858                         context->bw_ctx.dml.vba.maxMpcComb = 0;
1859                 } else
1860                         need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1861
1862                 if (need_split3d || need_split || force_split) {
1863                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
1864                                 /* pipe not split previously needs split */
1865                                 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
1866                                 ASSERT(hsplit_pipe || force_split);
1867                                 if (!hsplit_pipe)
1868                                         continue;
1869
1870                                 if (!dcn20_split_stream_for_combine(
1871                                                 &context->res_ctx, dc->res_pool,
1872                                                 pipe, hsplit_pipe,
1873                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
1874                                         goto validate_fail;
1875                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1876                         }
1877                 } else if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state) {
1878                         /* We do not support mpo + odm at the moment */
1879                         if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
1880                                 goto validate_fail;
1881                 } else if (hsplit_pipe) {
1882                         /* merge should already have been done */
1883                         ASSERT(0);
1884                 }
1885         }
1886
1887         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1888                 if (!context->res_ctx.pipe_ctx[i].stream)
1889                         continue;
1890
1891                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1892                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1893
1894                 if (pipe_split_from[i] < 0) {
1895                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1896                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1897                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1898                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1899                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
1900                         else
1901                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1902                         pipe_idx++;
1903                 } else {
1904                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1905                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1906                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1907                                 pipes[pipe_cnt].pipe.dest.odm_combine =
1908                                                 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
1909                         else
1910                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1911                 }
1912                 pipe_cnt++;
1913         }
1914
1915         if (pipe_cnt != pipe_idx)
1916                 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
1917
1918         /* only pipe 0 is read for voltage and dcf/soc clocks */
1919         if (vlevel < 1) {
1920                 pipes[0].clks_cfg.voltage = 1;
1921                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
1922                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
1923         }
1924         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1925         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1926         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1927         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1928         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1929
1930         if (vlevel < 2) {
1931                 pipes[0].clks_cfg.voltage = 2;
1932                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1933                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1934         }
1935         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1936         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1937         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1938         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1939         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1940
1941         if (vlevel < 3) {
1942                 pipes[0].clks_cfg.voltage = 3;
1943                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
1944                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
1945         }
1946         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1947         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1948         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1949         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1950         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1951
1952         pipes[0].clks_cfg.voltage = vlevel;
1953         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1954         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1955         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1956         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1957         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1958         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1959         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1960         /* Writeback MCIF_WB arbitration parameters */
1961         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1962
1963         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1964         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1965         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1966         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000;
1967         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1968         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1969         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1970                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1971                                                         != dm_dram_clock_change_unsupported;
1972         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1973
1974         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1975                 if (!context->res_ctx.pipe_ctx[i].stream)
1976                         continue;
1977                 pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
1978                 pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
1979                 pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
1980                 pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
1981                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1982                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1983                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1984                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1985                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1986                 pipe_idx++;
1987         }
1988
1989         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1990                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1991
1992                 if (!context->res_ctx.pipe_ctx[i].stream)
1993                         continue;
1994
1995                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
1996                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
1997                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
1998                                 pipes,
1999                                 pipe_cnt,
2000                                 pipe_idx,
2001                                 cstate_en,
2002                                 context->bw_ctx.bw.dcn.clk.p_state_change_support);
2003                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2004                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2005                                 pipes[pipe_idx].pipe);
2006                 pipe_idx++;
2007         }
2008
2009 validate_pass:
2010         kfree(pipes);
2011         return true;
2012
2013 validate_fail:
2014         kfree(pipes);
2015         return false;
2016 }
2017
2018 enum dc_status dcn20_validate_global(struct dc *dc,     struct dc_state *new_ctx)
2019 {
2020         enum dc_status result = DC_OK;
2021         int i, j;
2022
2023         /* Validate DSC */
2024         for (i = 0; i < new_ctx->stream_count; i++) {
2025                 struct dc_stream_state *stream = new_ctx->streams[i];
2026
2027                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2028                         struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2029
2030                         if (pipe_ctx->stream != stream)
2031                                 continue;
2032
2033                 }
2034         }
2035
2036         return result;
2037 }
2038
2039 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2040                 struct dc_state *state,
2041                 const struct resource_pool *pool,
2042                 struct dc_stream_state *stream)
2043 {
2044         struct resource_context *res_ctx = &state->res_ctx;
2045         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2046         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2047
2048         if (!head_pipe)
2049                 ASSERT(0);
2050
2051         if (!idle_pipe)
2052                 return false;
2053
2054         idle_pipe->stream = head_pipe->stream;
2055         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2056         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2057
2058         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2059         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2060         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2061         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2062
2063         return idle_pipe;
2064 }
2065
2066 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2067                 const struct dc_dcc_surface_param *input,
2068                 struct dc_surface_dcc_cap *output)
2069 {
2070         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2071                         dc->res_pool->hubbub,
2072                         input,
2073                         output);
2074 }
2075
2076 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2077 {
2078         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2079
2080         destruct(dcn20_pool);
2081         kfree(dcn20_pool);
2082         *pool = NULL;
2083 }
2084
2085
2086 static struct dc_cap_funcs cap_funcs = {
2087         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2088 };
2089
2090
2091 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2092 {
2093         enum dc_status result = DC_OK;
2094
2095         enum surface_pixel_format surf_pix_format = plane_state->format;
2096         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2097
2098         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2099
2100         if (bpp == 64)
2101                 swizzle = DC_SW_64KB_D;
2102         else
2103                 swizzle = DC_SW_64KB_S;
2104
2105         plane_state->tiling_info.gfx9.swizzle = swizzle;
2106         return result;
2107 }
2108
2109 static struct resource_funcs dcn20_res_pool_funcs = {
2110         .destroy = dcn20_destroy_resource_pool,
2111         .link_enc_create = dcn20_link_encoder_create,
2112         .validate_bandwidth = dcn20_validate_bandwidth,
2113         .validate_global = dcn20_validate_global,
2114         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2115         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
2116         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2117         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2118         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
2119         .set_mcif_arb_params = dcn20_set_mcif_arb_params
2120 };
2121
2122 struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2123 {
2124         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
2125
2126         if (!pp_smu)
2127                 return pp_smu;
2128
2129         dm_pp_get_funcs(ctx, pp_smu);
2130
2131         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2132                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2133
2134         return pp_smu;
2135 }
2136
2137 void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2138 {
2139         if (pp_smu && *pp_smu) {
2140                 kfree(*pp_smu);
2141                 *pp_smu = NULL;
2142         }
2143 }
2144
2145 static void cap_soc_clocks(
2146                 struct _vcs_dpi_soc_bounding_box_st *bb,
2147                 struct pp_smu_nv_clock_table max_clocks)
2148 {
2149         int i;
2150
2151         // First pass - cap all clocks higher than the reported max
2152         for (i = 0; i < bb->num_states; i++) {
2153                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
2154                                 && max_clocks.dcfClockInKhz != 0)
2155                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
2156
2157                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
2158                                                 && max_clocks.uClockInKhz != 0)
2159                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
2160
2161                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
2162                                                 && max_clocks.fabricClockInKhz != 0)
2163                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
2164
2165                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
2166                                                 && max_clocks.displayClockInKhz != 0)
2167                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
2168
2169                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
2170                                                 && max_clocks.dppClockInKhz != 0)
2171                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
2172
2173                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
2174                                                 && max_clocks.phyClockInKhz != 0)
2175                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
2176
2177                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
2178                                                 && max_clocks.socClockInKhz != 0)
2179                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
2180
2181                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
2182                                                 && max_clocks.dscClockInKhz != 0)
2183                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
2184         }
2185
2186         // Second pass - remove all duplicate clock states
2187         for (i = bb->num_states - 1; i > 1; i--) {
2188                 bool duplicate = true;
2189
2190                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
2191                         duplicate = false;
2192                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
2193                         duplicate = false;
2194                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
2195                         duplicate = false;
2196                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
2197                         duplicate = false;
2198                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
2199                         duplicate = false;
2200                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
2201                         duplicate = false;
2202                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
2203                         duplicate = false;
2204                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
2205                         duplicate = false;
2206
2207                 if (duplicate)
2208                         bb->num_states--;
2209         }
2210 }
2211
2212 static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
2213                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
2214 {
2215         struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
2216         int i, j;
2217         int num_calculated_states = 0;
2218
2219         if (num_states == 0)
2220                 return;
2221
2222         for (i = 0; i < num_states; i++) {
2223                 // Find lowest pre-silicon DPM that has equal or higher uCLK
2224                 for (j = 0; j < bb->num_states; j++) {
2225                         if (bb->clock_limits[j].dram_speed_mts * 1000 / 16 >= uclk_states[i])
2226                                 break;
2227                 }
2228
2229                 // If for some reason the available uCLK is higher than all pre-silicon'
2230                 // DPM targets, then we just use the highest one
2231                 if (j >= bb->num_states)
2232                         j = bb->num_states;
2233
2234                 // Copy that state
2235                 memcpy(&calculated_states[num_calculated_states], &bb->clock_limits[j],
2236                                 sizeof(calculated_states[num_calculated_states]));
2237
2238                 // Cap uClk to actual
2239                 calculated_states[num_calculated_states].dram_speed_mts = uclk_states[i] * 16 / 1000;
2240                 // Phy clock can be set to max for all states, since there's nothing to optimize
2241                 // for spreadsheet and we request voltage for phy clock by frequency anyway
2242                 calculated_states[num_calculated_states].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
2243
2244                 calculated_states[num_calculated_states].state = num_calculated_states;
2245
2246                 num_calculated_states++;
2247         }
2248
2249         if (max_clocks->dcfClockInKhz > 0)
2250                 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
2251
2252         if (max_clocks->displayClockInKhz > 0) {
2253                 calculated_states[num_calculated_states - 1].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
2254                 calculated_states[num_calculated_states - 1].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
2255                 // DSC always runs at 1/3 of disp clock
2256                 calculated_states[num_calculated_states - 1].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
2257         }
2258
2259         if (max_clocks->socClockInKhz > 0)
2260                 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
2261
2262         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
2263         bb->num_states = num_calculated_states;
2264 }
2265
2266 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
2267 {
2268         kernel_fpu_begin();
2269         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2270                         && dc->bb_overrides.sr_exit_time_ns) {
2271                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2272         }
2273
2274         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
2275                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
2276                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2277                 bb->sr_enter_plus_exit_time_us =
2278                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2279         }
2280
2281         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2282                         && dc->bb_overrides.urgent_latency_ns) {
2283                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2284         }
2285
2286         if ((int)(bb->dram_clock_change_latency_us * 1000)
2287                                 != dc->bb_overrides.dram_clock_change_latency_ns
2288                         && dc->bb_overrides.dram_clock_change_latency_ns) {
2289                 bb->dram_clock_change_latency_us =
2290                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2291         }
2292         kernel_fpu_end();
2293 }
2294
2295 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
2296 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
2297
2298 static bool init_soc_bounding_box(struct dc *dc,
2299                                   struct dcn20_resource_pool *pool)
2300 {
2301         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
2302         DC_LOGGER_INIT(dc->ctx->logger);
2303
2304         if (!bb && !SOC_BOUNDING_BOX_VALID) {
2305                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
2306                 return false;
2307         }
2308
2309         if (bb && !SOC_BOUNDING_BOX_VALID) {
2310                 int i;
2311
2312                 dcn2_0_soc.sr_exit_time_us =
2313                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
2314                 dcn2_0_soc.sr_enter_plus_exit_time_us =
2315                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
2316                 dcn2_0_soc.urgent_latency_us =
2317                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
2318                 dcn2_0_soc.urgent_latency_pixel_data_only_us =
2319                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
2320                 dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
2321                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
2322                 dcn2_0_soc.urgent_latency_vm_data_only_us =
2323                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
2324                 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
2325                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
2326                 dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
2327                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
2328                 dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
2329                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
2330                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
2331                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
2332                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
2333                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
2334                 dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
2335                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
2336                 dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
2337                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
2338                 dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
2339                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
2340                 dcn2_0_soc.writeback_latency_us =
2341                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
2342                 dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
2343                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
2344                 dcn2_0_soc.max_request_size_bytes =
2345                                 le32_to_cpu(bb->max_request_size_bytes);
2346                 dcn2_0_soc.dram_channel_width_bytes =
2347                                 le32_to_cpu(bb->dram_channel_width_bytes);
2348                 dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
2349                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
2350                 dcn2_0_soc.dcn_downspread_percent =
2351                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
2352                 dcn2_0_soc.downspread_percent =
2353                                 fixed16_to_double_to_cpu(bb->downspread_percent);
2354                 dcn2_0_soc.dram_page_open_time_ns =
2355                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
2356                 dcn2_0_soc.dram_rw_turnaround_time_ns =
2357                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
2358                 dcn2_0_soc.dram_return_buffer_per_channel_bytes =
2359                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
2360                 dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
2361                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
2362                 dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
2363                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
2364                 dcn2_0_soc.channel_interleave_bytes =
2365                                 le32_to_cpu(bb->channel_interleave_bytes);
2366                 dcn2_0_soc.num_banks =
2367                                 le32_to_cpu(bb->num_banks);
2368                 dcn2_0_soc.num_chans =
2369                                 le32_to_cpu(bb->num_chans);
2370                 dcn2_0_soc.vmm_page_size_bytes =
2371                                 le32_to_cpu(bb->vmm_page_size_bytes);
2372                 dcn2_0_soc.dram_clock_change_latency_us =
2373                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
2374                 dcn2_0_soc.writeback_dram_clock_change_latency_us =
2375                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
2376                 dcn2_0_soc.return_bus_width_bytes =
2377                                 le32_to_cpu(bb->return_bus_width_bytes);
2378                 dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
2379                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
2380                 dcn2_0_soc.xfc_bus_transport_time_us =
2381                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
2382                 dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
2383                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
2384                 dcn2_0_soc.use_urgent_burst_bw =
2385                                 le32_to_cpu(bb->use_urgent_burst_bw);
2386                 dcn2_0_soc.num_states =
2387                                 le32_to_cpu(bb->num_states);
2388
2389                 for (i = 0; i < dcn2_0_soc.num_states; i++) {
2390                         dcn2_0_soc.clock_limits[i].state =
2391                                         le32_to_cpu(bb->clock_limits[i].state);
2392                         dcn2_0_soc.clock_limits[i].dcfclk_mhz =
2393                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
2394                         dcn2_0_soc.clock_limits[i].fabricclk_mhz =
2395                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
2396                         dcn2_0_soc.clock_limits[i].dispclk_mhz =
2397                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
2398                         dcn2_0_soc.clock_limits[i].dppclk_mhz =
2399                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
2400                         dcn2_0_soc.clock_limits[i].phyclk_mhz =
2401                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
2402                         dcn2_0_soc.clock_limits[i].socclk_mhz =
2403                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
2404                         dcn2_0_soc.clock_limits[i].dscclk_mhz =
2405                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
2406                         dcn2_0_soc.clock_limits[i].dram_speed_mts =
2407                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
2408                 }
2409         }
2410
2411         if (pool->base.pp_smu) {
2412                 struct pp_smu_nv_clock_table max_clocks = {0};
2413                 unsigned int uclk_states[8] = {0};
2414                 unsigned int num_states = 0;
2415                 enum pp_smu_status status;
2416                 bool clock_limits_available = false;
2417                 bool uclk_states_available = false;
2418
2419                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2420                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2421                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2422
2423                         uclk_states_available = (status == PP_SMU_RESULT_OK);
2424                 }
2425
2426                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2427                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2428                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2429
2430                         clock_limits_available = (status == PP_SMU_RESULT_OK);
2431                 }
2432
2433                 if (clock_limits_available && uclk_states_available)
2434                         update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
2435                 else if (clock_limits_available)
2436                         cap_soc_clocks(&dcn2_0_soc, max_clocks);
2437         }
2438
2439         dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
2440         dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
2441         patch_bounding_box(dc, &dcn2_0_soc);
2442
2443         return true;
2444 }
2445
2446 static bool construct(
2447         uint8_t num_virtual_links,
2448         struct dc *dc,
2449         struct dcn20_resource_pool *pool)
2450 {
2451         int i;
2452         struct dc_context *ctx = dc->ctx;
2453         struct irq_service_init_data init_data;
2454
2455         ctx->dc_bios->regs = &bios_regs;
2456
2457         pool->base.res_cap = &res_cap_nv10;
2458         pool->base.funcs = &dcn20_res_pool_funcs;
2459
2460         /*************************************************
2461          *  Resource + asic cap harcoding                *
2462          *************************************************/
2463         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2464
2465         pool->base.pipe_count = 6;
2466         pool->base.mpcc_count = 6;
2467         dc->caps.max_downscale_ratio = 200;
2468         dc->caps.i2c_speed_in_khz = 100;
2469         dc->caps.max_cursor_size = 256;
2470         dc->caps.dmdata_alloc_size = 2048;
2471
2472         dc->caps.max_slave_planes = 1;
2473         dc->caps.post_blend_color_processing = true;
2474         dc->caps.force_dp_tps4_for_cp2520 = true;
2475         dc->caps.hw_3d_lut = true;
2476
2477         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2478                 dc->debug = debug_defaults_drv;
2479         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2480                         pool->base.pipe_count = 4;
2481
2482                 pool->base.mpcc_count = pool->base.pipe_count;
2483                 dc->debug = debug_defaults_diags;
2484         } else
2485                 dc->debug = debug_defaults_diags;
2486         //dcn2.0x
2487         dc->work_arounds.dedcn20_305_wa = true;
2488
2489         // Init the vm_helper
2490         if (dc->vm_helper)
2491                 init_vm_helper(dc->vm_helper, 16, pool->base.pipe_count);
2492
2493         /*************************************************
2494          *  Create resources                             *
2495          *************************************************/
2496
2497         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2498                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2499                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2500                                 &clk_src_regs[0], false);
2501         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2502                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2503                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2504                                 &clk_src_regs[1], false);
2505         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2506                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2507                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2508                                 &clk_src_regs[2], false);
2509         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2510                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2511                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2512                                 &clk_src_regs[3], false);
2513         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2514                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2515                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2516                                 &clk_src_regs[4], false);
2517         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2518                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2519                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
2520                                 &clk_src_regs[5], false);
2521         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2522         /* todo: not reuse phy_pll registers */
2523         pool->base.dp_clock_source =
2524                         dcn20_clock_source_create(ctx, ctx->dc_bios,
2525                                 CLOCK_SOURCE_ID_DP_DTO,
2526                                 &clk_src_regs[0], true);
2527
2528         for (i = 0; i < pool->base.clk_src_count; i++) {
2529                 if (pool->base.clock_sources[i] == NULL) {
2530                         dm_error("DC: failed to create clock sources!\n");
2531                         BREAK_TO_DEBUGGER();
2532                         goto create_fail;
2533                 }
2534         }
2535
2536         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2537         if (pool->base.dccg == NULL) {
2538                 dm_error("DC: failed to create dccg!\n");
2539                 BREAK_TO_DEBUGGER();
2540                 goto create_fail;
2541         }
2542
2543         pool->base.dmcu = dcn20_dmcu_create(ctx,
2544                         &dmcu_regs,
2545                         &dmcu_shift,
2546                         &dmcu_mask);
2547         if (pool->base.dmcu == NULL) {
2548                 dm_error("DC: failed to create dmcu!\n");
2549                 BREAK_TO_DEBUGGER();
2550                 goto create_fail;
2551         }
2552
2553         /*pool->base.abm = dce_abm_create(ctx,
2554                         &abm_regs,
2555                         &abm_shift,
2556                         &abm_mask);
2557         if (pool->base.abm == NULL) {
2558                 dm_error("DC: failed to create abm!\n");
2559                 BREAK_TO_DEBUGGER();
2560                 goto create_fail;
2561         }*/
2562
2563         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2564
2565
2566         if (!init_soc_bounding_box(dc, pool)) {
2567                 dm_error("DC: failed to initialize soc bounding box!\n");
2568                 BREAK_TO_DEBUGGER();
2569                 goto create_fail;
2570         }
2571
2572         dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
2573
2574         if (!dc->debug.disable_pplib_wm_range) {
2575                 struct pp_smu_wm_range_sets ranges = {0};
2576                 int i = 0;
2577
2578                 ranges.num_reader_wm_sets = 0;
2579
2580                 if (dcn2_0_soc.num_states == 1) {
2581                         ranges.reader_wm_sets[0].wm_inst = i;
2582                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2583                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2584                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2585                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2586
2587                         ranges.num_reader_wm_sets = 1;
2588                 } else if (dcn2_0_soc.num_states > 1) {
2589                         for (i = 0; i < 4 && i < dcn2_0_soc.num_states - 1; i++) {
2590                                 ranges.reader_wm_sets[i].wm_inst = i;
2591                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2592                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2593                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
2594                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i + 1].dram_speed_mts / 16;
2595
2596                                 ranges.num_reader_wm_sets = i + 1;
2597                         }
2598                 }
2599
2600                 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2601                 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2602                 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2603                 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2604
2605                 ranges.num_writer_wm_sets = 1;
2606
2607                 ranges.writer_wm_sets[0].wm_inst = 0;
2608                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2609                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2610                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2611                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2612
2613                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2614                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2615                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2616         }
2617
2618         init_data.ctx = dc->ctx;
2619         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2620         if (!pool->base.irqs)
2621                 goto create_fail;
2622
2623         /* mem input -> ipp -> dpp -> opp -> TG */
2624         for (i = 0; i < pool->base.pipe_count; i++) {
2625                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
2626                 if (pool->base.hubps[i] == NULL) {
2627                         BREAK_TO_DEBUGGER();
2628                         dm_error(
2629                                 "DC: failed to create memory input!\n");
2630                         goto create_fail;
2631                 }
2632
2633                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
2634                 if (pool->base.ipps[i] == NULL) {
2635                         BREAK_TO_DEBUGGER();
2636                         dm_error(
2637                                 "DC: failed to create input pixel processor!\n");
2638                         goto create_fail;
2639                 }
2640
2641                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
2642                 if (pool->base.dpps[i] == NULL) {
2643                         BREAK_TO_DEBUGGER();
2644                         dm_error(
2645                                 "DC: failed to create dpps!\n");
2646                         goto create_fail;
2647                 }
2648         }
2649         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2650                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
2651                 if (pool->base.engines[i] == NULL) {
2652                         BREAK_TO_DEBUGGER();
2653                         dm_error(
2654                                 "DC:failed to create aux engine!!\n");
2655                         goto create_fail;
2656                 }
2657                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
2658                 if (pool->base.hw_i2cs[i] == NULL) {
2659                         BREAK_TO_DEBUGGER();
2660                         dm_error(
2661                                 "DC:failed to create hw i2c!!\n");
2662                         goto create_fail;
2663                 }
2664                 pool->base.sw_i2cs[i] = NULL;
2665         }
2666
2667         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2668                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
2669                 if (pool->base.opps[i] == NULL) {
2670                         BREAK_TO_DEBUGGER();
2671                         dm_error(
2672                                 "DC: failed to create output pixel processor!\n");
2673                         goto create_fail;
2674                 }
2675         }
2676
2677         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2678                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
2679                                 ctx, i);
2680                 if (pool->base.timing_generators[i] == NULL) {
2681                         BREAK_TO_DEBUGGER();
2682                         dm_error("DC: failed to create tg!\n");
2683                         goto create_fail;
2684                 }
2685         }
2686
2687         pool->base.timing_generator_count = i;
2688
2689         pool->base.mpc = dcn20_mpc_create(ctx);
2690         if (pool->base.mpc == NULL) {
2691                 BREAK_TO_DEBUGGER();
2692                 dm_error("DC: failed to create mpc!\n");
2693                 goto create_fail;
2694         }
2695
2696         pool->base.hubbub = dcn20_hubbub_create(ctx);
2697         if (pool->base.hubbub == NULL) {
2698                 BREAK_TO_DEBUGGER();
2699                 dm_error("DC: failed to create hubbub!\n");
2700                 goto create_fail;
2701         }
2702
2703
2704         if (!resource_construct(num_virtual_links, dc, &pool->base,
2705                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2706                         &res_create_funcs : &res_create_maximus_funcs)))
2707                         goto create_fail;
2708
2709         dcn20_hw_sequencer_construct(dc);
2710
2711         dc->caps.max_planes =  pool->base.pipe_count;
2712
2713         for (i = 0; i < dc->caps.max_planes; ++i)
2714                 dc->caps.planes[i] = plane_cap;
2715
2716         dc->cap_funcs = cap_funcs;
2717
2718         return true;
2719
2720 create_fail:
2721
2722         destruct(pool);
2723
2724         return false;
2725 }
2726
2727 struct resource_pool *dcn20_create_resource_pool(
2728                 const struct dc_init_data *init_data,
2729                 struct dc *dc)
2730 {
2731         struct dcn20_resource_pool *pool =
2732                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
2733
2734         if (!pool)
2735                 return NULL;
2736
2737         if (construct(init_data->num_virtual_links, dc, pool))
2738                 return &pool->base;
2739
2740         BREAK_TO_DEBUGGER();
2741         kfree(pool);
2742         return NULL;
2743 }