drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn20_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "dcn10/dcn10_hubp.h"
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn20_hubbub.h"
  41 #include "dcn20_mpc.h"
  42 #include "dcn20_hubp.h"
  43 #include "irq/dcn20/irq_service_dcn20.h"
  44 #include "dcn20_dpp.h"
  45 #include "dcn20_optc.h"
  46 #include "dcn20_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn10/dcn10_resource.h"
  49 #include "dcn20_opp.h"
  50
  51 #include "dcn20_dsc.h"
  52
  53 #include "dcn20_link_encoder.h"
  54 #include "dcn20_stream_encoder.h"
  55 #include "dce/dce_clock_source.h"
  56 #include "dce/dce_audio.h"
  57 #include "dce/dce_hwseq.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn20_dccg.h"
  62 #include "dcn20_vmid.h"
  63 #include "dc_link_ddc.h"
  64
  65 #include "navi10_ip_offset.h"
  66
  67 #include "dcn/dcn_2_0_0_offset.h"
  68 #include "dcn/dcn_2_0_0_sh_mask.h"
  69 #include "dpcs/dpcs_2_0_0_offset.h"
  70 #include "dpcs/dpcs_2_0_0_sh_mask.h"
  71
  72 #include "nbio/nbio_2_3_offset.h"
  73
  74 #include "dcn20/dcn20_dwb.h"
  75 #include "dcn20/dcn20_mmhubbub.h"
  76
  77 #include "mmhub/mmhub_2_0_0_offset.h"
  78 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  79
  80 #include "reg_helper.h"
  81 #include "dce/dce_abm.h"
  82 #include "dce/dce_dmcu.h"
  83 #include "dce/dce_aux.h"
  84 #include "dce/dce_i2c.h"
  85 #include "vm_helper.h"
  86
  87 #include "amdgpu_socbb.h"
  88
  89 #define DC_LOGGER_INIT(logger)
  90
  91 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  92         .odm_capable = 1,
  93         .gpuvm_enable = 0,
  94         .hostvm_enable = 0,
  95         .gpuvm_max_page_table_levels = 4,
  96         .hostvm_max_page_table_levels = 4,
  97         .hostvm_cached_page_table_levels = 0,
  98         .pte_group_size_bytes = 2048,
  99         .num_dsc = 6,
 100         .rob_buffer_size_kbytes = 168,
 101         .det_buffer_size_kbytes = 164,
 102         .dpte_buffer_size_in_pte_reqs_luma = 84,
 103         .pde_proc_buffer_size_64k_reqs = 48,
 104         .dpp_output_buffer_pixels = 2560,
 105         .opp_output_buffer_lines = 1,
 106         .pixel_chunk_size_kbytes = 8,
 107         .pte_chunk_size_kbytes = 2,
 108         .meta_chunk_size_kbytes = 2,
 109         .writeback_chunk_size_kbytes = 2,
 110         .line_buffer_size_bits = 789504,
 111         .is_line_buffer_bpp_fixed = 0,
 112         .line_buffer_fixed_bpp = 0,
 113         .dcc_supported = true,
 114         .max_line_buffer_lines = 12,
 115         .writeback_luma_buffer_size_kbytes = 12,
 116         .writeback_chroma_buffer_size_kbytes = 8,
 117         .writeback_chroma_line_buffer_width_pixels = 4,
 118         .writeback_max_hscl_ratio = 1,
 119         .writeback_max_vscl_ratio = 1,
 120         .writeback_min_hscl_ratio = 1,
 121         .writeback_min_vscl_ratio = 1,
 122         .writeback_max_hscl_taps = 12,
 123         .writeback_max_vscl_taps = 12,
 124         .writeback_line_buffer_luma_buffer_size = 0,
 125         .writeback_line_buffer_chroma_buffer_size = 14643,
 126         .cursor_buffer_size = 8,
 127         .cursor_chunk_size = 2,
 128         .max_num_otg = 6,
 129         .max_num_dpp = 6,
 130         .max_num_wb = 1,
 131         .max_dchub_pscl_bw_pix_per_clk = 4,
 132         .max_pscl_lb_bw_pix_per_clk = 2,
 133         .max_lb_vscl_bw_pix_per_clk = 4,
 134         .max_vscl_hscl_bw_pix_per_clk = 4,
 135         .max_hscl_ratio = 8,
 136         .max_vscl_ratio = 8,
 137         .hscl_mults = 4,
 138         .vscl_mults = 4,
 139         .max_hscl_taps = 8,
 140         .max_vscl_taps = 8,
 141         .dispclk_ramp_margin_percent = 1,
 142         .underscan_factor = 1.10,
 143         .min_vblank_lines = 32, //
 144         .dppclk_delay_subtotal = 77, //
 145         .dppclk_delay_scl_lb_only = 16,
 146         .dppclk_delay_scl = 50,
 147         .dppclk_delay_cnvc_formatter = 8,
 148         .dppclk_delay_cnvc_cursor = 6,
 149         .dispclk_delay_subtotal = 87, //
 150         .dcfclk_cstate_latency = 10, // SRExitTime
 151         .max_inter_dcn_tile_repeaters = 8,
 152
 153         .xfc_supported = true,
 154         .xfc_fill_bw_overhead_percent = 10.0,
 155         .xfc_fill_constant_bytes = 0,
 156 };
 157
 158 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
 159         .odm_capable = 1,
 160         .gpuvm_enable = 0,
 161         .hostvm_enable = 0,
 162         .gpuvm_max_page_table_levels = 4,
 163         .hostvm_max_page_table_levels = 4,
 164         .hostvm_cached_page_table_levels = 0,
 165         .num_dsc = 5,
 166         .rob_buffer_size_kbytes = 168,
 167         .det_buffer_size_kbytes = 164,
 168         .dpte_buffer_size_in_pte_reqs_luma = 84,
 169         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 170         .dpp_output_buffer_pixels = 2560,
 171         .opp_output_buffer_lines = 1,
 172         .pixel_chunk_size_kbytes = 8,
 173         .pte_enable = 1,
 174         .max_page_table_levels = 4,
 175         .pte_chunk_size_kbytes = 2,
 176         .meta_chunk_size_kbytes = 2,
 177         .writeback_chunk_size_kbytes = 2,
 178         .line_buffer_size_bits = 789504,
 179         .is_line_buffer_bpp_fixed = 0,
 180         .line_buffer_fixed_bpp = 0,
 181         .dcc_supported = true,
 182         .max_line_buffer_lines = 12,
 183         .writeback_luma_buffer_size_kbytes = 12,
 184         .writeback_chroma_buffer_size_kbytes = 8,
 185         .writeback_chroma_line_buffer_width_pixels = 4,
 186         .writeback_max_hscl_ratio = 1,
 187         .writeback_max_vscl_ratio = 1,
 188         .writeback_min_hscl_ratio = 1,
 189         .writeback_min_vscl_ratio = 1,
 190         .writeback_max_hscl_taps = 12,
 191         .writeback_max_vscl_taps = 12,
 192         .writeback_line_buffer_luma_buffer_size = 0,
 193         .writeback_line_buffer_chroma_buffer_size = 14643,
 194         .cursor_buffer_size = 8,
 195         .cursor_chunk_size = 2,
 196         .max_num_otg = 5,
 197         .max_num_dpp = 5,
 198         .max_num_wb = 1,
 199         .max_dchub_pscl_bw_pix_per_clk = 4,
 200         .max_pscl_lb_bw_pix_per_clk = 2,
 201         .max_lb_vscl_bw_pix_per_clk = 4,
 202         .max_vscl_hscl_bw_pix_per_clk = 4,
 203         .max_hscl_ratio = 8,
 204         .max_vscl_ratio = 8,
 205         .hscl_mults = 4,
 206         .vscl_mults = 4,
 207         .max_hscl_taps = 8,
 208         .max_vscl_taps = 8,
 209         .dispclk_ramp_margin_percent = 1,
 210         .underscan_factor = 1.10,
 211         .min_vblank_lines = 32, //
 212         .dppclk_delay_subtotal = 77, //
 213         .dppclk_delay_scl_lb_only = 16,
 214         .dppclk_delay_scl = 50,
 215         .dppclk_delay_cnvc_formatter = 8,
 216         .dppclk_delay_cnvc_cursor = 6,
 217         .dispclk_delay_subtotal = 87, //
 218         .dcfclk_cstate_latency = 10, // SRExitTime
 219         .max_inter_dcn_tile_repeaters = 8,
 220         .xfc_supported = true,
 221         .xfc_fill_bw_overhead_percent = 10.0,
 222         .xfc_fill_constant_bytes = 0,
 223         .ptoi_supported = 0
 224 };
 225
 226 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 227         /* Defaults that get patched on driver load from firmware. */
 228         .clock_limits = {
 229                         {
 230                                 .state = 0,
 231                                 .dcfclk_mhz = 560.0,
 232                                 .fabricclk_mhz = 560.0,
 233                                 .dispclk_mhz = 513.0,
 234                                 .dppclk_mhz = 513.0,
 235                                 .phyclk_mhz = 540.0,
 236                                 .socclk_mhz = 560.0,
 237                                 .dscclk_mhz = 171.0,
 238                                 .dram_speed_mts = 8960.0,
 239                         },
 240                         {
 241                                 .state = 1,
 242                                 .dcfclk_mhz = 694.0,
 243                                 .fabricclk_mhz = 694.0,
 244                                 .dispclk_mhz = 642.0,
 245                                 .dppclk_mhz = 642.0,
 246                                 .phyclk_mhz = 600.0,
 247                                 .socclk_mhz = 694.0,
 248                                 .dscclk_mhz = 214.0,
 249                                 .dram_speed_mts = 11104.0,
 250                         },
 251                         {
 252                                 .state = 2,
 253                                 .dcfclk_mhz = 875.0,
 254                                 .fabricclk_mhz = 875.0,
 255                                 .dispclk_mhz = 734.0,
 256                                 .dppclk_mhz = 734.0,
 257                                 .phyclk_mhz = 810.0,
 258                                 .socclk_mhz = 875.0,
 259                                 .dscclk_mhz = 245.0,
 260                                 .dram_speed_mts = 14000.0,
 261                         },
 262                         {
 263                                 .state = 3,
 264                                 .dcfclk_mhz = 1000.0,
 265                                 .fabricclk_mhz = 1000.0,
 266                                 .dispclk_mhz = 1100.0,
 267                                 .dppclk_mhz = 1100.0,
 268                                 .phyclk_mhz = 810.0,
 269                                 .socclk_mhz = 1000.0,
 270                                 .dscclk_mhz = 367.0,
 271                                 .dram_speed_mts = 16000.0,
 272                         },
 273                         {
 274                                 .state = 4,
 275                                 .dcfclk_mhz = 1200.0,
 276                                 .fabricclk_mhz = 1200.0,
 277                                 .dispclk_mhz = 1284.0,
 278                                 .dppclk_mhz = 1284.0,
 279                                 .phyclk_mhz = 810.0,
 280                                 .socclk_mhz = 1200.0,
 281                                 .dscclk_mhz = 428.0,
 282                                 .dram_speed_mts = 16000.0,
 283                         },
 284                         /*Extra state, no dispclk ramping*/
 285                         {
 286                                 .state = 5,
 287                                 .dcfclk_mhz = 1200.0,
 288                                 .fabricclk_mhz = 1200.0,
 289                                 .dispclk_mhz = 1284.0,
 290                                 .dppclk_mhz = 1284.0,
 291                                 .phyclk_mhz = 810.0,
 292                                 .socclk_mhz = 1200.0,
 293                                 .dscclk_mhz = 428.0,
 294                                 .dram_speed_mts = 16000.0,
 295                         },
 296                 },
 297         .num_states = 5,
 298         .sr_exit_time_us = 8.6,
 299         .sr_enter_plus_exit_time_us = 10.9,
 300         .urgent_latency_us = 4.0,
 301         .urgent_latency_pixel_data_only_us = 4.0,
 302         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 303         .urgent_latency_vm_data_only_us = 4.0,
 304         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 305         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 306         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 307         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 308         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 309         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 310         .max_avg_sdp_bw_use_normal_percent = 40.0,
 311         .max_avg_dram_bw_use_normal_percent = 40.0,
 312         .writeback_latency_us = 12.0,
 313         .ideal_dram_bw_after_urgent_percent = 40.0,
 314         .max_request_size_bytes = 256,
 315         .dram_channel_width_bytes = 2,
 316         .fabric_datapath_to_dcn_data_return_bytes = 64,
 317         .dcn_downspread_percent = 0.5,
 318         .downspread_percent = 0.38,
 319         .dram_page_open_time_ns = 50.0,
 320         .dram_rw_turnaround_time_ns = 17.5,
 321         .dram_return_buffer_per_channel_bytes = 8192,
 322         .round_trip_ping_latency_dcfclk_cycles = 131,
 323         .urgent_out_of_order_return_per_channel_bytes = 256,
 324         .channel_interleave_bytes = 256,
 325         .num_banks = 8,
 326         .num_chans = 16,
 327         .vmm_page_size_bytes = 4096,
 328         .dram_clock_change_latency_us = 404.0,
 329         .dummy_pstate_latency_us = 5.0,
 330         .writeback_dram_clock_change_latency_us = 23.0,
 331         .return_bus_width_bytes = 64,
 332         .dispclk_dppclk_vco_speed_mhz = 3850,
 333         .xfc_bus_transport_time_us = 20,
 334         .xfc_xbuf_latency_tolerance_us = 4,
 335         .use_urgent_burst_bw = 0
 336 };
 337
 338 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 339
 340 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 341         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 342         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 343         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 344         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 345         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 346         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 347         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 348         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 349         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 350         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 351         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 352         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 353         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 354         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 355 #endif
 356
 357
 358 enum dcn20_clk_src_array_id {
 359         DCN20_CLK_SRC_PLL0,
 360         DCN20_CLK_SRC_PLL1,
 361         DCN20_CLK_SRC_PLL2,
 362         DCN20_CLK_SRC_PLL3,
 363         DCN20_CLK_SRC_PLL4,
 364         DCN20_CLK_SRC_PLL5,
 365         DCN20_CLK_SRC_TOTAL
 366 };
 367
 368 /* begin *********************
 369  * macros to expend register list macro defined in HW object header file */
 370
 371 /* DCN */
 372 /* TODO awful hack. fixup dcn20_dwb.h */
 373 #undef BASE_INNER
 374 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 375
 376 #define BASE(seg) BASE_INNER(seg)
 377
 378 #define SR(reg_name)\
 379                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 380                                         mm ## reg_name
 381
 382 #define SRI(reg_name, block, id)\
 383         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 384                                         mm ## block ## id ## _ ## reg_name
 385
 386 #define SRIR(var_name, reg_name, block, id)\
 387         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 388                                         mm ## block ## id ## _ ## reg_name
 389
 390 #define SRII(reg_name, block, id)\
 391         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 392                                         mm ## block ## id ## _ ## reg_name
 393
 394 #define DCCG_SRII(reg_name, block, id)\
 395         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 396                                         mm ## block ## id ## _ ## reg_name
 397
 398 /* NBIO */
 399 #define NBIO_BASE_INNER(seg) \
 400         NBIO_BASE__INST0_SEG ## seg
 401
 402 #define NBIO_BASE(seg) \
 403         NBIO_BASE_INNER(seg)
 404
 405 #define NBIO_SR(reg_name)\
 406                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 407                                         mm ## reg_name
 408
 409 /* MMHUB */
 410 #define MMHUB_BASE_INNER(seg) \
 411         MMHUB_BASE__INST0_SEG ## seg
 412
 413 #define MMHUB_BASE(seg) \
 414         MMHUB_BASE_INNER(seg)
 415
 416 #define MMHUB_SR(reg_name)\
 417                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 418                                         mmMM ## reg_name
 419
 420 static const struct bios_registers bios_regs = {
 421                 NBIO_SR(BIOS_SCRATCH_3),
 422                 NBIO_SR(BIOS_SCRATCH_6)
 423 };
 424
 425 #define clk_src_regs(index, pllid)\
 426 [index] = {\
 427         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 428 }
 429
 430 static const struct dce110_clk_src_regs clk_src_regs[] = {
 431         clk_src_regs(0, A),
 432         clk_src_regs(1, B),
 433         clk_src_regs(2, C),
 434         clk_src_regs(3, D),
 435         clk_src_regs(4, E),
 436         clk_src_regs(5, F)
 437 };
 438
 439 static const struct dce110_clk_src_shift cs_shift = {
 440                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 441 };
 442
 443 static const struct dce110_clk_src_mask cs_mask = {
 444                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 445 };
 446
 447 static const struct dce_dmcu_registers dmcu_regs = {
 448                 DMCU_DCN10_REG_LIST()
 449 };
 450
 451 static const struct dce_dmcu_shift dmcu_shift = {
 452                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 453 };
 454
 455 static const struct dce_dmcu_mask dmcu_mask = {
 456                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 457 };
 458
 459 static const struct dce_abm_registers abm_regs = {
 460                 ABM_DCN20_REG_LIST()
 461 };
 462
 463 static const struct dce_abm_shift abm_shift = {
 464                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 465 };
 466
 467 static const struct dce_abm_mask abm_mask = {
 468                 ABM_MASK_SH_LIST_DCN20(_MASK)
 469 };
 470
 471 #define audio_regs(id)\
 472 [id] = {\
 473                 AUD_COMMON_REG_LIST(id)\
 474 }
 475
 476 static const struct dce_audio_registers audio_regs[] = {
 477         audio_regs(0),
 478         audio_regs(1),
 479         audio_regs(2),
 480         audio_regs(3),
 481         audio_regs(4),
 482         audio_regs(5),
 483         audio_regs(6),
 484 };
 485
 486 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 487                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 488                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 489                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 490
 491 static const struct dce_audio_shift audio_shift = {
 492                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 493 };
 494
 495 static const struct dce_audio_mask audio_mask = {
 496                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 497 };
 498
 499 #define stream_enc_regs(id)\
 500 [id] = {\
 501         SE_DCN2_REG_LIST(id)\
 502 }
 503
 504 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 505         stream_enc_regs(0),
 506         stream_enc_regs(1),
 507         stream_enc_regs(2),
 508         stream_enc_regs(3),
 509         stream_enc_regs(4),
 510         stream_enc_regs(5),
 511 };
 512
 513 static const struct dcn10_stream_encoder_shift se_shift = {
 514                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 515 };
 516
 517 static const struct dcn10_stream_encoder_mask se_mask = {
 518                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 519 };
 520
 521
 522 #define aux_regs(id)\
 523 [id] = {\
 524         DCN2_AUX_REG_LIST(id)\
 525 }
 526
 527 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 528                 aux_regs(0),
 529                 aux_regs(1),
 530                 aux_regs(2),
 531                 aux_regs(3),
 532                 aux_regs(4),
 533                 aux_regs(5)
 534 };
 535
 536 #define hpd_regs(id)\
 537 [id] = {\
 538         HPD_REG_LIST(id)\
 539 }
 540
 541 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 542                 hpd_regs(0),
 543                 hpd_regs(1),
 544                 hpd_regs(2),
 545                 hpd_regs(3),
 546                 hpd_regs(4),
 547                 hpd_regs(5)
 548 };
 549
 550 #define link_regs(id, phyid)\
 551 [id] = {\
 552         LE_DCN10_REG_LIST(id), \
 553         UNIPHY_DCN2_REG_LIST(phyid), \
 554         DPCS_DCN2_REG_LIST(id), \
 555         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 556 }
 557
 558 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 559         link_regs(0, A),
 560         link_regs(1, B),
 561         link_regs(2, C),
 562         link_regs(3, D),
 563         link_regs(4, E),
 564         link_regs(5, F)
 565 };
 566
 567 static const struct dcn10_link_enc_shift le_shift = {
 568         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
 569         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 570 };
 571
 572 static const struct dcn10_link_enc_mask le_mask = {
 573         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
 574         DPCS_DCN2_MASK_SH_LIST(_MASK)
 575 };
 576
 577 #define ipp_regs(id)\
 578 [id] = {\
 579         IPP_REG_LIST_DCN20(id),\
 580 }
 581
 582 static const struct dcn10_ipp_registers ipp_regs[] = {
 583         ipp_regs(0),
 584         ipp_regs(1),
 585         ipp_regs(2),
 586         ipp_regs(3),
 587         ipp_regs(4),
 588         ipp_regs(5),
 589 };
 590
 591 static const struct dcn10_ipp_shift ipp_shift = {
 592                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 593 };
 594
 595 static const struct dcn10_ipp_mask ipp_mask = {
 596                 IPP_MASK_SH_LIST_DCN20(_MASK),
 597 };
 598
 599 #define opp_regs(id)\
 600 [id] = {\
 601         OPP_REG_LIST_DCN20(id),\
 602 }
 603
 604 static const struct dcn20_opp_registers opp_regs[] = {
 605         opp_regs(0),
 606         opp_regs(1),
 607         opp_regs(2),
 608         opp_regs(3),
 609         opp_regs(4),
 610         opp_regs(5),
 611 };
 612
 613 static const struct dcn20_opp_shift opp_shift = {
 614                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 615 };
 616
 617 static const struct dcn20_opp_mask opp_mask = {
 618                 OPP_MASK_SH_LIST_DCN20(_MASK)
 619 };
 620
 621 #define aux_engine_regs(id)\
 622 [id] = {\
 623         AUX_COMMON_REG_LIST0(id), \
 624         .AUXN_IMPCAL = 0, \
 625         .AUXP_IMPCAL = 0, \
 626         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 627 }
 628
 629 static const struct dce110_aux_registers aux_engine_regs[] = {
 630                 aux_engine_regs(0),
 631                 aux_engine_regs(1),
 632                 aux_engine_regs(2),
 633                 aux_engine_regs(3),
 634                 aux_engine_regs(4),
 635                 aux_engine_regs(5)
 636 };
 637
 638 #define tf_regs(id)\
 639 [id] = {\
 640         TF_REG_LIST_DCN20(id),\
 641 }
 642
 643 static const struct dcn2_dpp_registers tf_regs[] = {
 644         tf_regs(0),
 645         tf_regs(1),
 646         tf_regs(2),
 647         tf_regs(3),
 648         tf_regs(4),
 649         tf_regs(5),
 650 };
 651
 652 static const struct dcn2_dpp_shift tf_shift = {
 653                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 654                 TF_DEBUG_REG_LIST_SH_DCN10
 655 };
 656
 657 static const struct dcn2_dpp_mask tf_mask = {
 658                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 659                 TF_DEBUG_REG_LIST_MASK_DCN10
 660 };
 661
 662 #define dwbc_regs_dcn2(id)\
 663 [id] = {\
 664         DWBC_COMMON_REG_LIST_DCN2_0(id),\
 665                 }
 666
 667 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
 668         dwbc_regs_dcn2(0),
 669 };
 670
 671 static const struct dcn20_dwbc_shift dwbc20_shift = {
 672         DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 673 };
 674
 675 static const struct dcn20_dwbc_mask dwbc20_mask = {
 676         DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 677 };
 678
 679 #define mcif_wb_regs_dcn2(id)\
 680 [id] = {\
 681         MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
 682                 }
 683
 684 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
 685         mcif_wb_regs_dcn2(0),
 686 };
 687
 688 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
 689         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 690 };
 691
 692 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
 693         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 694 };
 695
 696 static const struct dcn20_mpc_registers mpc_regs = {
 697                 MPC_REG_LIST_DCN2_0(0),
 698                 MPC_REG_LIST_DCN2_0(1),
 699                 MPC_REG_LIST_DCN2_0(2),
 700                 MPC_REG_LIST_DCN2_0(3),
 701                 MPC_REG_LIST_DCN2_0(4),
 702                 MPC_REG_LIST_DCN2_0(5),
 703                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 704                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 705                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 706                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 707                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 708                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 709 };
 710
 711 static const struct dcn20_mpc_shift mpc_shift = {
 712         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 713 };
 714
 715 static const struct dcn20_mpc_mask mpc_mask = {
 716         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 717 };
 718
 719 #define tg_regs(id)\
 720 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 721
 722
 723 static const struct dcn_optc_registers tg_regs[] = {
 724         tg_regs(0),
 725         tg_regs(1),
 726         tg_regs(2),
 727         tg_regs(3),
 728         tg_regs(4),
 729         tg_regs(5)
 730 };
 731
 732 static const struct dcn_optc_shift tg_shift = {
 733         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 734 };
 735
 736 static const struct dcn_optc_mask tg_mask = {
 737         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 738 };
 739
 740 #define hubp_regs(id)\
 741 [id] = {\
 742         HUBP_REG_LIST_DCN20(id)\
 743 }
 744
 745 static const struct dcn_hubp2_registers hubp_regs[] = {
 746                 hubp_regs(0),
 747                 hubp_regs(1),
 748                 hubp_regs(2),
 749                 hubp_regs(3),
 750                 hubp_regs(4),
 751                 hubp_regs(5)
 752 };
 753
 754 static const struct dcn_hubp2_shift hubp_shift = {
 755                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 756 };
 757
 758 static const struct dcn_hubp2_mask hubp_mask = {
 759                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 760 };
 761
 762 static const struct dcn_hubbub_registers hubbub_reg = {
 763                 HUBBUB_REG_LIST_DCN20(0)
 764 };
 765
 766 static const struct dcn_hubbub_shift hubbub_shift = {
 767                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 768 };
 769
 770 static const struct dcn_hubbub_mask hubbub_mask = {
 771                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 772 };
 773
 774 #define vmid_regs(id)\
 775 [id] = {\
 776                 DCN20_VMID_REG_LIST(id)\
 777 }
 778
 779 static const struct dcn_vmid_registers vmid_regs[] = {
 780         vmid_regs(0),
 781         vmid_regs(1),
 782         vmid_regs(2),
 783         vmid_regs(3),
 784         vmid_regs(4),
 785         vmid_regs(5),
 786         vmid_regs(6),
 787         vmid_regs(7),
 788         vmid_regs(8),
 789         vmid_regs(9),
 790         vmid_regs(10),
 791         vmid_regs(11),
 792         vmid_regs(12),
 793         vmid_regs(13),
 794         vmid_regs(14),
 795         vmid_regs(15)
 796 };
 797
 798 static const struct dcn20_vmid_shift vmid_shifts = {
 799                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 800 };
 801
 802 static const struct dcn20_vmid_mask vmid_masks = {
 803                 DCN20_VMID_MASK_SH_LIST(_MASK)
 804 };
 805
 806 static const struct dce110_aux_registers_shift aux_shift = {
 807                 DCN_AUX_MASK_SH_LIST(__SHIFT)
 808 };
 809
 810 static const struct dce110_aux_registers_mask aux_mask = {
 811                 DCN_AUX_MASK_SH_LIST(_MASK)
 812 };
 813
 814 static int map_transmitter_id_to_phy_instance(
 815         enum transmitter transmitter)
 816 {
 817         switch (transmitter) {
 818         case TRANSMITTER_UNIPHY_A:
 819                 return 0;
 820         break;
 821         case TRANSMITTER_UNIPHY_B:
 822                 return 1;
 823         break;
 824         case TRANSMITTER_UNIPHY_C:
 825                 return 2;
 826         break;
 827         case TRANSMITTER_UNIPHY_D:
 828                 return 3;
 829         break;
 830         case TRANSMITTER_UNIPHY_E:
 831                 return 4;
 832         break;
 833         case TRANSMITTER_UNIPHY_F:
 834                 return 5;
 835         break;
 836         default:
 837                 ASSERT(0);
 838                 return 0;
 839         }
 840 }
 841
 842 #define dsc_regsDCN20(id)\
 843 [id] = {\
 844         DSC_REG_LIST_DCN20(id)\
 845 }
 846
 847 static const struct dcn20_dsc_registers dsc_regs[] = {
 848         dsc_regsDCN20(0),
 849         dsc_regsDCN20(1),
 850         dsc_regsDCN20(2),
 851         dsc_regsDCN20(3),
 852         dsc_regsDCN20(4),
 853         dsc_regsDCN20(5)
 854 };
 855
 856 static const struct dcn20_dsc_shift dsc_shift = {
 857         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 858 };
 859
 860 static const struct dcn20_dsc_mask dsc_mask = {
 861         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 862 };
 863
 864 static const struct dccg_registers dccg_regs = {
 865                 DCCG_REG_LIST_DCN2()
 866 };
 867
 868 static const struct dccg_shift dccg_shift = {
 869                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 870 };
 871
 872 static const struct dccg_mask dccg_mask = {
 873                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 874 };
 875
 876 static const struct resource_caps res_cap_nv10 = {
 877                 .num_timing_generator = 6,
 878                 .num_opp = 6,
 879                 .num_video_plane = 6,
 880                 .num_audio = 7,
 881                 .num_stream_encoder = 6,
 882                 .num_pll = 6,
 883                 .num_dwb = 1,
 884                 .num_ddc = 6,
 885                 .num_vmid = 16,
 886                 .num_dsc = 6,
 887 };
 888
 889 static const struct dc_plane_cap plane_cap = {
 890         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 891         .blends_with_above = true,
 892         .blends_with_below = true,
 893         .per_pixel_alpha = true,
 894
 895         .pixel_format_support = {
 896                         .argb8888 = true,
 897                         .nv12 = true,
 898                         .fp16 = true
 899         },
 900
 901         .max_upscale_factor = {
 902                         .argb8888 = 16000,
 903                         .nv12 = 16000,
 904                         .fp16 = 1
 905         },
 906
 907         .max_downscale_factor = {
 908                         .argb8888 = 250,
 909                         .nv12 = 250,
 910                         .fp16 = 1
 911         }
 912 };
 913 static const struct resource_caps res_cap_nv14 = {
 914                 .num_timing_generator = 5,
 915                 .num_opp = 5,
 916                 .num_video_plane = 5,
 917                 .num_audio = 6,
 918                 .num_stream_encoder = 5,
 919                 .num_pll = 5,
 920                 .num_dwb = 1,
 921                 .num_ddc = 5,
 922                 .num_vmid = 16,
 923                 .num_dsc = 5,
 924 };
 925
 926 static const struct dc_debug_options debug_defaults_drv = {
 927                 .disable_dmcu = true,
 928                 .force_abm_enable = false,
 929                 .timing_trace = false,
 930                 .clock_trace = true,
 931                 .disable_pplib_clock_request = true,
 932                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 933                 .force_single_disp_pipe_split = false,
 934                 .disable_dcc = DCC_ENABLE,
 935                 .vsr_support = true,
 936                 .performance_trace = false,
 937                 .max_downscale_src_width = 5120,/*upto 5K*/
 938                 .disable_pplib_wm_range = false,
 939                 .scl_reset_length10 = true,
 940                 .sanity_checks = false,
 941                 .disable_tri_buf = true,
 942                 .underflow_assert_delay_us = 0xFFFFFFFF,
 943 };
 944
 945 static const struct dc_debug_options debug_defaults_diags = {
 946                 .disable_dmcu = true,
 947                 .force_abm_enable = false,
 948                 .timing_trace = true,
 949                 .clock_trace = true,
 950                 .disable_dpp_power_gate = true,
 951                 .disable_hubp_power_gate = true,
 952                 .disable_clock_gate = true,
 953                 .disable_pplib_clock_request = true,
 954                 .disable_pplib_wm_range = true,
 955                 .disable_stutter = true,
 956                 .scl_reset_length10 = true,
 957                 .underflow_assert_delay_us = 0xFFFFFFFF,
 958 };
 959
 960 void dcn20_dpp_destroy(struct dpp **dpp)
 961 {
 962         kfree(TO_DCN20_DPP(*dpp));
 963         *dpp = NULL;
 964 }
 965
 966 struct dpp *dcn20_dpp_create(
 967         struct dc_context *ctx,
 968         uint32_t inst)
 969 {
 970         struct dcn20_dpp *dpp =
 971                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 972
 973         if (!dpp)
 974                 return NULL;
 975
 976         if (dpp2_construct(dpp, ctx, inst,
 977                         &tf_regs[inst], &tf_shift, &tf_mask))
 978                 return &dpp->base;
 979
 980         BREAK_TO_DEBUGGER();
 981         kfree(dpp);
 982         return NULL;
 983 }
 984
 985 struct input_pixel_processor *dcn20_ipp_create(
 986         struct dc_context *ctx, uint32_t inst)
 987 {
 988         struct dcn10_ipp *ipp =
 989                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 990
 991         if (!ipp) {
 992                 BREAK_TO_DEBUGGER();
 993                 return NULL;
 994         }
 995
 996         dcn20_ipp_construct(ipp, ctx, inst,
 997                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 998         return &ipp->base;
 999 }
1000
1001
1002 struct output_pixel_processor *dcn20_opp_create(
1003         struct dc_context *ctx, uint32_t inst)
1004 {
1005         struct dcn20_opp *opp =
1006                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1007
1008         if (!opp) {
1009                 BREAK_TO_DEBUGGER();
1010                 return NULL;
1011         }
1012
1013         dcn20_opp_construct(opp, ctx, inst,
1014                         &opp_regs[inst], &opp_shift, &opp_mask);
1015         return &opp->base;
1016 }
1017
1018 struct dce_aux *dcn20_aux_engine_create(
1019         struct dc_context *ctx,
1020         uint32_t inst)
1021 {
1022         struct aux_engine_dce110 *aux_engine =
1023                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1024
1025         if (!aux_engine)
1026                 return NULL;
1027
1028         dce110_aux_engine_construct(aux_engine, ctx, inst,
1029                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1030                                     &aux_engine_regs[inst],
1031                                         &aux_mask,
1032                                         &aux_shift,
1033                                         ctx->dc->caps.extended_aux_timeout_support);
1034
1035         return &aux_engine->base;
1036 }
1037 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1038
1039 static const struct dce_i2c_registers i2c_hw_regs[] = {
1040                 i2c_inst_regs(1),
1041                 i2c_inst_regs(2),
1042                 i2c_inst_regs(3),
1043                 i2c_inst_regs(4),
1044                 i2c_inst_regs(5),
1045                 i2c_inst_regs(6),
1046 };
1047
1048 static const struct dce_i2c_shift i2c_shifts = {
1049                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1050 };
1051
1052 static const struct dce_i2c_mask i2c_masks = {
1053                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1054 };
1055
1056 struct dce_i2c_hw *dcn20_i2c_hw_create(
1057         struct dc_context *ctx,
1058         uint32_t inst)
1059 {
1060         struct dce_i2c_hw *dce_i2c_hw =
1061                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1062
1063         if (!dce_i2c_hw)
1064                 return NULL;
1065
1066         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1067                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1068
1069         return dce_i2c_hw;
1070 }
1071 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1072 {
1073         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1074                                           GFP_KERNEL);
1075
1076         if (!mpc20)
1077                 return NULL;
1078
1079         dcn20_mpc_construct(mpc20, ctx,
1080                         &mpc_regs,
1081                         &mpc_shift,
1082                         &mpc_mask,
1083                         6);
1084
1085         return &mpc20->base;
1086 }
1087
1088 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1089 {
1090         int i;
1091         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1092                                           GFP_KERNEL);
1093
1094         if (!hubbub)
1095                 return NULL;
1096
1097         hubbub2_construct(hubbub, ctx,
1098                         &hubbub_reg,
1099                         &hubbub_shift,
1100                         &hubbub_mask);
1101
1102         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1103                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1104
1105                 vmid->ctx = ctx;
1106
1107                 vmid->regs = &vmid_regs[i];
1108                 vmid->shifts = &vmid_shifts;
1109                 vmid->masks = &vmid_masks;
1110         }
1111
1112         return &hubbub->base;
1113 }
1114
1115 struct timing_generator *dcn20_timing_generator_create(
1116                 struct dc_context *ctx,
1117                 uint32_t instance)
1118 {
1119         struct optc *tgn10 =
1120                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1121
1122         if (!tgn10)
1123                 return NULL;
1124
1125         tgn10->base.inst = instance;
1126         tgn10->base.ctx = ctx;
1127
1128         tgn10->tg_regs = &tg_regs[instance];
1129         tgn10->tg_shift = &tg_shift;
1130         tgn10->tg_mask = &tg_mask;
1131
1132         dcn20_timing_generator_init(tgn10);
1133
1134         return &tgn10->base;
1135 }
1136
1137 static const struct encoder_feature_support link_enc_feature = {
1138                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1139                 .max_hdmi_pixel_clock = 600000,
1140                 .hdmi_ycbcr420_supported = true,
1141                 .dp_ycbcr420_supported = true,
1142                 .flags.bits.IS_HBR2_CAPABLE = true,
1143                 .flags.bits.IS_HBR3_CAPABLE = true,
1144                 .flags.bits.IS_TPS3_CAPABLE = true,
1145                 .flags.bits.IS_TPS4_CAPABLE = true
1146 };
1147
1148 struct link_encoder *dcn20_link_encoder_create(
1149         const struct encoder_init_data *enc_init_data)
1150 {
1151         struct dcn20_link_encoder *enc20 =
1152                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1153         int link_regs_id;
1154
1155         if (!enc20)
1156                 return NULL;
1157
1158         link_regs_id =
1159                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1160
1161         dcn20_link_encoder_construct(enc20,
1162                                       enc_init_data,
1163                                       &link_enc_feature,
1164                                       &link_enc_regs[link_regs_id],
1165                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1166                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1167                                       &le_shift,
1168                                       &le_mask);
1169
1170         return &enc20->enc10.base;
1171 }
1172
1173 struct clock_source *dcn20_clock_source_create(
1174         struct dc_context *ctx,
1175         struct dc_bios *bios,
1176         enum clock_source_id id,
1177         const struct dce110_clk_src_regs *regs,
1178         bool dp_clk_src)
1179 {
1180         struct dce110_clk_src *clk_src =
1181                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1182
1183         if (!clk_src)
1184                 return NULL;
1185
1186         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1187                         regs, &cs_shift, &cs_mask)) {
1188                 clk_src->base.dp_clk_src = dp_clk_src;
1189                 return &clk_src->base;
1190         }
1191
1192         kfree(clk_src);
1193         BREAK_TO_DEBUGGER();
1194         return NULL;
1195 }
1196
1197 static void read_dce_straps(
1198         struct dc_context *ctx,
1199         struct resource_straps *straps)
1200 {
1201         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1202                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1203 }
1204
1205 static struct audio *dcn20_create_audio(
1206                 struct dc_context *ctx, unsigned int inst)
1207 {
1208         return dce_audio_create(ctx, inst,
1209                         &audio_regs[inst], &audio_shift, &audio_mask);
1210 }
1211
1212 struct stream_encoder *dcn20_stream_encoder_create(
1213         enum engine_id eng_id,
1214         struct dc_context *ctx)
1215 {
1216         struct dcn10_stream_encoder *enc1 =
1217                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1218
1219         if (!enc1)
1220                 return NULL;
1221
1222         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1223                 if (eng_id >= ENGINE_ID_DIGD)
1224                         eng_id++;
1225         }
1226
1227         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1228                                         &stream_enc_regs[eng_id],
1229                                         &se_shift, &se_mask);
1230
1231         return &enc1->base;
1232 }
1233
1234 static const struct dce_hwseq_registers hwseq_reg = {
1235                 HWSEQ_DCN2_REG_LIST()
1236 };
1237
1238 static const struct dce_hwseq_shift hwseq_shift = {
1239                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1240 };
1241
1242 static const struct dce_hwseq_mask hwseq_mask = {
1243                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1244 };
1245
1246 struct dce_hwseq *dcn20_hwseq_create(
1247         struct dc_context *ctx)
1248 {
1249         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1250
1251         if (hws) {
1252                 hws->ctx = ctx;
1253                 hws->regs = &hwseq_reg;
1254                 hws->shifts = &hwseq_shift;
1255                 hws->masks = &hwseq_mask;
1256         }
1257         return hws;
1258 }
1259
1260 static const struct resource_create_funcs res_create_funcs = {
1261         .read_dce_straps = read_dce_straps,
1262         .create_audio = dcn20_create_audio,
1263         .create_stream_encoder = dcn20_stream_encoder_create,
1264         .create_hwseq = dcn20_hwseq_create,
1265 };
1266
1267 static const struct resource_create_funcs res_create_maximus_funcs = {
1268         .read_dce_straps = NULL,
1269         .create_audio = NULL,
1270         .create_stream_encoder = NULL,
1271         .create_hwseq = dcn20_hwseq_create,
1272 };
1273
1274 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1275
1276 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1277 {
1278         kfree(TO_DCE110_CLK_SRC(*clk_src));
1279         *clk_src = NULL;
1280 }
1281
1282
1283 struct display_stream_compressor *dcn20_dsc_create(
1284         struct dc_context *ctx, uint32_t inst)
1285 {
1286         struct dcn20_dsc *dsc =
1287                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1288
1289         if (!dsc) {
1290                 BREAK_TO_DEBUGGER();
1291                 return NULL;
1292         }
1293
1294         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1295         return &dsc->base;
1296 }
1297
1298 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1299 {
1300         kfree(container_of(*dsc, struct dcn20_dsc, base));
1301         *dsc = NULL;
1302 }
1303
1304
1305 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1306 {
1307         unsigned int i;
1308
1309         for (i = 0; i < pool->base.stream_enc_count; i++) {
1310                 if (pool->base.stream_enc[i] != NULL) {
1311                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1312                         pool->base.stream_enc[i] = NULL;
1313                 }
1314         }
1315
1316         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1317                 if (pool->base.dscs[i] != NULL)
1318                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1319         }
1320
1321         if (pool->base.mpc != NULL) {
1322                 kfree(TO_DCN20_MPC(pool->base.mpc));
1323                 pool->base.mpc = NULL;
1324         }
1325         if (pool->base.hubbub != NULL) {
1326                 kfree(pool->base.hubbub);
1327                 pool->base.hubbub = NULL;
1328         }
1329         for (i = 0; i < pool->base.pipe_count; i++) {
1330                 if (pool->base.dpps[i] != NULL)
1331                         dcn20_dpp_destroy(&pool->base.dpps[i]);
1332
1333                 if (pool->base.ipps[i] != NULL)
1334                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1335
1336                 if (pool->base.hubps[i] != NULL) {
1337                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1338                         pool->base.hubps[i] = NULL;
1339                 }
1340
1341                 if (pool->base.irqs != NULL) {
1342                         dal_irq_service_destroy(&pool->base.irqs);
1343                 }
1344         }
1345
1346         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1347                 if (pool->base.engines[i] != NULL)
1348                         dce110_engine_destroy(&pool->base.engines[i]);
1349                 if (pool->base.hw_i2cs[i] != NULL) {
1350                         kfree(pool->base.hw_i2cs[i]);
1351                         pool->base.hw_i2cs[i] = NULL;
1352                 }
1353                 if (pool->base.sw_i2cs[i] != NULL) {
1354                         kfree(pool->base.sw_i2cs[i]);
1355                         pool->base.sw_i2cs[i] = NULL;
1356                 }
1357         }
1358
1359         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1360                 if (pool->base.opps[i] != NULL)
1361                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1362         }
1363
1364         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1365                 if (pool->base.timing_generators[i] != NULL)    {
1366                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1367                         pool->base.timing_generators[i] = NULL;
1368                 }
1369         }
1370
1371         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1372                 if (pool->base.dwbc[i] != NULL) {
1373                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1374                         pool->base.dwbc[i] = NULL;
1375                 }
1376                 if (pool->base.mcif_wb[i] != NULL) {
1377                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1378                         pool->base.mcif_wb[i] = NULL;
1379                 }
1380         }
1381
1382         for (i = 0; i < pool->base.audio_count; i++) {
1383                 if (pool->base.audios[i])
1384                         dce_aud_destroy(&pool->base.audios[i]);
1385         }
1386
1387         for (i = 0; i < pool->base.clk_src_count; i++) {
1388                 if (pool->base.clock_sources[i] != NULL) {
1389                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1390                         pool->base.clock_sources[i] = NULL;
1391                 }
1392         }
1393
1394         if (pool->base.dp_clock_source != NULL) {
1395                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1396                 pool->base.dp_clock_source = NULL;
1397         }
1398
1399
1400         if (pool->base.abm != NULL)
1401                 dce_abm_destroy(&pool->base.abm);
1402
1403         if (pool->base.dmcu != NULL)
1404                 dce_dmcu_destroy(&pool->base.dmcu);
1405
1406         if (pool->base.dccg != NULL)
1407                 dcn_dccg_destroy(&pool->base.dccg);
1408
1409         if (pool->base.pp_smu != NULL)
1410                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1411
1412         if (pool->base.oem_device != NULL)
1413                 dal_ddc_service_destroy(&pool->base.oem_device);
1414 }
1415
1416 struct hubp *dcn20_hubp_create(
1417         struct dc_context *ctx,
1418         uint32_t inst)
1419 {
1420         struct dcn20_hubp *hubp2 =
1421                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1422
1423         if (!hubp2)
1424                 return NULL;
1425
1426         if (hubp2_construct(hubp2, ctx, inst,
1427                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1428                 return &hubp2->base;
1429
1430         BREAK_TO_DEBUGGER();
1431         kfree(hubp2);
1432         return NULL;
1433 }
1434
1435 static void get_pixel_clock_parameters(
1436         struct pipe_ctx *pipe_ctx,
1437         struct pixel_clk_params *pixel_clk_params)
1438 {
1439         const struct dc_stream_state *stream = pipe_ctx->stream;
1440         struct pipe_ctx *odm_pipe;
1441         int opp_cnt = 1;
1442
1443         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1444                 opp_cnt++;
1445
1446         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1447         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1448         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1449         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1450         /* TODO: un-hardcode*/
1451         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1452                 LINK_RATE_REF_FREQ_IN_KHZ;
1453         pixel_clk_params->flags.ENABLE_SS = 0;
1454         pixel_clk_params->color_depth =
1455                 stream->timing.display_color_depth;
1456         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1457         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1458
1459         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1460                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1461
1462         if (opp_cnt == 4)
1463                 pixel_clk_params->requested_pix_clk_100hz /= 4;
1464         else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1465                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1466
1467         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1468                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1469
1470 }
1471
1472 static void build_clamping_params(struct dc_stream_state *stream)
1473 {
1474         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1475         stream->clamping.c_depth = stream->timing.display_color_depth;
1476         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1477 }
1478
1479 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1480 {
1481
1482         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1483
1484         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1485                 pipe_ctx->clock_source,
1486                 &pipe_ctx->stream_res.pix_clk_params,
1487                 &pipe_ctx->pll_settings);
1488
1489         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1490
1491         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1492                                         &pipe_ctx->stream->bit_depth_params);
1493         build_clamping_params(pipe_ctx->stream);
1494
1495         return DC_OK;
1496 }
1497
1498 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1499 {
1500         enum dc_status status = DC_OK;
1501         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1502
1503         /*TODO Seems unneeded anymore */
1504         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1505                         if (stream != NULL && old_context->streams[i] != NULL) {
1506                                  todo: shouldn't have to copy missing parameter here
1507                                 resource_build_bit_depth_reduction_params(stream,
1508                                                 &stream->bit_depth_params);
1509                                 stream->clamping.pixel_encoding =
1510                                                 stream->timing.pixel_encoding;
1511
1512                                 resource_build_bit_depth_reduction_params(stream,
1513                                                                 &stream->bit_depth_params);
1514                                 build_clamping_params(stream);
1515
1516                                 continue;
1517                         }
1518                 }
1519         */
1520
1521         if (!pipe_ctx)
1522                 return DC_ERROR_UNEXPECTED;
1523
1524
1525         status = build_pipe_hw_param(pipe_ctx);
1526
1527         return status;
1528 }
1529
1530
1531 static void acquire_dsc(struct resource_context *res_ctx,
1532                         const struct resource_pool *pool,
1533                         struct display_stream_compressor **dsc,
1534                         int pipe_idx)
1535 {
1536         int i;
1537
1538         ASSERT(*dsc == NULL);
1539         *dsc = NULL;
1540
1541         if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1542                 *dsc = pool->dscs[pipe_idx];
1543                 res_ctx->is_dsc_acquired[pipe_idx] = true;
1544                 return;
1545         }
1546
1547         /* Find first free DSC */
1548         for (i = 0; i < pool->res_cap->num_dsc; i++)
1549                 if (!res_ctx->is_dsc_acquired[i]) {
1550                         *dsc = pool->dscs[i];
1551                         res_ctx->is_dsc_acquired[i] = true;
1552                         break;
1553                 }
1554 }
1555
1556 static void release_dsc(struct resource_context *res_ctx,
1557                         const struct resource_pool *pool,
1558                         struct display_stream_compressor **dsc)
1559 {
1560         int i;
1561
1562         for (i = 0; i < pool->res_cap->num_dsc; i++)
1563                 if (pool->dscs[i] == *dsc) {
1564                         res_ctx->is_dsc_acquired[i] = false;
1565                         *dsc = NULL;
1566                         break;
1567                 }
1568 }
1569
1570
1571
1572 static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
1573                 struct dc_state *dc_ctx,
1574                 struct dc_stream_state *dc_stream)
1575 {
1576         enum dc_status result = DC_OK;
1577         int i;
1578         const struct resource_pool *pool = dc->res_pool;
1579
1580         /* Get a DSC if required and available */
1581         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1582                 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1583
1584                 if (pipe_ctx->stream != dc_stream)
1585                         continue;
1586
1587                 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
1588
1589                 /* The number of DSCs can be less than the number of pipes */
1590                 if (!pipe_ctx->stream_res.dsc) {
1591                         result = DC_NO_DSC_RESOURCE;
1592                 }
1593
1594                 break;
1595         }
1596
1597         return result;
1598 }
1599
1600
1601 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1602                 struct dc_state *new_ctx,
1603                 struct dc_stream_state *dc_stream)
1604 {
1605         struct pipe_ctx *pipe_ctx = NULL;
1606         int i;
1607
1608         for (i = 0; i < MAX_PIPES; i++) {
1609                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1610                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1611
1612                         if (pipe_ctx->stream_res.dsc)
1613                                 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1614                 }
1615         }
1616
1617         if (!pipe_ctx)
1618                 return DC_ERROR_UNEXPECTED;
1619         else
1620                 return DC_OK;
1621 }
1622
1623
1624 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1625 {
1626         enum dc_status result = DC_ERROR_UNEXPECTED;
1627
1628         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1629
1630         if (result == DC_OK)
1631                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1632
1633         /* Get a DSC if required and available */
1634         if (result == DC_OK && dc_stream->timing.flags.DSC)
1635                 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1636
1637         if (result == DC_OK)
1638                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1639
1640         return result;
1641 }
1642
1643
1644 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1645 {
1646         enum dc_status result = DC_OK;
1647
1648         result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1649
1650         return result;
1651 }
1652
1653
1654 static void swizzle_to_dml_params(
1655                 enum swizzle_mode_values swizzle,
1656                 unsigned int *sw_mode)
1657 {
1658         switch (swizzle) {
1659         case DC_SW_LINEAR:
1660                 *sw_mode = dm_sw_linear;
1661                 break;
1662         case DC_SW_4KB_S:
1663                 *sw_mode = dm_sw_4kb_s;
1664                 break;
1665         case DC_SW_4KB_S_X:
1666                 *sw_mode = dm_sw_4kb_s_x;
1667                 break;
1668         case DC_SW_4KB_D:
1669                 *sw_mode = dm_sw_4kb_d;
1670                 break;
1671         case DC_SW_4KB_D_X:
1672                 *sw_mode = dm_sw_4kb_d_x;
1673                 break;
1674         case DC_SW_64KB_S:
1675                 *sw_mode = dm_sw_64kb_s;
1676                 break;
1677         case DC_SW_64KB_S_X:
1678                 *sw_mode = dm_sw_64kb_s_x;
1679                 break;
1680         case DC_SW_64KB_S_T:
1681                 *sw_mode = dm_sw_64kb_s_t;
1682                 break;
1683         case DC_SW_64KB_D:
1684                 *sw_mode = dm_sw_64kb_d;
1685                 break;
1686         case DC_SW_64KB_D_X:
1687                 *sw_mode = dm_sw_64kb_d_x;
1688                 break;
1689         case DC_SW_64KB_D_T:
1690                 *sw_mode = dm_sw_64kb_d_t;
1691                 break;
1692         case DC_SW_64KB_R_X:
1693                 *sw_mode = dm_sw_64kb_r_x;
1694                 break;
1695         case DC_SW_VAR_S:
1696                 *sw_mode = dm_sw_var_s;
1697                 break;
1698         case DC_SW_VAR_S_X:
1699                 *sw_mode = dm_sw_var_s_x;
1700                 break;
1701         case DC_SW_VAR_D:
1702                 *sw_mode = dm_sw_var_d;
1703                 break;
1704         case DC_SW_VAR_D_X:
1705                 *sw_mode = dm_sw_var_d_x;
1706                 break;
1707
1708         default:
1709                 ASSERT(0); /* Not supported */
1710                 break;
1711         }
1712 }
1713
1714 bool dcn20_split_stream_for_odm(
1715                 struct resource_context *res_ctx,
1716                 const struct resource_pool *pool,
1717                 struct pipe_ctx *prev_odm_pipe,
1718                 struct pipe_ctx *next_odm_pipe)
1719 {
1720         int pipe_idx = next_odm_pipe->pipe_idx;
1721
1722         *next_odm_pipe = *prev_odm_pipe;
1723
1724         next_odm_pipe->pipe_idx = pipe_idx;
1725         next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1726         next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1727         next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1728         next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1729         next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1730         next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1731         next_odm_pipe->stream_res.dsc = NULL;
1732         if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1733                 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1734                 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1735         }
1736         prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1737         next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1738         ASSERT(next_odm_pipe->top_pipe == NULL);
1739
1740         if (prev_odm_pipe->plane_state) {
1741                 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1742                 int new_width;
1743
1744                 /* HACTIVE halved for odm combine */
1745                 sd->h_active /= 2;
1746                 /* Calculate new vp and recout for left pipe */
1747                 /* Need at least 16 pixels width per side */
1748                 if (sd->recout.x + 16 >= sd->h_active)
1749                         return false;
1750                 new_width = sd->h_active - sd->recout.x;
1751                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1752                                 sd->ratios.horz, sd->recout.width - new_width));
1753                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1754                                 sd->ratios.horz_c, sd->recout.width - new_width));
1755                 sd->recout.width = new_width;
1756
1757                 /* Calculate new vp and recout for right pipe */
1758                 sd = &next_odm_pipe->plane_res.scl_data;
1759                 /* HACTIVE halved for odm combine */
1760                 sd->h_active /= 2;
1761                 /* Need at least 16 pixels width per side */
1762                 if (new_width <= 16)
1763                         return false;
1764                 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1765                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1766                                 sd->ratios.horz, sd->recout.width - new_width));
1767                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1768                                 sd->ratios.horz_c, sd->recout.width - new_width));
1769                 sd->recout.width = new_width;
1770                 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1771                                 sd->ratios.horz, sd->h_active - sd->recout.x));
1772                 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1773                                 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1774                 sd->recout.x = 0;
1775         }
1776         next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1777         if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1778                 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1779                 ASSERT(next_odm_pipe->stream_res.dsc);
1780                 if (next_odm_pipe->stream_res.dsc == NULL)
1781                         return false;
1782         }
1783
1784         return true;
1785 }
1786
1787 void dcn20_split_stream_for_mpc(
1788                 struct resource_context *res_ctx,
1789                 const struct resource_pool *pool,
1790                 struct pipe_ctx *primary_pipe,
1791                 struct pipe_ctx *secondary_pipe)
1792 {
1793         int pipe_idx = secondary_pipe->pipe_idx;
1794         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1795
1796         *secondary_pipe = *primary_pipe;
1797         secondary_pipe->bottom_pipe = sec_bot_pipe;
1798
1799         secondary_pipe->pipe_idx = pipe_idx;
1800         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1801         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1802         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1803         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1804         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1805         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1806         secondary_pipe->stream_res.dsc = NULL;
1807         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1808                 ASSERT(!secondary_pipe->bottom_pipe);
1809                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1810                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1811         }
1812         primary_pipe->bottom_pipe = secondary_pipe;
1813         secondary_pipe->top_pipe = primary_pipe;
1814
1815         ASSERT(primary_pipe->plane_state);
1816         resource_build_scaling_params(primary_pipe);
1817         resource_build_scaling_params(secondary_pipe);
1818 }
1819
1820 void dcn20_populate_dml_writeback_from_context(
1821                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1822 {
1823         int pipe_cnt, i;
1824
1825         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1826                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1827
1828                 if (!res_ctx->pipe_ctx[i].stream)
1829                         continue;
1830
1831                 /* Set writeback information */
1832                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1833                 pipes[pipe_cnt].dout.num_active_wb++;
1834                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1835                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1836                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1837                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1838                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1839                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1840                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1841                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1842                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1843                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1844                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1845                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1846                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1847                         else
1848                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1849                 } else
1850                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1851
1852                 pipe_cnt++;
1853         }
1854
1855 }
1856
1857 int dcn20_populate_dml_pipes_from_context(
1858                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1859 {
1860         int pipe_cnt, i;
1861         bool synchronized_vblank = true;
1862         struct resource_context *res_ctx = &context->res_ctx;
1863
1864         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1865                 if (!res_ctx->pipe_ctx[i].stream)
1866                         continue;
1867
1868                 if (pipe_cnt < 0) {
1869                         pipe_cnt = i;
1870                         continue;
1871                 }
1872                 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
1873                                 res_ctx->pipe_ctx[pipe_cnt].stream,
1874                                 res_ctx->pipe_ctx[i].stream)) {
1875                         synchronized_vblank = false;
1876                         break;
1877                 }
1878         }
1879
1880         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1881                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1882                 unsigned int v_total;
1883                 int output_bpc;
1884
1885                 if (!res_ctx->pipe_ctx[i].stream)
1886                         continue;
1887
1888                 v_total = timing->v_total;
1889                 /* todo:
1890                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
1891                 pipes[pipe_cnt].pipe.src.dcc = 0;
1892                 pipes[pipe_cnt].pipe.src.vm = 0;*/
1893
1894                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1895                 /* todo: rotation?*/
1896                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1897                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1898                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1899                         /* 1/2 vblank */
1900                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1901                                 (v_total - timing->v_addressable
1902                                         - timing->v_border_top - timing->v_border_bottom) / 2;
1903                         /* 36 bytes dp, 32 hdmi */
1904                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1905                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1906                 }
1907                 pipes[pipe_cnt].pipe.src.dcc = false;
1908                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1909                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1910                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1911                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1912                                 - timing->h_addressable
1913                                 - timing->h_border_left
1914                                 - timing->h_border_right;
1915                 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;
1916                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1917                                 - timing->v_addressable
1918                                 - timing->v_border_top
1919                                 - timing->v_border_bottom;
1920                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1921                 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
1922                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1923                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1924                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1925                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1926                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1927                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1928                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1929                 pipes[pipe_cnt].dout.dp_lanes = 4;
1930                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1931                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1932                 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1933                                                         || res_ctx->pipe_ctx[i].next_odm_pipe;
1934                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1935                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1936                                 == res_ctx->pipe_ctx[i].plane_state)
1937                         pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1938                 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1939                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1940
1941                         while (first_pipe->prev_odm_pipe)
1942                                 first_pipe = first_pipe->prev_odm_pipe;
1943                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1944                 }
1945
1946                 switch (res_ctx->pipe_ctx[i].stream->signal) {
1947                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1948                 case SIGNAL_TYPE_DISPLAY_PORT:
1949                         pipes[pipe_cnt].dout.output_type = dm_dp;
1950                         break;
1951                 case SIGNAL_TYPE_EDP:
1952                         pipes[pipe_cnt].dout.output_type = dm_edp;
1953                         break;
1954                 case SIGNAL_TYPE_HDMI_TYPE_A:
1955                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1956                 case SIGNAL_TYPE_DVI_DUAL_LINK:
1957                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
1958                         break;
1959                 default:
1960                         /* In case there is no signal, set dp with 4 lanes to allow max config */
1961                         pipes[pipe_cnt].dout.output_type = dm_dp;
1962                         pipes[pipe_cnt].dout.dp_lanes = 4;
1963                 }
1964
1965                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1966                 case COLOR_DEPTH_666:
1967                         output_bpc = 6;
1968                         break;
1969                 case COLOR_DEPTH_888:
1970                         output_bpc = 8;
1971                         break;
1972                 case COLOR_DEPTH_101010:
1973                         output_bpc = 10;
1974                         break;
1975                 case COLOR_DEPTH_121212:
1976                         output_bpc = 12;
1977                         break;
1978                 case COLOR_DEPTH_141414:
1979                         output_bpc = 14;
1980                         break;
1981                 case COLOR_DEPTH_161616:
1982                         output_bpc = 16;
1983                         break;
1984                 case COLOR_DEPTH_999:
1985                         output_bpc = 9;
1986                         break;
1987                 case COLOR_DEPTH_111111:
1988                         output_bpc = 11;
1989                         break;
1990                 default:
1991                         output_bpc = 8;
1992                         break;
1993                 }
1994
1995                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
1996                 case PIXEL_ENCODING_RGB:
1997                 case PIXEL_ENCODING_YCBCR444:
1998                         pipes[pipe_cnt].dout.output_format = dm_444;
1999                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2000                         break;
2001                 case PIXEL_ENCODING_YCBCR420:
2002                         pipes[pipe_cnt].dout.output_format = dm_420;
2003                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2004                         break;
2005                 case PIXEL_ENCODING_YCBCR422:
2006                         if (true) /* todo */
2007                                 pipes[pipe_cnt].dout.output_format = dm_s422;
2008                         else
2009                                 pipes[pipe_cnt].dout.output_format = dm_n422;
2010                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2011                         break;
2012                 default:
2013                         pipes[pipe_cnt].dout.output_format = dm_444;
2014                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2015                 }
2016
2017                 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2018                         pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2019
2020                 /* todo: default max for now, until there is logic reflecting this in dc*/
2021                 pipes[pipe_cnt].dout.output_bpc = 12;
2022                 /*
2023                  * Use max cursor settings for calculations to minimize
2024                  * bw calculations due to cursor on/off
2025                  */
2026                 pipes[pipe_cnt].pipe.src.num_cursors = 2;
2027                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2028                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2029                 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2030                 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
2031
2032                 if (!res_ctx->pipe_ctx[i].plane_state) {
2033                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2034                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2035                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2036                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2037                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2038                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2039                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2040                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2041                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2042                         pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2043                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2044                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2045                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2046                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2047                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
2048                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2049                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2050                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2051                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2052                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2053                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2054                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2055                         pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2056                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2057                         pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2058                         pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2059                 } else {
2060                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2061                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2062
2063                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2064                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2065                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2066                                         || (res_ctx->pipe_ctx[i].top_pipe
2067                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
2068                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2069                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2070                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2071                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2072                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2073                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2074                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2075                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2076                         pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2077                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2078                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2079                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2080                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2081                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2082                         } else {
2083                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2084                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2085                         }
2086                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2087                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2088                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2089                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2090                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2091                         if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
2092                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2093                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2094                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2095                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2096                         } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
2097                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2098                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2099                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2100                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
2101                         }
2102
2103                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2104                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2105                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2106                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2107                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2108                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2109                                         scl->ratios.vert.value != dc_fixpt_one.value
2110                                         || scl->ratios.horz.value != dc_fixpt_one.value
2111                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
2112                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2113                                         || dc->debug.always_scale; /*support always scale*/
2114                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2115                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2116                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2117                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2118
2119                         pipes[pipe_cnt].pipe.src.macro_tile_size =
2120                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2121                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2122                                         &pipes[pipe_cnt].pipe.src.sw_mode);
2123
2124                         switch (pln->format) {
2125                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2126                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2127                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2128                                 break;
2129                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2130                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2131                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2132                                 break;
2133                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2134                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2135                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2136                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2137                                 break;
2138                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2139                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2140                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2141                                 break;
2142                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2143                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2144                                 break;
2145                         default:
2146                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2147                                 break;
2148                         }
2149                 }
2150
2151                 pipe_cnt++;
2152         }
2153
2154         /* populate writeback information */
2155         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2156
2157         return pipe_cnt;
2158 }
2159
2160 unsigned int dcn20_calc_max_scaled_time(
2161                 unsigned int time_per_pixel,
2162                 enum mmhubbub_wbif_mode mode,
2163                 unsigned int urgent_watermark)
2164 {
2165         unsigned int time_per_byte = 0;
2166         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2167         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2168         unsigned int small_free_entry, max_free_entry;
2169         unsigned int buf_lh_capability;
2170         unsigned int max_scaled_time;
2171
2172         if (mode == PACKED_444) /* packed mode */
2173                 time_per_byte = time_per_pixel/4;
2174         else if (mode == PLANAR_420_8BPC)
2175                 time_per_byte  = time_per_pixel;
2176         else if (mode == PLANAR_420_10BPC) /* p010 */
2177                 time_per_byte  = time_per_pixel * 819/1024;
2178
2179         if (time_per_byte == 0)
2180                 time_per_byte = 1;
2181
2182         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2183         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2184         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2185         max_scaled_time   = buf_lh_capability - urgent_watermark;
2186         return max_scaled_time;
2187 }
2188
2189 void dcn20_set_mcif_arb_params(
2190                 struct dc *dc,
2191                 struct dc_state *context,
2192                 display_e2e_pipe_params_st *pipes,
2193                 int pipe_cnt)
2194 {
2195         enum mmhubbub_wbif_mode wbif_mode;
2196         struct mcif_arb_params *wb_arb_params;
2197         int i, j, k, dwb_pipe;
2198
2199         /* Writeback MCIF_WB arbitration parameters */
2200         dwb_pipe = 0;
2201         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2202
2203                 if (!context->res_ctx.pipe_ctx[i].stream)
2204                         continue;
2205
2206                 for (j = 0; j < MAX_DWB_PIPES; j++) {
2207                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2208                                 continue;
2209
2210                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2211                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2212
2213                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2214                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2215                                         wbif_mode = PLANAR_420_8BPC;
2216                                 else
2217                                         wbif_mode = PLANAR_420_10BPC;
2218                         } else
2219                                 wbif_mode = PACKED_444;
2220
2221                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2222                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2223                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2224                         }
2225                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2226                         wb_arb_params->slice_lines = 32;
2227                         wb_arb_params->arbitration_slice = 2;
2228                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2229                                 wbif_mode,
2230                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2231
2232                         dwb_pipe++;
2233
2234                         if (dwb_pipe >= MAX_DWB_PIPES)
2235                                 return;
2236                 }
2237                 if (dwb_pipe >= MAX_DWB_PIPES)
2238                         return;
2239         }
2240 }
2241
2242 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2243 {
2244         int i;
2245
2246         /* Validate DSC config, dsc count validation is already done */
2247         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2248                 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2249                 struct dc_stream_state *stream = pipe_ctx->stream;
2250                 struct dsc_config dsc_cfg;
2251                 struct pipe_ctx *odm_pipe;
2252                 int opp_cnt = 1;
2253
2254                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2255                         opp_cnt++;
2256
2257                 /* Only need to validate top pipe */
2258                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2259                         continue;
2260
2261                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2262                                 + stream->timing.h_border_right) / opp_cnt;
2263                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2264                                 + stream->timing.v_border_bottom;
2265                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2266                 dsc_cfg.color_depth = stream->timing.display_color_depth;
2267                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2268                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2269
2270                 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2271                         return false;
2272         }
2273         return true;
2274 }
2275
2276 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2277                 struct resource_context *res_ctx,
2278                 const struct resource_pool *pool,
2279                 const struct pipe_ctx *primary_pipe)
2280 {
2281         struct pipe_ctx *secondary_pipe = NULL;
2282
2283         if (dc && primary_pipe) {
2284                 int j;
2285                 int preferred_pipe_idx = 0;
2286
2287                 /* first check the prev dc state:
2288                  * if this primary pipe has a bottom pipe in prev. state
2289                  * and if the bottom pipe is still available (which it should be),
2290                  * pick that pipe as secondary
2291                  * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2292                  * check in else case.
2293                  */
2294                 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2295                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2296                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2297                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2298                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2299                         }
2300                 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2301                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2302                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2303                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2304                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2305                         }
2306                 }
2307
2308                 /*
2309                  * if this primary pipe does not have a bottom pipe in prev. state
2310                  * start backward and find a pipe that did not used to be a bottom pipe in
2311                  * prev. dc state. This way we make sure we keep the same assignment as
2312                  * last state and will not have to reprogram every pipe
2313                  */
2314                 if (secondary_pipe == NULL) {
2315                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2316                                 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2317                                                 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2318                                         preferred_pipe_idx = j;
2319
2320                                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2321                                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2322                                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2323                                                 break;
2324                                         }
2325                                 }
2326                         }
2327                 }
2328                 /*
2329                  * We should never hit this assert unless assignments are shuffled around
2330                  * if this happens we will prob. hit a vsync tdr
2331                  */
2332                 ASSERT(secondary_pipe);
2333                 /*
2334                  * search backwards for the second pipe to keep pipe
2335                  * assignment more consistent
2336                  */
2337                 if (secondary_pipe == NULL) {
2338                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2339                                 preferred_pipe_idx = j;
2340
2341                                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2342                                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2343                                         secondary_pipe->pipe_idx = preferred_pipe_idx;
2344                                         break;
2345                                 }
2346                         }
2347                 }
2348         }
2349
2350         return secondary_pipe;
2351 }
2352
2353 void dcn20_merge_pipes_for_validate(
2354                 struct dc *dc,
2355                 struct dc_state *context)
2356 {
2357         int i;
2358
2359         /* merge previously split odm pipes since mode support needs to make the decision */
2360         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2361                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2362                 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2363
2364                 if (pipe->prev_odm_pipe)
2365                         continue;
2366
2367                 pipe->next_odm_pipe = NULL;
2368                 while (odm_pipe) {
2369                         struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2370
2371                         odm_pipe->plane_state = NULL;
2372                         odm_pipe->stream = NULL;
2373                         odm_pipe->top_pipe = NULL;
2374                         odm_pipe->bottom_pipe = NULL;
2375                         odm_pipe->prev_odm_pipe = NULL;
2376                         odm_pipe->next_odm_pipe = NULL;
2377                         if (odm_pipe->stream_res.dsc)
2378                                 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2379                         /* Clear plane_res and stream_res */
2380                         memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2381                         memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2382                         odm_pipe = next_odm_pipe;
2383                 }
2384                 if (pipe->plane_state)
2385                         resource_build_scaling_params(pipe);
2386         }
2387
2388         /* merge previously mpc split pipes since mode support needs to make the decision */
2389         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2390                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2391                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2392
2393                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2394                         continue;
2395
2396                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2397                 if (hsplit_pipe->bottom_pipe)
2398                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
2399                 hsplit_pipe->plane_state = NULL;
2400                 hsplit_pipe->stream = NULL;
2401                 hsplit_pipe->top_pipe = NULL;
2402                 hsplit_pipe->bottom_pipe = NULL;
2403
2404                 /* Clear plane_res and stream_res */
2405                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2406                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2407                 if (pipe->plane_state)
2408                         resource_build_scaling_params(pipe);
2409         }
2410 }
2411
2412 int dcn20_validate_apply_pipe_split_flags(
2413                 struct dc *dc,
2414                 struct dc_state *context,
2415                 int vlevel,
2416                 bool *split)
2417 {
2418         int i, pipe_idx, vlevel_split;
2419         bool force_split = false;
2420         bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2421
2422         /* Single display loop, exits if there is more than one display */
2423         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2424                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2425                 bool exit_loop = false;
2426
2427                 if (!pipe->stream || pipe->top_pipe)
2428                         continue;
2429
2430                 if (dc->debug.force_single_disp_pipe_split) {
2431                         if (!force_split)
2432                                 force_split = true;
2433                         else {
2434                                 force_split = false;
2435                                 exit_loop = true;
2436                         }
2437                 }
2438                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2439                         if (avoid_split)
2440                                 avoid_split = false;
2441                         else {
2442                                 avoid_split = true;
2443                                 exit_loop = true;
2444                         }
2445                 }
2446                 if (exit_loop)
2447                         break;
2448         }
2449         /* TODO: fix dc bugs and remove this split threshold thing */
2450         if (context->stream_count > dc->res_pool->pipe_count / 2)
2451                 avoid_split = true;
2452
2453         /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2454         if (avoid_split) {
2455                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2456                         if (!context->res_ctx.pipe_ctx[i].stream)
2457                                 continue;
2458
2459                         for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2460                                 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2461                                         break;
2462                         /* Impossible to not split this pipe */
2463                         if (vlevel > context->bw_ctx.dml.soc.num_states)
2464                                 vlevel = vlevel_split;
2465                         pipe_idx++;
2466                 }
2467                 context->bw_ctx.dml.vba.maxMpcComb = 0;
2468         }
2469
2470         /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2471         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2472                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2473
2474                 if (!context->res_ctx.pipe_ctx[i].stream)
2475                         continue;
2476
2477                 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2478                         split[i] = true;
2479                 if ((pipe->stream->view_format ==
2480                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2481                                 pipe->stream->view_format ==
2482                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2483                                 (pipe->stream->timing.timing_3d_format ==
2484                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2485                                  pipe->stream->timing.timing_3d_format ==
2486                                 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2487                         split[i] = true;
2488                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2489                         split[i] = true;
2490                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2491                 }
2492                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
2493                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2494                 /* Adjust dppclk when split is forced, do not bother with dispclk */
2495                 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2496                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2497                 pipe_idx++;
2498         }
2499
2500         return vlevel;
2501 }
2502
2503 bool dcn20_fast_validate_bw(
2504                 struct dc *dc,
2505                 struct dc_state *context,
2506                 display_e2e_pipe_params_st *pipes,
2507                 int *pipe_cnt_out,
2508                 int *pipe_split_from,
2509                 int *vlevel_out)
2510 {
2511         bool out = false;
2512         bool split[MAX_PIPES] = { false };
2513         int pipe_cnt, i, pipe_idx, vlevel;
2514
2515         ASSERT(pipes);
2516         if (!pipes)
2517                 return false;
2518
2519         dcn20_merge_pipes_for_validate(dc, context);
2520
2521         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2522
2523         *pipe_cnt_out = pipe_cnt;
2524
2525         if (!pipe_cnt) {
2526                 out = true;
2527                 goto validate_out;
2528         }
2529
2530         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2531
2532         if (vlevel > context->bw_ctx.dml.soc.num_states)
2533                 goto validate_fail;
2534
2535         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
2536
2537         /*initialize pipe_just_split_from to invalid idx*/
2538         for (i = 0; i < MAX_PIPES; i++)
2539                 pipe_split_from[i] = -1;
2540
2541         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2542                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2543                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2544
2545                 if (!pipe->stream || pipe_split_from[i] >= 0)
2546                         continue;
2547
2548                 pipe_idx++;
2549
2550                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2551                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2552                         ASSERT(hsplit_pipe);
2553                         if (!dcn20_split_stream_for_odm(
2554                                         &context->res_ctx, dc->res_pool,
2555                                         pipe, hsplit_pipe))
2556                                 goto validate_fail;
2557                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2558                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2559                 }
2560
2561                 if (!pipe->plane_state)
2562                         continue;
2563                 /* Skip 2nd half of already split pipe */
2564                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2565                         continue;
2566
2567                 /* We do not support mpo + odm at the moment */
2568                 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2569                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2570                         goto validate_fail;
2571
2572                 if (split[i]) {
2573                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2574                                 /* pipe not split previously needs split */
2575                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2576                                 ASSERT(hsplit_pipe);
2577                                 if (!hsplit_pipe) {
2578                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2579                                         continue;
2580                                 }
2581                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2582                                         if (!dcn20_split_stream_for_odm(
2583                                                         &context->res_ctx, dc->res_pool,
2584                                                         pipe, hsplit_pipe))
2585                                                 goto validate_fail;
2586                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2587                                 } else
2588                                         dcn20_split_stream_for_mpc(
2589                                                 &context->res_ctx, dc->res_pool,
2590                                                 pipe, hsplit_pipe);
2591                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2592                         }
2593                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2594                         /* merge should already have been done */
2595                         ASSERT(0);
2596                 }
2597         }
2598         /* Actual dsc count per stream dsc validation*/
2599         if (!dcn20_validate_dsc(dc, context)) {
2600                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2601                                 DML_FAIL_DSC_VALIDATION_FAILURE;
2602                 goto validate_fail;
2603         }
2604
2605         *vlevel_out = vlevel;
2606
2607         out = true;
2608         goto validate_out;
2609
2610 validate_fail:
2611         out = false;
2612
2613 validate_out:
2614         return out;
2615 }
2616
2617 static void dcn20_calculate_wm(
2618                 struct dc *dc, struct dc_state *context,
2619                 display_e2e_pipe_params_st *pipes,
2620                 int *out_pipe_cnt,
2621                 int *pipe_split_from,
2622                 int vlevel)
2623 {
2624         int pipe_cnt, i, pipe_idx;
2625
2626         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2627                 if (!context->res_ctx.pipe_ctx[i].stream)
2628                         continue;
2629
2630                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2631                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2632
2633                 if (pipe_split_from[i] < 0) {
2634                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2635                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2636                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2637                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2638                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2639                         else
2640                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2641                         pipe_idx++;
2642                 } else {
2643                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2644                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2645                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2646                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2647                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2648                         else
2649                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2650                 }
2651
2652                 if (dc->config.forced_clocks) {
2653                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2654                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2655                 }
2656                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2657                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2658                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2659                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2660
2661                 pipe_cnt++;
2662         }
2663
2664         if (pipe_cnt != pipe_idx) {
2665                 if (dc->res_pool->funcs->populate_dml_pipes)
2666                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2667                                 context, pipes);
2668                 else
2669                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2670                                 context, pipes);
2671         }
2672
2673         *out_pipe_cnt = pipe_cnt;
2674
2675         pipes[0].clks_cfg.voltage = vlevel;
2676         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2677         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2678
2679         /* only pipe 0 is read for voltage and dcf/soc clocks */
2680         if (vlevel < 1) {
2681                 pipes[0].clks_cfg.voltage = 1;
2682                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2683                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2684         }
2685         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2686         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2687         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2688         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2689         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2690         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2691         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2692         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2693
2694         if (vlevel < 2) {
2695                 pipes[0].clks_cfg.voltage = 2;
2696                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2697                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2698         }
2699         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2700         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2701         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2702         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2703         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2704         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2705         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2706
2707         if (vlevel < 3) {
2708                 pipes[0].clks_cfg.voltage = 3;
2709                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2710                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2711         }
2712         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2713         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2714         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2715         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2716         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2717         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2718         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2719
2720         pipes[0].clks_cfg.voltage = vlevel;
2721         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2722         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2723         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2724         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2725         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2726         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2727         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2728         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 }
2731
2732 void dcn20_calculate_dlg_params(
2733                 struct dc *dc, struct dc_state *context,
2734                 display_e2e_pipe_params_st *pipes,
2735                 int pipe_cnt,
2736                 int vlevel)
2737 {
2738         int i, j, pipe_idx, pipe_idx_unsplit;
2739         bool visited[MAX_PIPES] = { 0 };
2740
2741         /* Writeback MCIF_WB arbitration parameters */
2742         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2743
2744         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2745         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2746         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2747         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2748         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2749         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2750         context->bw_ctx.bw.dcn.clk.p_state_change_support =
2751                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2752                                                         != dm_dram_clock_change_unsupported;
2753         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2754
2755         /*
2756          * An artifact of dml pipe split/odm is that pipes get merged back together for
2757          * calculation. Therefore we need to only extract for first pipe in ascending index order
2758          * and copy into the other split half.
2759          */
2760         for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2761                 if (!context->res_ctx.pipe_ctx[i].stream)
2762                         continue;
2763
2764                 if (!visited[pipe_idx]) {
2765                         display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2766                         display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
2767
2768                         dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2769                         dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2770                         dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2771                         dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2772                         /*
2773                          * j iterates inside pipes array, unlike i which iterates inside
2774                          * pipe_ctx array
2775                          */
2776                         if (src->is_hsplit)
2777                                 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2778                                         display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2779                                         display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2780
2781                                         if (src_j->is_hsplit && !visited[j]
2782                                                         && src->hsplit_grp == src_j->hsplit_grp) {
2783                                                 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2784                                                 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2785                                                 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2786                                                 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2787                                                 visited[j] = true;
2788                                         }
2789                                 }
2790                         visited[pipe_idx] = true;
2791                         pipe_idx_unsplit++;
2792                 }
2793                 pipe_idx++;
2794         }
2795
2796         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2797                 if (!context->res_ctx.pipe_ctx[i].stream)
2798                         continue;
2799                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2800                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2801                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2802                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2803                 ASSERT(visited[pipe_idx]);
2804                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2805                 pipe_idx++;
2806         }
2807         /*save a original dppclock copy*/
2808         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2809         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2810         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2811         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
2812
2813         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2814                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2815
2816                 if (!context->res_ctx.pipe_ctx[i].stream)
2817                         continue;
2818
2819                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2820                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2821                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
2822                                 pipes,
2823                                 pipe_cnt,
2824                                 pipe_idx,
2825                                 cstate_en,
2826                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2827                                 false, false, false);
2828
2829                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2830                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2831                                 pipes[pipe_idx].pipe);
2832                 pipe_idx++;
2833         }
2834 }
2835
2836 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2837                 bool fast_validate)
2838 {
2839         bool out = false;
2840
2841         BW_VAL_TRACE_SETUP();
2842
2843         int vlevel = 0;
2844         int pipe_split_from[MAX_PIPES];
2845         int pipe_cnt = 0;
2846         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2847         DC_LOGGER_INIT(dc->ctx->logger);
2848
2849         BW_VAL_TRACE_COUNT();
2850
2851         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2852
2853         if (pipe_cnt == 0)
2854                 goto validate_out;
2855
2856         if (!out)
2857                 goto validate_fail;
2858
2859         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2860
2861         if (fast_validate) {
2862                 BW_VAL_TRACE_SKIP(fast);
2863                 goto validate_out;
2864         }
2865
2866         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2867         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2868
2869         BW_VAL_TRACE_END_WATERMARKS();
2870
2871         goto validate_out;
2872
2873 validate_fail:
2874         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2875                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2876
2877         BW_VAL_TRACE_SKIP(fail);
2878         out = false;
2879
2880 validate_out:
2881         kfree(pipes);
2882
2883         BW_VAL_TRACE_FINISH();
2884
2885         return out;
2886 }
2887
2888
2889 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2890                 bool fast_validate)
2891 {
2892         bool voltage_supported = false;
2893         bool full_pstate_supported = false;
2894         bool dummy_pstate_supported = false;
2895         double p_state_latency_us;
2896
2897         DC_FP_START();
2898         p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2899         context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
2900                 dc->debug.disable_dram_clock_change_vactive_support;
2901
2902         if (fast_validate) {
2903                 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
2904
2905                 DC_FP_END();
2906                 return voltage_supported;
2907         }
2908
2909         // Best case, we support full UCLK switch latency
2910         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2911         full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2912
2913         if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2914                 (voltage_supported && full_pstate_supported)) {
2915                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2916                 goto restore_dml_state;
2917         }
2918
2919         // Fallback: Try to only support G6 temperature read latency
2920         context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2921
2922         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2923         dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2924
2925         if (voltage_supported && dummy_pstate_supported) {
2926                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2927                 goto restore_dml_state;
2928         }
2929
2930         // ERROR: fallback is supposed to always work.
2931         ASSERT(false);
2932
2933 restore_dml_state:
2934         context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2935
2936         DC_FP_END();
2937         return voltage_supported;
2938 }
2939
2940 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2941                 struct dc_state *state,
2942                 const struct resource_pool *pool,
2943                 struct dc_stream_state *stream)
2944 {
2945         struct resource_context *res_ctx = &state->res_ctx;
2946         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2947         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2948
2949         if (!head_pipe)
2950                 ASSERT(0);
2951
2952         if (!idle_pipe)
2953                 return NULL;
2954
2955         idle_pipe->stream = head_pipe->stream;
2956         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2957         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2958
2959         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2960         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2961         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2962         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2963
2964         return idle_pipe;
2965 }
2966
2967 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2968                 const struct dc_dcc_surface_param *input,
2969                 struct dc_surface_dcc_cap *output)
2970 {
2971         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2972                         dc->res_pool->hubbub,
2973                         input,
2974                         output);
2975 }
2976
2977 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2978 {
2979         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2980
2981         dcn20_resource_destruct(dcn20_pool);
2982         kfree(dcn20_pool);
2983         *pool = NULL;
2984 }
2985
2986
2987 static struct dc_cap_funcs cap_funcs = {
2988         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2989 };
2990
2991
2992 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2993 {
2994         enum dc_status result = DC_OK;
2995
2996         enum surface_pixel_format surf_pix_format = plane_state->format;
2997         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2998
2999         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3000
3001         if (bpp == 64)
3002                 swizzle = DC_SW_64KB_D;
3003         else
3004                 swizzle = DC_SW_64KB_S;
3005
3006         plane_state->tiling_info.gfx9.swizzle = swizzle;
3007         return result;
3008 }
3009
3010 static struct resource_funcs dcn20_res_pool_funcs = {
3011         .destroy = dcn20_destroy_resource_pool,
3012         .link_enc_create = dcn20_link_encoder_create,
3013         .validate_bandwidth = dcn20_validate_bandwidth,
3014         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3015         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3016         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3017         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3018         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
3019         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3020         .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3021         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3022 };
3023
3024 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3025 {
3026         int i;
3027         uint32_t pipe_count = pool->res_cap->num_dwb;
3028
3029         for (i = 0; i < pipe_count; i++) {
3030                 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3031                                                     GFP_KERNEL);
3032
3033                 if (!dwbc20) {
3034                         dm_error("DC: failed to create dwbc20!\n");
3035                         return false;
3036                 }
3037                 dcn20_dwbc_construct(dwbc20, ctx,
3038                                 &dwbc20_regs[i],
3039                                 &dwbc20_shift,
3040                                 &dwbc20_mask,
3041                                 i);
3042                 pool->dwbc[i] = &dwbc20->base;
3043         }
3044         return true;
3045 }
3046
3047 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3048 {
3049         int i;
3050         uint32_t pipe_count = pool->res_cap->num_dwb;
3051
3052         ASSERT(pipe_count > 0);
3053
3054         for (i = 0; i < pipe_count; i++) {
3055                 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3056                                                     GFP_KERNEL);
3057
3058                 if (!mcif_wb20) {
3059                         dm_error("DC: failed to create mcif_wb20!\n");
3060                         return false;
3061                 }
3062
3063                 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3064                                 &mcif_wb20_regs[i],
3065                                 &mcif_wb20_shift,
3066                                 &mcif_wb20_mask,
3067                                 i);
3068
3069                 pool->mcif_wb[i] = &mcif_wb20->base;
3070         }
3071         return true;
3072 }
3073
3074 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3075 {
3076         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3077
3078         if (!pp_smu)
3079                 return pp_smu;
3080
3081         dm_pp_get_funcs(ctx, pp_smu);
3082
3083         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3084                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3085
3086         return pp_smu;
3087 }
3088
3089 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3090 {
3091         if (pp_smu && *pp_smu) {
3092                 kfree(*pp_smu);
3093                 *pp_smu = NULL;
3094         }
3095 }
3096
3097 void dcn20_cap_soc_clocks(
3098                 struct _vcs_dpi_soc_bounding_box_st *bb,
3099                 struct pp_smu_nv_clock_table max_clocks)
3100 {
3101         int i;
3102
3103         // First pass - cap all clocks higher than the reported max
3104         for (i = 0; i < bb->num_states; i++) {
3105                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3106                                 && max_clocks.dcfClockInKhz != 0)
3107                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3108
3109                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3110                                                 && max_clocks.uClockInKhz != 0)
3111                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3112
3113                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3114                                                 && max_clocks.fabricClockInKhz != 0)
3115                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3116
3117                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3118                                                 && max_clocks.displayClockInKhz != 0)
3119                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3120
3121                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3122                                                 && max_clocks.dppClockInKhz != 0)
3123                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3124
3125                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3126                                                 && max_clocks.phyClockInKhz != 0)
3127                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3128
3129                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3130                                                 && max_clocks.socClockInKhz != 0)
3131                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3132
3133                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3134                                                 && max_clocks.dscClockInKhz != 0)
3135                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3136         }
3137
3138         // Second pass - remove all duplicate clock states
3139         for (i = bb->num_states - 1; i > 1; i--) {
3140                 bool duplicate = true;
3141
3142                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3143                         duplicate = false;
3144                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3145                         duplicate = false;
3146                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3147                         duplicate = false;
3148                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3149                         duplicate = false;
3150                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3151                         duplicate = false;
3152                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3153                         duplicate = false;
3154                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3155                         duplicate = false;
3156                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3157                         duplicate = false;
3158
3159                 if (duplicate)
3160                         bb->num_states--;
3161         }
3162 }
3163
3164 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3165                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3166 {
3167         struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
3168         int i;
3169         int num_calculated_states = 0;
3170         int min_dcfclk = 0;
3171
3172         if (num_states == 0)
3173                 return;
3174
3175         memset(calculated_states, 0, sizeof(calculated_states));
3176
3177         if (dc->bb_overrides.min_dcfclk_mhz > 0)
3178                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3179         else {
3180                 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3181                         min_dcfclk = 310;
3182                 else
3183                         // Accounting for SOC/DCF relationship, we can go as high as
3184                         // 506Mhz in Vmin.
3185                         min_dcfclk = 506;
3186         }
3187
3188         for (i = 0; i < num_states; i++) {
3189                 int min_fclk_required_by_uclk;
3190                 calculated_states[i].state = i;
3191                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3192
3193                 // FCLK:UCLK ratio is 1.08
3194                 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3195
3196                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3197                                 min_dcfclk : min_fclk_required_by_uclk;
3198
3199                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3200                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3201
3202                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3203                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3204
3205                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3206                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3207                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3208
3209                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3210
3211                 num_calculated_states++;
3212         }
3213
3214         calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3215         calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3216         calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3217
3218         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3219         bb->num_states = num_calculated_states;
3220
3221         // Duplicate the last state, DML always an extra state identical to max state to work
3222         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3223         bb->clock_limits[num_calculated_states].state = bb->num_states;
3224 }
3225
3226 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3227 {
3228         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3229                         && dc->bb_overrides.sr_exit_time_ns) {
3230                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3231         }
3232
3233         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3234                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3235                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3236                 bb->sr_enter_plus_exit_time_us =
3237                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3238         }
3239
3240         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3241                         && dc->bb_overrides.urgent_latency_ns) {
3242                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3243         }
3244
3245         if ((int)(bb->dram_clock_change_latency_us * 1000)
3246                                 != dc->bb_overrides.dram_clock_change_latency_ns
3247                         && dc->bb_overrides.dram_clock_change_latency_ns) {
3248                 bb->dram_clock_change_latency_us =
3249                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3250         }
3251 }
3252
3253 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3254         uint32_t hw_internal_rev)
3255 {
3256         if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3257                 return &dcn2_0_nv12_soc;
3258
3259         return &dcn2_0_soc;
3260 }
3261
3262 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3263         uint32_t hw_internal_rev)
3264 {
3265         /* NV14 */
3266         if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3267                 return &dcn2_0_nv14_ip;
3268
3269         /* NV12 and NV10 */
3270         return &dcn2_0_ip;
3271 }
3272
3273 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3274 {
3275         return DML_PROJECT_NAVI10v2;
3276 }
3277
3278 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3279 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3280
3281 static bool init_soc_bounding_box(struct dc *dc,
3282                                   struct dcn20_resource_pool *pool)
3283 {
3284         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3285         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3286                         get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3287         struct _vcs_dpi_ip_params_st *loaded_ip =
3288                         get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3289
3290         DC_LOGGER_INIT(dc->ctx->logger);
3291
3292         /* TODO: upstream NV12 bounding box when its launched */
3293         if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3294                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3295                 return false;
3296         }
3297
3298         if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3299                 int i;
3300
3301                 dcn2_0_nv12_soc.sr_exit_time_us =
3302                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3303                 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3304                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3305                 dcn2_0_nv12_soc.urgent_latency_us =
3306                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3307                 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3308                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3309                 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3310                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3311                 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3312                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3313                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3314                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3315                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3316                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3317                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3318                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3319                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3320                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3321                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3322                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3323                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3324                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3325                 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3326                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3327                 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3328                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3329                 dcn2_0_nv12_soc.writeback_latency_us =
3330                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3331                 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3332                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3333                 dcn2_0_nv12_soc.max_request_size_bytes =
3334                                 le32_to_cpu(bb->max_request_size_bytes);
3335                 dcn2_0_nv12_soc.dram_channel_width_bytes =
3336                                 le32_to_cpu(bb->dram_channel_width_bytes);
3337                 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3338                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3339                 dcn2_0_nv12_soc.dcn_downspread_percent =
3340                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3341                 dcn2_0_nv12_soc.downspread_percent =
3342                                 fixed16_to_double_to_cpu(bb->downspread_percent);
3343                 dcn2_0_nv12_soc.dram_page_open_time_ns =
3344                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3345                 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3346                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3347                 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3348                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3349                 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3350                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3351                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3352                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3353                 dcn2_0_nv12_soc.channel_interleave_bytes =
3354                                 le32_to_cpu(bb->channel_interleave_bytes);
3355                 dcn2_0_nv12_soc.num_banks =
3356                                 le32_to_cpu(bb->num_banks);
3357                 dcn2_0_nv12_soc.num_chans =
3358                                 le32_to_cpu(bb->num_chans);
3359                 dcn2_0_nv12_soc.vmm_page_size_bytes =
3360                                 le32_to_cpu(bb->vmm_page_size_bytes);
3361                 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3362                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3363                 // HACK!! Lower uclock latency switch time so we don't switch
3364                 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3365                 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3366                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3367                 dcn2_0_nv12_soc.return_bus_width_bytes =
3368                                 le32_to_cpu(bb->return_bus_width_bytes);
3369                 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3370                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3371                 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3372                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
3373                 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3374                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3375                 dcn2_0_nv12_soc.use_urgent_burst_bw =
3376                                 le32_to_cpu(bb->use_urgent_burst_bw);
3377                 dcn2_0_nv12_soc.num_states =
3378                                 le32_to_cpu(bb->num_states);
3379
3380                 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3381                         dcn2_0_nv12_soc.clock_limits[i].state =
3382                                         le32_to_cpu(bb->clock_limits[i].state);
3383                         dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3384                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3385                         dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3386                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3387                         dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3388                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3389                         dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3390                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3391                         dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3392                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3393                         dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3394                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3395                         dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3396                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3397                         dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3398                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3399                 }
3400         }
3401
3402         if (pool->base.pp_smu) {
3403                 struct pp_smu_nv_clock_table max_clocks = {0};
3404                 unsigned int uclk_states[8] = {0};
3405                 unsigned int num_states = 0;
3406                 enum pp_smu_status status;
3407                 bool clock_limits_available = false;
3408                 bool uclk_states_available = false;
3409
3410                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3411                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3412                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3413
3414                         uclk_states_available = (status == PP_SMU_RESULT_OK);
3415                 }
3416
3417                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3418                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3419                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3420                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3421                          */
3422                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3423                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3424                         clock_limits_available = (status == PP_SMU_RESULT_OK);
3425                 }
3426
3427                 if (clock_limits_available && uclk_states_available && num_states)
3428                         dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3429                 else if (clock_limits_available)
3430                         dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3431         }
3432
3433         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3434         loaded_ip->max_num_dpp = pool->base.pipe_count;
3435         dcn20_patch_bounding_box(dc, loaded_bb);
3436
3437         return true;
3438 }
3439
3440 static bool dcn20_resource_construct(
3441         uint8_t num_virtual_links,
3442         struct dc *dc,
3443         struct dcn20_resource_pool *pool)
3444 {
3445         int i;
3446         struct dc_context *ctx = dc->ctx;
3447         struct irq_service_init_data init_data;
3448         struct ddc_service_init_data ddc_init_data;
3449         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3450                         get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3451         struct _vcs_dpi_ip_params_st *loaded_ip =
3452                         get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3453         enum dml_project dml_project_version =
3454                         get_dml_project_version(ctx->asic_id.hw_internal_rev);
3455
3456         DC_FP_START();
3457
3458         ctx->dc_bios->regs = &bios_regs;
3459         pool->base.funcs = &dcn20_res_pool_funcs;
3460
3461         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3462                 pool->base.res_cap = &res_cap_nv14;
3463                 pool->base.pipe_count = 5;
3464                 pool->base.mpcc_count = 5;
3465         } else {
3466                 pool->base.res_cap = &res_cap_nv10;
3467                 pool->base.pipe_count = 6;
3468                 pool->base.mpcc_count = 6;
3469         }
3470         /*************************************************
3471          *  Resource + asic cap harcoding                *
3472          *************************************************/
3473         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3474
3475         dc->caps.max_downscale_ratio = 200;
3476         dc->caps.i2c_speed_in_khz = 100;
3477         dc->caps.max_cursor_size = 256;
3478         dc->caps.dmdata_alloc_size = 2048;
3479
3480         dc->caps.max_slave_planes = 1;
3481         dc->caps.post_blend_color_processing = true;
3482         dc->caps.force_dp_tps4_for_cp2520 = true;
3483         dc->caps.hw_3d_lut = true;
3484         dc->caps.extended_aux_timeout_support = true;
3485
3486         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3487                 dc->debug = debug_defaults_drv;
3488         } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3489                 pool->base.pipe_count = 4;
3490                 pool->base.mpcc_count = pool->base.pipe_count;
3491                 dc->debug = debug_defaults_diags;
3492         } else {
3493                 dc->debug = debug_defaults_diags;
3494         }
3495         //dcn2.0x
3496         dc->work_arounds.dedcn20_305_wa = true;
3497
3498         // Init the vm_helper
3499         if (dc->vm_helper)
3500                 vm_helper_init(dc->vm_helper, 16);
3501
3502         /*************************************************
3503          *  Create resources                             *
3504          *************************************************/
3505
3506         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3507                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3508                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3509                                 &clk_src_regs[0], false);
3510         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3511                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3512                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3513                                 &clk_src_regs[1], false);
3514         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3515                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3516                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3517                                 &clk_src_regs[2], false);
3518         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3519                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3520                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3521                                 &clk_src_regs[3], false);
3522         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3523                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3524                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3525                                 &clk_src_regs[4], false);
3526         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3527                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3528                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
3529                                 &clk_src_regs[5], false);
3530         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3531         /* todo: not reuse phy_pll registers */
3532         pool->base.dp_clock_source =
3533                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3534                                 CLOCK_SOURCE_ID_DP_DTO,
3535                                 &clk_src_regs[0], true);
3536
3537         for (i = 0; i < pool->base.clk_src_count; i++) {
3538                 if (pool->base.clock_sources[i] == NULL) {
3539                         dm_error("DC: failed to create clock sources!\n");
3540                         BREAK_TO_DEBUGGER();
3541                         goto create_fail;
3542                 }
3543         }
3544
3545         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3546         if (pool->base.dccg == NULL) {
3547                 dm_error("DC: failed to create dccg!\n");
3548                 BREAK_TO_DEBUGGER();
3549                 goto create_fail;
3550         }
3551
3552         pool->base.dmcu = dcn20_dmcu_create(ctx,
3553                         &dmcu_regs,
3554                         &dmcu_shift,
3555                         &dmcu_mask);
3556         if (pool->base.dmcu == NULL) {
3557                 dm_error("DC: failed to create dmcu!\n");
3558                 BREAK_TO_DEBUGGER();
3559                 goto create_fail;
3560         }
3561
3562         pool->base.abm = dce_abm_create(ctx,
3563                         &abm_regs,
3564                         &abm_shift,
3565                         &abm_mask);
3566         if (pool->base.abm == NULL) {
3567                 dm_error("DC: failed to create abm!\n");
3568                 BREAK_TO_DEBUGGER();
3569                 goto create_fail;
3570         }
3571
3572         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3573
3574
3575         if (!init_soc_bounding_box(dc, pool)) {
3576                 dm_error("DC: failed to initialize soc bounding box!\n");
3577                 BREAK_TO_DEBUGGER();
3578                 goto create_fail;
3579         }
3580
3581         dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3582
3583         if (!dc->debug.disable_pplib_wm_range) {
3584                 struct pp_smu_wm_range_sets ranges = {0};
3585                 int i = 0;
3586
3587                 ranges.num_reader_wm_sets = 0;
3588
3589                 if (loaded_bb->num_states == 1) {
3590                         ranges.reader_wm_sets[0].wm_inst = i;
3591                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3592                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3593                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3594                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3595
3596                         ranges.num_reader_wm_sets = 1;
3597                 } else if (loaded_bb->num_states > 1) {
3598                         for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3599                                 ranges.reader_wm_sets[i].wm_inst = i;
3600                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3601                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3602                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3603                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3604
3605                                 ranges.num_reader_wm_sets = i + 1;
3606                         }
3607
3608                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3609                         ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3610                 }
3611
3612                 ranges.num_writer_wm_sets = 1;
3613
3614                 ranges.writer_wm_sets[0].wm_inst = 0;
3615                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3616                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3617                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3618                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3619
3620                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3621                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3622                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3623         }
3624
3625         init_data.ctx = dc->ctx;
3626         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3627         if (!pool->base.irqs)
3628                 goto create_fail;
3629
3630         /* mem input -> ipp -> dpp -> opp -> TG */
3631         for (i = 0; i < pool->base.pipe_count; i++) {
3632                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3633                 if (pool->base.hubps[i] == NULL) {
3634                         BREAK_TO_DEBUGGER();
3635                         dm_error(
3636                                 "DC: failed to create memory input!\n");
3637                         goto create_fail;
3638                 }
3639
3640                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3641                 if (pool->base.ipps[i] == NULL) {
3642                         BREAK_TO_DEBUGGER();
3643                         dm_error(
3644                                 "DC: failed to create input pixel processor!\n");
3645                         goto create_fail;
3646                 }
3647
3648                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3649                 if (pool->base.dpps[i] == NULL) {
3650                         BREAK_TO_DEBUGGER();
3651                         dm_error(
3652                                 "DC: failed to create dpps!\n");
3653                         goto create_fail;
3654                 }
3655         }
3656         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3657                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3658                 if (pool->base.engines[i] == NULL) {
3659                         BREAK_TO_DEBUGGER();
3660                         dm_error(
3661                                 "DC:failed to create aux engine!!\n");
3662                         goto create_fail;
3663                 }
3664                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3665                 if (pool->base.hw_i2cs[i] == NULL) {
3666                         BREAK_TO_DEBUGGER();
3667                         dm_error(
3668                                 "DC:failed to create hw i2c!!\n");
3669                         goto create_fail;
3670                 }
3671                 pool->base.sw_i2cs[i] = NULL;
3672         }
3673
3674         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3675                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3676                 if (pool->base.opps[i] == NULL) {
3677                         BREAK_TO_DEBUGGER();
3678                         dm_error(
3679                                 "DC: failed to create output pixel processor!\n");
3680                         goto create_fail;
3681                 }
3682         }
3683
3684         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3685                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3686                                 ctx, i);
3687                 if (pool->base.timing_generators[i] == NULL) {
3688                         BREAK_TO_DEBUGGER();
3689                         dm_error("DC: failed to create tg!\n");
3690                         goto create_fail;
3691                 }
3692         }
3693
3694         pool->base.timing_generator_count = i;
3695
3696         pool->base.mpc = dcn20_mpc_create(ctx);
3697         if (pool->base.mpc == NULL) {
3698                 BREAK_TO_DEBUGGER();
3699                 dm_error("DC: failed to create mpc!\n");
3700                 goto create_fail;
3701         }
3702
3703         pool->base.hubbub = dcn20_hubbub_create(ctx);
3704         if (pool->base.hubbub == NULL) {
3705                 BREAK_TO_DEBUGGER();
3706                 dm_error("DC: failed to create hubbub!\n");
3707                 goto create_fail;
3708         }
3709
3710         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3711                 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3712                 if (pool->base.dscs[i] == NULL) {
3713                         BREAK_TO_DEBUGGER();
3714                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3715                         goto create_fail;
3716                 }
3717         }
3718
3719         if (!dcn20_dwbc_create(ctx, &pool->base)) {
3720                 BREAK_TO_DEBUGGER();
3721                 dm_error("DC: failed to create dwbc!\n");
3722                 goto create_fail;
3723         }
3724         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3725                 BREAK_TO_DEBUGGER();
3726                 dm_error("DC: failed to create mcif_wb!\n");
3727                 goto create_fail;
3728         }
3729
3730         if (!resource_construct(num_virtual_links, dc, &pool->base,
3731                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3732                         &res_create_funcs : &res_create_maximus_funcs)))
3733                         goto create_fail;
3734
3735         dcn20_hw_sequencer_construct(dc);
3736
3737         dc->caps.max_planes =  pool->base.pipe_count;
3738
3739         for (i = 0; i < dc->caps.max_planes; ++i)
3740                 dc->caps.planes[i] = plane_cap;
3741
3742         dc->cap_funcs = cap_funcs;
3743
3744         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3745                 ddc_init_data.ctx = dc->ctx;
3746                 ddc_init_data.link = NULL;
3747                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3748                 ddc_init_data.id.enum_id = 0;
3749                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3750                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3751         } else {
3752                 pool->base.oem_device = NULL;
3753         }
3754
3755         DC_FP_END();
3756         return true;
3757
3758 create_fail:
3759
3760         DC_FP_END();
3761         dcn20_resource_destruct(pool);
3762
3763         return false;
3764 }
3765
3766 struct resource_pool *dcn20_create_resource_pool(
3767                 const struct dc_init_data *init_data,
3768                 struct dc *dc)
3769 {
3770         struct dcn20_resource_pool *pool =
3771                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3772
3773         if (!pool)
3774                 return NULL;
3775
3776         if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
3777                 return &pool->base;
3778
3779         BREAK_TO_DEBUGGER();
3780         kfree(pool);
3781         return NULL;
3782 }