drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce110/dce110_hw_sequencer.h"
  27 #include "dcn10/dcn10_hw_sequencer.h"
  28 #include "dcn20/dcn20_hwseq.h"
  29 #include "dcn21_hwseq.h"
  30
  31 static const struct hw_sequencer_funcs dcn21_funcs = {
  32         .program_gamut_remap = dcn10_program_gamut_remap,
  33         .init_hw = dcn10_init_hw,
  34         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
  35         .apply_ctx_for_surface = NULL,
  36         .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
  37         .update_plane_addr = dcn20_update_plane_addr,
  38         .update_dchub = dcn10_update_dchub,
  39         .update_pending_status = dcn10_update_pending_status,
  40         .program_output_csc = dcn20_program_output_csc,
  41         .enable_accelerated_mode = dce110_enable_accelerated_mode,
  42         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
  43         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
  44         .update_info_frame = dce110_update_info_frame,
  45         .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
  46         .enable_stream = dcn20_enable_stream,
  47         .disable_stream = dce110_disable_stream,
  48         .unblank_stream = dcn20_unblank_stream,
  49         .blank_stream = dce110_blank_stream,
  50         .enable_audio_stream = dce110_enable_audio_stream,
  51         .disable_audio_stream = dce110_disable_audio_stream,
  52         .disable_plane = dcn20_disable_plane,
  53         .pipe_control_lock = dcn20_pipe_control_lock,
  54         .pipe_control_lock_global = dcn20_pipe_control_lock_global,
  55         .prepare_bandwidth = dcn20_prepare_bandwidth,
  56         .optimize_bandwidth = dcn20_optimize_bandwidth,
  57         .update_bandwidth = dcn20_update_bandwidth,
  58         .set_drr = dcn10_set_drr,
  59         .get_position = dcn10_get_position,
  60         .set_static_screen_control = dcn10_set_static_screen_control,
  61         .setup_stereo = dcn10_setup_stereo,
  62         .set_avmute = dce110_set_avmute,
  63         .log_hw_state = dcn10_log_hw_state,
  64         .get_hw_state = dcn10_get_hw_state,
  65         .clear_status_bits = dcn10_clear_status_bits,
  66         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
  67         .edp_power_control = dce110_edp_power_control,
  68         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
  69         .set_cursor_position = dcn10_set_cursor_position,
  70         .set_cursor_attribute = dcn10_set_cursor_attribute,
  71         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
  72         .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
  73         .set_clock = dcn10_set_clock,
  74         .get_clock = dcn10_get_clock,
  75         .program_triplebuffer = dcn20_program_triple_buffer,
  76         .enable_writeback = dcn20_enable_writeback,
  77         .disable_writeback = dcn20_disable_writeback,
  78         .dmdata_status_done = dcn20_dmdata_status_done,
  79         .program_dmdata_engine = dcn20_program_dmdata_engine,
  80         .set_dmdata_attributes = dcn20_set_dmdata_attributes,
  81         .init_sys_ctx = dcn21_init_sys_ctx,
  82         .init_vm_ctx = dcn20_init_vm_ctx,
  83         .set_flip_control_gsl = dcn20_set_flip_control_gsl,
  84         .optimize_pwr_state = dcn21_optimize_pwr_state,
  85         .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
  86         .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
  87         .set_cursor_position = dcn10_set_cursor_position,
  88         .set_cursor_attribute = dcn10_set_cursor_attribute,
  89         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
  90         .optimize_pwr_state = dcn21_optimize_pwr_state,
  91         .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
  92 };
  93
  94 static const struct hwseq_private_funcs dcn21_private_funcs = {
  95         .init_pipes = dcn10_init_pipes,
  96         .update_plane_addr = dcn20_update_plane_addr,
  97         .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
  98         .update_mpcc = dcn20_update_mpcc,
  99         .set_input_transfer_func = dcn20_set_input_transfer_func,
 100         .set_output_transfer_func = dcn20_set_output_transfer_func,
 101         .power_down = dce110_power_down,
 102         .enable_display_power_gating = dcn10_dummy_display_power_gating,
 103         .blank_pixel_data = dcn20_blank_pixel_data,
 104         .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
 105         .enable_stream_timing = dcn20_enable_stream_timing,
 106         .edp_backlight_control = dce110_edp_backlight_control,
 107         .disable_stream_gating = dcn20_disable_stream_gating,
 108         .enable_stream_gating = dcn20_enable_stream_gating,
 109         .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
 110         .did_underflow_occur = dcn10_did_underflow_occur,
 111         .init_blank = dcn20_init_blank,
 112         .disable_vga = dcn20_disable_vga,
 113         .bios_golden_init = dcn10_bios_golden_init,
 114         .plane_atomic_disable = dcn20_plane_atomic_disable,
 115         .plane_atomic_power_down = dcn10_plane_atomic_power_down,
 116         .enable_power_gating_plane = dcn20_enable_power_gating_plane,
 117         .dpp_pg_control = dcn20_dpp_pg_control,
 118         .hubp_pg_control = dcn20_hubp_pg_control,
 119         .dsc_pg_control = NULL,
 120         .update_odm = dcn20_update_odm,
 121         .dsc_pg_control = dcn20_dsc_pg_control,
 122         .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
 123         .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 124         .set_hdr_multiplier = dcn10_set_hdr_multiplier,
 125         .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 126         .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
 127         .wait_for_blank_complete = dcn20_wait_for_blank_complete,
 128         .dccg_init = dcn20_dccg_init,
 129         .set_blend_lut = dcn20_set_blend_lut,
 130         .set_shaper_3dlut = dcn20_set_shaper_3dlut,
 131 };
 132
 133 void dcn21_hw_sequencer_construct(struct dc *dc)
 134 {
 135         dc->hwss = dcn21_funcs;
 136         dc->hwseq->funcs = dcn21_private_funcs;
 137
 138         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 139                 dc->hwss.init_hw = dcn20_fpga_init_hw;
 140                 dc->hwseq->funcs.init_pipes = NULL;
 141         }
 142 }