drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "display_rq_dlg_helpers.h"
  27
  28 void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param)
  29 {
  30         dml_print("DML_RQ_DLG_CALC: ***************************\n");
  31         dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n");
  32         dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
  33         print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_l);
  34         dml_print("DML_RQ_DLG_CALC:  <CHROMA> ===\n");
  35         print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_c);
  36
  37         dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
  38         print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_l);
  39         dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
  40         print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_c);
  41
  42         dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
  43         print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_l);
  44         dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
  45         print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_c);
  46         dml_print("DML_RQ_DLG_CALC: ***************************\n");
  47 }
  48
  49 void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing)
  50 {
  51         dml_print("DML_RQ_DLG_CALC: =====================================\n");
  52         dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
  53         dml_print("DML_RQ_DLG_CALC:    chunk_bytes           = %0d\n", rq_sizing.chunk_bytes);
  54         dml_print("DML_RQ_DLG_CALC:    min_chunk_bytes       = %0d\n", rq_sizing.min_chunk_bytes);
  55         dml_print("DML_RQ_DLG_CALC:    meta_chunk_bytes      = %0d\n", rq_sizing.meta_chunk_bytes);
  56         dml_print(
  57                         "DML_RQ_DLG_CALC:    min_meta_chunk_bytes  = %0d\n",
  58                         rq_sizing.min_meta_chunk_bytes);
  59         dml_print("DML_RQ_DLG_CALC:    mpte_group_bytes      = %0d\n", rq_sizing.mpte_group_bytes);
  60         dml_print("DML_RQ_DLG_CALC:    dpte_group_bytes      = %0d\n", rq_sizing.dpte_group_bytes);
  61         dml_print("DML_RQ_DLG_CALC: =====================================\n");
  62 }
  63
  64 void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param)
  65 {
  66         dml_print("DML_RQ_DLG_CALC: =====================================\n");
  67         dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
  68         dml_print(
  69                         "DML_RQ_DLG_CALC:    swath_width_ub              = %0d\n",
  70                         rq_dlg_param.swath_width_ub);
  71         dml_print(
  72                         "DML_RQ_DLG_CALC:    swath_height                = %0d\n",
  73                         rq_dlg_param.swath_height);
  74         dml_print(
  75                         "DML_RQ_DLG_CALC:    req_per_swath_ub            = %0d\n",
  76                         rq_dlg_param.req_per_swath_ub);
  77         dml_print(
  78                         "DML_RQ_DLG_CALC:    meta_pte_bytes_per_frame_ub = %0d\n",
  79                         rq_dlg_param.meta_pte_bytes_per_frame_ub);
  80         dml_print(
  81                         "DML_RQ_DLG_CALC:    dpte_req_per_row_ub         = %0d\n",
  82                         rq_dlg_param.dpte_req_per_row_ub);
  83         dml_print(
  84                         "DML_RQ_DLG_CALC:    dpte_groups_per_row_ub      = %0d\n",
  85                         rq_dlg_param.dpte_groups_per_row_ub);
  86         dml_print(
  87                         "DML_RQ_DLG_CALC:    dpte_row_height             = %0d\n",
  88                         rq_dlg_param.dpte_row_height);
  89         dml_print(
  90                         "DML_RQ_DLG_CALC:    dpte_bytes_per_row_ub       = %0d\n",
  91                         rq_dlg_param.dpte_bytes_per_row_ub);
  92         dml_print(
  93                         "DML_RQ_DLG_CALC:    meta_chunks_per_row_ub      = %0d\n",
  94                         rq_dlg_param.meta_chunks_per_row_ub);
  95         dml_print(
  96                         "DML_RQ_DLG_CALC:    meta_req_per_row_ub         = %0d\n",
  97                         rq_dlg_param.meta_req_per_row_ub);
  98         dml_print(
  99                         "DML_RQ_DLG_CALC:    meta_row_height             = %0d\n",
 100                         rq_dlg_param.meta_row_height);
 101         dml_print(
 102                         "DML_RQ_DLG_CALC:    meta_bytes_per_row_ub       = %0d\n",
 103                         rq_dlg_param.meta_bytes_per_row_ub);
 104         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 105 }
 106
 107 void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param)
 108 {
 109         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 110         dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
 111         dml_print(
 112                         "DML_RQ_DLG_CALC:     full_swath_bytes   = %0d\n",
 113                         rq_misc_param.full_swath_bytes);
 114         dml_print(
 115                         "DML_RQ_DLG_CALC:     stored_swath_bytes = %0d\n",
 116                         rq_misc_param.stored_swath_bytes);
 117         dml_print("DML_RQ_DLG_CALC:     blk256_width       = %0d\n", rq_misc_param.blk256_width);
 118         dml_print("DML_RQ_DLG_CALC:     blk256_height      = %0d\n", rq_misc_param.blk256_height);
 119         dml_print("DML_RQ_DLG_CALC:     req_width          = %0d\n", rq_misc_param.req_width);
 120         dml_print("DML_RQ_DLG_CALC:     req_height         = %0d\n", rq_misc_param.req_height);
 121         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 122 }
 123
 124 void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param)
 125 {
 126         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 127         dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
 128         dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
 129         print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l);
 130         dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
 131         print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c);
 132         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 133 }
 134
 135 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param)
 136 {
 137         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 138         dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
 139         dml_print("DML_RQ_DLG_CALC:    t_mclk_wm_us         = %3.2f\n", dlg_sys_param.t_mclk_wm_us);
 140         dml_print("DML_RQ_DLG_CALC:    t_urg_wm_us          = %3.2f\n", dlg_sys_param.t_urg_wm_us);
 141         dml_print("DML_RQ_DLG_CALC:    t_sr_wm_us           = %3.2f\n", dlg_sys_param.t_sr_wm_us);
 142         dml_print("DML_RQ_DLG_CALC:    t_extra_us           = %3.2f\n", dlg_sys_param.t_extra_us);
 143         dml_print(
 144                         "DML_RQ_DLG_CALC:    t_srx_delay_us       = %3.2f\n",
 145                         dlg_sys_param.t_srx_delay_us);
 146         dml_print(
 147                         "DML_RQ_DLG_CALC:    deepsleep_dcfclk_mhz = %3.2f\n",
 148                         dlg_sys_param.deepsleep_dcfclk_mhz);
 149         dml_print(
 150                         "DML_RQ_DLG_CALC:    total_flip_bw        = %3.2f\n",
 151                         dlg_sys_param.total_flip_bw);
 152         dml_print(
 153                         "DML_RQ_DLG_CALC:    total_flip_bytes     = %i\n",
 154                         dlg_sys_param.total_flip_bytes);
 155         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 156 }
 157
 158 void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs)
 159 {
 160         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 161         dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
 162         dml_print("DML_RQ_DLG_CALC:    chunk_size              = 0x%0x\n", rq_regs.chunk_size);
 163         dml_print("DML_RQ_DLG_CALC:    min_chunk_size          = 0x%0x\n", rq_regs.min_chunk_size);
 164         dml_print("DML_RQ_DLG_CALC:    meta_chunk_size         = 0x%0x\n", rq_regs.meta_chunk_size);
 165         dml_print(
 166                         "DML_RQ_DLG_CALC:    min_meta_chunk_size     = 0x%0x\n",
 167                         rq_regs.min_meta_chunk_size);
 168         dml_print("DML_RQ_DLG_CALC:    dpte_group_size         = 0x%0x\n", rq_regs.dpte_group_size);
 169         dml_print("DML_RQ_DLG_CALC:    mpte_group_size         = 0x%0x\n", rq_regs.mpte_group_size);
 170         dml_print("DML_RQ_DLG_CALC:    swath_height            = 0x%0x\n", rq_regs.swath_height);
 171         dml_print(
 172                         "DML_RQ_DLG_CALC:    pte_row_height_linear   = 0x%0x\n",
 173                         rq_regs.pte_row_height_linear);
 174         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 175 }
 176
 177 void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs)
 178 {
 179         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 180         dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n");
 181         dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
 182         print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
 183         dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
 184         print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c);
 185         dml_print("DML_RQ_DLG_CALC:    drq_expansion_mode  = 0x%0x\n", rq_regs.drq_expansion_mode);
 186         dml_print("DML_RQ_DLG_CALC:    prq_expansion_mode  = 0x%0x\n", rq_regs.prq_expansion_mode);
 187         dml_print("DML_RQ_DLG_CALC:    mrq_expansion_mode  = 0x%0x\n", rq_regs.mrq_expansion_mode);
 188         dml_print("DML_RQ_DLG_CALC:    crq_expansion_mode  = 0x%0x\n", rq_regs.crq_expansion_mode);
 189         dml_print("DML_RQ_DLG_CALC:    plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address);
 190         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 191 }
 192
 193 void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs)
 194 {
 195         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 196         dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
 197         dml_print(
 198                         "DML_RQ_DLG_CALC:    refcyc_h_blank_end              = 0x%0x\n",
 199                         dlg_regs.refcyc_h_blank_end);
 200         dml_print(
 201                         "DML_RQ_DLG_CALC:    dlg_vblank_end                  = 0x%0x\n",
 202                         dlg_regs.dlg_vblank_end);
 203         dml_print(
 204                         "DML_RQ_DLG_CALC:    min_dst_y_next_start            = 0x%0x\n",
 205                         dlg_regs.min_dst_y_next_start);
 206         dml_print(
 207                         "DML_RQ_DLG_CALC:    refcyc_per_htotal               = 0x%0x\n",
 208                         dlg_regs.refcyc_per_htotal);
 209         dml_print(
 210                         "DML_RQ_DLG_CALC:    refcyc_x_after_scaler           = 0x%0x\n",
 211                         dlg_regs.refcyc_x_after_scaler);
 212         dml_print(
 213                         "DML_RQ_DLG_CALC:    dst_y_after_scaler              = 0x%0x\n",
 214                         dlg_regs.dst_y_after_scaler);
 215         dml_print(
 216                         "DML_RQ_DLG_CALC:    dst_y_prefetch                  = 0x%0x\n",
 217                         dlg_regs.dst_y_prefetch);
 218         dml_print(
 219                         "DML_RQ_DLG_CALC:    dst_y_per_vm_vblank             = 0x%0x\n",
 220                         dlg_regs.dst_y_per_vm_vblank);
 221         dml_print(
 222                         "DML_RQ_DLG_CALC:    dst_y_per_row_vblank            = 0x%0x\n",
 223                         dlg_regs.dst_y_per_row_vblank);
 224         dml_print(
 225                         "DML_RQ_DLG_CALC:    dst_y_per_vm_flip               = 0x%0x\n",
 226                         dlg_regs.dst_y_per_vm_flip);
 227         dml_print(
 228                         "DML_RQ_DLG_CALC:    dst_y_per_row_flip              = 0x%0x\n",
 229                         dlg_regs.dst_y_per_row_flip);
 230         dml_print(
 231                         "DML_RQ_DLG_CALC:    ref_freq_to_pix_freq            = 0x%0x\n",
 232                         dlg_regs.ref_freq_to_pix_freq);
 233         dml_print(
 234                         "DML_RQ_DLG_CALC:    vratio_prefetch                 = 0x%0x\n",
 235                         dlg_regs.vratio_prefetch);
 236         dml_print(
 237                         "DML_RQ_DLG_CALC:    vratio_prefetch_c               = 0x%0x\n",
 238                         dlg_regs.vratio_prefetch_c);
 239         dml_print(
 240                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_l   = 0x%0x\n",
 241                         dlg_regs.refcyc_per_pte_group_vblank_l);
 242         dml_print(
 243                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_c   = 0x%0x\n",
 244                         dlg_regs.refcyc_per_pte_group_vblank_c);
 245         dml_print(
 246                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_l  = 0x%0x\n",
 247                         dlg_regs.refcyc_per_meta_chunk_vblank_l);
 248         dml_print(
 249                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_c  = 0x%0x\n",
 250                         dlg_regs.refcyc_per_meta_chunk_vblank_c);
 251         dml_print(
 252                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_l     = 0x%0x\n",
 253                         dlg_regs.refcyc_per_pte_group_flip_l);
 254         dml_print(
 255                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_c     = 0x%0x\n",
 256                         dlg_regs.refcyc_per_pte_group_flip_c);
 257         dml_print(
 258                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_l    = 0x%0x\n",
 259                         dlg_regs.refcyc_per_meta_chunk_flip_l);
 260         dml_print(
 261                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_c    = 0x%0x\n",
 262                         dlg_regs.refcyc_per_meta_chunk_flip_c);
 263         dml_print(
 264                         "DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_l         = 0x%0x\n",
 265                         dlg_regs.dst_y_per_pte_row_nom_l);
 266         dml_print(
 267                         "DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_c         = 0x%0x\n",
 268                         dlg_regs.dst_y_per_pte_row_nom_c);
 269         dml_print(
 270                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_l      = 0x%0x\n",
 271                         dlg_regs.refcyc_per_pte_group_nom_l);
 272         dml_print(
 273                         "DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_c      = 0x%0x\n",
 274                         dlg_regs.refcyc_per_pte_group_nom_c);
 275         dml_print(
 276                         "DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_l        = 0x%0x\n",
 277                         dlg_regs.dst_y_per_meta_row_nom_l);
 278         dml_print(
 279                         "DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_c        = 0x%0x\n",
 280                         dlg_regs.dst_y_per_meta_row_nom_c);
 281         dml_print(
 282                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_l     = 0x%0x\n",
 283                         dlg_regs.refcyc_per_meta_chunk_nom_l);
 284         dml_print(
 285                         "DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_c     = 0x%0x\n",
 286                         dlg_regs.refcyc_per_meta_chunk_nom_c);
 287         dml_print(
 288                         "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_l  = 0x%0x\n",
 289                         dlg_regs.refcyc_per_line_delivery_pre_l);
 290         dml_print(
 291                         "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_c  = 0x%0x\n",
 292                         dlg_regs.refcyc_per_line_delivery_pre_c);
 293         dml_print(
 294                         "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_l      = 0x%0x\n",
 295                         dlg_regs.refcyc_per_line_delivery_l);
 296         dml_print(
 297                         "DML_RQ_DLG_CALC:    refcyc_per_line_delivery_c      = 0x%0x\n",
 298                         dlg_regs.refcyc_per_line_delivery_c);
 299         dml_print(
 300                         "DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur0           = 0x%0x\n",
 301                         dlg_regs.chunk_hdl_adjust_cur0);
 302         dml_print(
 303                         "DML_RQ_DLG_CALC:    dst_y_offset_cur1               = 0x%0x\n",
 304                         dlg_regs.dst_y_offset_cur1);
 305         dml_print(
 306                         "DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur1           = 0x%0x\n",
 307                         dlg_regs.chunk_hdl_adjust_cur1);
 308         dml_print(
 309                         "DML_RQ_DLG_CALC:    vready_after_vcount0            = 0x%0x\n",
 310                         dlg_regs.vready_after_vcount0);
 311         dml_print(
 312                         "DML_RQ_DLG_CALC:    dst_y_delta_drq_limit           = 0x%0x\n",
 313                         dlg_regs.dst_y_delta_drq_limit);
 314         dml_print(
 315                         "DML_RQ_DLG_CALC:    xfc_reg_transfer_delay          = 0x%0x\n",
 316                         dlg_regs.xfc_reg_transfer_delay);
 317         dml_print(
 318                         "DML_RQ_DLG_CALC:    xfc_reg_precharge_delay         = 0x%0x\n",
 319                         dlg_regs.xfc_reg_precharge_delay);
 320         dml_print(
 321                         "DML_RQ_DLG_CALC:    xfc_reg_remote_surface_flip_latency = 0x%0x\n",
 322                         dlg_regs.xfc_reg_remote_surface_flip_latency);
 323
 324         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 325 }
 326
 327 void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs)
 328 {
 329         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 330         dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
 331         dml_print(
 332                         "DML_RQ_DLG_CALC:    qos_level_low_wm                  = 0x%0x\n",
 333                         ttu_regs.qos_level_low_wm);
 334         dml_print(
 335                         "DML_RQ_DLG_CALC:    qos_level_high_wm                 = 0x%0x\n",
 336                         ttu_regs.qos_level_high_wm);
 337         dml_print(
 338                         "DML_RQ_DLG_CALC:    min_ttu_vblank                    = 0x%0x\n",
 339                         ttu_regs.min_ttu_vblank);
 340         dml_print(
 341                         "DML_RQ_DLG_CALC:    qos_level_flip                    = 0x%0x\n",
 342                         ttu_regs.qos_level_flip);
 343         dml_print(
 344                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_l     = 0x%0x\n",
 345                         ttu_regs.refcyc_per_req_delivery_pre_l);
 346         dml_print(
 347                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_l         = 0x%0x\n",
 348                         ttu_regs.refcyc_per_req_delivery_l);
 349         dml_print(
 350                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_c     = 0x%0x\n",
 351                         ttu_regs.refcyc_per_req_delivery_pre_c);
 352         dml_print(
 353                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_c         = 0x%0x\n",
 354                         ttu_regs.refcyc_per_req_delivery_c);
 355         dml_print(
 356                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur0      = 0x%0x\n",
 357                         ttu_regs.refcyc_per_req_delivery_cur0);
 358         dml_print(
 359                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur0  = 0x%0x\n",
 360                         ttu_regs.refcyc_per_req_delivery_pre_cur0);
 361         dml_print(
 362                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur1      = 0x%0x\n",
 363                         ttu_regs.refcyc_per_req_delivery_cur1);
 364         dml_print(
 365                         "DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur1  = 0x%0x\n",
 366                         ttu_regs.refcyc_per_req_delivery_pre_cur1);
 367         dml_print(
 368                         "DML_RQ_DLG_CALC:    qos_level_fixed_l                 = 0x%0x\n",
 369                         ttu_regs.qos_level_fixed_l);
 370         dml_print(
 371                         "DML_RQ_DLG_CALC:    qos_ramp_disable_l                = 0x%0x\n",
 372                         ttu_regs.qos_ramp_disable_l);
 373         dml_print(
 374                         "DML_RQ_DLG_CALC:    qos_level_fixed_c                 = 0x%0x\n",
 375                         ttu_regs.qos_level_fixed_c);
 376         dml_print(
 377                         "DML_RQ_DLG_CALC:    qos_ramp_disable_c                = 0x%0x\n",
 378                         ttu_regs.qos_ramp_disable_c);
 379         dml_print(
 380                         "DML_RQ_DLG_CALC:    qos_level_fixed_cur0              = 0x%0x\n",
 381                         ttu_regs.qos_level_fixed_cur0);
 382         dml_print(
 383                         "DML_RQ_DLG_CALC:    qos_ramp_disable_cur0             = 0x%0x\n",
 384                         ttu_regs.qos_ramp_disable_cur0);
 385         dml_print(
 386                         "DML_RQ_DLG_CALC:    qos_level_fixed_cur1              = 0x%0x\n",
 387                         ttu_regs.qos_level_fixed_cur1);
 388         dml_print(
 389                         "DML_RQ_DLG_CALC:    qos_ramp_disable_cur1             = 0x%0x\n",
 390                         ttu_regs.qos_ramp_disable_cur1);
 391         dml_print("DML_RQ_DLG_CALC: =====================================\n");
 392 }