drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../inc/dmub_srv.h"
  27 #include "dmub_reg.h"
  28
  29 #include "dcn/dcn_2_0_0_offset.h"
  30 #include "dcn/dcn_2_0_0_sh_mask.h"
  31 #include "soc15_hw_ip.h"
  32 #include "vega10_ip_offset.h"
  33
  34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
  35 #define CTX dmub
  36
  37 void dmub_dcn20_reset(struct dmub_srv *dmub)
  38 {
  39         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
  40         REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
  41 }
  42
  43 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
  44 {
  45         REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
  46         REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
  47         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
  48 }
  49
  50 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
  51                               struct dmub_window *cw1)
  52 {
  53         REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
  54         REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,
  55                      DMCUB_MEM_WRITE_SPACE, 0x4);
  56
  57         REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part);
  58         REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part);
  59         REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
  60         REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
  61                   DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
  62                   DMCUB_REGION3_CW0_ENABLE, 1);
  63
  64         REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part);
  65         REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part);
  66         REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
  67         REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
  68                   DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
  69                   DMCUB_REGION3_CW1_ENABLE, 1);
  70
  71         REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
  72                      0x20);
  73 }
  74
  75 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
  76                               const struct dmub_window *cw2,
  77                               const struct dmub_window *cw3,
  78                               const struct dmub_window *cw4,
  79                                   const struct dmub_window *cw5)
  80 {
  81         REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
  82         REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
  83         REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
  84         REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
  85                   DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
  86                   DMCUB_REGION3_CW2_ENABLE, 1);
  87
  88         REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part);
  89         REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part);
  90         REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
  91         REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
  92                   DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
  93                   DMCUB_REGION3_CW3_ENABLE, 1);
  94
  95         /* TODO: Move this to CW4. */
  96
  97         REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part);
  98         REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part);
  99         REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
 100                   cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
 101                   1);
 102 }
 103
 104 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
 105                               const struct dmub_region *inbox1)
 106 {
 107         /* TODO: Use CW4 instead of region 4. */
 108
 109         REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
 110         REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
 111         REG_WRITE(DMCUB_INBOX1_RPTR, 0);
 112         REG_WRITE(DMCUB_INBOX1_WPTR, 0);
 113 }
 114
 115 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
 116 {
 117         return REG_READ(DMCUB_INBOX1_RPTR);
 118 }
 119
 120 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
 121 {
 122         REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
 123 }
 124
 125 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
 126 {
 127         return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
 128 }
 129
 130 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
 131 {
 132         uint32_t supported = 0;
 133
 134         REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
 135
 136         return supported;
 137 }
 138
 139 bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
 140 {
 141         return REG_READ(DMCUB_SCRATCH10) == 0;
 142 }