drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../inc/dmub_srv.h"
  27 #include "dmub_dcn20.h"
  28 #include "dmub_dcn21.h"
  29 /*
  30  * Note: the DMUB service is standalone. No additional headers should be
  31  * added below or above this line unless they reside within the DMUB
  32  * folder.
  33  */
  34
  35 /* Alignment for framebuffer memory. */
  36 #define DMUB_FB_ALIGNMENT (1024 * 1024)
  37
  38 /* Stack size. */
  39 #define DMUB_STACK_SIZE (128 * 1024)
  40
  41 /* Context size. */
  42 #define DMUB_CONTEXT_SIZE (512 * 1024)
  43
  44 /* Mailbox size */
  45 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
  46
  47 /* Tracebuffer size */
  48 #define DMUB_TRACEBUFF_SIZE (1024) //1kB buffer
  49
  50 /* Number of windows in use. */
  51 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
  52 /* Base addresses. */
  53
  54 #define DMUB_CW0_BASE (0x60000000)
  55 #define DMUB_CW1_BASE (0x61000000)
  56 #define DMUB_CW5_BASE (0x65000000)
  57
  58 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
  59 {
  60         return (val + factor - 1) / factor * factor;
  61 }
  62
  63 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
  64 {
  65         struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
  66
  67         switch (asic) {
  68         case DMUB_ASIC_DCN20:
  69         case DMUB_ASIC_DCN21:
  70                 funcs->reset = dmub_dcn20_reset;
  71                 funcs->reset_release = dmub_dcn20_reset_release;
  72                 funcs->backdoor_load = dmub_dcn20_backdoor_load;
  73                 funcs->setup_windows = dmub_dcn20_setup_windows;
  74                 funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
  75                 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
  76                 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
  77                 funcs->is_supported = dmub_dcn20_is_supported;
  78                 funcs->is_phy_init = dmub_dcn20_is_phy_init;
  79                 funcs->is_hw_init = dmub_dcn20_is_hw_init;
  80
  81                 if (asic == DMUB_ASIC_DCN21) {
  82                         funcs->backdoor_load = dmub_dcn21_backdoor_load;
  83                         funcs->setup_windows = dmub_dcn21_setup_windows;
  84                         funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
  85                 }
  86                 break;
  87
  88         default:
  89                 return false;
  90         }
  91
  92         return true;
  93 }
  94
  95 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
  96                                  const struct dmub_srv_create_params *params)
  97 {
  98         enum dmub_status status = DMUB_STATUS_OK;
  99
 100         dmub_memset(dmub, 0, sizeof(*dmub));
 101
 102         dmub->funcs = params->funcs;
 103         dmub->user_ctx = params->user_ctx;
 104         dmub->asic = params->asic;
 105         dmub->is_virtual = params->is_virtual;
 106
 107         /* Setup asic dependent hardware funcs. */
 108         if (!dmub_srv_hw_setup(dmub, params->asic)) {
 109                 status = DMUB_STATUS_INVALID;
 110                 goto cleanup;
 111         }
 112
 113         /* Override (some) hardware funcs based on user params. */
 114         if (params->hw_funcs) {
 115                 if (params->hw_funcs->get_inbox1_rptr)
 116                         dmub->hw_funcs.get_inbox1_rptr =
 117                                 params->hw_funcs->get_inbox1_rptr;
 118
 119                 if (params->hw_funcs->set_inbox1_wptr)
 120                         dmub->hw_funcs.set_inbox1_wptr =
 121                                 params->hw_funcs->set_inbox1_wptr;
 122
 123                 if (params->hw_funcs->is_supported)
 124                         dmub->hw_funcs.is_supported =
 125                                 params->hw_funcs->is_supported;
 126         }
 127
 128         /* Sanity checks for required hw func pointers. */
 129         if (!dmub->hw_funcs.get_inbox1_rptr ||
 130             !dmub->hw_funcs.set_inbox1_wptr) {
 131                 status = DMUB_STATUS_INVALID;
 132                 goto cleanup;
 133         }
 134
 135 cleanup:
 136         if (status == DMUB_STATUS_OK)
 137                 dmub->sw_init = true;
 138         else
 139                 dmub_srv_destroy(dmub);
 140
 141         return status;
 142 }
 143
 144 void dmub_srv_destroy(struct dmub_srv *dmub)
 145 {
 146         dmub_memset(dmub, 0, sizeof(*dmub));
 147 }
 148
 149 enum dmub_status
 150 dmub_srv_calc_region_info(struct dmub_srv *dmub,
 151                           const struct dmub_srv_region_params *params,
 152                           struct dmub_srv_region_info *out)
 153 {
 154         struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
 155         struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
 156         struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
 157         struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
 158         struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
 159         struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
 160
 161         if (!dmub->sw_init)
 162                 return DMUB_STATUS_INVALID;
 163
 164         memset(out, 0, sizeof(*out));
 165
 166         out->num_regions = DMUB_NUM_WINDOWS;
 167
 168         inst->base = 0x0;
 169         inst->top = inst->base + params->inst_const_size;
 170
 171         data->base = dmub_align(inst->top, 256);
 172         data->top = data->base + params->bss_data_size;
 173
 174         stack->base = dmub_align(data->top, 256);
 175         stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
 176
 177         bios->base = dmub_align(stack->top, 256);
 178         bios->top = bios->base + params->vbios_size;
 179
 180         mail->base = dmub_align(bios->top, 256);
 181         mail->top = mail->base + DMUB_MAILBOX_SIZE;
 182
 183         trace_buff->base = dmub_align(mail->top, 256);
 184         trace_buff->top = trace_buff->base + DMUB_TRACEBUFF_SIZE;
 185
 186         out->fb_size = dmub_align(trace_buff->top, 4096);
 187
 188         return DMUB_STATUS_OK;
 189 }
 190
 191 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
 192                                        const struct dmub_srv_fb_params *params,
 193                                        struct dmub_srv_fb_info *out)
 194 {
 195         uint8_t *cpu_base;
 196         uint64_t gpu_base;
 197         uint32_t i;
 198
 199         if (!dmub->sw_init)
 200                 return DMUB_STATUS_INVALID;
 201
 202         memset(out, 0, sizeof(*out));
 203
 204         if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
 205                 return DMUB_STATUS_INVALID;
 206
 207         cpu_base = (uint8_t *)params->cpu_addr;
 208         gpu_base = params->gpu_addr;
 209
 210         for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
 211                 const struct dmub_region *reg =
 212                         &params->region_info->regions[i];
 213
 214                 out->fb[i].cpu_addr = cpu_base + reg->base;
 215                 out->fb[i].gpu_addr = gpu_base + reg->base;
 216                 out->fb[i].size = reg->top - reg->base;
 217         }
 218
 219         out->num_fb = DMUB_NUM_WINDOWS;
 220
 221         return DMUB_STATUS_OK;
 222 }
 223
 224 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
 225                                          bool *is_supported)
 226 {
 227         *is_supported = false;
 228
 229         if (!dmub->sw_init)
 230                 return DMUB_STATUS_INVALID;
 231
 232         if (dmub->hw_funcs.is_supported)
 233                 *is_supported = dmub->hw_funcs.is_supported(dmub);
 234
 235         return DMUB_STATUS_OK;
 236 }
 237
 238 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
 239 {
 240         *is_hw_init = false;
 241
 242         if (!dmub->sw_init)
 243                 return DMUB_STATUS_INVALID;
 244
 245         if (dmub->hw_funcs.is_hw_init)
 246                 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
 247
 248         return DMUB_STATUS_OK;
 249 }
 250
 251 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 252                                   const struct dmub_srv_hw_params *params)
 253 {
 254         struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
 255         struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
 256         struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
 257         struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
 258         struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
 259         struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
 260
 261         struct dmub_rb_init_params rb_params;
 262         struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5;
 263         struct dmub_region inbox1;
 264
 265         if (!dmub->sw_init)
 266                 return DMUB_STATUS_INVALID;
 267
 268         dmub->fb_base = params->fb_base;
 269         dmub->fb_offset = params->fb_offset;
 270         dmub->psp_version = params->psp_version;
 271
 272         if (inst_fb && data_fb) {
 273                 cw0.offset.quad_part = inst_fb->gpu_addr;
 274                 cw0.region.base = DMUB_CW0_BASE;
 275                 cw0.region.top = cw0.region.base + inst_fb->size - 1;
 276
 277                 cw1.offset.quad_part = stack_fb->gpu_addr;
 278                 cw1.region.base = DMUB_CW1_BASE;
 279                 cw1.region.top = cw1.region.base + stack_fb->size - 1;
 280
 281                 if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
 282                         dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 283         }
 284
 285         if (dmub->hw_funcs.reset)
 286                 dmub->hw_funcs.reset(dmub);
 287
 288         if (inst_fb && data_fb && bios_fb && mail_fb) {
 289                 cw2.offset.quad_part = data_fb->gpu_addr;
 290                 cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
 291                 cw2.region.top = cw2.region.base + data_fb->size;
 292
 293                 cw3.offset.quad_part = bios_fb->gpu_addr;
 294                 cw3.region.base = DMUB_CW1_BASE + stack_fb->size;
 295                 cw3.region.top = cw3.region.base + bios_fb->size;
 296
 297                 cw4.offset.quad_part = mail_fb->gpu_addr;
 298                 cw4.region.base = cw3.region.top + 1;
 299                 cw4.region.top = cw4.region.base + mail_fb->size;
 300
 301                 inbox1.base = cw4.region.base;
 302                 inbox1.top = cw4.region.top;
 303
 304                 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
 305                 cw5.region.base = DMUB_CW5_BASE;
 306                 cw5.region.top = cw5.region.base + tracebuff_fb->size;
 307
 308                 if (dmub->hw_funcs.setup_windows)
 309                         dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5);
 310
 311                 if (dmub->hw_funcs.setup_mailbox)
 312                         dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
 313         }
 314
 315         if (mail_fb) {
 316                 dmub_memset(&rb_params, 0, sizeof(rb_params));
 317                 rb_params.ctx = dmub;
 318                 rb_params.base_address = mail_fb->cpu_addr;
 319                 rb_params.capacity = DMUB_RB_SIZE;
 320
 321                 dmub_rb_init(&dmub->inbox1_rb, &rb_params);
 322         }
 323
 324         if (dmub->hw_funcs.reset_release)
 325                 dmub->hw_funcs.reset_release(dmub);
 326
 327         dmub->hw_init = true;
 328
 329         return DMUB_STATUS_OK;
 330 }
 331
 332 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
 333                                     const struct dmub_cmd_header *cmd)
 334 {
 335         if (!dmub->hw_init)
 336                 return DMUB_STATUS_INVALID;
 337
 338         if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
 339                 return DMUB_STATUS_OK;
 340
 341         return DMUB_STATUS_QUEUE_FULL;
 342 }
 343
 344 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
 345 {
 346         if (!dmub->hw_init)
 347                 return DMUB_STATUS_INVALID;
 348
 349         dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
 350         return DMUB_STATUS_OK;
 351 }
 352
 353 enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
 354                                      const struct dmub_cmd_header *cmd,
 355                                      uint32_t timeout_us)
 356 {
 357         uint32_t i = 0;
 358
 359         if (!dmub->hw_init)
 360                 return DMUB_STATUS_INVALID;
 361
 362         for (i = 0; i <= timeout_us; ++i) {
 363                 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
 364                 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) {
 365                         dmub->hw_funcs.set_inbox1_wptr(dmub,
 366                                                        dmub->inbox1_rb.wrpt);
 367                         return DMUB_STATUS_OK;
 368                 }
 369
 370                 udelay(1);
 371         }
 372
 373         return DMUB_STATUS_TIMEOUT;
 374 }
 375
 376 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
 377                                              uint32_t timeout_us)
 378 {
 379         uint32_t i;
 380
 381         if (!dmub->hw_init || !dmub->hw_funcs.is_auto_load_done)
 382                 return DMUB_STATUS_INVALID;
 383
 384         for (i = 0; i <= timeout_us; i += 100) {
 385                 if (dmub->hw_funcs.is_auto_load_done(dmub))
 386                         return DMUB_STATUS_OK;
 387
 388                 udelay(100);
 389         }
 390
 391         return DMUB_STATUS_TIMEOUT;
 392 }
 393
 394 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
 395                                             uint32_t timeout_us)
 396 {
 397         uint32_t i;
 398
 399         if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
 400                 return DMUB_STATUS_INVALID;
 401
 402         for (i = 0; i <= timeout_us; i += 10) {
 403                 if (dmub->hw_funcs.is_phy_init(dmub))
 404                         return DMUB_STATUS_OK;
 405
 406                 udelay(10);
 407         }
 408
 409         return DMUB_STATUS_TIMEOUT;
 410 }
 411
 412 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
 413                                         uint32_t timeout_us)
 414 {
 415         uint32_t i;
 416
 417         if (!dmub->hw_init)
 418                 return DMUB_STATUS_INVALID;
 419
 420         for (i = 0; i <= timeout_us; ++i) {
 421                 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
 422                 if (dmub_rb_empty(&dmub->inbox1_rb))
 423                         return DMUB_STATUS_OK;
 424
 425                 udelay(1);
 426         }
 427
 428         return DMUB_STATUS_TIMEOUT;
 429 }