drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "atom.h"
  31 #include "amd_pcie.h"
  32
  33 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
  34 {
  35         int ret = 0;
  36
  37         if (!if_version && !smu_version)
  38                 return -EINVAL;
  39
  40         if (if_version) {
  41                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
  42                 if (ret)
  43                         return ret;
  44
  45                 ret = smu_read_smc_arg(smu, if_version);
  46                 if (ret)
  47                         return ret;
  48         }
  49
  50         if (smu_version) {
  51                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
  52                 if (ret)
  53                         return ret;
  54
  55                 ret = smu_read_smc_arg(smu, smu_version);
  56                 if (ret)
  57                         return ret;
  58         }
  59
  60         return ret;
  61 }
  62
  63 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
  64                             uint32_t min, uint32_t max)
  65 {
  66         int ret = 0, clk_id = 0;
  67         uint32_t param;
  68
  69         if (min <= 0 && max <= 0)
  70                 return -EINVAL;
  71
  72         clk_id = smu_clk_get_index(smu, clk_type);
  73         if (clk_id < 0)
  74                 return clk_id;
  75
  76         if (max > 0) {
  77                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
  78                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
  79                                                   param);
  80                 if (ret)
  81                         return ret;
  82         }
  83
  84         if (min > 0) {
  85                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
  86                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
  87                                                   param);
  88                 if (ret)
  89                         return ret;
  90         }
  91
  92
  93         return ret;
  94 }
  95
  96 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
  97                             uint32_t min, uint32_t max)
  98 {
  99         int ret = 0, clk_id = 0;
 100         uint32_t param;
 101
 102         if (min <= 0 && max <= 0)
 103                 return -EINVAL;
 104
 105         clk_id = smu_clk_get_index(smu, clk_type);
 106         if (clk_id < 0)
 107                 return clk_id;
 108
 109         if (max > 0) {
 110                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 111                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 112                                                   param);
 113                 if (ret)
 114                         return ret;
 115         }
 116
 117         if (min > 0) {
 118                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 119                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 120                                                   param);
 121                 if (ret)
 122                         return ret;
 123         }
 124
 125
 126         return ret;
 127 }
 128
 129 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 130                            uint32_t *min, uint32_t *max)
 131 {
 132         int ret = 0, clk_id = 0;
 133         uint32_t param = 0;
 134
 135         if (!min && !max)
 136                 return -EINVAL;
 137
 138         switch (clk_type) {
 139         case SMU_UCLK:
 140                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 141                         pr_warn("uclk dpm is not enabled\n");
 142                         return 0;
 143                 }
 144                 break;
 145         case SMU_GFXCLK:
 146                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 147                         pr_warn("gfxclk dpm is not enabled\n");
 148                         return 0;
 149                 }
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         mutex_lock(&smu->mutex);
 156         clk_id = smu_clk_get_index(smu, clk_type);
 157         if (clk_id < 0) {
 158                 ret = -EINVAL;
 159                 goto failed;
 160         }
 161
 162         param = (clk_id & 0xffff) << 16;
 163
 164         if (max) {
 165                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
 166                 if (ret)
 167                         goto failed;
 168                 ret = smu_read_smc_arg(smu, max);
 169                 if (ret)
 170                         goto failed;
 171         }
 172
 173         if (min) {
 174                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
 175                 if (ret)
 176                         goto failed;
 177                 ret = smu_read_smc_arg(smu, min);
 178                 if (ret)
 179                         goto failed;
 180         }
 181
 182 failed:
 183         mutex_unlock(&smu->mutex);
 184         return ret;
 185 }
 186
 187 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 188                               uint16_t level, uint32_t *value)
 189 {
 190         int ret = 0, clk_id = 0;
 191         uint32_t param;
 192
 193         if (!value)
 194                 return -EINVAL;
 195
 196         clk_id = smu_clk_get_index(smu, clk_type);
 197         if (clk_id < 0)
 198                 return clk_id;
 199
 200         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 201
 202         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 203                                           param);
 204         if (ret)
 205                 return ret;
 206
 207         ret = smu_read_smc_arg(smu, &param);
 208         if (ret)
 209                 return ret;
 210
 211         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 212          * now, we un-support it */
 213         *value = param & 0x7fffffff;
 214
 215         return ret;
 216 }
 217
 218 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 219                             uint32_t *value)
 220 {
 221         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 222 }
 223
 224 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 225                            bool gate)
 226 {
 227         int ret = 0;
 228
 229         switch (block_type) {
 230         case AMD_IP_BLOCK_TYPE_UVD:
 231                 ret = smu_dpm_set_uvd_enable(smu, gate);
 232                 break;
 233         case AMD_IP_BLOCK_TYPE_VCE:
 234                 ret = smu_dpm_set_vce_enable(smu, gate);
 235                 break;
 236         case AMD_IP_BLOCK_TYPE_GFX:
 237                 ret = smu_gfx_off_control(smu, gate);
 238                 break;
 239         default:
 240                 break;
 241         }
 242
 243         return ret;
 244 }
 245
 246 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 247 {
 248         /* not support power state */
 249         return POWER_STATE_TYPE_DEFAULT;
 250 }
 251
 252 int smu_get_power_num_states(struct smu_context *smu,
 253                              struct pp_states_info *state_info)
 254 {
 255         if (!state_info)
 256                 return -EINVAL;
 257
 258         /* not support power state */
 259         memset(state_info, 0, sizeof(struct pp_states_info));
 260         state_info->nums = 0;
 261
 262         return 0;
 263 }
 264
 265 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 266                            void *data, uint32_t *size)
 267 {
 268         int ret = 0;
 269
 270         switch (sensor) {
 271         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 272                 *((uint32_t *)data) = smu->pstate_sclk;
 273                 *size = 4;
 274                 break;
 275         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 276                 *((uint32_t *)data) = smu->pstate_mclk;
 277                 *size = 4;
 278                 break;
 279         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 280                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 281                 *size = 8;
 282                 break;
 283         case AMDGPU_PP_SENSOR_UVD_POWER:
 284                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 285                 *size = 4;
 286                 break;
 287         case AMDGPU_PP_SENSOR_VCE_POWER:
 288                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 289                 *size = 4;
 290                 break;
 291         default:
 292                 ret = -EINVAL;
 293                 break;
 294         }
 295
 296         if (ret)
 297                 *size = 0;
 298
 299         return ret;
 300 }
 301
 302 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
 303                      void *table_data, bool drv2smu)
 304 {
 305         struct smu_table_context *smu_table = &smu->smu_table;
 306         struct smu_table *table = NULL;
 307         int ret = 0;
 308         int table_id = smu_table_get_index(smu, table_index);
 309
 310         if (!table_data || table_id >= smu_table->table_count)
 311                 return -EINVAL;
 312
 313         table = &smu_table->tables[table_index];
 314
 315         if (drv2smu)
 316                 memcpy(table->cpu_addr, table_data, table->size);
 317
 318         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 319                                           upper_32_bits(table->mc_address));
 320         if (ret)
 321                 return ret;
 322         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 323                                           lower_32_bits(table->mc_address));
 324         if (ret)
 325                 return ret;
 326         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 327                                           SMU_MSG_TransferTableDram2Smu :
 328                                           SMU_MSG_TransferTableSmu2Dram,
 329                                           table_id);
 330         if (ret)
 331                 return ret;
 332
 333         if (!drv2smu)
 334                 memcpy(table_data, table->cpu_addr, table->size);
 335
 336         return ret;
 337 }
 338
 339 bool is_support_sw_smu(struct amdgpu_device *adev)
 340 {
 341         if (adev->asic_type == CHIP_VEGA20)
 342                 return (amdgpu_dpm == 2) ? true : false;
 343         else if (adev->asic_type >= CHIP_NAVI10)
 344                 return true;
 345         else
 346                 return false;
 347 }
 348
 349 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 350 {
 351         struct smu_table_context *smu_table = &smu->smu_table;
 352
 353         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 354                 return -EINVAL;
 355
 356         if (smu_table->hardcode_pptable)
 357                 *table = smu_table->hardcode_pptable;
 358         else
 359                 *table = smu_table->power_play_table;
 360
 361         return smu_table->power_play_table_size;
 362 }
 363
 364 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 365 {
 366         struct smu_table_context *smu_table = &smu->smu_table;
 367         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 368         int ret = 0;
 369
 370         if (!smu->pm_enabled)
 371                 return -EINVAL;
 372         if (header->usStructureSize != size) {
 373                 pr_err("pp table size not matched !\n");
 374                 return -EIO;
 375         }
 376
 377         mutex_lock(&smu->mutex);
 378         if (!smu_table->hardcode_pptable)
 379                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 380         if (!smu_table->hardcode_pptable) {
 381                 ret = -ENOMEM;
 382                 goto failed;
 383         }
 384
 385         memcpy(smu_table->hardcode_pptable, buf, size);
 386         smu_table->power_play_table = smu_table->hardcode_pptable;
 387         smu_table->power_play_table_size = size;
 388         mutex_unlock(&smu->mutex);
 389
 390         ret = smu_reset(smu);
 391         if (ret)
 392                 pr_info("smu reset failed, ret = %d\n", ret);
 393
 394         return ret;
 395
 396 failed:
 397         mutex_unlock(&smu->mutex);
 398         return ret;
 399 }
 400
 401 int smu_feature_init_dpm(struct smu_context *smu)
 402 {
 403         struct smu_feature *feature = &smu->smu_feature;
 404         int ret = 0;
 405         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 406
 407         if (!smu->pm_enabled)
 408                 return ret;
 409         mutex_lock(&feature->mutex);
 410         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 411         mutex_unlock(&feature->mutex);
 412
 413         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 414                                              SMU_FEATURE_MAX/32);
 415         if (ret)
 416                 return ret;
 417
 418         mutex_lock(&feature->mutex);
 419         bitmap_or(feature->allowed, feature->allowed,
 420                       (unsigned long *)allowed_feature_mask,
 421                       feature->feature_num);
 422         mutex_unlock(&feature->mutex);
 423
 424         return ret;
 425 }
 426
 427 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 428 {
 429         struct smu_feature *feature = &smu->smu_feature;
 430         uint32_t feature_id;
 431         int ret = 0;
 432
 433         feature_id = smu_feature_get_index(smu, mask);
 434
 435         WARN_ON(feature_id > feature->feature_num);
 436
 437         mutex_lock(&feature->mutex);
 438         ret = test_bit(feature_id, feature->enabled);
 439         mutex_unlock(&feature->mutex);
 440
 441         return ret;
 442 }
 443
 444 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 445                             bool enable)
 446 {
 447         struct smu_feature *feature = &smu->smu_feature;
 448         uint32_t feature_id;
 449         int ret = 0;
 450
 451         feature_id = smu_feature_get_index(smu, mask);
 452
 453         WARN_ON(feature_id > feature->feature_num);
 454
 455         mutex_lock(&feature->mutex);
 456         ret = smu_feature_update_enable_state(smu, feature_id, enable);
 457         if (ret)
 458                 goto failed;
 459
 460         if (enable)
 461                 test_and_set_bit(feature_id, feature->enabled);
 462         else
 463                 test_and_clear_bit(feature_id, feature->enabled);
 464
 465 failed:
 466         mutex_unlock(&feature->mutex);
 467
 468         return ret;
 469 }
 470
 471 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 472 {
 473         struct smu_feature *feature = &smu->smu_feature;
 474         uint32_t feature_id;
 475         int ret = 0;
 476
 477         feature_id = smu_feature_get_index(smu, mask);
 478
 479         WARN_ON(feature_id > feature->feature_num);
 480
 481         mutex_lock(&feature->mutex);
 482         ret = test_bit(feature_id, feature->supported);
 483         mutex_unlock(&feature->mutex);
 484
 485         return ret;
 486 }
 487
 488 int smu_feature_set_supported(struct smu_context *smu,
 489                               enum smu_feature_mask mask,
 490                               bool enable)
 491 {
 492         struct smu_feature *feature = &smu->smu_feature;
 493         uint32_t feature_id;
 494         int ret = 0;
 495
 496         feature_id = smu_feature_get_index(smu, mask);
 497
 498         WARN_ON(feature_id > feature->feature_num);
 499
 500         mutex_lock(&feature->mutex);
 501         if (enable)
 502                 test_and_set_bit(feature_id, feature->supported);
 503         else
 504                 test_and_clear_bit(feature_id, feature->supported);
 505         mutex_unlock(&feature->mutex);
 506
 507         return ret;
 508 }
 509
 510 static int smu_set_funcs(struct amdgpu_device *adev)
 511 {
 512         struct smu_context *smu = &adev->smu;
 513
 514         switch (adev->asic_type) {
 515         case CHIP_VEGA20:
 516         case CHIP_NAVI10:
 517                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 518                         smu->od_enabled = true;
 519                 smu_v11_0_set_smu_funcs(smu);
 520                 break;
 521         default:
 522                 return -EINVAL;
 523         }
 524
 525         return 0;
 526 }
 527
 528 static int smu_early_init(void *handle)
 529 {
 530         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 531         struct smu_context *smu = &adev->smu;
 532
 533         smu->adev = adev;
 534         smu->pm_enabled = !!amdgpu_dpm;
 535         mutex_init(&smu->mutex);
 536
 537         return smu_set_funcs(adev);
 538 }
 539
 540 static int smu_late_init(void *handle)
 541 {
 542         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 543         struct smu_context *smu = &adev->smu;
 544
 545         if (!smu->pm_enabled)
 546                 return 0;
 547         mutex_lock(&smu->mutex);
 548         smu_handle_task(&adev->smu,
 549                         smu->smu_dpm.dpm_level,
 550                         AMD_PP_TASK_COMPLETE_INIT);
 551         mutex_unlock(&smu->mutex);
 552
 553         return 0;
 554 }
 555
 556 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 557                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 558                             uint8_t **addr)
 559 {
 560         struct amdgpu_device *adev = smu->adev;
 561         uint16_t data_start;
 562
 563         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 564                                            size, frev, crev, &data_start))
 565                 return -EINVAL;
 566
 567         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 568
 569         return 0;
 570 }
 571
 572 static int smu_initialize_pptable(struct smu_context *smu)
 573 {
 574         /* TODO */
 575         return 0;
 576 }
 577
 578 static int smu_smc_table_sw_init(struct smu_context *smu)
 579 {
 580         int ret;
 581
 582         ret = smu_initialize_pptable(smu);
 583         if (ret) {
 584                 pr_err("Failed to init smu_initialize_pptable!\n");
 585                 return ret;
 586         }
 587
 588         /**
 589          * Create smu_table structure, and init smc tables such as
 590          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 591          */
 592         ret = smu_init_smc_tables(smu);
 593         if (ret) {
 594                 pr_err("Failed to init smc tables!\n");
 595                 return ret;
 596         }
 597
 598         /**
 599          * Create smu_power_context structure, and allocate smu_dpm_context and
 600          * context size to fill the smu_power_context data.
 601          */
 602         ret = smu_init_power(smu);
 603         if (ret) {
 604                 pr_err("Failed to init smu_init_power!\n");
 605                 return ret;
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int smu_smc_table_sw_fini(struct smu_context *smu)
 612 {
 613         int ret;
 614
 615         ret = smu_fini_smc_tables(smu);
 616         if (ret) {
 617                 pr_err("Failed to smu_fini_smc_tables!\n");
 618                 return ret;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int smu_sw_init(void *handle)
 625 {
 626         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 627         struct smu_context *smu = &adev->smu;
 628         int ret;
 629
 630         smu->pool_size = adev->pm.smu_prv_buffer_size;
 631         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 632         mutex_init(&smu->smu_feature.mutex);
 633         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 634         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 635         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 636         smu->watermarks_bitmap = 0;
 637         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 638         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 639
 640         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 641         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 642         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 643         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 644         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 645         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 646         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 647         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 648
 649         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 650         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 651         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 652         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 653         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 654         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 655         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 656         smu->display_config = &adev->pm.pm_display_cfg;
 657
 658         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 659         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 660         ret = smu_init_microcode(smu);
 661         if (ret) {
 662                 pr_err("Failed to load smu firmware!\n");
 663                 return ret;
 664         }
 665
 666         ret = smu_smc_table_sw_init(smu);
 667         if (ret) {
 668                 pr_err("Failed to sw init smc table!\n");
 669                 return ret;
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int smu_sw_fini(void *handle)
 676 {
 677         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 678         struct smu_context *smu = &adev->smu;
 679         int ret;
 680
 681         ret = smu_smc_table_sw_fini(smu);
 682         if (ret) {
 683                 pr_err("Failed to sw fini smc table!\n");
 684                 return ret;
 685         }
 686
 687         ret = smu_fini_power(smu);
 688         if (ret) {
 689                 pr_err("Failed to init smu_fini_power!\n");
 690                 return ret;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int smu_init_fb_allocations(struct smu_context *smu)
 697 {
 698         struct amdgpu_device *adev = smu->adev;
 699         struct smu_table_context *smu_table = &smu->smu_table;
 700         struct smu_table *tables = smu_table->tables;
 701         uint32_t table_count = smu_table->table_count;
 702         uint32_t i = 0;
 703         int32_t ret = 0;
 704
 705         if (table_count <= 0)
 706                 return -EINVAL;
 707
 708         for (i = 0 ; i < table_count; i++) {
 709                 if (tables[i].size == 0)
 710                         continue;
 711                 ret = amdgpu_bo_create_kernel(adev,
 712                                               tables[i].size,
 713                                               tables[i].align,
 714                                               tables[i].domain,
 715                                               &tables[i].bo,
 716                                               &tables[i].mc_address,
 717                                               &tables[i].cpu_addr);
 718                 if (ret)
 719                         goto failed;
 720         }
 721
 722         return 0;
 723 failed:
 724         for (; i > 0; i--) {
 725                 if (tables[i].size == 0)
 726                         continue;
 727                 amdgpu_bo_free_kernel(&tables[i].bo,
 728                                       &tables[i].mc_address,
 729                                       &tables[i].cpu_addr);
 730
 731         }
 732         return ret;
 733 }
 734
 735 static int smu_fini_fb_allocations(struct smu_context *smu)
 736 {
 737         struct smu_table_context *smu_table = &smu->smu_table;
 738         struct smu_table *tables = smu_table->tables;
 739         uint32_t table_count = smu_table->table_count;
 740         uint32_t i = 0;
 741
 742         if (table_count == 0 || tables == NULL)
 743                 return 0;
 744
 745         for (i = 0 ; i < table_count; i++) {
 746                 if (tables[i].size == 0)
 747                         continue;
 748                 amdgpu_bo_free_kernel(&tables[i].bo,
 749                                       &tables[i].mc_address,
 750                                       &tables[i].cpu_addr);
 751         }
 752
 753         return 0;
 754 }
 755
 756 static int smu_override_pcie_parameters(struct smu_context *smu)
 757 {
 758         struct amdgpu_device *adev = smu->adev;
 759         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 760         int ret;
 761
 762         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 763                 pcie_gen = 3;
 764         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 765                 pcie_gen = 2;
 766         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 767                 pcie_gen = 1;
 768         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 769                 pcie_gen = 0;
 770
 771         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 772          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 773          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 774          */
 775         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 776                 pcie_width = 6;
 777         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 778                 pcie_width = 5;
 779         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 780                 pcie_width = 4;
 781         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 782                 pcie_width = 3;
 783         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 784                 pcie_width = 2;
 785         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 786                 pcie_width = 1;
 787
 788         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 789         ret = smu_send_smc_msg_with_param(smu,
 790                                           SMU_MSG_OverridePcieParameters,
 791                                           smu_pcie_arg);
 792         if (ret)
 793                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
 794         return ret;
 795 }
 796
 797 static int smu_smc_table_hw_init(struct smu_context *smu,
 798                                  bool initialize)
 799 {
 800         struct amdgpu_device *adev = smu->adev;
 801         int ret;
 802
 803         if (smu_is_dpm_running(smu) && adev->in_suspend) {
 804                 pr_info("dpm has been enabled\n");
 805                 return 0;
 806         }
 807
 808         ret = smu_init_display_count(smu, 0);
 809         if (ret)
 810                 return ret;
 811
 812         if (initialize) {
 813                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
 814                 ret = smu_get_vbios_bootup_values(smu);
 815                 if (ret)
 816                         return ret;
 817
 818                 ret = smu_setup_pptable(smu);
 819                 if (ret)
 820                         return ret;
 821
 822                 /*
 823                  * check if the format_revision in vbios is up to pptable header
 824                  * version, and the structure size is not 0.
 825                  */
 826                 ret = smu_check_pptable(smu);
 827                 if (ret)
 828                         return ret;
 829
 830                 /*
 831                  * allocate vram bos to store smc table contents.
 832                  */
 833                 ret = smu_init_fb_allocations(smu);
 834                 if (ret)
 835                         return ret;
 836
 837                 /*
 838                  * Parse pptable format and fill PPTable_t smc_pptable to
 839                  * smu_table_context structure. And read the smc_dpm_table from vbios,
 840                  * then fill it into smc_pptable.
 841                  */
 842                 ret = smu_parse_pptable(smu);
 843                 if (ret)
 844                         return ret;
 845
 846                 /*
 847                  * Send msg GetDriverIfVersion to check if the return value is equal
 848                  * with DRIVER_IF_VERSION of smc header.
 849                  */
 850                 ret = smu_check_fw_version(smu);
 851                 if (ret)
 852                         return ret;
 853         }
 854
 855         /*
 856          * Copy pptable bo in the vram to smc with SMU MSGs such as
 857          * SetDriverDramAddr and TransferTableDram2Smu.
 858          */
 859         ret = smu_write_pptable(smu);
 860         if (ret)
 861                 return ret;
 862
 863         /* issue RunAfllBtc msg */
 864         ret = smu_run_afll_btc(smu);
 865         if (ret)
 866                 return ret;
 867
 868         ret = smu_feature_set_allowed_mask(smu);
 869         if (ret)
 870                 return ret;
 871
 872         ret = smu_system_features_control(smu, true);
 873         if (ret)
 874                 return ret;
 875
 876         ret = smu_override_pcie_parameters(smu);
 877         if (ret)
 878                 return ret;
 879
 880         ret = smu_notify_display_change(smu);
 881         if (ret)
 882                 return ret;
 883
 884         /*
 885          * Set min deep sleep dce fclk with bootup value from vbios via
 886          * SetMinDeepSleepDcefclk MSG.
 887          */
 888         ret = smu_set_min_dcef_deep_sleep(smu);
 889         if (ret)
 890                 return ret;
 891
 892         /*
 893          * Set initialized values (get from vbios) to dpm tables context such as
 894          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 895          * type of clks.
 896          */
 897         if (initialize) {
 898                 ret = smu_populate_smc_pptable(smu);
 899                 if (ret)
 900                         return ret;
 901
 902                 ret = smu_init_max_sustainable_clocks(smu);
 903                 if (ret)
 904                         return ret;
 905         }
 906
 907         ret = smu_set_default_od_settings(smu, initialize);
 908         if (ret)
 909                 return ret;
 910
 911         if (initialize) {
 912                 ret = smu_populate_umd_state_clk(smu);
 913                 if (ret)
 914                         return ret;
 915
 916                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 917                 if (ret)
 918                         return ret;
 919         }
 920
 921         /*
 922          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 923          */
 924         ret = smu_set_tool_table_location(smu);
 925
 926         if (!smu_is_dpm_running(smu))
 927                 pr_info("dpm has been disabled\n");
 928
 929         return ret;
 930 }
 931
 932 /**
 933  * smu_alloc_memory_pool - allocate memory pool in the system memory
 934  *
 935  * @smu: amdgpu_device pointer
 936  *
 937  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 938  * and DramLogSetDramAddr can notify it changed.
 939  *
 940  * Returns 0 on success, error on failure.
 941  */
 942 static int smu_alloc_memory_pool(struct smu_context *smu)
 943 {
 944         struct amdgpu_device *adev = smu->adev;
 945         struct smu_table_context *smu_table = &smu->smu_table;
 946         struct smu_table *memory_pool = &smu_table->memory_pool;
 947         uint64_t pool_size = smu->pool_size;
 948         int ret = 0;
 949
 950         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 951                 return ret;
 952
 953         memory_pool->size = pool_size;
 954         memory_pool->align = PAGE_SIZE;
 955         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 956
 957         switch (pool_size) {
 958         case SMU_MEMORY_POOL_SIZE_256_MB:
 959         case SMU_MEMORY_POOL_SIZE_512_MB:
 960         case SMU_MEMORY_POOL_SIZE_1_GB:
 961         case SMU_MEMORY_POOL_SIZE_2_GB:
 962                 ret = amdgpu_bo_create_kernel(adev,
 963                                               memory_pool->size,
 964                                               memory_pool->align,
 965                                               memory_pool->domain,
 966                                               &memory_pool->bo,
 967                                               &memory_pool->mc_address,
 968                                               &memory_pool->cpu_addr);
 969                 break;
 970         default:
 971                 break;
 972         }
 973
 974         return ret;
 975 }
 976
 977 static int smu_free_memory_pool(struct smu_context *smu)
 978 {
 979         struct smu_table_context *smu_table = &smu->smu_table;
 980         struct smu_table *memory_pool = &smu_table->memory_pool;
 981         int ret = 0;
 982
 983         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 984                 return ret;
 985
 986         amdgpu_bo_free_kernel(&memory_pool->bo,
 987                               &memory_pool->mc_address,
 988                               &memory_pool->cpu_addr);
 989
 990         memset(memory_pool, 0, sizeof(struct smu_table));
 991
 992         return ret;
 993 }
 994
 995 static int smu_hw_init(void *handle)
 996 {
 997         int ret;
 998         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 999         struct smu_context *smu = &adev->smu;
1000
1001         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1002                 ret = smu_check_fw_status(smu);
1003                 if (ret) {
1004                         pr_err("SMC firmware status is not correct\n");
1005                         return ret;
1006                 }
1007         }
1008
1009         ret = smu_feature_init_dpm(smu);
1010         if (ret)
1011                 goto failed;
1012
1013         ret = smu_smc_table_hw_init(smu, true);
1014         if (ret)
1015                 goto failed;
1016
1017         ret = smu_alloc_memory_pool(smu);
1018         if (ret)
1019                 goto failed;
1020
1021         /*
1022          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1023          * pool location.
1024          */
1025         ret = smu_notify_memory_pool_location(smu);
1026         if (ret)
1027                 goto failed;
1028
1029         ret = smu_start_thermal_control(smu);
1030         if (ret)
1031                 goto failed;
1032
1033         ret = smu_register_irq_handler(smu);
1034         if (ret)
1035                 goto failed;
1036
1037         if (!smu->pm_enabled)
1038                 adev->pm.dpm_enabled = false;
1039         else
1040                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1041
1042         pr_info("SMU is initialized successfully!\n");
1043
1044         return 0;
1045
1046 failed:
1047         mutex_unlock(&smu->mutex);
1048         return ret;
1049 }
1050
1051 static int smu_hw_fini(void *handle)
1052 {
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054         struct smu_context *smu = &adev->smu;
1055         struct smu_table_context *table_context = &smu->smu_table;
1056         int ret = 0;
1057
1058         kfree(table_context->driver_pptable);
1059         table_context->driver_pptable = NULL;
1060
1061         kfree(table_context->max_sustainable_clocks);
1062         table_context->max_sustainable_clocks = NULL;
1063
1064         kfree(table_context->overdrive_table);
1065         table_context->overdrive_table = NULL;
1066
1067         kfree(smu->irq_source);
1068         smu->irq_source = NULL;
1069
1070         ret = smu_fini_fb_allocations(smu);
1071         if (ret)
1072                 return ret;
1073
1074         ret = smu_free_memory_pool(smu);
1075         if (ret)
1076                 return ret;
1077
1078         return 0;
1079 }
1080
1081 int smu_reset(struct smu_context *smu)
1082 {
1083         struct amdgpu_device *adev = smu->adev;
1084         int ret = 0;
1085
1086         ret = smu_hw_fini(adev);
1087         if (ret)
1088                 return ret;
1089
1090         ret = smu_hw_init(adev);
1091         if (ret)
1092                 return ret;
1093
1094         return ret;
1095 }
1096
1097 static int smu_suspend(void *handle)
1098 {
1099         int ret;
1100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101         struct smu_context *smu = &adev->smu;
1102
1103         ret = smu_system_features_control(smu, false);
1104         if (ret)
1105                 return ret;
1106
1107         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1108
1109         if (adev->asic_type >= CHIP_NAVI10 &&
1110             adev->gfx.rlc.funcs->stop)
1111                 adev->gfx.rlc.funcs->stop(adev);
1112
1113         return 0;
1114 }
1115
1116 static int smu_resume(void *handle)
1117 {
1118         int ret;
1119         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120         struct smu_context *smu = &adev->smu;
1121
1122         pr_info("SMU is resuming...\n");
1123
1124         mutex_lock(&smu->mutex);
1125
1126         ret = smu_smc_table_hw_init(smu, false);
1127         if (ret)
1128                 goto failed;
1129
1130         ret = smu_start_thermal_control(smu);
1131         if (ret)
1132                 goto failed;
1133
1134         mutex_unlock(&smu->mutex);
1135
1136         pr_info("SMU is resumed successfully!\n");
1137
1138         return 0;
1139 failed:
1140         mutex_unlock(&smu->mutex);
1141         return ret;
1142 }
1143
1144 int smu_display_configuration_change(struct smu_context *smu,
1145                                      const struct amd_pp_display_configuration *display_config)
1146 {
1147         int index = 0;
1148         int num_of_active_display = 0;
1149
1150         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1151                 return -EINVAL;
1152
1153         if (!display_config)
1154                 return -EINVAL;
1155
1156         mutex_lock(&smu->mutex);
1157
1158         smu_set_deep_sleep_dcefclk(smu,
1159                                    display_config->min_dcef_deep_sleep_set_clk / 100);
1160
1161         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1162                 if (display_config->displays[index].controller_id != 0)
1163                         num_of_active_display++;
1164         }
1165
1166         smu_set_active_display_count(smu, num_of_active_display);
1167
1168         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1169                            display_config->cpu_cc6_disable,
1170                            display_config->cpu_pstate_disable,
1171                            display_config->nb_pstate_switch_disable);
1172
1173         mutex_unlock(&smu->mutex);
1174
1175         return 0;
1176 }
1177
1178 static int smu_get_clock_info(struct smu_context *smu,
1179                               struct smu_clock_info *clk_info,
1180                               enum smu_perf_level_designation designation)
1181 {
1182         int ret;
1183         struct smu_performance_level level = {0};
1184
1185         if (!clk_info)
1186                 return -EINVAL;
1187
1188         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1189         if (ret)
1190                 return -EINVAL;
1191
1192         clk_info->min_mem_clk = level.memory_clock;
1193         clk_info->min_eng_clk = level.core_clock;
1194         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1195
1196         ret = smu_get_perf_level(smu, designation, &level);
1197         if (ret)
1198                 return -EINVAL;
1199
1200         clk_info->min_mem_clk = level.memory_clock;
1201         clk_info->min_eng_clk = level.core_clock;
1202         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1203
1204         return 0;
1205 }
1206
1207 int smu_get_current_clocks(struct smu_context *smu,
1208                            struct amd_pp_clock_info *clocks)
1209 {
1210         struct amd_pp_simple_clock_info simple_clocks = {0};
1211         struct smu_clock_info hw_clocks;
1212         int ret = 0;
1213
1214         if (!is_support_sw_smu(smu->adev))
1215                 return -EINVAL;
1216
1217         mutex_lock(&smu->mutex);
1218
1219         smu_get_dal_power_level(smu, &simple_clocks);
1220
1221         if (smu->support_power_containment)
1222                 ret = smu_get_clock_info(smu, &hw_clocks,
1223                                          PERF_LEVEL_POWER_CONTAINMENT);
1224         else
1225                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1226
1227         if (ret) {
1228                 pr_err("Error in smu_get_clock_info\n");
1229                 goto failed;
1230         }
1231
1232         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1233         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1234         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1235         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1236         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1237         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1238         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1239         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1240
1241         if (simple_clocks.level == 0)
1242                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1243         else
1244                 clocks->max_clocks_state = simple_clocks.level;
1245
1246         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1247                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1248                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1249         }
1250
1251 failed:
1252         mutex_unlock(&smu->mutex);
1253         return ret;
1254 }
1255
1256 static int smu_set_clockgating_state(void *handle,
1257                                      enum amd_clockgating_state state)
1258 {
1259         return 0;
1260 }
1261
1262 static int smu_set_powergating_state(void *handle,
1263                                      enum amd_powergating_state state)
1264 {
1265         return 0;
1266 }
1267
1268 static int smu_enable_umd_pstate(void *handle,
1269                       enum amd_dpm_forced_level *level)
1270 {
1271         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1272                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1273                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1274                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1275
1276         struct smu_context *smu = (struct smu_context*)(handle);
1277         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1278         if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1279                 return -EINVAL;
1280
1281         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1282                 /* enter umd pstate, save current level, disable gfx cg*/
1283                 if (*level & profile_mode_mask) {
1284                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1285                         smu_dpm_ctx->enable_umd_pstate = true;
1286                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1287                                                                AMD_IP_BLOCK_TYPE_GFX,
1288                                                                AMD_CG_STATE_UNGATE);
1289                         amdgpu_device_ip_set_powergating_state(smu->adev,
1290                                                                AMD_IP_BLOCK_TYPE_GFX,
1291                                                                AMD_PG_STATE_UNGATE);
1292                 }
1293         } else {
1294                 /* exit umd pstate, restore level, enable gfx cg*/
1295                 if (!(*level & profile_mode_mask)) {
1296                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1297                                 *level = smu_dpm_ctx->saved_dpm_level;
1298                         smu_dpm_ctx->enable_umd_pstate = false;
1299                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1300                                                                AMD_IP_BLOCK_TYPE_GFX,
1301                                                                AMD_CG_STATE_GATE);
1302                         amdgpu_device_ip_set_powergating_state(smu->adev,
1303                                                                AMD_IP_BLOCK_TYPE_GFX,
1304                                                                AMD_PG_STATE_GATE);
1305                 }
1306         }
1307
1308         return 0;
1309 }
1310
1311 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1312                                    enum amd_dpm_forced_level level,
1313                                    bool skip_display_settings)
1314 {
1315         int ret = 0;
1316         int index = 0;
1317         uint32_t sclk_mask, mclk_mask, soc_mask;
1318         long workload;
1319         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1320
1321         if (!smu->pm_enabled)
1322                 return -EINVAL;
1323         if (!skip_display_settings) {
1324                 ret = smu_display_config_changed(smu);
1325                 if (ret) {
1326                         pr_err("Failed to change display config!");
1327                         return ret;
1328                 }
1329         }
1330
1331         if (!smu->pm_enabled)
1332                 return -EINVAL;
1333         ret = smu_apply_clocks_adjust_rules(smu);
1334         if (ret) {
1335                 pr_err("Failed to apply clocks adjust rules!");
1336                 return ret;
1337         }
1338
1339         if (!skip_display_settings) {
1340                 ret = smu_notify_smc_dispaly_config(smu);
1341                 if (ret) {
1342                         pr_err("Failed to notify smc display config!");
1343                         return ret;
1344                 }
1345         }
1346
1347         if (smu_dpm_ctx->dpm_level != level) {
1348                 switch (level) {
1349                 case AMD_DPM_FORCED_LEVEL_HIGH:
1350                         ret = smu_force_dpm_limit_value(smu, true);
1351                         break;
1352                 case AMD_DPM_FORCED_LEVEL_LOW:
1353                         ret = smu_force_dpm_limit_value(smu, false);
1354                         break;
1355
1356                 case AMD_DPM_FORCED_LEVEL_AUTO:
1357                         ret = smu_unforce_dpm_levels(smu);
1358                         break;
1359
1360                 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1361                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1362                 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1363                 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1364                         ret = smu_get_profiling_clk_mask(smu, level,
1365                                                          &sclk_mask,
1366                                                          &mclk_mask,
1367                                                          &soc_mask);
1368                         if (ret)
1369                                 return ret;
1370                         smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
1371                         smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
1372                         break;
1373
1374                 case AMD_DPM_FORCED_LEVEL_MANUAL:
1375                 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1376                 default:
1377                         break;
1378                 }
1379
1380                 if (!ret)
1381                         smu_dpm_ctx->dpm_level = level;
1382         }
1383
1384         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1385                 index = fls(smu->workload_mask);
1386                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1387                 workload = smu->workload_setting[index];
1388
1389                 if (smu->power_profile_mode != workload)
1390                         smu_set_power_profile_mode(smu, &workload, 0);
1391         }
1392
1393         return ret;
1394 }
1395
1396 int smu_handle_task(struct smu_context *smu,
1397                     enum amd_dpm_forced_level level,
1398                     enum amd_pp_task task_id)
1399 {
1400         int ret = 0;
1401
1402         switch (task_id) {
1403         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1404                 ret = smu_pre_display_config_changed(smu);
1405                 if (ret)
1406                         return ret;
1407                 ret = smu_set_cpu_power_state(smu);
1408                 if (ret)
1409                         return ret;
1410                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1411                 break;
1412         case AMD_PP_TASK_COMPLETE_INIT:
1413         case AMD_PP_TASK_READJUST_POWER_STATE:
1414                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1415                 break;
1416         default:
1417                 break;
1418         }
1419
1420         return ret;
1421 }
1422
1423 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1424 {
1425         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1426
1427         if (!smu_dpm_ctx->dpm_context)
1428                 return -EINVAL;
1429
1430         mutex_lock(&(smu->mutex));
1431         if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
1432                 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1433         }
1434         mutex_unlock(&(smu->mutex));
1435
1436         return smu_dpm_ctx->dpm_level;
1437 }
1438
1439 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1440 {
1441         int ret = 0;
1442         int i;
1443         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1444
1445         if (!smu_dpm_ctx->dpm_context)
1446                 return -EINVAL;
1447
1448         for (i = 0; i < smu->adev->num_ip_blocks; i++) {
1449                 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
1450                         break;
1451         }
1452
1453
1454         smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
1455         ret = smu_handle_task(smu, level,
1456                               AMD_PP_TASK_READJUST_POWER_STATE);
1457         if (ret)
1458                 return ret;
1459
1460         mutex_lock(&smu->mutex);
1461         smu_dpm_ctx->dpm_level = level;
1462         mutex_unlock(&smu->mutex);
1463
1464         return ret;
1465 }
1466
1467 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1468 {
1469         int ret = 0;
1470
1471         mutex_lock(&smu->mutex);
1472         ret = smu_init_display_count(smu, count);
1473         mutex_unlock(&smu->mutex);
1474
1475         return ret;
1476 }
1477
1478 const struct amd_ip_funcs smu_ip_funcs = {
1479         .name = "smu",
1480         .early_init = smu_early_init,
1481         .late_init = smu_late_init,
1482         .sw_init = smu_sw_init,
1483         .sw_fini = smu_sw_fini,
1484         .hw_init = smu_hw_init,
1485         .hw_fini = smu_hw_fini,
1486         .suspend = smu_suspend,
1487         .resume = smu_resume,
1488         .is_idle = NULL,
1489         .check_soft_reset = NULL,
1490         .wait_for_idle = NULL,
1491         .soft_reset = NULL,
1492         .set_clockgating_state = smu_set_clockgating_state,
1493         .set_powergating_state = smu_set_powergating_state,
1494         .enable_umd_pstate = smu_enable_umd_pstate,
1495 };
1496
1497 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1498 {
1499         .type = AMD_IP_BLOCK_TYPE_SMC,
1500         .major = 11,
1501         .minor = 0,
1502         .rev = 0,
1503         .funcs = &smu_ip_funcs,
1504 };