2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "soc15_common.h"
29 #include "smu_v11_0.h"
33 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
37 if (!if_version && !smu_version)
41 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
45 ret = smu_read_smc_arg(smu, if_version);
51 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
55 ret = smu_read_smc_arg(smu, smu_version);
63 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
64 uint32_t min, uint32_t max)
66 int ret = 0, clk_id = 0;
69 if (min <= 0 && max <= 0)
72 clk_id = smu_clk_get_index(smu, clk_type);
77 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
78 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
85 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
86 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
96 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
97 uint32_t min, uint32_t max)
99 int ret = 0, clk_id = 0;
102 if (min <= 0 && max <= 0)
105 clk_id = smu_clk_get_index(smu, clk_type);
110 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
111 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
118 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
119 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
129 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
130 uint32_t *min, uint32_t *max)
132 int ret = 0, clk_id = 0;
138 clk_id = smu_clk_get_index(smu, clk_type);
142 param = (clk_id & 0xffff) << 16;
145 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
148 ret = smu_read_smc_arg(smu, max);
154 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
157 ret = smu_read_smc_arg(smu, min);
165 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
166 uint16_t level, uint32_t *value)
168 int ret = 0, clk_id = 0;
174 clk_id = smu_clk_get_index(smu, clk_type);
178 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
180 ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
185 ret = smu_read_smc_arg(smu, ¶m);
189 /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
190 * now, we un-support it */
191 *value = param & 0x7fffffff;
196 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
199 return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
202 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
207 switch (block_type) {
208 case AMD_IP_BLOCK_TYPE_UVD:
209 ret = smu_dpm_set_uvd_enable(smu, gate);
211 case AMD_IP_BLOCK_TYPE_VCE:
212 ret = smu_dpm_set_vce_enable(smu, gate);
221 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
223 /* not support power state */
224 return POWER_STATE_TYPE_DEFAULT;
227 int smu_get_power_num_states(struct smu_context *smu,
228 struct pp_states_info *state_info)
233 /* not support power state */
234 memset(state_info, 0, sizeof(struct pp_states_info));
235 state_info->nums = 0;
240 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
241 void *data, uint32_t *size)
246 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
247 *((uint32_t *)data) = smu->pstate_sclk;
250 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
251 *((uint32_t *)data) = smu->pstate_mclk;
254 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
255 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
258 case AMDGPU_PP_SENSOR_UVD_POWER:
259 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
262 case AMDGPU_PP_SENSOR_VCE_POWER:
263 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
277 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
278 void *table_data, bool drv2smu)
280 struct smu_table_context *smu_table = &smu->smu_table;
281 struct smu_table *table = NULL;
283 int table_id = smu_table_get_index(smu, table_index);
285 if (!table_data || table_id >= smu_table->table_count)
288 table = &smu_table->tables[table_index];
291 memcpy(table->cpu_addr, table_data, table->size);
293 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
294 upper_32_bits(table->mc_address));
297 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
298 lower_32_bits(table->mc_address));
301 ret = smu_send_smc_msg_with_param(smu, drv2smu ?
302 SMU_MSG_TransferTableDram2Smu :
303 SMU_MSG_TransferTableSmu2Dram,
309 memcpy(table_data, table->cpu_addr, table->size);
314 bool is_support_sw_smu(struct amdgpu_device *adev)
316 if (adev->asic_type == CHIP_VEGA20)
317 return (amdgpu_dpm == 2) ? true : false;
318 else if (adev->asic_type >= CHIP_NAVI10)
324 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
326 struct smu_table_context *smu_table = &smu->smu_table;
328 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
331 if (smu_table->hardcode_pptable)
332 *table = smu_table->hardcode_pptable;
334 *table = smu_table->power_play_table;
336 return smu_table->power_play_table_size;
339 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
341 struct smu_table_context *smu_table = &smu->smu_table;
342 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
345 if (!smu->pm_enabled)
347 if (header->usStructureSize != size) {
348 pr_err("pp table size not matched !\n");
352 mutex_lock(&smu->mutex);
353 if (!smu_table->hardcode_pptable)
354 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
355 if (!smu_table->hardcode_pptable) {
360 memcpy(smu_table->hardcode_pptable, buf, size);
361 smu_table->power_play_table = smu_table->hardcode_pptable;
362 smu_table->power_play_table_size = size;
363 mutex_unlock(&smu->mutex);
365 ret = smu_reset(smu);
367 pr_info("smu reset failed, ret = %d\n", ret);
372 mutex_unlock(&smu->mutex);
376 int smu_feature_init_dpm(struct smu_context *smu)
378 struct smu_feature *feature = &smu->smu_feature;
380 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
382 if (!smu->pm_enabled)
384 mutex_lock(&feature->mutex);
385 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
386 mutex_unlock(&feature->mutex);
388 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
393 mutex_lock(&feature->mutex);
394 bitmap_or(feature->allowed, feature->allowed,
395 (unsigned long *)allowed_feature_mask,
396 feature->feature_num);
397 mutex_unlock(&feature->mutex);
402 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
404 struct smu_feature *feature = &smu->smu_feature;
408 feature_id = smu_feature_get_index(smu, mask);
410 WARN_ON(feature_id > feature->feature_num);
412 mutex_lock(&feature->mutex);
413 ret = test_bit(feature_id, feature->enabled);
414 mutex_unlock(&feature->mutex);
419 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
422 struct smu_feature *feature = &smu->smu_feature;
426 feature_id = smu_feature_get_index(smu, mask);
428 WARN_ON(feature_id > feature->feature_num);
430 mutex_lock(&feature->mutex);
431 ret = smu_feature_update_enable_state(smu, feature_id, enable);
436 test_and_set_bit(feature_id, feature->enabled);
438 test_and_clear_bit(feature_id, feature->enabled);
441 mutex_unlock(&feature->mutex);
446 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
448 struct smu_feature *feature = &smu->smu_feature;
452 feature_id = smu_feature_get_index(smu, mask);
454 WARN_ON(feature_id > feature->feature_num);
456 mutex_lock(&feature->mutex);
457 ret = test_bit(feature_id, feature->supported);
458 mutex_unlock(&feature->mutex);
463 int smu_feature_set_supported(struct smu_context *smu,
464 enum smu_feature_mask mask,
467 struct smu_feature *feature = &smu->smu_feature;
471 feature_id = smu_feature_get_index(smu, mask);
473 WARN_ON(feature_id > feature->feature_num);
475 mutex_lock(&feature->mutex);
477 test_and_set_bit(feature_id, feature->supported);
479 test_and_clear_bit(feature_id, feature->supported);
480 mutex_unlock(&feature->mutex);
485 static int smu_set_funcs(struct amdgpu_device *adev)
487 struct smu_context *smu = &adev->smu;
489 switch (adev->asic_type) {
492 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
493 smu->od_enabled = true;
494 smu_v11_0_set_smu_funcs(smu);
503 static int smu_early_init(void *handle)
505 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
506 struct smu_context *smu = &adev->smu;
509 smu->pm_enabled = !!amdgpu_dpm;
510 mutex_init(&smu->mutex);
512 return smu_set_funcs(adev);
515 static int smu_late_init(void *handle)
517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
518 struct smu_context *smu = &adev->smu;
520 if (!smu->pm_enabled)
522 mutex_lock(&smu->mutex);
523 smu_handle_task(&adev->smu,
524 smu->smu_dpm.dpm_level,
525 AMD_PP_TASK_COMPLETE_INIT);
526 mutex_unlock(&smu->mutex);
531 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
532 uint16_t *size, uint8_t *frev, uint8_t *crev,
535 struct amdgpu_device *adev = smu->adev;
538 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
539 size, frev, crev, &data_start))
542 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
547 static int smu_initialize_pptable(struct smu_context *smu)
553 static int smu_smc_table_sw_init(struct smu_context *smu)
557 ret = smu_initialize_pptable(smu);
559 pr_err("Failed to init smu_initialize_pptable!\n");
564 * Create smu_table structure, and init smc tables such as
565 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
567 ret = smu_init_smc_tables(smu);
569 pr_err("Failed to init smc tables!\n");
574 * Create smu_power_context structure, and allocate smu_dpm_context and
575 * context size to fill the smu_power_context data.
577 ret = smu_init_power(smu);
579 pr_err("Failed to init smu_init_power!\n");
586 static int smu_smc_table_sw_fini(struct smu_context *smu)
590 ret = smu_fini_smc_tables(smu);
592 pr_err("Failed to smu_fini_smc_tables!\n");
599 static int smu_sw_init(void *handle)
601 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
602 struct smu_context *smu = &adev->smu;
605 smu->pool_size = adev->pm.smu_prv_buffer_size;
606 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
607 mutex_init(&smu->smu_feature.mutex);
608 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
609 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
610 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
611 smu->watermarks_bitmap = 0;
612 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
613 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
615 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
616 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
617 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
618 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
619 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
620 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
621 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
622 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
624 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
625 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
626 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
627 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
628 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
629 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
630 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
631 smu->display_config = &adev->pm.pm_display_cfg;
633 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
634 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
635 ret = smu_init_microcode(smu);
637 pr_err("Failed to load smu firmware!\n");
641 ret = smu_smc_table_sw_init(smu);
643 pr_err("Failed to sw init smc table!\n");
650 static int smu_sw_fini(void *handle)
652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
653 struct smu_context *smu = &adev->smu;
656 ret = smu_smc_table_sw_fini(smu);
658 pr_err("Failed to sw fini smc table!\n");
662 ret = smu_fini_power(smu);
664 pr_err("Failed to init smu_fini_power!\n");
671 static int smu_init_fb_allocations(struct smu_context *smu)
673 struct amdgpu_device *adev = smu->adev;
674 struct smu_table_context *smu_table = &smu->smu_table;
675 struct smu_table *tables = smu_table->tables;
676 uint32_t table_count = smu_table->table_count;
680 if (table_count <= 0)
683 for (i = 0 ; i < table_count; i++) {
684 if (tables[i].size == 0)
686 ret = amdgpu_bo_create_kernel(adev,
691 &tables[i].mc_address,
692 &tables[i].cpu_addr);
700 if (tables[i].size == 0)
702 amdgpu_bo_free_kernel(&tables[i].bo,
703 &tables[i].mc_address,
704 &tables[i].cpu_addr);
710 static int smu_fini_fb_allocations(struct smu_context *smu)
712 struct smu_table_context *smu_table = &smu->smu_table;
713 struct smu_table *tables = smu_table->tables;
714 uint32_t table_count = smu_table->table_count;
717 if (table_count == 0 || tables == NULL)
720 for (i = 0 ; i < table_count; i++) {
721 if (tables[i].size == 0)
723 amdgpu_bo_free_kernel(&tables[i].bo,
724 &tables[i].mc_address,
725 &tables[i].cpu_addr);
731 static int smu_override_pcie_parameters(struct smu_context *smu)
733 struct amdgpu_device *adev = smu->adev;
734 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
737 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
739 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
741 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
743 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
746 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
747 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
748 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
750 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
752 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
754 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
756 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
758 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
760 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
763 smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
764 ret = smu_send_smc_msg_with_param(smu,
765 SMU_MSG_OverridePcieParameters,
768 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
772 static int smu_smc_table_hw_init(struct smu_context *smu,
775 struct amdgpu_device *adev = smu->adev;
778 if (smu_is_dpm_running(smu) && adev->in_suspend) {
779 pr_info("dpm has been enabled\n");
783 ret = smu_init_display(smu);
788 /* get boot_values from vbios to set revision, gfxclk, and etc. */
789 ret = smu_get_vbios_bootup_values(smu);
793 ret = smu_setup_pptable(smu);
798 * check if the format_revision in vbios is up to pptable header
799 * version, and the structure size is not 0.
801 ret = smu_check_pptable(smu);
806 * allocate vram bos to store smc table contents.
808 ret = smu_init_fb_allocations(smu);
813 * Parse pptable format and fill PPTable_t smc_pptable to
814 * smu_table_context structure. And read the smc_dpm_table from vbios,
815 * then fill it into smc_pptable.
817 ret = smu_parse_pptable(smu);
822 * Send msg GetDriverIfVersion to check if the return value is equal
823 * with DRIVER_IF_VERSION of smc header.
825 ret = smu_check_fw_version(smu);
831 * Copy pptable bo in the vram to smc with SMU MSGs such as
832 * SetDriverDramAddr and TransferTableDram2Smu.
834 ret = smu_write_pptable(smu);
838 /* issue RunAfllBtc msg */
839 ret = smu_run_afll_btc(smu);
843 ret = smu_feature_set_allowed_mask(smu);
847 ret = smu_system_features_control(smu, true);
851 ret = smu_override_pcie_parameters(smu);
855 ret = smu_notify_display_change(smu);
860 * Set min deep sleep dce fclk with bootup value from vbios via
861 * SetMinDeepSleepDcefclk MSG.
863 ret = smu_set_min_dcef_deep_sleep(smu);
868 * Set initialized values (get from vbios) to dpm tables context such as
869 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
873 ret = smu_populate_smc_pptable(smu);
877 ret = smu_init_max_sustainable_clocks(smu);
882 ret = smu_set_od8_default_settings(smu, initialize);
887 ret = smu_populate_umd_state_clk(smu);
891 ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
897 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
899 ret = smu_set_tool_table_location(smu);
901 if (!smu_is_dpm_running(smu))
902 pr_info("dpm has been disabled\n");
908 * smu_alloc_memory_pool - allocate memory pool in the system memory
910 * @smu: amdgpu_device pointer
912 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
913 * and DramLogSetDramAddr can notify it changed.
915 * Returns 0 on success, error on failure.
917 static int smu_alloc_memory_pool(struct smu_context *smu)
919 struct amdgpu_device *adev = smu->adev;
920 struct smu_table_context *smu_table = &smu->smu_table;
921 struct smu_table *memory_pool = &smu_table->memory_pool;
922 uint64_t pool_size = smu->pool_size;
925 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
928 memory_pool->size = pool_size;
929 memory_pool->align = PAGE_SIZE;
930 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
933 case SMU_MEMORY_POOL_SIZE_256_MB:
934 case SMU_MEMORY_POOL_SIZE_512_MB:
935 case SMU_MEMORY_POOL_SIZE_1_GB:
936 case SMU_MEMORY_POOL_SIZE_2_GB:
937 ret = amdgpu_bo_create_kernel(adev,
942 &memory_pool->mc_address,
943 &memory_pool->cpu_addr);
952 static int smu_free_memory_pool(struct smu_context *smu)
954 struct smu_table_context *smu_table = &smu->smu_table;
955 struct smu_table *memory_pool = &smu_table->memory_pool;
958 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
961 amdgpu_bo_free_kernel(&memory_pool->bo,
962 &memory_pool->mc_address,
963 &memory_pool->cpu_addr);
965 memset(memory_pool, 0, sizeof(struct smu_table));
970 static int smu_hw_init(void *handle)
973 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
974 struct smu_context *smu = &adev->smu;
976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
977 ret = smu_check_fw_status(smu);
979 pr_err("SMC firmware status is not correct\n");
984 mutex_lock(&smu->mutex);
986 ret = smu_feature_init_dpm(smu);
990 ret = smu_smc_table_hw_init(smu, true);
994 ret = smu_alloc_memory_pool(smu);
999 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1002 ret = smu_notify_memory_pool_location(smu);
1006 ret = smu_start_thermal_control(smu);
1010 mutex_unlock(&smu->mutex);
1012 if (!smu->pm_enabled)
1013 adev->pm.dpm_enabled = false;
1015 adev->pm.dpm_enabled = true; /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1017 pr_info("SMU is initialized successfully!\n");
1022 mutex_unlock(&smu->mutex);
1026 static int smu_hw_fini(void *handle)
1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 struct smu_context *smu = &adev->smu;
1030 struct smu_table_context *table_context = &smu->smu_table;
1033 kfree(table_context->driver_pptable);
1034 table_context->driver_pptable = NULL;
1036 kfree(table_context->max_sustainable_clocks);
1037 table_context->max_sustainable_clocks = NULL;
1039 kfree(table_context->od_feature_capabilities);
1040 table_context->od_feature_capabilities = NULL;
1042 kfree(table_context->od_settings_max);
1043 table_context->od_settings_max = NULL;
1045 kfree(table_context->od_settings_min);
1046 table_context->od_settings_min = NULL;
1048 kfree(table_context->overdrive_table);
1049 table_context->overdrive_table = NULL;
1051 kfree(table_context->od8_settings);
1052 table_context->od8_settings = NULL;
1054 ret = smu_fini_fb_allocations(smu);
1058 ret = smu_free_memory_pool(smu);
1065 int smu_reset(struct smu_context *smu)
1067 struct amdgpu_device *adev = smu->adev;
1070 ret = smu_hw_fini(adev);
1074 ret = smu_hw_init(adev);
1081 static int smu_suspend(void *handle)
1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085 struct smu_context *smu = &adev->smu;
1087 ret = smu_system_features_control(smu, false);
1091 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1093 if (adev->asic_type >= CHIP_NAVI10 &&
1094 adev->gfx.rlc.funcs->stop)
1095 adev->gfx.rlc.funcs->stop(adev);
1100 static int smu_resume(void *handle)
1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104 struct smu_context *smu = &adev->smu;
1106 pr_info("SMU is resuming...\n");
1108 mutex_lock(&smu->mutex);
1110 ret = smu_smc_table_hw_init(smu, false);
1114 ret = smu_start_thermal_control(smu);
1118 mutex_unlock(&smu->mutex);
1120 pr_info("SMU is resumed successfully!\n");
1124 mutex_unlock(&smu->mutex);
1128 int smu_display_configuration_change(struct smu_context *smu,
1129 const struct amd_pp_display_configuration *display_config)
1132 int num_of_active_display = 0;
1134 if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1137 if (!display_config)
1140 mutex_lock(&smu->mutex);
1142 smu_set_deep_sleep_dcefclk(smu,
1143 display_config->min_dcef_deep_sleep_set_clk / 100);
1145 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1146 if (display_config->displays[index].controller_id != 0)
1147 num_of_active_display++;
1150 smu_set_active_display_count(smu, num_of_active_display);
1152 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1153 display_config->cpu_cc6_disable,
1154 display_config->cpu_pstate_disable,
1155 display_config->nb_pstate_switch_disable);
1157 mutex_unlock(&smu->mutex);
1162 static int smu_get_clock_info(struct smu_context *smu,
1163 struct smu_clock_info *clk_info,
1164 enum smu_perf_level_designation designation)
1167 struct smu_performance_level level = {0};
1172 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1176 clk_info->min_mem_clk = level.memory_clock;
1177 clk_info->min_eng_clk = level.core_clock;
1178 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1180 ret = smu_get_perf_level(smu, designation, &level);
1184 clk_info->min_mem_clk = level.memory_clock;
1185 clk_info->min_eng_clk = level.core_clock;
1186 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1191 int smu_get_current_clocks(struct smu_context *smu,
1192 struct amd_pp_clock_info *clocks)
1194 struct amd_pp_simple_clock_info simple_clocks = {0};
1195 struct smu_clock_info hw_clocks;
1198 if (!is_support_sw_smu(smu->adev))
1201 mutex_lock(&smu->mutex);
1203 smu_get_dal_power_level(smu, &simple_clocks);
1205 if (smu->support_power_containment)
1206 ret = smu_get_clock_info(smu, &hw_clocks,
1207 PERF_LEVEL_POWER_CONTAINMENT);
1209 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1212 pr_err("Error in smu_get_clock_info\n");
1216 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1217 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1218 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1219 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1220 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1221 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1222 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1223 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1225 if (simple_clocks.level == 0)
1226 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1228 clocks->max_clocks_state = simple_clocks.level;
1230 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1231 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1232 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1236 mutex_unlock(&smu->mutex);
1240 static int smu_set_clockgating_state(void *handle,
1241 enum amd_clockgating_state state)
1246 static int smu_set_powergating_state(void *handle,
1247 enum amd_powergating_state state)
1252 static int smu_enable_umd_pstate(void *handle,
1253 enum amd_dpm_forced_level *level)
1255 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1256 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1257 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1258 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1260 struct smu_context *smu = (struct smu_context*)(handle);
1261 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1262 if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1265 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1266 /* enter umd pstate, save current level, disable gfx cg*/
1267 if (*level & profile_mode_mask) {
1268 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1269 smu_dpm_ctx->enable_umd_pstate = true;
1270 amdgpu_device_ip_set_clockgating_state(smu->adev,
1271 AMD_IP_BLOCK_TYPE_GFX,
1272 AMD_CG_STATE_UNGATE);
1273 amdgpu_device_ip_set_powergating_state(smu->adev,
1274 AMD_IP_BLOCK_TYPE_GFX,
1275 AMD_PG_STATE_UNGATE);
1278 /* exit umd pstate, restore level, enable gfx cg*/
1279 if (!(*level & profile_mode_mask)) {
1280 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1281 *level = smu_dpm_ctx->saved_dpm_level;
1282 smu_dpm_ctx->enable_umd_pstate = false;
1283 amdgpu_device_ip_set_clockgating_state(smu->adev,
1284 AMD_IP_BLOCK_TYPE_GFX,
1286 amdgpu_device_ip_set_powergating_state(smu->adev,
1287 AMD_IP_BLOCK_TYPE_GFX,
1295 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1296 enum amd_dpm_forced_level level,
1297 bool skip_display_settings)
1301 uint32_t sclk_mask, mclk_mask, soc_mask;
1303 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1305 if (!smu->pm_enabled)
1307 if (!skip_display_settings) {
1308 ret = smu_display_config_changed(smu);
1310 pr_err("Failed to change display config!");
1315 if (!smu->pm_enabled)
1317 ret = smu_apply_clocks_adjust_rules(smu);
1319 pr_err("Failed to apply clocks adjust rules!");
1323 if (!skip_display_settings) {
1324 ret = smu_notify_smc_dispaly_config(smu);
1326 pr_err("Failed to notify smc display config!");
1331 if (smu_dpm_ctx->dpm_level != level) {
1333 case AMD_DPM_FORCED_LEVEL_HIGH:
1334 ret = smu_force_dpm_limit_value(smu, true);
1336 case AMD_DPM_FORCED_LEVEL_LOW:
1337 ret = smu_force_dpm_limit_value(smu, false);
1340 case AMD_DPM_FORCED_LEVEL_AUTO:
1341 ret = smu_unforce_dpm_levels(smu);
1344 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1345 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1346 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1347 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1348 ret = smu_get_profiling_clk_mask(smu, level,
1354 smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
1355 smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
1358 case AMD_DPM_FORCED_LEVEL_MANUAL:
1359 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1365 smu_dpm_ctx->dpm_level = level;
1368 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1369 index = fls(smu->workload_mask);
1370 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1371 workload = smu->workload_setting[index];
1373 if (smu->power_profile_mode != workload)
1374 smu_set_power_profile_mode(smu, &workload, 0);
1380 int smu_handle_task(struct smu_context *smu,
1381 enum amd_dpm_forced_level level,
1382 enum amd_pp_task task_id)
1387 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1388 ret = smu_pre_display_config_changed(smu);
1391 ret = smu_set_cpu_power_state(smu);
1394 ret = smu_adjust_power_state_dynamic(smu, level, false);
1396 case AMD_PP_TASK_COMPLETE_INIT:
1397 case AMD_PP_TASK_READJUST_POWER_STATE:
1398 ret = smu_adjust_power_state_dynamic(smu, level, true);
1407 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1409 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1411 if (!smu_dpm_ctx->dpm_context)
1414 mutex_lock(&(smu->mutex));
1415 if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
1416 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1418 mutex_unlock(&(smu->mutex));
1420 return smu_dpm_ctx->dpm_level;
1423 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1427 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1429 if (!smu_dpm_ctx->dpm_context)
1432 for (i = 0; i < smu->adev->num_ip_blocks; i++) {
1433 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
1437 mutex_lock(&smu->mutex);
1439 smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
1440 ret = smu_handle_task(smu, level,
1441 AMD_PP_TASK_READJUST_POWER_STATE);
1443 mutex_unlock(&smu->mutex);
1448 const struct amd_ip_funcs smu_ip_funcs = {
1450 .early_init = smu_early_init,
1451 .late_init = smu_late_init,
1452 .sw_init = smu_sw_init,
1453 .sw_fini = smu_sw_fini,
1454 .hw_init = smu_hw_init,
1455 .hw_fini = smu_hw_fini,
1456 .suspend = smu_suspend,
1457 .resume = smu_resume,
1459 .check_soft_reset = NULL,
1460 .wait_for_idle = NULL,
1462 .set_clockgating_state = smu_set_clockgating_state,
1463 .set_powergating_state = smu_set_powergating_state,
1464 .enable_umd_pstate = smu_enable_umd_pstate,
1467 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1469 .type = AMD_IP_BLOCK_TYPE_SMC,
1473 .funcs = &smu_ip_funcs,