drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "soc15_common.h"
  30 #include "smu_v11_0.h"
  31 #include "smu_v12_0.h"
  32 #include "atom.h"
  33 #include "amd_pcie.h"
  34 #include "vega20_ppt.h"
  35 #include "arcturus_ppt.h"
  36 #include "navi10_ppt.h"
  37 #include "renoir_ppt.h"
  38
  39 #undef __SMU_DUMMY_MAP
  40 #define __SMU_DUMMY_MAP(type)   #type
  41 static const char* __smu_message_names[] = {
  42         SMU_MESSAGE_TYPES
  43 };
  44
  45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  46 {
  47         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  48                 return "unknown smu message";
  49         return __smu_message_names[type];
  50 }
  51
  52 #undef __SMU_DUMMY_MAP
  53 #define __SMU_DUMMY_MAP(fea)    #fea
  54 static const char* __smu_feature_names[] = {
  55         SMU_FEATURE_MASKS
  56 };
  57
  58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  59 {
  60         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  61                 return "unknown smu feature";
  62         return __smu_feature_names[feature];
  63 }
  64
  65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  66 {
  67         size_t size = 0;
  68         int ret = 0, i = 0;
  69         uint32_t feature_mask[2] = { 0 };
  70         int32_t feature_index = 0;
  71         uint32_t count = 0;
  72         uint32_t sort_feature[SMU_FEATURE_COUNT];
  73         uint64_t hw_feature_count = 0;
  74
  75         mutex_lock(&smu->mutex);
  76
  77         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  78         if (ret)
  79                 goto failed;
  80
  81         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  82                         feature_mask[1], feature_mask[0]);
  83
  84         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  85                 feature_index = smu_feature_get_index(smu, i);
  86                 if (feature_index < 0)
  87                         continue;
  88                 sort_feature[feature_index] = i;
  89                 hw_feature_count++;
  90         }
  91
  92         for (i = 0; i < hw_feature_count; i++) {
  93                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  94                                count++,
  95                                smu_get_feature_name(smu, sort_feature[i]),
  96                                i,
  97                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  98                                "enabled" : "disabled");
  99         }
 100
 101 failed:
 102         mutex_unlock(&smu->mutex);
 103
 104         return size;
 105 }
 106
 107 static int smu_feature_update_enable_state(struct smu_context *smu,
 108                                            uint64_t feature_mask,
 109                                            bool enabled)
 110 {
 111         struct smu_feature *feature = &smu->smu_feature;
 112         uint32_t feature_low = 0, feature_high = 0;
 113         int ret = 0;
 114
 115         if (!smu->pm_enabled)
 116                 return ret;
 117
 118         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 119         feature_high = (feature_mask >> 32) & 0xffffffff;
 120
 121         if (enabled) {
 122                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 123                                                   feature_low);
 124                 if (ret)
 125                         return ret;
 126                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 127                                                   feature_high);
 128                 if (ret)
 129                         return ret;
 130         } else {
 131                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 132                                                   feature_low);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 136                                                   feature_high);
 137                 if (ret)
 138                         return ret;
 139         }
 140
 141         mutex_lock(&feature->mutex);
 142         if (enabled)
 143                 bitmap_or(feature->enabled, feature->enabled,
 144                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 145         else
 146                 bitmap_andnot(feature->enabled, feature->enabled,
 147                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 148         mutex_unlock(&feature->mutex);
 149
 150         return ret;
 151 }
 152
 153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 154 {
 155         int ret = 0;
 156         uint32_t feature_mask[2] = { 0 };
 157         uint64_t feature_2_enabled = 0;
 158         uint64_t feature_2_disabled = 0;
 159         uint64_t feature_enables = 0;
 160
 161         mutex_lock(&smu->mutex);
 162
 163         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 164         if (ret)
 165                 goto out;
 166
 167         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 168
 169         feature_2_enabled  = ~feature_enables & new_mask;
 170         feature_2_disabled = feature_enables & ~new_mask;
 171
 172         if (feature_2_enabled) {
 173                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 174                 if (ret)
 175                         goto out;
 176         }
 177         if (feature_2_disabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 179                 if (ret)
 180                         goto out;
 181         }
 182
 183 out:
 184         mutex_unlock(&smu->mutex);
 185
 186         return ret;
 187 }
 188
 189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 190 {
 191         int ret = 0;
 192
 193         if (!if_version && !smu_version)
 194                 return -EINVAL;
 195
 196         if (if_version) {
 197                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 198                 if (ret)
 199                         return ret;
 200
 201                 ret = smu_read_smc_arg(smu, if_version);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         if (smu_version) {
 207                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 208                 if (ret)
 209                         return ret;
 210
 211                 ret = smu_read_smc_arg(smu, smu_version);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return ret;
 217 }
 218
 219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 220                             uint32_t min, uint32_t max)
 221 {
 222         int ret = 0;
 223
 224         if (min <= 0 && max <= 0)
 225                 return -EINVAL;
 226
 227         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 228                 return 0;
 229
 230         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 231         return ret;
 232 }
 233
 234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 235                             uint32_t min, uint32_t max)
 236 {
 237         int ret = 0, clk_id = 0;
 238         uint32_t param;
 239
 240         if (min <= 0 && max <= 0)
 241                 return -EINVAL;
 242
 243         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 244                 return 0;
 245
 246         clk_id = smu_clk_get_index(smu, clk_type);
 247         if (clk_id < 0)
 248                 return clk_id;
 249
 250         if (max > 0) {
 251                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 252                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 253                                                   param);
 254                 if (ret)
 255                         return ret;
 256         }
 257
 258         if (min > 0) {
 259                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 260                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 261                                                   param);
 262                 if (ret)
 263                         return ret;
 264         }
 265
 266
 267         return ret;
 268 }
 269
 270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 271                            uint32_t *min, uint32_t *max, bool lock_needed)
 272 {
 273         uint32_t clock_limit;
 274         int ret = 0;
 275
 276         if (!min && !max)
 277                 return -EINVAL;
 278
 279         if (lock_needed)
 280                 mutex_lock(&smu->mutex);
 281
 282         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 283                 switch (clk_type) {
 284                 case SMU_MCLK:
 285                 case SMU_UCLK:
 286                         clock_limit = smu->smu_table.boot_values.uclk;
 287                         break;
 288                 case SMU_GFXCLK:
 289                 case SMU_SCLK:
 290                         clock_limit = smu->smu_table.boot_values.gfxclk;
 291                         break;
 292                 case SMU_SOCCLK:
 293                         clock_limit = smu->smu_table.boot_values.socclk;
 294                         break;
 295                 default:
 296                         clock_limit = 0;
 297                         break;
 298                 }
 299
 300                 /* clock in Mhz unit */
 301                 if (min)
 302                         *min = clock_limit / 100;
 303                 if (max)
 304                         *max = clock_limit / 100;
 305         } else {
 306                 /*
 307                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 308                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 309                  */
 310                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 311         }
 312
 313         if (lock_needed)
 314                 mutex_unlock(&smu->mutex);
 315
 316         return ret;
 317 }
 318
 319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 320                               uint16_t level, uint32_t *value)
 321 {
 322         int ret = 0, clk_id = 0;
 323         uint32_t param;
 324
 325         if (!value)
 326                 return -EINVAL;
 327
 328         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 329                 return 0;
 330
 331         clk_id = smu_clk_get_index(smu, clk_type);
 332         if (clk_id < 0)
 333                 return clk_id;
 334
 335         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 336
 337         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 338                                           param);
 339         if (ret)
 340                 return ret;
 341
 342         ret = smu_read_smc_arg(smu, &param);
 343         if (ret)
 344                 return ret;
 345
 346         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 347          * now, we un-support it */
 348         *value = param & 0x7fffffff;
 349
 350         return ret;
 351 }
 352
 353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 354                             uint32_t *value)
 355 {
 356         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 357 }
 358
 359 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
 360                             uint32_t *min_value, uint32_t *max_value)
 361 {
 362         int ret = 0;
 363         uint32_t level_count = 0;
 364
 365         if (!min_value && !max_value)
 366                 return -EINVAL;
 367
 368         if (min_value) {
 369                 /* by default, level 0 clock value as min value */
 370                 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
 371                 if (ret)
 372                         return ret;
 373         }
 374
 375         if (max_value) {
 376                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 377                 if (ret)
 378                         return ret;
 379
 380                 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         return ret;
 386 }
 387
 388 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 389 {
 390         enum smu_feature_mask feature_id = 0;
 391
 392         switch (clk_type) {
 393         case SMU_MCLK:
 394         case SMU_UCLK:
 395                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 396                 break;
 397         case SMU_GFXCLK:
 398         case SMU_SCLK:
 399                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 400                 break;
 401         case SMU_SOCCLK:
 402                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 403                 break;
 404         default:
 405                 return true;
 406         }
 407
 408         if(!smu_feature_is_enabled(smu, feature_id)) {
 409                 return false;
 410         }
 411
 412         return true;
 413 }
 414
 415 /**
 416  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 417  *
 418  * @smu:        smu_context pointer
 419  * @block_type: the IP block to power gate/ungate
 420  * @gate:       to power gate if true, ungate otherwise
 421  *
 422  * This API uses no smu->mutex lock protection due to:
 423  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 424  *    This is guarded to be race condition free by the caller.
 425  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 426  *    Under this case, the smu->mutex lock protection is already enforced on
 427  *    the parent API smu_force_performance_level of the call path.
 428  */
 429 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 430                            bool gate)
 431 {
 432         int ret = 0;
 433
 434         switch (block_type) {
 435         case AMD_IP_BLOCK_TYPE_UVD:
 436                 ret = smu_dpm_set_uvd_enable(smu, !gate);
 437                 break;
 438         case AMD_IP_BLOCK_TYPE_VCE:
 439                 ret = smu_dpm_set_vce_enable(smu, !gate);
 440                 break;
 441         case AMD_IP_BLOCK_TYPE_GFX:
 442                 ret = smu_gfx_off_control(smu, gate);
 443                 break;
 444         case AMD_IP_BLOCK_TYPE_SDMA:
 445                 ret = smu_powergate_sdma(smu, gate);
 446                 break;
 447         case AMD_IP_BLOCK_TYPE_JPEG:
 448                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 449                 break;
 450         default:
 451                 break;
 452         }
 453
 454         return ret;
 455 }
 456
 457 int smu_get_power_num_states(struct smu_context *smu,
 458                              struct pp_states_info *state_info)
 459 {
 460         if (!state_info)
 461                 return -EINVAL;
 462
 463         /* not support power state */
 464         memset(state_info, 0, sizeof(struct pp_states_info));
 465         state_info->nums = 1;
 466         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 467
 468         return 0;
 469 }
 470
 471 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 472                            void *data, uint32_t *size)
 473 {
 474         struct smu_power_context *smu_power = &smu->smu_power;
 475         struct smu_power_gate *power_gate = &smu_power->power_gate;
 476         int ret = 0;
 477
 478         if(!data || !size)
 479                 return -EINVAL;
 480
 481         switch (sensor) {
 482         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 483                 *((uint32_t *)data) = smu->pstate_sclk;
 484                 *size = 4;
 485                 break;
 486         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 487                 *((uint32_t *)data) = smu->pstate_mclk;
 488                 *size = 4;
 489                 break;
 490         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 491                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 492                 *size = 8;
 493                 break;
 494         case AMDGPU_PP_SENSOR_UVD_POWER:
 495                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 496                 *size = 4;
 497                 break;
 498         case AMDGPU_PP_SENSOR_VCE_POWER:
 499                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 500                 *size = 4;
 501                 break;
 502         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 503                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 504                 *size = 4;
 505                 break;
 506         default:
 507                 ret = -EINVAL;
 508                 break;
 509         }
 510
 511         if (ret)
 512                 *size = 0;
 513
 514         return ret;
 515 }
 516
 517 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 518                      void *table_data, bool drv2smu)
 519 {
 520         struct smu_table_context *smu_table = &smu->smu_table;
 521         struct amdgpu_device *adev = smu->adev;
 522         struct smu_table *table = &smu_table->driver_table;
 523         int table_id = smu_table_get_index(smu, table_index);
 524         uint32_t table_size;
 525         int ret = 0;
 526
 527         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 528                 return -EINVAL;
 529
 530         table_size = smu_table->tables[table_index].size;
 531
 532         if (drv2smu) {
 533                 memcpy(table->cpu_addr, table_data, table_size);
 534                 /*
 535                  * Flush hdp cache: to guard the content seen by
 536                  * GPU is consitent with CPU.
 537                  */
 538                 amdgpu_asic_flush_hdp(adev, NULL);
 539         }
 540
 541         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 542                                           SMU_MSG_TransferTableDram2Smu :
 543                                           SMU_MSG_TransferTableSmu2Dram,
 544                                           table_id | ((argument & 0xFFFF) << 16));
 545         if (ret)
 546                 return ret;
 547
 548         if (!drv2smu) {
 549                 amdgpu_asic_flush_hdp(adev, NULL);
 550                 memcpy(table_data, table->cpu_addr, table_size);
 551         }
 552
 553         return ret;
 554 }
 555
 556 bool is_support_sw_smu(struct amdgpu_device *adev)
 557 {
 558         if (adev->asic_type == CHIP_VEGA20)
 559                 return (amdgpu_dpm == 2) ? true : false;
 560         else if (adev->asic_type >= CHIP_ARCTURUS) {
 561                 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
 562                         return false;
 563                 else
 564                         return true;
 565         } else
 566                 return false;
 567 }
 568
 569 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 570 {
 571         if (!is_support_sw_smu(adev))
 572                 return false;
 573
 574         if (adev->asic_type == CHIP_VEGA20)
 575                 return true;
 576
 577         return false;
 578 }
 579
 580 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 581 {
 582         struct smu_table_context *smu_table = &smu->smu_table;
 583         uint32_t powerplay_table_size;
 584
 585         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 586                 return -EINVAL;
 587
 588         mutex_lock(&smu->mutex);
 589
 590         if (smu_table->hardcode_pptable)
 591                 *table = smu_table->hardcode_pptable;
 592         else
 593                 *table = smu_table->power_play_table;
 594
 595         powerplay_table_size = smu_table->power_play_table_size;
 596
 597         mutex_unlock(&smu->mutex);
 598
 599         return powerplay_table_size;
 600 }
 601
 602 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 603 {
 604         struct smu_table_context *smu_table = &smu->smu_table;
 605         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 606         int ret = 0;
 607
 608         if (!smu->pm_enabled)
 609                 return -EINVAL;
 610         if (header->usStructureSize != size) {
 611                 pr_err("pp table size not matched !\n");
 612                 return -EIO;
 613         }
 614
 615         mutex_lock(&smu->mutex);
 616         if (!smu_table->hardcode_pptable)
 617                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 618         if (!smu_table->hardcode_pptable) {
 619                 ret = -ENOMEM;
 620                 goto failed;
 621         }
 622
 623         memcpy(smu_table->hardcode_pptable, buf, size);
 624         smu_table->power_play_table = smu_table->hardcode_pptable;
 625         smu_table->power_play_table_size = size;
 626
 627         /*
 628          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 629          * skipped) may be needed for custom pptable uploading.
 630          */
 631         smu->uploading_custom_pp_table = true;
 632
 633         ret = smu_reset(smu);
 634         if (ret)
 635                 pr_info("smu reset failed, ret = %d\n", ret);
 636
 637         smu->uploading_custom_pp_table = false;
 638
 639 failed:
 640         mutex_unlock(&smu->mutex);
 641         return ret;
 642 }
 643
 644 int smu_feature_init_dpm(struct smu_context *smu)
 645 {
 646         struct smu_feature *feature = &smu->smu_feature;
 647         int ret = 0;
 648         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 649
 650         if (!smu->pm_enabled)
 651                 return ret;
 652         mutex_lock(&feature->mutex);
 653         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 654         mutex_unlock(&feature->mutex);
 655
 656         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 657                                              SMU_FEATURE_MAX/32);
 658         if (ret)
 659                 return ret;
 660
 661         mutex_lock(&feature->mutex);
 662         bitmap_or(feature->allowed, feature->allowed,
 663                       (unsigned long *)allowed_feature_mask,
 664                       feature->feature_num);
 665         mutex_unlock(&feature->mutex);
 666
 667         return ret;
 668 }
 669
 670
 671 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 672 {
 673         struct smu_feature *feature = &smu->smu_feature;
 674         int feature_id;
 675         int ret = 0;
 676
 677         if (smu->is_apu)
 678                 return 1;
 679
 680         feature_id = smu_feature_get_index(smu, mask);
 681         if (feature_id < 0)
 682                 return 0;
 683
 684         WARN_ON(feature_id > feature->feature_num);
 685
 686         mutex_lock(&feature->mutex);
 687         ret = test_bit(feature_id, feature->enabled);
 688         mutex_unlock(&feature->mutex);
 689
 690         return ret;
 691 }
 692
 693 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 694                             bool enable)
 695 {
 696         struct smu_feature *feature = &smu->smu_feature;
 697         int feature_id;
 698
 699         feature_id = smu_feature_get_index(smu, mask);
 700         if (feature_id < 0)
 701                 return -EINVAL;
 702
 703         WARN_ON(feature_id > feature->feature_num);
 704
 705         return smu_feature_update_enable_state(smu,
 706                                                1ULL << feature_id,
 707                                                enable);
 708 }
 709
 710 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 711 {
 712         struct smu_feature *feature = &smu->smu_feature;
 713         int feature_id;
 714         int ret = 0;
 715
 716         feature_id = smu_feature_get_index(smu, mask);
 717         if (feature_id < 0)
 718                 return 0;
 719
 720         WARN_ON(feature_id > feature->feature_num);
 721
 722         mutex_lock(&feature->mutex);
 723         ret = test_bit(feature_id, feature->supported);
 724         mutex_unlock(&feature->mutex);
 725
 726         return ret;
 727 }
 728
 729 int smu_feature_set_supported(struct smu_context *smu,
 730                               enum smu_feature_mask mask,
 731                               bool enable)
 732 {
 733         struct smu_feature *feature = &smu->smu_feature;
 734         int feature_id;
 735         int ret = 0;
 736
 737         feature_id = smu_feature_get_index(smu, mask);
 738         if (feature_id < 0)
 739                 return -EINVAL;
 740
 741         WARN_ON(feature_id > feature->feature_num);
 742
 743         mutex_lock(&feature->mutex);
 744         if (enable)
 745                 test_and_set_bit(feature_id, feature->supported);
 746         else
 747                 test_and_clear_bit(feature_id, feature->supported);
 748         mutex_unlock(&feature->mutex);
 749
 750         return ret;
 751 }
 752
 753 static int smu_set_funcs(struct amdgpu_device *adev)
 754 {
 755         struct smu_context *smu = &adev->smu;
 756
 757         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 758                 smu->od_enabled = true;
 759
 760         switch (adev->asic_type) {
 761         case CHIP_VEGA20:
 762                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 763                 vega20_set_ppt_funcs(smu);
 764                 break;
 765         case CHIP_NAVI10:
 766         case CHIP_NAVI14:
 767         case CHIP_NAVI12:
 768                 navi10_set_ppt_funcs(smu);
 769                 break;
 770         case CHIP_ARCTURUS:
 771                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 772                 arcturus_set_ppt_funcs(smu);
 773                 /* OD is not supported on Arcturus */
 774                 smu->od_enabled =false;
 775                 break;
 776         case CHIP_RENOIR:
 777                 renoir_set_ppt_funcs(smu);
 778                 break;
 779         default:
 780                 return -EINVAL;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int smu_early_init(void *handle)
 787 {
 788         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 789         struct smu_context *smu = &adev->smu;
 790
 791         smu->adev = adev;
 792         smu->pm_enabled = !!amdgpu_dpm;
 793         smu->is_apu = false;
 794         mutex_init(&smu->mutex);
 795
 796         return smu_set_funcs(adev);
 797 }
 798
 799 static int smu_late_init(void *handle)
 800 {
 801         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 802         struct smu_context *smu = &adev->smu;
 803
 804         if (!smu->pm_enabled)
 805                 return 0;
 806
 807         smu_handle_task(&adev->smu,
 808                         smu->smu_dpm.dpm_level,
 809                         AMD_PP_TASK_COMPLETE_INIT,
 810                         false);
 811
 812         return 0;
 813 }
 814
 815 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 816                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 817                             uint8_t **addr)
 818 {
 819         struct amdgpu_device *adev = smu->adev;
 820         uint16_t data_start;
 821
 822         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 823                                            size, frev, crev, &data_start))
 824                 return -EINVAL;
 825
 826         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 827
 828         return 0;
 829 }
 830
 831 static int smu_initialize_pptable(struct smu_context *smu)
 832 {
 833         /* TODO */
 834         return 0;
 835 }
 836
 837 static int smu_smc_table_sw_init(struct smu_context *smu)
 838 {
 839         int ret;
 840
 841         ret = smu_initialize_pptable(smu);
 842         if (ret) {
 843                 pr_err("Failed to init smu_initialize_pptable!\n");
 844                 return ret;
 845         }
 846
 847         /**
 848          * Create smu_table structure, and init smc tables such as
 849          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 850          */
 851         ret = smu_init_smc_tables(smu);
 852         if (ret) {
 853                 pr_err("Failed to init smc tables!\n");
 854                 return ret;
 855         }
 856
 857         /**
 858          * Create smu_power_context structure, and allocate smu_dpm_context and
 859          * context size to fill the smu_power_context data.
 860          */
 861         ret = smu_init_power(smu);
 862         if (ret) {
 863                 pr_err("Failed to init smu_init_power!\n");
 864                 return ret;
 865         }
 866
 867         return 0;
 868 }
 869
 870 static int smu_smc_table_sw_fini(struct smu_context *smu)
 871 {
 872         int ret;
 873
 874         ret = smu_fini_smc_tables(smu);
 875         if (ret) {
 876                 pr_err("Failed to smu_fini_smc_tables!\n");
 877                 return ret;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int smu_sw_init(void *handle)
 884 {
 885         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 886         struct smu_context *smu = &adev->smu;
 887         int ret;
 888
 889         smu->pool_size = adev->pm.smu_prv_buffer_size;
 890         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 891         mutex_init(&smu->smu_feature.mutex);
 892         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 893         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 894         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 895
 896         mutex_init(&smu->smu_baco.mutex);
 897         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 898         smu->smu_baco.platform_support = false;
 899
 900         mutex_init(&smu->sensor_lock);
 901         mutex_init(&smu->metrics_lock);
 902
 903         smu->watermarks_bitmap = 0;
 904         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 905         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 906
 907         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 908         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 909         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 910         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 911         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 912         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 913         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 914         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 915
 916         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 917         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 918         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 919         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 920         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 921         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 922         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 923         smu->display_config = &adev->pm.pm_display_cfg;
 924
 925         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 926         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 927         ret = smu_init_microcode(smu);
 928         if (ret) {
 929                 pr_err("Failed to load smu firmware!\n");
 930                 return ret;
 931         }
 932
 933         ret = smu_smc_table_sw_init(smu);
 934         if (ret) {
 935                 pr_err("Failed to sw init smc table!\n");
 936                 return ret;
 937         }
 938
 939         ret = smu_register_irq_handler(smu);
 940         if (ret) {
 941                 pr_err("Failed to register smc irq handler!\n");
 942                 return ret;
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int smu_sw_fini(void *handle)
 949 {
 950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 951         struct smu_context *smu = &adev->smu;
 952         int ret;
 953
 954         kfree(smu->irq_source);
 955         smu->irq_source = NULL;
 956
 957         ret = smu_smc_table_sw_fini(smu);
 958         if (ret) {
 959                 pr_err("Failed to sw fini smc table!\n");
 960                 return ret;
 961         }
 962
 963         ret = smu_fini_power(smu);
 964         if (ret) {
 965                 pr_err("Failed to init smu_fini_power!\n");
 966                 return ret;
 967         }
 968
 969         return 0;
 970 }
 971
 972 static int smu_init_fb_allocations(struct smu_context *smu)
 973 {
 974         struct amdgpu_device *adev = smu->adev;
 975         struct smu_table_context *smu_table = &smu->smu_table;
 976         struct smu_table *tables = smu_table->tables;
 977         struct smu_table *driver_table = &(smu_table->driver_table);
 978         uint32_t max_table_size = 0;
 979         int ret, i;
 980
 981         /* VRAM allocation for tool table */
 982         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 983                 ret = amdgpu_bo_create_kernel(adev,
 984                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 985                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 986                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 987                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 988                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 989                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 990                 if (ret) {
 991                         pr_err("VRAM allocation for tool table failed!\n");
 992                         return ret;
 993                 }
 994         }
 995
 996         /* VRAM allocation for driver table */
 997         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 998                 if (tables[i].size == 0)
 999                         continue;
1000
1001                 if (i == SMU_TABLE_PMSTATUSLOG)
1002                         continue;
1003
1004                 if (max_table_size < tables[i].size)
1005                         max_table_size = tables[i].size;
1006         }
1007
1008         driver_table->size = max_table_size;
1009         driver_table->align = PAGE_SIZE;
1010         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
1011
1012         ret = amdgpu_bo_create_kernel(adev,
1013                                       driver_table->size,
1014                                       driver_table->align,
1015                                       driver_table->domain,
1016                                       &driver_table->bo,
1017                                       &driver_table->mc_address,
1018                                       &driver_table->cpu_addr);
1019         if (ret) {
1020                 pr_err("VRAM allocation for driver table failed!\n");
1021                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1022                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1023                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1024                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1025         }
1026
1027         return ret;
1028 }
1029
1030 static int smu_fini_fb_allocations(struct smu_context *smu)
1031 {
1032         struct smu_table_context *smu_table = &smu->smu_table;
1033         struct smu_table *tables = smu_table->tables;
1034         struct smu_table *driver_table = &(smu_table->driver_table);
1035
1036         if (!tables)
1037                 return 0;
1038
1039         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1040                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1041                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1042                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1043
1044         amdgpu_bo_free_kernel(&driver_table->bo,
1045                               &driver_table->mc_address,
1046                               &driver_table->cpu_addr);
1047
1048         return 0;
1049 }
1050
1051 static int smu_smc_table_hw_init(struct smu_context *smu,
1052                                  bool initialize)
1053 {
1054         struct amdgpu_device *adev = smu->adev;
1055         int ret;
1056
1057         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1058                 pr_info("dpm has been enabled\n");
1059                 return 0;
1060         }
1061
1062         if (adev->asic_type != CHIP_ARCTURUS) {
1063                 ret = smu_init_display_count(smu, 0);
1064                 if (ret)
1065                         return ret;
1066         }
1067
1068         if (initialize) {
1069                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1070                 ret = smu_get_vbios_bootup_values(smu);
1071                 if (ret)
1072                         return ret;
1073
1074                 ret = smu_setup_pptable(smu);
1075                 if (ret)
1076                         return ret;
1077
1078                 ret = smu_get_clk_info_from_vbios(smu);
1079                 if (ret)
1080                         return ret;
1081
1082                 /*
1083                  * check if the format_revision in vbios is up to pptable header
1084                  * version, and the structure size is not 0.
1085                  */
1086                 ret = smu_check_pptable(smu);
1087                 if (ret)
1088                         return ret;
1089
1090                 /*
1091                  * allocate vram bos to store smc table contents.
1092                  */
1093                 ret = smu_init_fb_allocations(smu);
1094                 if (ret)
1095                         return ret;
1096
1097                 /*
1098                  * Parse pptable format and fill PPTable_t smc_pptable to
1099                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1100                  * then fill it into smc_pptable.
1101                  */
1102                 ret = smu_parse_pptable(smu);
1103                 if (ret)
1104                         return ret;
1105
1106                 /*
1107                  * Send msg GetDriverIfVersion to check if the return value is equal
1108                  * with DRIVER_IF_VERSION of smc header.
1109                  */
1110                 ret = smu_check_fw_version(smu);
1111                 if (ret)
1112                         return ret;
1113         }
1114
1115         /* smu_dump_pptable(smu); */
1116         if (!amdgpu_sriov_vf(adev)) {
1117                 ret = smu_set_driver_table_location(smu);
1118                 if (ret)
1119                         return ret;
1120
1121                 /*
1122                  * Copy pptable bo in the vram to smc with SMU MSGs such as
1123                  * SetDriverDramAddr and TransferTableDram2Smu.
1124                  */
1125                 ret = smu_write_pptable(smu);
1126                 if (ret)
1127                         return ret;
1128
1129                 /* issue Run*Btc msg */
1130                 ret = smu_run_btc(smu);
1131                 if (ret)
1132                         return ret;
1133                 ret = smu_feature_set_allowed_mask(smu);
1134                 if (ret)
1135                         return ret;
1136
1137                 ret = smu_system_features_control(smu, true);
1138                 if (ret)
1139                         return ret;
1140         }
1141         if (adev->asic_type != CHIP_ARCTURUS) {
1142                 ret = smu_notify_display_change(smu);
1143                 if (ret)
1144                         return ret;
1145
1146                 /*
1147                  * Set min deep sleep dce fclk with bootup value from vbios via
1148                  * SetMinDeepSleepDcefclk MSG.
1149                  */
1150                 ret = smu_set_min_dcef_deep_sleep(smu);
1151                 if (ret)
1152                         return ret;
1153         }
1154
1155         /*
1156          * Set initialized values (get from vbios) to dpm tables context such as
1157          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1158          * type of clks.
1159          */
1160         if (initialize) {
1161                 ret = smu_populate_smc_tables(smu);
1162                 if (ret)
1163                         return ret;
1164
1165                 ret = smu_init_max_sustainable_clocks(smu);
1166                 if (ret)
1167                         return ret;
1168         }
1169
1170         if (adev->asic_type != CHIP_ARCTURUS) {
1171                 ret = smu_override_pcie_parameters(smu);
1172                 if (ret)
1173                         return ret;
1174         }
1175
1176         ret = smu_set_default_od_settings(smu, initialize);
1177         if (ret)
1178                 return ret;
1179
1180         if (initialize) {
1181                 ret = smu_populate_umd_state_clk(smu);
1182                 if (ret)
1183                         return ret;
1184
1185                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1186                 if (ret)
1187                         return ret;
1188         }
1189
1190         /*
1191          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1192          */
1193         if (!amdgpu_sriov_vf(adev)) {
1194                 ret = smu_set_tool_table_location(smu);
1195         }
1196         if (!smu_is_dpm_running(smu))
1197                 pr_info("dpm has been disabled\n");
1198
1199         return ret;
1200 }
1201
1202 /**
1203  * smu_alloc_memory_pool - allocate memory pool in the system memory
1204  *
1205  * @smu: amdgpu_device pointer
1206  *
1207  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1208  * and DramLogSetDramAddr can notify it changed.
1209  *
1210  * Returns 0 on success, error on failure.
1211  */
1212 static int smu_alloc_memory_pool(struct smu_context *smu)
1213 {
1214         struct amdgpu_device *adev = smu->adev;
1215         struct smu_table_context *smu_table = &smu->smu_table;
1216         struct smu_table *memory_pool = &smu_table->memory_pool;
1217         uint64_t pool_size = smu->pool_size;
1218         int ret = 0;
1219
1220         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1221                 return ret;
1222
1223         memory_pool->size = pool_size;
1224         memory_pool->align = PAGE_SIZE;
1225         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1226
1227         switch (pool_size) {
1228         case SMU_MEMORY_POOL_SIZE_256_MB:
1229         case SMU_MEMORY_POOL_SIZE_512_MB:
1230         case SMU_MEMORY_POOL_SIZE_1_GB:
1231         case SMU_MEMORY_POOL_SIZE_2_GB:
1232                 ret = amdgpu_bo_create_kernel(adev,
1233                                               memory_pool->size,
1234                                               memory_pool->align,
1235                                               memory_pool->domain,
1236                                               &memory_pool->bo,
1237                                               &memory_pool->mc_address,
1238                                               &memory_pool->cpu_addr);
1239                 break;
1240         default:
1241                 break;
1242         }
1243
1244         return ret;
1245 }
1246
1247 static int smu_free_memory_pool(struct smu_context *smu)
1248 {
1249         struct smu_table_context *smu_table = &smu->smu_table;
1250         struct smu_table *memory_pool = &smu_table->memory_pool;
1251
1252         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1253                 return 0;
1254
1255         amdgpu_bo_free_kernel(&memory_pool->bo,
1256                               &memory_pool->mc_address,
1257                               &memory_pool->cpu_addr);
1258
1259         memset(memory_pool, 0, sizeof(struct smu_table));
1260
1261         return 0;
1262 }
1263
1264 static int smu_start_smc_engine(struct smu_context *smu)
1265 {
1266         struct amdgpu_device *adev = smu->adev;
1267         int ret = 0;
1268
1269         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1270                 if (adev->asic_type < CHIP_NAVI10) {
1271                         if (smu->ppt_funcs->load_microcode) {
1272                                 ret = smu->ppt_funcs->load_microcode(smu);
1273                                 if (ret)
1274                                         return ret;
1275                         }
1276                 }
1277         }
1278
1279         if (smu->ppt_funcs->check_fw_status) {
1280                 ret = smu->ppt_funcs->check_fw_status(smu);
1281                 if (ret)
1282                         pr_err("SMC is not ready\n");
1283         }
1284
1285         return ret;
1286 }
1287
1288 static int smu_hw_init(void *handle)
1289 {
1290         int ret;
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292         struct smu_context *smu = &adev->smu;
1293
1294         ret = smu_start_smc_engine(smu);
1295         if (ret) {
1296                 pr_err("SMU is not ready yet!\n");
1297                 return ret;
1298         }
1299
1300         if (smu->is_apu) {
1301                 smu_powergate_sdma(&adev->smu, false);
1302                 smu_powergate_vcn(&adev->smu, false);
1303                 smu_powergate_jpeg(&adev->smu, false);
1304                 smu_set_gfx_cgpg(&adev->smu, true);
1305         }
1306
1307         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1308                 return 0;
1309
1310         if (!smu->pm_enabled)
1311                 return 0;
1312
1313         ret = smu_feature_init_dpm(smu);
1314         if (ret)
1315                 goto failed;
1316
1317         ret = smu_smc_table_hw_init(smu, true);
1318         if (ret)
1319                 goto failed;
1320
1321         ret = smu_alloc_memory_pool(smu);
1322         if (ret)
1323                 goto failed;
1324
1325         /*
1326          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1327          * pool location.
1328          */
1329         ret = smu_notify_memory_pool_location(smu);
1330         if (ret)
1331                 goto failed;
1332
1333         ret = smu_start_thermal_control(smu);
1334         if (ret)
1335                 goto failed;
1336
1337         if (!smu->pm_enabled)
1338                 adev->pm.dpm_enabled = false;
1339         else
1340                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1341
1342         pr_info("SMU is initialized successfully!\n");
1343
1344         return 0;
1345
1346 failed:
1347         return ret;
1348 }
1349
1350 static int smu_stop_dpms(struct smu_context *smu)
1351 {
1352         return smu_system_features_control(smu, false);
1353 }
1354
1355 static int smu_hw_fini(void *handle)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358         struct smu_context *smu = &adev->smu;
1359         struct smu_table_context *table_context = &smu->smu_table;
1360         int ret = 0;
1361
1362         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1363                 return 0;
1364
1365         if (smu->is_apu) {
1366                 smu_powergate_sdma(&adev->smu, true);
1367                 smu_powergate_vcn(&adev->smu, true);
1368                 smu_powergate_jpeg(&adev->smu, true);
1369         }
1370
1371         if (!smu->pm_enabled)
1372                 return 0;
1373
1374         if (!amdgpu_sriov_vf(adev)){
1375                 ret = smu_stop_thermal_control(smu);
1376                 if (ret) {
1377                         pr_warn("Fail to stop thermal control!\n");
1378                         return ret;
1379                 }
1380
1381                 /*
1382                  * For custom pptable uploading, skip the DPM features
1383                  * disable process on Navi1x ASICs.
1384                  *   - As the gfx related features are under control of
1385                  *     RLC on those ASICs. RLC reinitialization will be
1386                  *     needed to reenable them. That will cost much more
1387                  *     efforts.
1388                  *
1389                  *   - SMU firmware can handle the DPM reenablement
1390                  *     properly.
1391                  */
1392                 if (!smu->uploading_custom_pp_table ||
1393                                 !((adev->asic_type >= CHIP_NAVI10) &&
1394                                         (adev->asic_type <= CHIP_NAVI12))) {
1395                         ret = smu_stop_dpms(smu);
1396                         if (ret) {
1397                                 pr_warn("Fail to stop Dpms!\n");
1398                                 return ret;
1399                         }
1400                 }
1401         }
1402
1403         kfree(table_context->driver_pptable);
1404         table_context->driver_pptable = NULL;
1405
1406         kfree(table_context->max_sustainable_clocks);
1407         table_context->max_sustainable_clocks = NULL;
1408
1409         kfree(table_context->overdrive_table);
1410         table_context->overdrive_table = NULL;
1411
1412         ret = smu_fini_fb_allocations(smu);
1413         if (ret)
1414                 return ret;
1415
1416         ret = smu_free_memory_pool(smu);
1417         if (ret)
1418                 return ret;
1419
1420         return 0;
1421 }
1422
1423 int smu_reset(struct smu_context *smu)
1424 {
1425         struct amdgpu_device *adev = smu->adev;
1426         int ret = 0;
1427
1428         ret = smu_hw_fini(adev);
1429         if (ret)
1430                 return ret;
1431
1432         ret = smu_hw_init(adev);
1433         if (ret)
1434                 return ret;
1435
1436         return ret;
1437 }
1438
1439 static int smu_suspend(void *handle)
1440 {
1441         int ret;
1442         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1443         struct smu_context *smu = &adev->smu;
1444         bool baco_feature_is_enabled = false;
1445
1446         if (!smu->pm_enabled)
1447                 return 0;
1448
1449         if(!smu->is_apu)
1450                 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1451
1452         ret = smu_system_features_control(smu, false);
1453         if (ret)
1454                 return ret;
1455
1456         if (baco_feature_is_enabled) {
1457                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1458                 if (ret) {
1459                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1460                         return ret;
1461                 }
1462         }
1463
1464         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1465
1466         if (adev->asic_type >= CHIP_NAVI10 &&
1467             adev->gfx.rlc.funcs->stop)
1468                 adev->gfx.rlc.funcs->stop(adev);
1469         if (smu->is_apu)
1470                 smu_set_gfx_cgpg(&adev->smu, false);
1471
1472         return 0;
1473 }
1474
1475 static int smu_resume(void *handle)
1476 {
1477         int ret;
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479         struct smu_context *smu = &adev->smu;
1480
1481         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1482                 return 0;
1483
1484         if (!smu->pm_enabled)
1485                 return 0;
1486
1487         pr_info("SMU is resuming...\n");
1488
1489         ret = smu_start_smc_engine(smu);
1490         if (ret) {
1491                 pr_err("SMU is not ready yet!\n");
1492                 goto failed;
1493         }
1494
1495         ret = smu_smc_table_hw_init(smu, false);
1496         if (ret)
1497                 goto failed;
1498
1499         ret = smu_start_thermal_control(smu);
1500         if (ret)
1501                 goto failed;
1502
1503         if (smu->is_apu)
1504                 smu_set_gfx_cgpg(&adev->smu, true);
1505
1506         smu->disable_uclk_switch = 0;
1507
1508         pr_info("SMU is resumed successfully!\n");
1509
1510         return 0;
1511
1512 failed:
1513         return ret;
1514 }
1515
1516 int smu_display_configuration_change(struct smu_context *smu,
1517                                      const struct amd_pp_display_configuration *display_config)
1518 {
1519         int index = 0;
1520         int num_of_active_display = 0;
1521
1522         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1523                 return -EINVAL;
1524
1525         if (!display_config)
1526                 return -EINVAL;
1527
1528         mutex_lock(&smu->mutex);
1529
1530         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1531                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1532                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1533
1534         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1535                 if (display_config->displays[index].controller_id != 0)
1536                         num_of_active_display++;
1537         }
1538
1539         smu_set_active_display_count(smu, num_of_active_display);
1540
1541         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1542                            display_config->cpu_cc6_disable,
1543                            display_config->cpu_pstate_disable,
1544                            display_config->nb_pstate_switch_disable);
1545
1546         mutex_unlock(&smu->mutex);
1547
1548         return 0;
1549 }
1550
1551 static int smu_get_clock_info(struct smu_context *smu,
1552                               struct smu_clock_info *clk_info,
1553                               enum smu_perf_level_designation designation)
1554 {
1555         int ret;
1556         struct smu_performance_level level = {0};
1557
1558         if (!clk_info)
1559                 return -EINVAL;
1560
1561         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1562         if (ret)
1563                 return -EINVAL;
1564
1565         clk_info->min_mem_clk = level.memory_clock;
1566         clk_info->min_eng_clk = level.core_clock;
1567         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1568
1569         ret = smu_get_perf_level(smu, designation, &level);
1570         if (ret)
1571                 return -EINVAL;
1572
1573         clk_info->min_mem_clk = level.memory_clock;
1574         clk_info->min_eng_clk = level.core_clock;
1575         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1576
1577         return 0;
1578 }
1579
1580 int smu_get_current_clocks(struct smu_context *smu,
1581                            struct amd_pp_clock_info *clocks)
1582 {
1583         struct amd_pp_simple_clock_info simple_clocks = {0};
1584         struct smu_clock_info hw_clocks;
1585         int ret = 0;
1586
1587         if (!is_support_sw_smu(smu->adev))
1588                 return -EINVAL;
1589
1590         mutex_lock(&smu->mutex);
1591
1592         smu_get_dal_power_level(smu, &simple_clocks);
1593
1594         if (smu->support_power_containment)
1595                 ret = smu_get_clock_info(smu, &hw_clocks,
1596                                          PERF_LEVEL_POWER_CONTAINMENT);
1597         else
1598                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1599
1600         if (ret) {
1601                 pr_err("Error in smu_get_clock_info\n");
1602                 goto failed;
1603         }
1604
1605         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1606         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1607         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1608         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1609         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1610         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1611         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1612         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1613
1614         if (simple_clocks.level == 0)
1615                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1616         else
1617                 clocks->max_clocks_state = simple_clocks.level;
1618
1619         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1620                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1621                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1622         }
1623
1624 failed:
1625         mutex_unlock(&smu->mutex);
1626         return ret;
1627 }
1628
1629 static int smu_set_clockgating_state(void *handle,
1630                                      enum amd_clockgating_state state)
1631 {
1632         return 0;
1633 }
1634
1635 static int smu_set_powergating_state(void *handle,
1636                                      enum amd_powergating_state state)
1637 {
1638         return 0;
1639 }
1640
1641 static int smu_enable_umd_pstate(void *handle,
1642                       enum amd_dpm_forced_level *level)
1643 {
1644         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1645                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1646                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1647                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1648
1649         struct smu_context *smu = (struct smu_context*)(handle);
1650         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1651
1652         if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1653                 return -EINVAL;
1654
1655         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1656                 /* enter umd pstate, save current level, disable gfx cg*/
1657                 if (*level & profile_mode_mask) {
1658                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1659                         smu_dpm_ctx->enable_umd_pstate = true;
1660                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1661                                                                AMD_IP_BLOCK_TYPE_GFX,
1662                                                                AMD_CG_STATE_UNGATE);
1663                         amdgpu_device_ip_set_powergating_state(smu->adev,
1664                                                                AMD_IP_BLOCK_TYPE_GFX,
1665                                                                AMD_PG_STATE_UNGATE);
1666                 }
1667         } else {
1668                 /* exit umd pstate, restore level, enable gfx cg*/
1669                 if (!(*level & profile_mode_mask)) {
1670                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1671                                 *level = smu_dpm_ctx->saved_dpm_level;
1672                         smu_dpm_ctx->enable_umd_pstate = false;
1673                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1674                                                                AMD_IP_BLOCK_TYPE_GFX,
1675                                                                AMD_CG_STATE_GATE);
1676                         amdgpu_device_ip_set_powergating_state(smu->adev,
1677                                                                AMD_IP_BLOCK_TYPE_GFX,
1678                                                                AMD_PG_STATE_GATE);
1679                 }
1680         }
1681
1682         return 0;
1683 }
1684
1685 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1686                                    enum amd_dpm_forced_level level,
1687                                    bool skip_display_settings)
1688 {
1689         int ret = 0;
1690         int index = 0;
1691         long workload;
1692         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1693
1694         if (!smu->pm_enabled)
1695                 return -EINVAL;
1696
1697         if (!skip_display_settings) {
1698                 ret = smu_display_config_changed(smu);
1699                 if (ret) {
1700                         pr_err("Failed to change display config!");
1701                         return ret;
1702                 }
1703         }
1704
1705         ret = smu_apply_clocks_adjust_rules(smu);
1706         if (ret) {
1707                 pr_err("Failed to apply clocks adjust rules!");
1708                 return ret;
1709         }
1710
1711         if (!skip_display_settings) {
1712                 ret = smu_notify_smc_display_config(smu);
1713                 if (ret) {
1714                         pr_err("Failed to notify smc display config!");
1715                         return ret;
1716                 }
1717         }
1718
1719         if (smu_dpm_ctx->dpm_level != level) {
1720                 ret = smu_asic_set_performance_level(smu, level);
1721                 if (ret) {
1722                         pr_err("Failed to set performance level!");
1723                         return ret;
1724                 }
1725
1726                 /* update the saved copy */
1727                 smu_dpm_ctx->dpm_level = level;
1728         }
1729
1730         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1731                 index = fls(smu->workload_mask);
1732                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1733                 workload = smu->workload_setting[index];
1734
1735                 if (smu->power_profile_mode != workload)
1736                         smu_set_power_profile_mode(smu, &workload, 0, false);
1737         }
1738
1739         return ret;
1740 }
1741
1742 int smu_handle_task(struct smu_context *smu,
1743                     enum amd_dpm_forced_level level,
1744                     enum amd_pp_task task_id,
1745                     bool lock_needed)
1746 {
1747         int ret = 0;
1748
1749         if (lock_needed)
1750                 mutex_lock(&smu->mutex);
1751
1752         switch (task_id) {
1753         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1754                 ret = smu_pre_display_config_changed(smu);
1755                 if (ret)
1756                         goto out;
1757                 ret = smu_set_cpu_power_state(smu);
1758                 if (ret)
1759                         goto out;
1760                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1761                 break;
1762         case AMD_PP_TASK_COMPLETE_INIT:
1763         case AMD_PP_TASK_READJUST_POWER_STATE:
1764                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1765                 break;
1766         default:
1767                 break;
1768         }
1769
1770 out:
1771         if (lock_needed)
1772                 mutex_unlock(&smu->mutex);
1773
1774         return ret;
1775 }
1776
1777 int smu_switch_power_profile(struct smu_context *smu,
1778                              enum PP_SMC_POWER_PROFILE type,
1779                              bool en)
1780 {
1781         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1782         long workload;
1783         uint32_t index;
1784
1785         if (!smu->pm_enabled)
1786                 return -EINVAL;
1787
1788         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1789                 return -EINVAL;
1790
1791         mutex_lock(&smu->mutex);
1792
1793         if (!en) {
1794                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1795                 index = fls(smu->workload_mask);
1796                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1797                 workload = smu->workload_setting[index];
1798         } else {
1799                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1800                 index = fls(smu->workload_mask);
1801                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1802                 workload = smu->workload_setting[index];
1803         }
1804
1805         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1806                 smu_set_power_profile_mode(smu, &workload, 0, false);
1807
1808         mutex_unlock(&smu->mutex);
1809
1810         return 0;
1811 }
1812
1813 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1814 {
1815         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1816         enum amd_dpm_forced_level level;
1817
1818         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1819                 return -EINVAL;
1820
1821         mutex_lock(&(smu->mutex));
1822         level = smu_dpm_ctx->dpm_level;
1823         mutex_unlock(&(smu->mutex));
1824
1825         return level;
1826 }
1827
1828 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1829 {
1830         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1831         int ret = 0;
1832
1833         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1834                 return -EINVAL;
1835
1836         mutex_lock(&smu->mutex);
1837
1838         ret = smu_enable_umd_pstate(smu, &level);
1839         if (ret) {
1840                 mutex_unlock(&smu->mutex);
1841                 return ret;
1842         }
1843
1844         ret = smu_handle_task(smu, level,
1845                               AMD_PP_TASK_READJUST_POWER_STATE,
1846                               false);
1847
1848         mutex_unlock(&smu->mutex);
1849
1850         return ret;
1851 }
1852
1853 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1854 {
1855         int ret = 0;
1856
1857         mutex_lock(&smu->mutex);
1858         ret = smu_init_display_count(smu, count);
1859         mutex_unlock(&smu->mutex);
1860
1861         return ret;
1862 }
1863
1864 int smu_force_clk_levels(struct smu_context *smu,
1865                          enum smu_clk_type clk_type,
1866                          uint32_t mask,
1867                          bool lock_needed)
1868 {
1869         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1870         int ret = 0;
1871
1872         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1873                 pr_debug("force clock level is for dpm manual mode only.\n");
1874                 return -EINVAL;
1875         }
1876
1877         if (lock_needed)
1878                 mutex_lock(&smu->mutex);
1879
1880         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1881                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1882
1883         if (lock_needed)
1884                 mutex_unlock(&smu->mutex);
1885
1886         return ret;
1887 }
1888
1889 int smu_set_mp1_state(struct smu_context *smu,
1890                       enum pp_mp1_state mp1_state)
1891 {
1892         uint16_t msg;
1893         int ret;
1894
1895         /*
1896          * The SMC is not fully ready. That may be
1897          * expected as the IP may be masked.
1898          * So, just return without error.
1899          */
1900         if (!smu->pm_enabled)
1901                 return 0;
1902
1903         mutex_lock(&smu->mutex);
1904
1905         switch (mp1_state) {
1906         case PP_MP1_STATE_SHUTDOWN:
1907                 msg = SMU_MSG_PrepareMp1ForShutdown;
1908                 break;
1909         case PP_MP1_STATE_UNLOAD:
1910                 msg = SMU_MSG_PrepareMp1ForUnload;
1911                 break;
1912         case PP_MP1_STATE_RESET:
1913                 msg = SMU_MSG_PrepareMp1ForReset;
1914                 break;
1915         case PP_MP1_STATE_NONE:
1916         default:
1917                 mutex_unlock(&smu->mutex);
1918                 return 0;
1919         }
1920
1921         /* some asics may not support those messages */
1922         if (smu_msg_get_index(smu, msg) < 0) {
1923                 mutex_unlock(&smu->mutex);
1924                 return 0;
1925         }
1926
1927         ret = smu_send_smc_msg(smu, msg);
1928         if (ret)
1929                 pr_err("[PrepareMp1] Failed!\n");
1930
1931         mutex_unlock(&smu->mutex);
1932
1933         return ret;
1934 }
1935
1936 int smu_set_df_cstate(struct smu_context *smu,
1937                       enum pp_df_cstate state)
1938 {
1939         int ret = 0;
1940
1941         /*
1942          * The SMC is not fully ready. That may be
1943          * expected as the IP may be masked.
1944          * So, just return without error.
1945          */
1946         if (!smu->pm_enabled)
1947                 return 0;
1948
1949         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1950                 return 0;
1951
1952         mutex_lock(&smu->mutex);
1953
1954         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1955         if (ret)
1956                 pr_err("[SetDfCstate] failed!\n");
1957
1958         mutex_unlock(&smu->mutex);
1959
1960         return ret;
1961 }
1962
1963 int smu_write_watermarks_table(struct smu_context *smu)
1964 {
1965         void *watermarks_table = smu->smu_table.watermarks_table;
1966
1967         if (!watermarks_table)
1968                 return -EINVAL;
1969
1970         return smu_update_table(smu,
1971                                 SMU_TABLE_WATERMARKS,
1972                                 0,
1973                                 watermarks_table,
1974                                 true);
1975 }
1976
1977 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1978                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1979 {
1980         void *table = smu->smu_table.watermarks_table;
1981
1982         if (!table)
1983                 return -EINVAL;
1984
1985         mutex_lock(&smu->mutex);
1986
1987         if (!smu->disable_watermark &&
1988                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1989                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1990                 smu_set_watermarks_table(smu, table, clock_ranges);
1991                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1992                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1993         }
1994
1995         mutex_unlock(&smu->mutex);
1996
1997         return 0;
1998 }
1999
2000 const struct amd_ip_funcs smu_ip_funcs = {
2001         .name = "smu",
2002         .early_init = smu_early_init,
2003         .late_init = smu_late_init,
2004         .sw_init = smu_sw_init,
2005         .sw_fini = smu_sw_fini,
2006         .hw_init = smu_hw_init,
2007         .hw_fini = smu_hw_fini,
2008         .suspend = smu_suspend,
2009         .resume = smu_resume,
2010         .is_idle = NULL,
2011         .check_soft_reset = NULL,
2012         .wait_for_idle = NULL,
2013         .soft_reset = NULL,
2014         .set_clockgating_state = smu_set_clockgating_state,
2015         .set_powergating_state = smu_set_powergating_state,
2016         .enable_umd_pstate = smu_enable_umd_pstate,
2017 };
2018
2019 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2020 {
2021         .type = AMD_IP_BLOCK_TYPE_SMC,
2022         .major = 11,
2023         .minor = 0,
2024         .rev = 0,
2025         .funcs = &smu_ip_funcs,
2026 };
2027
2028 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2029 {
2030         .type = AMD_IP_BLOCK_TYPE_SMC,
2031         .major = 12,
2032         .minor = 0,
2033         .rev = 0,
2034         .funcs = &smu_ip_funcs,
2035 };
2036
2037 int smu_load_microcode(struct smu_context *smu)
2038 {
2039         int ret = 0;
2040
2041         mutex_lock(&smu->mutex);
2042
2043         if (smu->ppt_funcs->load_microcode)
2044                 ret = smu->ppt_funcs->load_microcode(smu);
2045
2046         mutex_unlock(&smu->mutex);
2047
2048         return ret;
2049 }
2050
2051 int smu_check_fw_status(struct smu_context *smu)
2052 {
2053         int ret = 0;
2054
2055         mutex_lock(&smu->mutex);
2056
2057         if (smu->ppt_funcs->check_fw_status)
2058                 ret = smu->ppt_funcs->check_fw_status(smu);
2059
2060         mutex_unlock(&smu->mutex);
2061
2062         return ret;
2063 }
2064
2065 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2066 {
2067         int ret = 0;
2068
2069         mutex_lock(&smu->mutex);
2070
2071         if (smu->ppt_funcs->set_gfx_cgpg)
2072                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2073
2074         mutex_unlock(&smu->mutex);
2075
2076         return ret;
2077 }
2078
2079 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2080 {
2081         int ret = 0;
2082
2083         mutex_lock(&smu->mutex);
2084
2085         if (smu->ppt_funcs->set_fan_speed_rpm)
2086                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2087
2088         mutex_unlock(&smu->mutex);
2089
2090         return ret;
2091 }
2092
2093 int smu_get_power_limit(struct smu_context *smu,
2094                         uint32_t *limit,
2095                         bool def,
2096                         bool lock_needed)
2097 {
2098         int ret = 0;
2099
2100         if (lock_needed)
2101                 mutex_lock(&smu->mutex);
2102
2103         if (smu->ppt_funcs->get_power_limit)
2104                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2105
2106         if (lock_needed)
2107                 mutex_unlock(&smu->mutex);
2108
2109         return ret;
2110 }
2111
2112 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2113 {
2114         int ret = 0;
2115
2116         mutex_lock(&smu->mutex);
2117
2118         if (smu->ppt_funcs->set_power_limit)
2119                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2120
2121         mutex_unlock(&smu->mutex);
2122
2123         return ret;
2124 }
2125
2126 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2127 {
2128         int ret = 0;
2129
2130         mutex_lock(&smu->mutex);
2131
2132         if (smu->ppt_funcs->print_clk_levels)
2133                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2134
2135         mutex_unlock(&smu->mutex);
2136
2137         return ret;
2138 }
2139
2140 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2141 {
2142         int ret = 0;
2143
2144         mutex_lock(&smu->mutex);
2145
2146         if (smu->ppt_funcs->get_od_percentage)
2147                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2148
2149         mutex_unlock(&smu->mutex);
2150
2151         return ret;
2152 }
2153
2154 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2155 {
2156         int ret = 0;
2157
2158         mutex_lock(&smu->mutex);
2159
2160         if (smu->ppt_funcs->set_od_percentage)
2161                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2162
2163         mutex_unlock(&smu->mutex);
2164
2165         return ret;
2166 }
2167
2168 int smu_od_edit_dpm_table(struct smu_context *smu,
2169                           enum PP_OD_DPM_TABLE_COMMAND type,
2170                           long *input, uint32_t size)
2171 {
2172         int ret = 0;
2173
2174         mutex_lock(&smu->mutex);
2175
2176         if (smu->ppt_funcs->od_edit_dpm_table)
2177                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2178
2179         mutex_unlock(&smu->mutex);
2180
2181         return ret;
2182 }
2183
2184 int smu_read_sensor(struct smu_context *smu,
2185                     enum amd_pp_sensors sensor,
2186                     void *data, uint32_t *size)
2187 {
2188         int ret = 0;
2189
2190         mutex_lock(&smu->mutex);
2191
2192         if (smu->ppt_funcs->read_sensor)
2193                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2194
2195         mutex_unlock(&smu->mutex);
2196
2197         return ret;
2198 }
2199
2200 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2201 {
2202         int ret = 0;
2203
2204         mutex_lock(&smu->mutex);
2205
2206         if (smu->ppt_funcs->get_power_profile_mode)
2207                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2208
2209         mutex_unlock(&smu->mutex);
2210
2211         return ret;
2212 }
2213
2214 int smu_set_power_profile_mode(struct smu_context *smu,
2215                                long *param,
2216                                uint32_t param_size,
2217                                bool lock_needed)
2218 {
2219         int ret = 0;
2220
2221         if (lock_needed)
2222                 mutex_lock(&smu->mutex);
2223
2224         if (smu->ppt_funcs->set_power_profile_mode)
2225                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2226
2227         if (lock_needed)
2228                 mutex_unlock(&smu->mutex);
2229
2230         return ret;
2231 }
2232
2233
2234 int smu_get_fan_control_mode(struct smu_context *smu)
2235 {
2236         int ret = 0;
2237
2238         mutex_lock(&smu->mutex);
2239
2240         if (smu->ppt_funcs->get_fan_control_mode)
2241                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2242
2243         mutex_unlock(&smu->mutex);
2244
2245         return ret;
2246 }
2247
2248 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2249 {
2250         int ret = 0;
2251
2252         mutex_lock(&smu->mutex);
2253
2254         if (smu->ppt_funcs->set_fan_control_mode)
2255                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2256
2257         mutex_unlock(&smu->mutex);
2258
2259         return ret;
2260 }
2261
2262 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2263 {
2264         int ret = 0;
2265
2266         mutex_lock(&smu->mutex);
2267
2268         if (smu->ppt_funcs->get_fan_speed_percent)
2269                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2270
2271         mutex_unlock(&smu->mutex);
2272
2273         return ret;
2274 }
2275
2276 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2277 {
2278         int ret = 0;
2279
2280         mutex_lock(&smu->mutex);
2281
2282         if (smu->ppt_funcs->set_fan_speed_percent)
2283                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2284
2285         mutex_unlock(&smu->mutex);
2286
2287         return ret;
2288 }
2289
2290 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2291 {
2292         int ret = 0;
2293
2294         mutex_lock(&smu->mutex);
2295
2296         if (smu->ppt_funcs->get_fan_speed_rpm)
2297                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2298
2299         mutex_unlock(&smu->mutex);
2300
2301         return ret;
2302 }
2303
2304 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2305 {
2306         int ret = 0;
2307
2308         mutex_lock(&smu->mutex);
2309
2310         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2311                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2312
2313         mutex_unlock(&smu->mutex);
2314
2315         return ret;
2316 }
2317
2318 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2319 {
2320         int ret = 0;
2321
2322         if (smu->ppt_funcs->set_active_display_count)
2323                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2324
2325         return ret;
2326 }
2327
2328 int smu_get_clock_by_type(struct smu_context *smu,
2329                           enum amd_pp_clock_type type,
2330                           struct amd_pp_clocks *clocks)
2331 {
2332         int ret = 0;
2333
2334         mutex_lock(&smu->mutex);
2335
2336         if (smu->ppt_funcs->get_clock_by_type)
2337                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2338
2339         mutex_unlock(&smu->mutex);
2340
2341         return ret;
2342 }
2343
2344 int smu_get_max_high_clocks(struct smu_context *smu,
2345                             struct amd_pp_simple_clock_info *clocks)
2346 {
2347         int ret = 0;
2348
2349         mutex_lock(&smu->mutex);
2350
2351         if (smu->ppt_funcs->get_max_high_clocks)
2352                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2353
2354         mutex_unlock(&smu->mutex);
2355
2356         return ret;
2357 }
2358
2359 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2360                                        enum smu_clk_type clk_type,
2361                                        struct pp_clock_levels_with_latency *clocks)
2362 {
2363         int ret = 0;
2364
2365         mutex_lock(&smu->mutex);
2366
2367         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2368                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2369
2370         mutex_unlock(&smu->mutex);
2371
2372         return ret;
2373 }
2374
2375 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2376                                        enum amd_pp_clock_type type,
2377                                        struct pp_clock_levels_with_voltage *clocks)
2378 {
2379         int ret = 0;
2380
2381         mutex_lock(&smu->mutex);
2382
2383         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2384                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2385
2386         mutex_unlock(&smu->mutex);
2387
2388         return ret;
2389 }
2390
2391
2392 int smu_display_clock_voltage_request(struct smu_context *smu,
2393                                       struct pp_display_clock_request *clock_req)
2394 {
2395         int ret = 0;
2396
2397         mutex_lock(&smu->mutex);
2398
2399         if (smu->ppt_funcs->display_clock_voltage_request)
2400                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2401
2402         mutex_unlock(&smu->mutex);
2403
2404         return ret;
2405 }
2406
2407
2408 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2409 {
2410         int ret = -EINVAL;
2411
2412         mutex_lock(&smu->mutex);
2413
2414         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2415                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2416
2417         mutex_unlock(&smu->mutex);
2418
2419         return ret;
2420 }
2421
2422 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2423 {
2424         int ret = 0;
2425
2426         mutex_lock(&smu->mutex);
2427
2428         if (smu->ppt_funcs->notify_smu_enable_pwe)
2429                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2430
2431         mutex_unlock(&smu->mutex);
2432
2433         return ret;
2434 }
2435
2436 int smu_set_xgmi_pstate(struct smu_context *smu,
2437                         uint32_t pstate)
2438 {
2439         int ret = 0;
2440
2441         mutex_lock(&smu->mutex);
2442
2443         if (smu->ppt_funcs->set_xgmi_pstate)
2444                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2445
2446         mutex_unlock(&smu->mutex);
2447
2448         return ret;
2449 }
2450
2451 int smu_set_azalia_d3_pme(struct smu_context *smu)
2452 {
2453         int ret = 0;
2454
2455         mutex_lock(&smu->mutex);
2456
2457         if (smu->ppt_funcs->set_azalia_d3_pme)
2458                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2459
2460         mutex_unlock(&smu->mutex);
2461
2462         return ret;
2463 }
2464
2465 bool smu_baco_is_support(struct smu_context *smu)
2466 {
2467         bool ret = false;
2468
2469         mutex_lock(&smu->mutex);
2470
2471         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2472                 ret = smu->ppt_funcs->baco_is_support(smu);
2473
2474         mutex_unlock(&smu->mutex);
2475
2476         return ret;
2477 }
2478
2479 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2480 {
2481         if (smu->ppt_funcs->baco_get_state)
2482                 return -EINVAL;
2483
2484         mutex_lock(&smu->mutex);
2485         *state = smu->ppt_funcs->baco_get_state(smu);
2486         mutex_unlock(&smu->mutex);
2487
2488         return 0;
2489 }
2490
2491 int smu_baco_enter(struct smu_context *smu)
2492 {
2493         int ret = 0;
2494
2495         mutex_lock(&smu->mutex);
2496
2497         if (smu->ppt_funcs->baco_enter)
2498                 ret = smu->ppt_funcs->baco_enter(smu);
2499
2500         mutex_unlock(&smu->mutex);
2501
2502         return ret;
2503 }
2504
2505 int smu_baco_exit(struct smu_context *smu)
2506 {
2507         int ret = 0;
2508
2509         mutex_lock(&smu->mutex);
2510
2511         if (smu->ppt_funcs->baco_exit)
2512                 ret = smu->ppt_funcs->baco_exit(smu);
2513
2514         mutex_unlock(&smu->mutex);
2515
2516         return ret;
2517 }
2518
2519 int smu_mode2_reset(struct smu_context *smu)
2520 {
2521         int ret = 0;
2522
2523         mutex_lock(&smu->mutex);
2524
2525         if (smu->ppt_funcs->mode2_reset)
2526                 ret = smu->ppt_funcs->mode2_reset(smu);
2527
2528         mutex_unlock(&smu->mutex);
2529
2530         return ret;
2531 }
2532
2533 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2534                                          struct pp_smu_nv_clock_table *max_clocks)
2535 {
2536         int ret = 0;
2537
2538         mutex_lock(&smu->mutex);
2539
2540         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2541                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2542
2543         mutex_unlock(&smu->mutex);
2544
2545         return ret;
2546 }
2547
2548 int smu_get_uclk_dpm_states(struct smu_context *smu,
2549                             unsigned int *clock_values_in_khz,
2550                             unsigned int *num_states)
2551 {
2552         int ret = 0;
2553
2554         mutex_lock(&smu->mutex);
2555
2556         if (smu->ppt_funcs->get_uclk_dpm_states)
2557                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2558
2559         mutex_unlock(&smu->mutex);
2560
2561         return ret;
2562 }
2563
2564 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2565 {
2566         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2567
2568         mutex_lock(&smu->mutex);
2569
2570         if (smu->ppt_funcs->get_current_power_state)
2571                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2572
2573         mutex_unlock(&smu->mutex);
2574
2575         return pm_state;
2576 }
2577
2578 int smu_get_dpm_clock_table(struct smu_context *smu,
2579                             struct dpm_clocks *clock_table)
2580 {
2581         int ret = 0;
2582
2583         mutex_lock(&smu->mutex);
2584
2585         if (smu->ppt_funcs->get_dpm_clock_table)
2586                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2587
2588         mutex_unlock(&smu->mutex);
2589
2590         return ret;
2591 }
2592
2593 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2594 {
2595         uint32_t ret = 0;
2596
2597         if (smu->ppt_funcs->get_pptable_power_limit)
2598                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2599
2600         return ret;
2601 }
2602
2603 int smu_send_smc_msg(struct smu_context *smu,
2604                      enum smu_message_type msg)
2605 {
2606         int ret;
2607
2608         ret = smu_send_smc_msg_with_param(smu, msg, 0);
2609         return ret;
2610 }