drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "soc15_common.h"
  30 #include "smu_v11_0.h"
  31 #include "smu_v12_0.h"
  32 #include "atom.h"
  33 #include "amd_pcie.h"
  34 #include "vega20_ppt.h"
  35 #include "arcturus_ppt.h"
  36 #include "navi10_ppt.h"
  37 #include "renoir_ppt.h"
  38
  39 #undef __SMU_DUMMY_MAP
  40 #define __SMU_DUMMY_MAP(type)   #type
  41 static const char* __smu_message_names[] = {
  42         SMU_MESSAGE_TYPES
  43 };
  44
  45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  46 {
  47         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  48                 return "unknown smu message";
  49         return __smu_message_names[type];
  50 }
  51
  52 #undef __SMU_DUMMY_MAP
  53 #define __SMU_DUMMY_MAP(fea)    #fea
  54 static const char* __smu_feature_names[] = {
  55         SMU_FEATURE_MASKS
  56 };
  57
  58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  59 {
  60         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  61                 return "unknown smu feature";
  62         return __smu_feature_names[feature];
  63 }
  64
  65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  66 {
  67         size_t size = 0;
  68         int ret = 0, i = 0;
  69         uint32_t feature_mask[2] = { 0 };
  70         int32_t feature_index = 0;
  71         uint32_t count = 0;
  72         uint32_t sort_feature[SMU_FEATURE_COUNT];
  73         uint64_t hw_feature_count = 0;
  74
  75         mutex_lock(&smu->mutex);
  76
  77         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  78         if (ret)
  79                 goto failed;
  80
  81         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  82                         feature_mask[1], feature_mask[0]);
  83
  84         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  85                 feature_index = smu_feature_get_index(smu, i);
  86                 if (feature_index < 0)
  87                         continue;
  88                 sort_feature[feature_index] = i;
  89                 hw_feature_count++;
  90         }
  91
  92         for (i = 0; i < hw_feature_count; i++) {
  93                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  94                                count++,
  95                                smu_get_feature_name(smu, sort_feature[i]),
  96                                i,
  97                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  98                                "enabled" : "disabled");
  99         }
 100
 101 failed:
 102         mutex_unlock(&smu->mutex);
 103
 104         return size;
 105 }
 106
 107 static int smu_feature_update_enable_state(struct smu_context *smu,
 108                                            uint64_t feature_mask,
 109                                            bool enabled)
 110 {
 111         struct smu_feature *feature = &smu->smu_feature;
 112         uint32_t feature_low = 0, feature_high = 0;
 113         int ret = 0;
 114
 115         if (!smu->pm_enabled)
 116                 return ret;
 117
 118         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 119         feature_high = (feature_mask >> 32) & 0xffffffff;
 120
 121         if (enabled) {
 122                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 123                                                   feature_low);
 124                 if (ret)
 125                         return ret;
 126                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 127                                                   feature_high);
 128                 if (ret)
 129                         return ret;
 130         } else {
 131                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 132                                                   feature_low);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 136                                                   feature_high);
 137                 if (ret)
 138                         return ret;
 139         }
 140
 141         mutex_lock(&feature->mutex);
 142         if (enabled)
 143                 bitmap_or(feature->enabled, feature->enabled,
 144                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 145         else
 146                 bitmap_andnot(feature->enabled, feature->enabled,
 147                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 148         mutex_unlock(&feature->mutex);
 149
 150         return ret;
 151 }
 152
 153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 154 {
 155         int ret = 0;
 156         uint32_t feature_mask[2] = { 0 };
 157         uint64_t feature_2_enabled = 0;
 158         uint64_t feature_2_disabled = 0;
 159         uint64_t feature_enables = 0;
 160
 161         mutex_lock(&smu->mutex);
 162
 163         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 164         if (ret)
 165                 goto out;
 166
 167         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 168
 169         feature_2_enabled  = ~feature_enables & new_mask;
 170         feature_2_disabled = feature_enables & ~new_mask;
 171
 172         if (feature_2_enabled) {
 173                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 174                 if (ret)
 175                         goto out;
 176         }
 177         if (feature_2_disabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 179                 if (ret)
 180                         goto out;
 181         }
 182
 183 out:
 184         mutex_unlock(&smu->mutex);
 185
 186         return ret;
 187 }
 188
 189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 190 {
 191         int ret = 0;
 192
 193         if (!if_version && !smu_version)
 194                 return -EINVAL;
 195
 196         if (if_version) {
 197                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 198                 if (ret)
 199                         return ret;
 200
 201                 ret = smu_read_smc_arg(smu, if_version);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         if (smu_version) {
 207                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 208                 if (ret)
 209                         return ret;
 210
 211                 ret = smu_read_smc_arg(smu, smu_version);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return ret;
 217 }
 218
 219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 220                             uint32_t min, uint32_t max)
 221 {
 222         int ret = 0;
 223
 224         if (min <= 0 && max <= 0)
 225                 return -EINVAL;
 226
 227         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 228                 return 0;
 229
 230         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 231         return ret;
 232 }
 233
 234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 235                             uint32_t min, uint32_t max)
 236 {
 237         int ret = 0, clk_id = 0;
 238         uint32_t param;
 239
 240         if (min <= 0 && max <= 0)
 241                 return -EINVAL;
 242
 243         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 244                 return 0;
 245
 246         clk_id = smu_clk_get_index(smu, clk_type);
 247         if (clk_id < 0)
 248                 return clk_id;
 249
 250         if (max > 0) {
 251                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 252                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 253                                                   param);
 254                 if (ret)
 255                         return ret;
 256         }
 257
 258         if (min > 0) {
 259                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 260                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 261                                                   param);
 262                 if (ret)
 263                         return ret;
 264         }
 265
 266
 267         return ret;
 268 }
 269
 270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 271                            uint32_t *min, uint32_t *max, bool lock_needed)
 272 {
 273         uint32_t clock_limit;
 274         int ret = 0;
 275
 276         if (!min && !max)
 277                 return -EINVAL;
 278
 279         if (lock_needed)
 280                 mutex_lock(&smu->mutex);
 281
 282         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 283                 switch (clk_type) {
 284                 case SMU_MCLK:
 285                 case SMU_UCLK:
 286                         clock_limit = smu->smu_table.boot_values.uclk;
 287                         break;
 288                 case SMU_GFXCLK:
 289                 case SMU_SCLK:
 290                         clock_limit = smu->smu_table.boot_values.gfxclk;
 291                         break;
 292                 case SMU_SOCCLK:
 293                         clock_limit = smu->smu_table.boot_values.socclk;
 294                         break;
 295                 default:
 296                         clock_limit = 0;
 297                         break;
 298                 }
 299
 300                 /* clock in Mhz unit */
 301                 if (min)
 302                         *min = clock_limit / 100;
 303                 if (max)
 304                         *max = clock_limit / 100;
 305         } else {
 306                 /*
 307                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 308                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 309                  */
 310                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 311         }
 312
 313         if (lock_needed)
 314                 mutex_unlock(&smu->mutex);
 315
 316         return ret;
 317 }
 318
 319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 320                               uint16_t level, uint32_t *value)
 321 {
 322         int ret = 0, clk_id = 0;
 323         uint32_t param;
 324
 325         if (!value)
 326                 return -EINVAL;
 327
 328         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 329                 return 0;
 330
 331         clk_id = smu_clk_get_index(smu, clk_type);
 332         if (clk_id < 0)
 333                 return clk_id;
 334
 335         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 336
 337         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 338                                           param);
 339         if (ret)
 340                 return ret;
 341
 342         ret = smu_read_smc_arg(smu, &param);
 343         if (ret)
 344                 return ret;
 345
 346         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 347          * now, we un-support it */
 348         *value = param & 0x7fffffff;
 349
 350         return ret;
 351 }
 352
 353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 354                             uint32_t *value)
 355 {
 356         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 357 }
 358
 359 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
 360                             uint32_t *min_value, uint32_t *max_value)
 361 {
 362         int ret = 0;
 363         uint32_t level_count = 0;
 364
 365         if (!min_value && !max_value)
 366                 return -EINVAL;
 367
 368         if (min_value) {
 369                 /* by default, level 0 clock value as min value */
 370                 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
 371                 if (ret)
 372                         return ret;
 373         }
 374
 375         if (max_value) {
 376                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 377                 if (ret)
 378                         return ret;
 379
 380                 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         return ret;
 386 }
 387
 388 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 389 {
 390         enum smu_feature_mask feature_id = 0;
 391
 392         switch (clk_type) {
 393         case SMU_MCLK:
 394         case SMU_UCLK:
 395                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 396                 break;
 397         case SMU_GFXCLK:
 398         case SMU_SCLK:
 399                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 400                 break;
 401         case SMU_SOCCLK:
 402                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 403                 break;
 404         default:
 405                 return true;
 406         }
 407
 408         if(!smu_feature_is_enabled(smu, feature_id)) {
 409                 return false;
 410         }
 411
 412         return true;
 413 }
 414
 415 /**
 416  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 417  *
 418  * @smu:        smu_context pointer
 419  * @block_type: the IP block to power gate/ungate
 420  * @gate:       to power gate if true, ungate otherwise
 421  *
 422  * This API uses no smu->mutex lock protection due to:
 423  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 424  *    This is guarded to be race condition free by the caller.
 425  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 426  *    Under this case, the smu->mutex lock protection is already enforced on
 427  *    the parent API smu_force_performance_level of the call path.
 428  */
 429 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 430                            bool gate)
 431 {
 432         int ret = 0;
 433
 434         switch (block_type) {
 435         case AMD_IP_BLOCK_TYPE_UVD:
 436                 ret = smu_dpm_set_uvd_enable(smu, gate);
 437                 break;
 438         case AMD_IP_BLOCK_TYPE_VCE:
 439                 ret = smu_dpm_set_vce_enable(smu, gate);
 440                 break;
 441         case AMD_IP_BLOCK_TYPE_GFX:
 442                 ret = smu_gfx_off_control(smu, gate);
 443                 break;
 444         case AMD_IP_BLOCK_TYPE_SDMA:
 445                 ret = smu_powergate_sdma(smu, gate);
 446                 break;
 447         case AMD_IP_BLOCK_TYPE_JPEG:
 448                 ret = smu_dpm_set_jpeg_enable(smu, gate);
 449                 break;
 450         default:
 451                 break;
 452         }
 453
 454         return ret;
 455 }
 456
 457 int smu_get_power_num_states(struct smu_context *smu,
 458                              struct pp_states_info *state_info)
 459 {
 460         if (!state_info)
 461                 return -EINVAL;
 462
 463         /* not support power state */
 464         memset(state_info, 0, sizeof(struct pp_states_info));
 465         state_info->nums = 1;
 466         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 467
 468         return 0;
 469 }
 470
 471 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 472                            void *data, uint32_t *size)
 473 {
 474         struct smu_power_context *smu_power = &smu->smu_power;
 475         struct smu_power_gate *power_gate = &smu_power->power_gate;
 476         int ret = 0;
 477
 478         if(!data || !size)
 479                 return -EINVAL;
 480
 481         switch (sensor) {
 482         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 483                 *((uint32_t *)data) = smu->pstate_sclk;
 484                 *size = 4;
 485                 break;
 486         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 487                 *((uint32_t *)data) = smu->pstate_mclk;
 488                 *size = 4;
 489                 break;
 490         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 491                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 492                 *size = 8;
 493                 break;
 494         case AMDGPU_PP_SENSOR_UVD_POWER:
 495                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 496                 *size = 4;
 497                 break;
 498         case AMDGPU_PP_SENSOR_VCE_POWER:
 499                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 500                 *size = 4;
 501                 break;
 502         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 503                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 504                 *size = 4;
 505                 break;
 506         default:
 507                 ret = -EINVAL;
 508                 break;
 509         }
 510
 511         if (ret)
 512                 *size = 0;
 513
 514         return ret;
 515 }
 516
 517 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 518                      void *table_data, bool drv2smu)
 519 {
 520         struct smu_table_context *smu_table = &smu->smu_table;
 521         struct amdgpu_device *adev = smu->adev;
 522         struct smu_table *table = &smu_table->driver_table;
 523         int table_id = smu_table_get_index(smu, table_index);
 524         uint32_t table_size;
 525         int ret = 0;
 526
 527         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 528                 return -EINVAL;
 529
 530         table_size = smu_table->tables[table_index].size;
 531
 532         if (drv2smu)
 533                 memcpy(table->cpu_addr, table_data, table_size);
 534
 535         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 536                                           SMU_MSG_TransferTableDram2Smu :
 537                                           SMU_MSG_TransferTableSmu2Dram,
 538                                           table_id | ((argument & 0xFFFF) << 16));
 539         if (ret)
 540                 return ret;
 541
 542         /* flush hdp cache */
 543         adev->nbio.funcs->hdp_flush(adev, NULL);
 544
 545         if (!drv2smu)
 546                 memcpy(table_data, table->cpu_addr, table_size);
 547
 548         return ret;
 549 }
 550
 551 bool is_support_sw_smu(struct amdgpu_device *adev)
 552 {
 553         if (adev->asic_type == CHIP_VEGA20)
 554                 return (amdgpu_dpm == 2) ? true : false;
 555         else if (adev->asic_type >= CHIP_ARCTURUS) {
 556                 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
 557                         return false;
 558                 else
 559                         return true;
 560         } else
 561                 return false;
 562 }
 563
 564 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 565 {
 566         if (!is_support_sw_smu(adev))
 567                 return false;
 568
 569         if (adev->asic_type == CHIP_VEGA20)
 570                 return true;
 571
 572         return false;
 573 }
 574
 575 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 576 {
 577         struct smu_table_context *smu_table = &smu->smu_table;
 578         uint32_t powerplay_table_size;
 579
 580         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 581                 return -EINVAL;
 582
 583         mutex_lock(&smu->mutex);
 584
 585         if (smu_table->hardcode_pptable)
 586                 *table = smu_table->hardcode_pptable;
 587         else
 588                 *table = smu_table->power_play_table;
 589
 590         powerplay_table_size = smu_table->power_play_table_size;
 591
 592         mutex_unlock(&smu->mutex);
 593
 594         return powerplay_table_size;
 595 }
 596
 597 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 598 {
 599         struct smu_table_context *smu_table = &smu->smu_table;
 600         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 601         int ret = 0;
 602
 603         if (!smu->pm_enabled)
 604                 return -EINVAL;
 605         if (header->usStructureSize != size) {
 606                 pr_err("pp table size not matched !\n");
 607                 return -EIO;
 608         }
 609
 610         mutex_lock(&smu->mutex);
 611         if (!smu_table->hardcode_pptable)
 612                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 613         if (!smu_table->hardcode_pptable) {
 614                 ret = -ENOMEM;
 615                 goto failed;
 616         }
 617
 618         memcpy(smu_table->hardcode_pptable, buf, size);
 619         smu_table->power_play_table = smu_table->hardcode_pptable;
 620         smu_table->power_play_table_size = size;
 621
 622         /*
 623          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 624          * skipped) may be needed for custom pptable uploading.
 625          */
 626         smu->uploading_custom_pp_table = true;
 627
 628         ret = smu_reset(smu);
 629         if (ret)
 630                 pr_info("smu reset failed, ret = %d\n", ret);
 631
 632         smu->uploading_custom_pp_table = false;
 633
 634 failed:
 635         mutex_unlock(&smu->mutex);
 636         return ret;
 637 }
 638
 639 int smu_feature_init_dpm(struct smu_context *smu)
 640 {
 641         struct smu_feature *feature = &smu->smu_feature;
 642         int ret = 0;
 643         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 644
 645         if (!smu->pm_enabled)
 646                 return ret;
 647         mutex_lock(&feature->mutex);
 648         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 649         mutex_unlock(&feature->mutex);
 650
 651         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 652                                              SMU_FEATURE_MAX/32);
 653         if (ret)
 654                 return ret;
 655
 656         mutex_lock(&feature->mutex);
 657         bitmap_or(feature->allowed, feature->allowed,
 658                       (unsigned long *)allowed_feature_mask,
 659                       feature->feature_num);
 660         mutex_unlock(&feature->mutex);
 661
 662         return ret;
 663 }
 664
 665
 666 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 667 {
 668         struct smu_feature *feature = &smu->smu_feature;
 669         int feature_id;
 670         int ret = 0;
 671
 672         if (smu->is_apu)
 673                 return 1;
 674
 675         feature_id = smu_feature_get_index(smu, mask);
 676         if (feature_id < 0)
 677                 return 0;
 678
 679         WARN_ON(feature_id > feature->feature_num);
 680
 681         mutex_lock(&feature->mutex);
 682         ret = test_bit(feature_id, feature->enabled);
 683         mutex_unlock(&feature->mutex);
 684
 685         return ret;
 686 }
 687
 688 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 689                             bool enable)
 690 {
 691         struct smu_feature *feature = &smu->smu_feature;
 692         int feature_id;
 693
 694         feature_id = smu_feature_get_index(smu, mask);
 695         if (feature_id < 0)
 696                 return -EINVAL;
 697
 698         WARN_ON(feature_id > feature->feature_num);
 699
 700         return smu_feature_update_enable_state(smu,
 701                                                1ULL << feature_id,
 702                                                enable);
 703 }
 704
 705 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 706 {
 707         struct smu_feature *feature = &smu->smu_feature;
 708         int feature_id;
 709         int ret = 0;
 710
 711         feature_id = smu_feature_get_index(smu, mask);
 712         if (feature_id < 0)
 713                 return 0;
 714
 715         WARN_ON(feature_id > feature->feature_num);
 716
 717         mutex_lock(&feature->mutex);
 718         ret = test_bit(feature_id, feature->supported);
 719         mutex_unlock(&feature->mutex);
 720
 721         return ret;
 722 }
 723
 724 int smu_feature_set_supported(struct smu_context *smu,
 725                               enum smu_feature_mask mask,
 726                               bool enable)
 727 {
 728         struct smu_feature *feature = &smu->smu_feature;
 729         int feature_id;
 730         int ret = 0;
 731
 732         feature_id = smu_feature_get_index(smu, mask);
 733         if (feature_id < 0)
 734                 return -EINVAL;
 735
 736         WARN_ON(feature_id > feature->feature_num);
 737
 738         mutex_lock(&feature->mutex);
 739         if (enable)
 740                 test_and_set_bit(feature_id, feature->supported);
 741         else
 742                 test_and_clear_bit(feature_id, feature->supported);
 743         mutex_unlock(&feature->mutex);
 744
 745         return ret;
 746 }
 747
 748 static int smu_set_funcs(struct amdgpu_device *adev)
 749 {
 750         struct smu_context *smu = &adev->smu;
 751
 752         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 753                 smu->od_enabled = true;
 754
 755         switch (adev->asic_type) {
 756         case CHIP_VEGA20:
 757                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 758                 vega20_set_ppt_funcs(smu);
 759                 break;
 760         case CHIP_NAVI10:
 761         case CHIP_NAVI14:
 762         case CHIP_NAVI12:
 763                 navi10_set_ppt_funcs(smu);
 764                 break;
 765         case CHIP_ARCTURUS:
 766                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 767                 arcturus_set_ppt_funcs(smu);
 768                 /* OD is not supported on Arcturus */
 769                 smu->od_enabled =false;
 770                 break;
 771         case CHIP_RENOIR:
 772                 renoir_set_ppt_funcs(smu);
 773                 break;
 774         default:
 775                 return -EINVAL;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int smu_early_init(void *handle)
 782 {
 783         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 784         struct smu_context *smu = &adev->smu;
 785
 786         smu->adev = adev;
 787         smu->pm_enabled = !!amdgpu_dpm;
 788         smu->is_apu = false;
 789         mutex_init(&smu->mutex);
 790
 791         return smu_set_funcs(adev);
 792 }
 793
 794 static int smu_late_init(void *handle)
 795 {
 796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 797         struct smu_context *smu = &adev->smu;
 798
 799         if (!smu->pm_enabled)
 800                 return 0;
 801
 802         smu_handle_task(&adev->smu,
 803                         smu->smu_dpm.dpm_level,
 804                         AMD_PP_TASK_COMPLETE_INIT,
 805                         false);
 806
 807         return 0;
 808 }
 809
 810 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 811                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 812                             uint8_t **addr)
 813 {
 814         struct amdgpu_device *adev = smu->adev;
 815         uint16_t data_start;
 816
 817         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 818                                            size, frev, crev, &data_start))
 819                 return -EINVAL;
 820
 821         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 822
 823         return 0;
 824 }
 825
 826 static int smu_initialize_pptable(struct smu_context *smu)
 827 {
 828         /* TODO */
 829         return 0;
 830 }
 831
 832 static int smu_smc_table_sw_init(struct smu_context *smu)
 833 {
 834         int ret;
 835
 836         ret = smu_initialize_pptable(smu);
 837         if (ret) {
 838                 pr_err("Failed to init smu_initialize_pptable!\n");
 839                 return ret;
 840         }
 841
 842         /**
 843          * Create smu_table structure, and init smc tables such as
 844          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 845          */
 846         ret = smu_init_smc_tables(smu);
 847         if (ret) {
 848                 pr_err("Failed to init smc tables!\n");
 849                 return ret;
 850         }
 851
 852         /**
 853          * Create smu_power_context structure, and allocate smu_dpm_context and
 854          * context size to fill the smu_power_context data.
 855          */
 856         ret = smu_init_power(smu);
 857         if (ret) {
 858                 pr_err("Failed to init smu_init_power!\n");
 859                 return ret;
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int smu_smc_table_sw_fini(struct smu_context *smu)
 866 {
 867         int ret;
 868
 869         ret = smu_fini_smc_tables(smu);
 870         if (ret) {
 871                 pr_err("Failed to smu_fini_smc_tables!\n");
 872                 return ret;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static int smu_sw_init(void *handle)
 879 {
 880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 881         struct smu_context *smu = &adev->smu;
 882         int ret;
 883
 884         smu->pool_size = adev->pm.smu_prv_buffer_size;
 885         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 886         mutex_init(&smu->smu_feature.mutex);
 887         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 888         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 889         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 890
 891         mutex_init(&smu->smu_baco.mutex);
 892         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 893         smu->smu_baco.platform_support = false;
 894
 895         mutex_init(&smu->sensor_lock);
 896         mutex_init(&smu->metrics_lock);
 897
 898         smu->watermarks_bitmap = 0;
 899         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 900         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 901
 902         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 903         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 904         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 905         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 906         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 907         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 908         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 909         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 910
 911         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 912         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 913         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 914         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 915         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 916         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 917         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 918         smu->display_config = &adev->pm.pm_display_cfg;
 919
 920         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 921         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 922         ret = smu_init_microcode(smu);
 923         if (ret) {
 924                 pr_err("Failed to load smu firmware!\n");
 925                 return ret;
 926         }
 927
 928         ret = smu_smc_table_sw_init(smu);
 929         if (ret) {
 930                 pr_err("Failed to sw init smc table!\n");
 931                 return ret;
 932         }
 933
 934         ret = smu_register_irq_handler(smu);
 935         if (ret) {
 936                 pr_err("Failed to register smc irq handler!\n");
 937                 return ret;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int smu_sw_fini(void *handle)
 944 {
 945         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 946         struct smu_context *smu = &adev->smu;
 947         int ret;
 948
 949         kfree(smu->irq_source);
 950         smu->irq_source = NULL;
 951
 952         ret = smu_smc_table_sw_fini(smu);
 953         if (ret) {
 954                 pr_err("Failed to sw fini smc table!\n");
 955                 return ret;
 956         }
 957
 958         ret = smu_fini_power(smu);
 959         if (ret) {
 960                 pr_err("Failed to init smu_fini_power!\n");
 961                 return ret;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int smu_init_fb_allocations(struct smu_context *smu)
 968 {
 969         struct amdgpu_device *adev = smu->adev;
 970         struct smu_table_context *smu_table = &smu->smu_table;
 971         struct smu_table *tables = smu_table->tables;
 972         struct smu_table *driver_table = &(smu_table->driver_table);
 973         uint32_t max_table_size = 0;
 974         int ret, i;
 975
 976         /* VRAM allocation for tool table */
 977         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 978                 ret = amdgpu_bo_create_kernel(adev,
 979                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 980                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 981                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 982                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 983                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 984                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 985                 if (ret) {
 986                         pr_err("VRAM allocation for tool table failed!\n");
 987                         return ret;
 988                 }
 989         }
 990
 991         /* VRAM allocation for driver table */
 992         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 993                 if (tables[i].size == 0)
 994                         continue;
 995
 996                 if (i == SMU_TABLE_PMSTATUSLOG)
 997                         continue;
 998
 999                 if (max_table_size < tables[i].size)
1000                         max_table_size = tables[i].size;
1001         }
1002
1003         driver_table->size = max_table_size;
1004         driver_table->align = PAGE_SIZE;
1005         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
1006
1007         ret = amdgpu_bo_create_kernel(adev,
1008                                       driver_table->size,
1009                                       driver_table->align,
1010                                       driver_table->domain,
1011                                       &driver_table->bo,
1012                                       &driver_table->mc_address,
1013                                       &driver_table->cpu_addr);
1014         if (ret) {
1015                 pr_err("VRAM allocation for driver table failed!\n");
1016                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1017                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1018                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1019                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1020         }
1021
1022         return ret;
1023 }
1024
1025 static int smu_fini_fb_allocations(struct smu_context *smu)
1026 {
1027         struct smu_table_context *smu_table = &smu->smu_table;
1028         struct smu_table *tables = smu_table->tables;
1029         struct smu_table *driver_table = &(smu_table->driver_table);
1030
1031         if (!tables)
1032                 return 0;
1033
1034         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1035                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1036                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1037                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1038
1039         amdgpu_bo_free_kernel(&driver_table->bo,
1040                               &driver_table->mc_address,
1041                               &driver_table->cpu_addr);
1042
1043         return 0;
1044 }
1045
1046 static int smu_smc_table_hw_init(struct smu_context *smu,
1047                                  bool initialize)
1048 {
1049         struct amdgpu_device *adev = smu->adev;
1050         int ret;
1051
1052         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1053                 pr_info("dpm has been enabled\n");
1054                 return 0;
1055         }
1056
1057         if (adev->asic_type != CHIP_ARCTURUS) {
1058                 ret = smu_init_display_count(smu, 0);
1059                 if (ret)
1060                         return ret;
1061         }
1062
1063         if (initialize) {
1064                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1065                 ret = smu_get_vbios_bootup_values(smu);
1066                 if (ret)
1067                         return ret;
1068
1069                 ret = smu_setup_pptable(smu);
1070                 if (ret)
1071                         return ret;
1072
1073                 ret = smu_get_clk_info_from_vbios(smu);
1074                 if (ret)
1075                         return ret;
1076
1077                 /*
1078                  * check if the format_revision in vbios is up to pptable header
1079                  * version, and the structure size is not 0.
1080                  */
1081                 ret = smu_check_pptable(smu);
1082                 if (ret)
1083                         return ret;
1084
1085                 /*
1086                  * allocate vram bos to store smc table contents.
1087                  */
1088                 ret = smu_init_fb_allocations(smu);
1089                 if (ret)
1090                         return ret;
1091
1092                 /*
1093                  * Parse pptable format and fill PPTable_t smc_pptable to
1094                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1095                  * then fill it into smc_pptable.
1096                  */
1097                 ret = smu_parse_pptable(smu);
1098                 if (ret)
1099                         return ret;
1100
1101                 /*
1102                  * Send msg GetDriverIfVersion to check if the return value is equal
1103                  * with DRIVER_IF_VERSION of smc header.
1104                  */
1105                 ret = smu_check_fw_version(smu);
1106                 if (ret)
1107                         return ret;
1108         }
1109
1110         /* smu_dump_pptable(smu); */
1111         if (!amdgpu_sriov_vf(adev)) {
1112                 ret = smu_set_driver_table_location(smu);
1113                 if (ret)
1114                         return ret;
1115
1116                 /*
1117                  * Copy pptable bo in the vram to smc with SMU MSGs such as
1118                  * SetDriverDramAddr and TransferTableDram2Smu.
1119                  */
1120                 ret = smu_write_pptable(smu);
1121                 if (ret)
1122                         return ret;
1123
1124                 /* issue Run*Btc msg */
1125                 ret = smu_run_btc(smu);
1126                 if (ret)
1127                         return ret;
1128                 ret = smu_feature_set_allowed_mask(smu);
1129                 if (ret)
1130                         return ret;
1131
1132                 ret = smu_system_features_control(smu, true);
1133                 if (ret)
1134                         return ret;
1135         }
1136         if (adev->asic_type != CHIP_ARCTURUS) {
1137                 ret = smu_notify_display_change(smu);
1138                 if (ret)
1139                         return ret;
1140
1141                 /*
1142                  * Set min deep sleep dce fclk with bootup value from vbios via
1143                  * SetMinDeepSleepDcefclk MSG.
1144                  */
1145                 ret = smu_set_min_dcef_deep_sleep(smu);
1146                 if (ret)
1147                         return ret;
1148         }
1149
1150         /*
1151          * Set initialized values (get from vbios) to dpm tables context such as
1152          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1153          * type of clks.
1154          */
1155         if (initialize) {
1156                 ret = smu_populate_smc_tables(smu);
1157                 if (ret)
1158                         return ret;
1159
1160                 ret = smu_init_max_sustainable_clocks(smu);
1161                 if (ret)
1162                         return ret;
1163         }
1164
1165         if (adev->asic_type != CHIP_ARCTURUS) {
1166                 ret = smu_override_pcie_parameters(smu);
1167                 if (ret)
1168                         return ret;
1169         }
1170
1171         ret = smu_set_default_od_settings(smu, initialize);
1172         if (ret)
1173                 return ret;
1174
1175         if (initialize) {
1176                 ret = smu_populate_umd_state_clk(smu);
1177                 if (ret)
1178                         return ret;
1179
1180                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1181                 if (ret)
1182                         return ret;
1183         }
1184
1185         /*
1186          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1187          */
1188         if (!amdgpu_sriov_vf(adev)) {
1189                 ret = smu_set_tool_table_location(smu);
1190         }
1191         if (!smu_is_dpm_running(smu))
1192                 pr_info("dpm has been disabled\n");
1193
1194         return ret;
1195 }
1196
1197 /**
1198  * smu_alloc_memory_pool - allocate memory pool in the system memory
1199  *
1200  * @smu: amdgpu_device pointer
1201  *
1202  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1203  * and DramLogSetDramAddr can notify it changed.
1204  *
1205  * Returns 0 on success, error on failure.
1206  */
1207 static int smu_alloc_memory_pool(struct smu_context *smu)
1208 {
1209         struct amdgpu_device *adev = smu->adev;
1210         struct smu_table_context *smu_table = &smu->smu_table;
1211         struct smu_table *memory_pool = &smu_table->memory_pool;
1212         uint64_t pool_size = smu->pool_size;
1213         int ret = 0;
1214
1215         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1216                 return ret;
1217
1218         memory_pool->size = pool_size;
1219         memory_pool->align = PAGE_SIZE;
1220         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1221
1222         switch (pool_size) {
1223         case SMU_MEMORY_POOL_SIZE_256_MB:
1224         case SMU_MEMORY_POOL_SIZE_512_MB:
1225         case SMU_MEMORY_POOL_SIZE_1_GB:
1226         case SMU_MEMORY_POOL_SIZE_2_GB:
1227                 ret = amdgpu_bo_create_kernel(adev,
1228                                               memory_pool->size,
1229                                               memory_pool->align,
1230                                               memory_pool->domain,
1231                                               &memory_pool->bo,
1232                                               &memory_pool->mc_address,
1233                                               &memory_pool->cpu_addr);
1234                 break;
1235         default:
1236                 break;
1237         }
1238
1239         return ret;
1240 }
1241
1242 static int smu_free_memory_pool(struct smu_context *smu)
1243 {
1244         struct smu_table_context *smu_table = &smu->smu_table;
1245         struct smu_table *memory_pool = &smu_table->memory_pool;
1246
1247         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1248                 return 0;
1249
1250         amdgpu_bo_free_kernel(&memory_pool->bo,
1251                               &memory_pool->mc_address,
1252                               &memory_pool->cpu_addr);
1253
1254         memset(memory_pool, 0, sizeof(struct smu_table));
1255
1256         return 0;
1257 }
1258
1259 static int smu_start_smc_engine(struct smu_context *smu)
1260 {
1261         struct amdgpu_device *adev = smu->adev;
1262         int ret = 0;
1263
1264         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1265                 if (adev->asic_type < CHIP_NAVI10) {
1266                         if (smu->ppt_funcs->load_microcode) {
1267                                 ret = smu->ppt_funcs->load_microcode(smu);
1268                                 if (ret)
1269                                         return ret;
1270                         }
1271                 }
1272         }
1273
1274         if (smu->ppt_funcs->check_fw_status) {
1275                 ret = smu->ppt_funcs->check_fw_status(smu);
1276                 if (ret)
1277                         pr_err("SMC is not ready\n");
1278         }
1279
1280         return ret;
1281 }
1282
1283 static int smu_hw_init(void *handle)
1284 {
1285         int ret;
1286         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287         struct smu_context *smu = &adev->smu;
1288
1289         ret = smu_start_smc_engine(smu);
1290         if (ret) {
1291                 pr_err("SMU is not ready yet!\n");
1292                 return ret;
1293         }
1294
1295         if (smu->is_apu) {
1296                 smu_powergate_sdma(&adev->smu, false);
1297                 smu_powergate_vcn(&adev->smu, false);
1298                 smu_powergate_jpeg(&adev->smu, false);
1299                 smu_set_gfx_cgpg(&adev->smu, true);
1300         }
1301
1302         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1303                 return 0;
1304
1305         if (!smu->pm_enabled)
1306                 return 0;
1307
1308         ret = smu_feature_init_dpm(smu);
1309         if (ret)
1310                 goto failed;
1311
1312         ret = smu_smc_table_hw_init(smu, true);
1313         if (ret)
1314                 goto failed;
1315
1316         ret = smu_alloc_memory_pool(smu);
1317         if (ret)
1318                 goto failed;
1319
1320         /*
1321          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1322          * pool location.
1323          */
1324         ret = smu_notify_memory_pool_location(smu);
1325         if (ret)
1326                 goto failed;
1327
1328         ret = smu_start_thermal_control(smu);
1329         if (ret)
1330                 goto failed;
1331
1332         if (!smu->pm_enabled)
1333                 adev->pm.dpm_enabled = false;
1334         else
1335                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1336
1337         pr_info("SMU is initialized successfully!\n");
1338
1339         return 0;
1340
1341 failed:
1342         return ret;
1343 }
1344
1345 static int smu_stop_dpms(struct smu_context *smu)
1346 {
1347         return smu_system_features_control(smu, false);
1348 }
1349
1350 static int smu_hw_fini(void *handle)
1351 {
1352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353         struct smu_context *smu = &adev->smu;
1354         struct smu_table_context *table_context = &smu->smu_table;
1355         int ret = 0;
1356
1357         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1358                 return 0;
1359
1360         if (smu->is_apu) {
1361                 smu_powergate_sdma(&adev->smu, true);
1362                 smu_powergate_vcn(&adev->smu, true);
1363                 smu_powergate_jpeg(&adev->smu, true);
1364         }
1365
1366         if (!amdgpu_sriov_vf(adev)){
1367                 ret = smu_stop_thermal_control(smu);
1368                 if (ret) {
1369                         pr_warn("Fail to stop thermal control!\n");
1370                         return ret;
1371                 }
1372
1373                 /*
1374                  * For custom pptable uploading, skip the DPM features
1375                  * disable process on Navi1x ASICs.
1376                  *   - As the gfx related features are under control of
1377                  *     RLC on those ASICs. RLC reinitialization will be
1378                  *     needed to reenable them. That will cost much more
1379                  *     efforts.
1380                  *
1381                  *   - SMU firmware can handle the DPM reenablement
1382                  *     properly.
1383                  */
1384                 if (!smu->uploading_custom_pp_table ||
1385                                 !((adev->asic_type >= CHIP_NAVI10) &&
1386                                         (adev->asic_type <= CHIP_NAVI12))) {
1387                         ret = smu_stop_dpms(smu);
1388                         if (ret) {
1389                                 pr_warn("Fail to stop Dpms!\n");
1390                                 return ret;
1391                         }
1392                 }
1393         }
1394
1395         kfree(table_context->driver_pptable);
1396         table_context->driver_pptable = NULL;
1397
1398         kfree(table_context->max_sustainable_clocks);
1399         table_context->max_sustainable_clocks = NULL;
1400
1401         kfree(table_context->overdrive_table);
1402         table_context->overdrive_table = NULL;
1403
1404         ret = smu_fini_fb_allocations(smu);
1405         if (ret)
1406                 return ret;
1407
1408         ret = smu_free_memory_pool(smu);
1409         if (ret)
1410                 return ret;
1411
1412         return 0;
1413 }
1414
1415 int smu_reset(struct smu_context *smu)
1416 {
1417         struct amdgpu_device *adev = smu->adev;
1418         int ret = 0;
1419
1420         ret = smu_hw_fini(adev);
1421         if (ret)
1422                 return ret;
1423
1424         ret = smu_hw_init(adev);
1425         if (ret)
1426                 return ret;
1427
1428         return ret;
1429 }
1430
1431 static int smu_suspend(void *handle)
1432 {
1433         int ret;
1434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1435         struct smu_context *smu = &adev->smu;
1436         bool baco_feature_is_enabled = false;
1437
1438         if(!smu->is_apu)
1439                 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1440
1441         ret = smu_system_features_control(smu, false);
1442         if (ret)
1443                 return ret;
1444
1445         if (baco_feature_is_enabled) {
1446                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1447                 if (ret) {
1448                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1449                         return ret;
1450                 }
1451         }
1452
1453         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1454
1455         if (adev->asic_type >= CHIP_NAVI10 &&
1456             adev->gfx.rlc.funcs->stop)
1457                 adev->gfx.rlc.funcs->stop(adev);
1458         if (smu->is_apu)
1459                 smu_set_gfx_cgpg(&adev->smu, false);
1460
1461         return 0;
1462 }
1463
1464 static int smu_resume(void *handle)
1465 {
1466         int ret;
1467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468         struct smu_context *smu = &adev->smu;
1469
1470         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1471                 return 0;
1472
1473         if (!smu->pm_enabled)
1474                 return 0;
1475
1476         pr_info("SMU is resuming...\n");
1477
1478         ret = smu_start_smc_engine(smu);
1479         if (ret) {
1480                 pr_err("SMU is not ready yet!\n");
1481                 goto failed;
1482         }
1483
1484         ret = smu_smc_table_hw_init(smu, false);
1485         if (ret)
1486                 goto failed;
1487
1488         ret = smu_start_thermal_control(smu);
1489         if (ret)
1490                 goto failed;
1491
1492         if (smu->is_apu)
1493                 smu_set_gfx_cgpg(&adev->smu, true);
1494
1495         smu->disable_uclk_switch = 0;
1496
1497         pr_info("SMU is resumed successfully!\n");
1498
1499         return 0;
1500
1501 failed:
1502         return ret;
1503 }
1504
1505 int smu_display_configuration_change(struct smu_context *smu,
1506                                      const struct amd_pp_display_configuration *display_config)
1507 {
1508         int index = 0;
1509         int num_of_active_display = 0;
1510
1511         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1512                 return -EINVAL;
1513
1514         if (!display_config)
1515                 return -EINVAL;
1516
1517         mutex_lock(&smu->mutex);
1518
1519         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1520                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1521                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1522
1523         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1524                 if (display_config->displays[index].controller_id != 0)
1525                         num_of_active_display++;
1526         }
1527
1528         smu_set_active_display_count(smu, num_of_active_display);
1529
1530         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1531                            display_config->cpu_cc6_disable,
1532                            display_config->cpu_pstate_disable,
1533                            display_config->nb_pstate_switch_disable);
1534
1535         mutex_unlock(&smu->mutex);
1536
1537         return 0;
1538 }
1539
1540 static int smu_get_clock_info(struct smu_context *smu,
1541                               struct smu_clock_info *clk_info,
1542                               enum smu_perf_level_designation designation)
1543 {
1544         int ret;
1545         struct smu_performance_level level = {0};
1546
1547         if (!clk_info)
1548                 return -EINVAL;
1549
1550         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1551         if (ret)
1552                 return -EINVAL;
1553
1554         clk_info->min_mem_clk = level.memory_clock;
1555         clk_info->min_eng_clk = level.core_clock;
1556         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1557
1558         ret = smu_get_perf_level(smu, designation, &level);
1559         if (ret)
1560                 return -EINVAL;
1561
1562         clk_info->min_mem_clk = level.memory_clock;
1563         clk_info->min_eng_clk = level.core_clock;
1564         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1565
1566         return 0;
1567 }
1568
1569 int smu_get_current_clocks(struct smu_context *smu,
1570                            struct amd_pp_clock_info *clocks)
1571 {
1572         struct amd_pp_simple_clock_info simple_clocks = {0};
1573         struct smu_clock_info hw_clocks;
1574         int ret = 0;
1575
1576         if (!is_support_sw_smu(smu->adev))
1577                 return -EINVAL;
1578
1579         mutex_lock(&smu->mutex);
1580
1581         smu_get_dal_power_level(smu, &simple_clocks);
1582
1583         if (smu->support_power_containment)
1584                 ret = smu_get_clock_info(smu, &hw_clocks,
1585                                          PERF_LEVEL_POWER_CONTAINMENT);
1586         else
1587                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1588
1589         if (ret) {
1590                 pr_err("Error in smu_get_clock_info\n");
1591                 goto failed;
1592         }
1593
1594         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1595         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1596         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1597         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1598         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1599         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1600         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1601         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1602
1603         if (simple_clocks.level == 0)
1604                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1605         else
1606                 clocks->max_clocks_state = simple_clocks.level;
1607
1608         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1609                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1610                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1611         }
1612
1613 failed:
1614         mutex_unlock(&smu->mutex);
1615         return ret;
1616 }
1617
1618 static int smu_set_clockgating_state(void *handle,
1619                                      enum amd_clockgating_state state)
1620 {
1621         return 0;
1622 }
1623
1624 static int smu_set_powergating_state(void *handle,
1625                                      enum amd_powergating_state state)
1626 {
1627         return 0;
1628 }
1629
1630 static int smu_enable_umd_pstate(void *handle,
1631                       enum amd_dpm_forced_level *level)
1632 {
1633         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1634                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1635                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1636                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1637
1638         struct smu_context *smu = (struct smu_context*)(handle);
1639         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1640
1641         if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1642                 return -EINVAL;
1643
1644         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1645                 /* enter umd pstate, save current level, disable gfx cg*/
1646                 if (*level & profile_mode_mask) {
1647                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1648                         smu_dpm_ctx->enable_umd_pstate = true;
1649                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1650                                                                AMD_IP_BLOCK_TYPE_GFX,
1651                                                                AMD_CG_STATE_UNGATE);
1652                         amdgpu_device_ip_set_powergating_state(smu->adev,
1653                                                                AMD_IP_BLOCK_TYPE_GFX,
1654                                                                AMD_PG_STATE_UNGATE);
1655                 }
1656         } else {
1657                 /* exit umd pstate, restore level, enable gfx cg*/
1658                 if (!(*level & profile_mode_mask)) {
1659                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1660                                 *level = smu_dpm_ctx->saved_dpm_level;
1661                         smu_dpm_ctx->enable_umd_pstate = false;
1662                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1663                                                                AMD_IP_BLOCK_TYPE_GFX,
1664                                                                AMD_CG_STATE_GATE);
1665                         amdgpu_device_ip_set_powergating_state(smu->adev,
1666                                                                AMD_IP_BLOCK_TYPE_GFX,
1667                                                                AMD_PG_STATE_GATE);
1668                 }
1669         }
1670
1671         return 0;
1672 }
1673
1674 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1675                                    enum amd_dpm_forced_level level,
1676                                    bool skip_display_settings)
1677 {
1678         int ret = 0;
1679         int index = 0;
1680         long workload;
1681         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1682
1683         if (!smu->pm_enabled)
1684                 return -EINVAL;
1685
1686         if (!skip_display_settings) {
1687                 ret = smu_display_config_changed(smu);
1688                 if (ret) {
1689                         pr_err("Failed to change display config!");
1690                         return ret;
1691                 }
1692         }
1693
1694         ret = smu_apply_clocks_adjust_rules(smu);
1695         if (ret) {
1696                 pr_err("Failed to apply clocks adjust rules!");
1697                 return ret;
1698         }
1699
1700         if (!skip_display_settings) {
1701                 ret = smu_notify_smc_display_config(smu);
1702                 if (ret) {
1703                         pr_err("Failed to notify smc display config!");
1704                         return ret;
1705                 }
1706         }
1707
1708         if (smu_dpm_ctx->dpm_level != level) {
1709                 ret = smu_asic_set_performance_level(smu, level);
1710                 if (ret) {
1711                         pr_err("Failed to set performance level!");
1712                         return ret;
1713                 }
1714
1715                 /* update the saved copy */
1716                 smu_dpm_ctx->dpm_level = level;
1717         }
1718
1719         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1720                 index = fls(smu->workload_mask);
1721                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1722                 workload = smu->workload_setting[index];
1723
1724                 if (smu->power_profile_mode != workload)
1725                         smu_set_power_profile_mode(smu, &workload, 0, false);
1726         }
1727
1728         return ret;
1729 }
1730
1731 int smu_handle_task(struct smu_context *smu,
1732                     enum amd_dpm_forced_level level,
1733                     enum amd_pp_task task_id,
1734                     bool lock_needed)
1735 {
1736         int ret = 0;
1737
1738         if (lock_needed)
1739                 mutex_lock(&smu->mutex);
1740
1741         switch (task_id) {
1742         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1743                 ret = smu_pre_display_config_changed(smu);
1744                 if (ret)
1745                         goto out;
1746                 ret = smu_set_cpu_power_state(smu);
1747                 if (ret)
1748                         goto out;
1749                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1750                 break;
1751         case AMD_PP_TASK_COMPLETE_INIT:
1752         case AMD_PP_TASK_READJUST_POWER_STATE:
1753                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1754                 break;
1755         default:
1756                 break;
1757         }
1758
1759 out:
1760         if (lock_needed)
1761                 mutex_unlock(&smu->mutex);
1762
1763         return ret;
1764 }
1765
1766 int smu_switch_power_profile(struct smu_context *smu,
1767                              enum PP_SMC_POWER_PROFILE type,
1768                              bool en)
1769 {
1770         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1771         long workload;
1772         uint32_t index;
1773
1774         if (!smu->pm_enabled)
1775                 return -EINVAL;
1776
1777         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1778                 return -EINVAL;
1779
1780         mutex_lock(&smu->mutex);
1781
1782         if (!en) {
1783                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1784                 index = fls(smu->workload_mask);
1785                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1786                 workload = smu->workload_setting[index];
1787         } else {
1788                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1789                 index = fls(smu->workload_mask);
1790                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1791                 workload = smu->workload_setting[index];
1792         }
1793
1794         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1795                 smu_set_power_profile_mode(smu, &workload, 0, false);
1796
1797         mutex_unlock(&smu->mutex);
1798
1799         return 0;
1800 }
1801
1802 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1803 {
1804         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1805         enum amd_dpm_forced_level level;
1806
1807         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1808                 return -EINVAL;
1809
1810         mutex_lock(&(smu->mutex));
1811         level = smu_dpm_ctx->dpm_level;
1812         mutex_unlock(&(smu->mutex));
1813
1814         return level;
1815 }
1816
1817 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1818 {
1819         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1820         int ret = 0;
1821
1822         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1823                 return -EINVAL;
1824
1825         mutex_lock(&smu->mutex);
1826
1827         ret = smu_enable_umd_pstate(smu, &level);
1828         if (ret) {
1829                 mutex_unlock(&smu->mutex);
1830                 return ret;
1831         }
1832
1833         ret = smu_handle_task(smu, level,
1834                               AMD_PP_TASK_READJUST_POWER_STATE,
1835                               false);
1836
1837         mutex_unlock(&smu->mutex);
1838
1839         return ret;
1840 }
1841
1842 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1843 {
1844         int ret = 0;
1845
1846         mutex_lock(&smu->mutex);
1847         ret = smu_init_display_count(smu, count);
1848         mutex_unlock(&smu->mutex);
1849
1850         return ret;
1851 }
1852
1853 int smu_force_clk_levels(struct smu_context *smu,
1854                          enum smu_clk_type clk_type,
1855                          uint32_t mask,
1856                          bool lock_needed)
1857 {
1858         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1859         int ret = 0;
1860
1861         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1862                 pr_debug("force clock level is for dpm manual mode only.\n");
1863                 return -EINVAL;
1864         }
1865
1866         if (lock_needed)
1867                 mutex_lock(&smu->mutex);
1868
1869         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1870                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1871
1872         if (lock_needed)
1873                 mutex_unlock(&smu->mutex);
1874
1875         return ret;
1876 }
1877
1878 int smu_set_mp1_state(struct smu_context *smu,
1879                       enum pp_mp1_state mp1_state)
1880 {
1881         uint16_t msg;
1882         int ret;
1883
1884         /*
1885          * The SMC is not fully ready. That may be
1886          * expected as the IP may be masked.
1887          * So, just return without error.
1888          */
1889         if (!smu->pm_enabled)
1890                 return 0;
1891
1892         mutex_lock(&smu->mutex);
1893
1894         switch (mp1_state) {
1895         case PP_MP1_STATE_SHUTDOWN:
1896                 msg = SMU_MSG_PrepareMp1ForShutdown;
1897                 break;
1898         case PP_MP1_STATE_UNLOAD:
1899                 msg = SMU_MSG_PrepareMp1ForUnload;
1900                 break;
1901         case PP_MP1_STATE_RESET:
1902                 msg = SMU_MSG_PrepareMp1ForReset;
1903                 break;
1904         case PP_MP1_STATE_NONE:
1905         default:
1906                 mutex_unlock(&smu->mutex);
1907                 return 0;
1908         }
1909
1910         /* some asics may not support those messages */
1911         if (smu_msg_get_index(smu, msg) < 0) {
1912                 mutex_unlock(&smu->mutex);
1913                 return 0;
1914         }
1915
1916         ret = smu_send_smc_msg(smu, msg);
1917         if (ret)
1918                 pr_err("[PrepareMp1] Failed!\n");
1919
1920         mutex_unlock(&smu->mutex);
1921
1922         return ret;
1923 }
1924
1925 int smu_set_df_cstate(struct smu_context *smu,
1926                       enum pp_df_cstate state)
1927 {
1928         int ret = 0;
1929
1930         /*
1931          * The SMC is not fully ready. That may be
1932          * expected as the IP may be masked.
1933          * So, just return without error.
1934          */
1935         if (!smu->pm_enabled)
1936                 return 0;
1937
1938         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1939                 return 0;
1940
1941         mutex_lock(&smu->mutex);
1942
1943         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1944         if (ret)
1945                 pr_err("[SetDfCstate] failed!\n");
1946
1947         mutex_unlock(&smu->mutex);
1948
1949         return ret;
1950 }
1951
1952 int smu_write_watermarks_table(struct smu_context *smu)
1953 {
1954         void *watermarks_table = smu->smu_table.watermarks_table;
1955
1956         if (!watermarks_table)
1957                 return -EINVAL;
1958
1959         return smu_update_table(smu,
1960                                 SMU_TABLE_WATERMARKS,
1961                                 0,
1962                                 watermarks_table,
1963                                 true);
1964 }
1965
1966 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1967                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1968 {
1969         void *table = smu->smu_table.watermarks_table;
1970
1971         if (!table)
1972                 return -EINVAL;
1973
1974         mutex_lock(&smu->mutex);
1975
1976         if (!smu->disable_watermark &&
1977                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1978                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1979                 smu_set_watermarks_table(smu, table, clock_ranges);
1980                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1981                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1982         }
1983
1984         mutex_unlock(&smu->mutex);
1985
1986         return 0;
1987 }
1988
1989 const struct amd_ip_funcs smu_ip_funcs = {
1990         .name = "smu",
1991         .early_init = smu_early_init,
1992         .late_init = smu_late_init,
1993         .sw_init = smu_sw_init,
1994         .sw_fini = smu_sw_fini,
1995         .hw_init = smu_hw_init,
1996         .hw_fini = smu_hw_fini,
1997         .suspend = smu_suspend,
1998         .resume = smu_resume,
1999         .is_idle = NULL,
2000         .check_soft_reset = NULL,
2001         .wait_for_idle = NULL,
2002         .soft_reset = NULL,
2003         .set_clockgating_state = smu_set_clockgating_state,
2004         .set_powergating_state = smu_set_powergating_state,
2005         .enable_umd_pstate = smu_enable_umd_pstate,
2006 };
2007
2008 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2009 {
2010         .type = AMD_IP_BLOCK_TYPE_SMC,
2011         .major = 11,
2012         .minor = 0,
2013         .rev = 0,
2014         .funcs = &smu_ip_funcs,
2015 };
2016
2017 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2018 {
2019         .type = AMD_IP_BLOCK_TYPE_SMC,
2020         .major = 12,
2021         .minor = 0,
2022         .rev = 0,
2023         .funcs = &smu_ip_funcs,
2024 };
2025
2026 int smu_load_microcode(struct smu_context *smu)
2027 {
2028         int ret = 0;
2029
2030         mutex_lock(&smu->mutex);
2031
2032         if (smu->ppt_funcs->load_microcode)
2033                 ret = smu->ppt_funcs->load_microcode(smu);
2034
2035         mutex_unlock(&smu->mutex);
2036
2037         return ret;
2038 }
2039
2040 int smu_check_fw_status(struct smu_context *smu)
2041 {
2042         int ret = 0;
2043
2044         mutex_lock(&smu->mutex);
2045
2046         if (smu->ppt_funcs->check_fw_status)
2047                 ret = smu->ppt_funcs->check_fw_status(smu);
2048
2049         mutex_unlock(&smu->mutex);
2050
2051         return ret;
2052 }
2053
2054 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2055 {
2056         int ret = 0;
2057
2058         mutex_lock(&smu->mutex);
2059
2060         if (smu->ppt_funcs->set_gfx_cgpg)
2061                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2062
2063         mutex_unlock(&smu->mutex);
2064
2065         return ret;
2066 }
2067
2068 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2069 {
2070         int ret = 0;
2071
2072         mutex_lock(&smu->mutex);
2073
2074         if (smu->ppt_funcs->set_fan_speed_rpm)
2075                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2076
2077         mutex_unlock(&smu->mutex);
2078
2079         return ret;
2080 }
2081
2082 int smu_get_power_limit(struct smu_context *smu,
2083                         uint32_t *limit,
2084                         bool def,
2085                         bool lock_needed)
2086 {
2087         int ret = 0;
2088
2089         if (lock_needed)
2090                 mutex_lock(&smu->mutex);
2091
2092         if (smu->ppt_funcs->get_power_limit)
2093                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2094
2095         if (lock_needed)
2096                 mutex_unlock(&smu->mutex);
2097
2098         return ret;
2099 }
2100
2101 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2102 {
2103         int ret = 0;
2104
2105         mutex_lock(&smu->mutex);
2106
2107         if (smu->ppt_funcs->set_power_limit)
2108                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2109
2110         mutex_unlock(&smu->mutex);
2111
2112         return ret;
2113 }
2114
2115 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2116 {
2117         int ret = 0;
2118
2119         mutex_lock(&smu->mutex);
2120
2121         if (smu->ppt_funcs->print_clk_levels)
2122                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2123
2124         mutex_unlock(&smu->mutex);
2125
2126         return ret;
2127 }
2128
2129 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2130 {
2131         int ret = 0;
2132
2133         mutex_lock(&smu->mutex);
2134
2135         if (smu->ppt_funcs->get_od_percentage)
2136                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2137
2138         mutex_unlock(&smu->mutex);
2139
2140         return ret;
2141 }
2142
2143 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2144 {
2145         int ret = 0;
2146
2147         mutex_lock(&smu->mutex);
2148
2149         if (smu->ppt_funcs->set_od_percentage)
2150                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2151
2152         mutex_unlock(&smu->mutex);
2153
2154         return ret;
2155 }
2156
2157 int smu_od_edit_dpm_table(struct smu_context *smu,
2158                           enum PP_OD_DPM_TABLE_COMMAND type,
2159                           long *input, uint32_t size)
2160 {
2161         int ret = 0;
2162
2163         mutex_lock(&smu->mutex);
2164
2165         if (smu->ppt_funcs->od_edit_dpm_table)
2166                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2167
2168         mutex_unlock(&smu->mutex);
2169
2170         return ret;
2171 }
2172
2173 int smu_read_sensor(struct smu_context *smu,
2174                     enum amd_pp_sensors sensor,
2175                     void *data, uint32_t *size)
2176 {
2177         int ret = 0;
2178
2179         mutex_lock(&smu->mutex);
2180
2181         if (smu->ppt_funcs->read_sensor)
2182                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2183
2184         mutex_unlock(&smu->mutex);
2185
2186         return ret;
2187 }
2188
2189 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2190 {
2191         int ret = 0;
2192
2193         mutex_lock(&smu->mutex);
2194
2195         if (smu->ppt_funcs->get_power_profile_mode)
2196                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2197
2198         mutex_unlock(&smu->mutex);
2199
2200         return ret;
2201 }
2202
2203 int smu_set_power_profile_mode(struct smu_context *smu,
2204                                long *param,
2205                                uint32_t param_size,
2206                                bool lock_needed)
2207 {
2208         int ret = 0;
2209
2210         if (lock_needed)
2211                 mutex_lock(&smu->mutex);
2212
2213         if (smu->ppt_funcs->set_power_profile_mode)
2214                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2215
2216         if (lock_needed)
2217                 mutex_unlock(&smu->mutex);
2218
2219         return ret;
2220 }
2221
2222
2223 int smu_get_fan_control_mode(struct smu_context *smu)
2224 {
2225         int ret = 0;
2226
2227         mutex_lock(&smu->mutex);
2228
2229         if (smu->ppt_funcs->get_fan_control_mode)
2230                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2231
2232         mutex_unlock(&smu->mutex);
2233
2234         return ret;
2235 }
2236
2237 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2238 {
2239         int ret = 0;
2240
2241         mutex_lock(&smu->mutex);
2242
2243         if (smu->ppt_funcs->set_fan_control_mode)
2244                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2245
2246         mutex_unlock(&smu->mutex);
2247
2248         return ret;
2249 }
2250
2251 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2252 {
2253         int ret = 0;
2254
2255         mutex_lock(&smu->mutex);
2256
2257         if (smu->ppt_funcs->get_fan_speed_percent)
2258                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2259
2260         mutex_unlock(&smu->mutex);
2261
2262         return ret;
2263 }
2264
2265 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2266 {
2267         int ret = 0;
2268
2269         mutex_lock(&smu->mutex);
2270
2271         if (smu->ppt_funcs->set_fan_speed_percent)
2272                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2273
2274         mutex_unlock(&smu->mutex);
2275
2276         return ret;
2277 }
2278
2279 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2280 {
2281         int ret = 0;
2282
2283         mutex_lock(&smu->mutex);
2284
2285         if (smu->ppt_funcs->get_fan_speed_rpm)
2286                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2287
2288         mutex_unlock(&smu->mutex);
2289
2290         return ret;
2291 }
2292
2293 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2294 {
2295         int ret = 0;
2296
2297         mutex_lock(&smu->mutex);
2298
2299         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2300                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2301
2302         mutex_unlock(&smu->mutex);
2303
2304         return ret;
2305 }
2306
2307 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2308 {
2309         int ret = 0;
2310
2311         if (smu->ppt_funcs->set_active_display_count)
2312                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2313
2314         return ret;
2315 }
2316
2317 int smu_get_clock_by_type(struct smu_context *smu,
2318                           enum amd_pp_clock_type type,
2319                           struct amd_pp_clocks *clocks)
2320 {
2321         int ret = 0;
2322
2323         mutex_lock(&smu->mutex);
2324
2325         if (smu->ppt_funcs->get_clock_by_type)
2326                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2327
2328         mutex_unlock(&smu->mutex);
2329
2330         return ret;
2331 }
2332
2333 int smu_get_max_high_clocks(struct smu_context *smu,
2334                             struct amd_pp_simple_clock_info *clocks)
2335 {
2336         int ret = 0;
2337
2338         mutex_lock(&smu->mutex);
2339
2340         if (smu->ppt_funcs->get_max_high_clocks)
2341                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2342
2343         mutex_unlock(&smu->mutex);
2344
2345         return ret;
2346 }
2347
2348 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2349                                        enum smu_clk_type clk_type,
2350                                        struct pp_clock_levels_with_latency *clocks)
2351 {
2352         int ret = 0;
2353
2354         mutex_lock(&smu->mutex);
2355
2356         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2357                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2358
2359         mutex_unlock(&smu->mutex);
2360
2361         return ret;
2362 }
2363
2364 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2365                                        enum amd_pp_clock_type type,
2366                                        struct pp_clock_levels_with_voltage *clocks)
2367 {
2368         int ret = 0;
2369
2370         mutex_lock(&smu->mutex);
2371
2372         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2373                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2374
2375         mutex_unlock(&smu->mutex);
2376
2377         return ret;
2378 }
2379
2380
2381 int smu_display_clock_voltage_request(struct smu_context *smu,
2382                                       struct pp_display_clock_request *clock_req)
2383 {
2384         int ret = 0;
2385
2386         mutex_lock(&smu->mutex);
2387
2388         if (smu->ppt_funcs->display_clock_voltage_request)
2389                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2390
2391         mutex_unlock(&smu->mutex);
2392
2393         return ret;
2394 }
2395
2396
2397 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2398 {
2399         int ret = -EINVAL;
2400
2401         mutex_lock(&smu->mutex);
2402
2403         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2404                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2405
2406         mutex_unlock(&smu->mutex);
2407
2408         return ret;
2409 }
2410
2411 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2412 {
2413         int ret = 0;
2414
2415         mutex_lock(&smu->mutex);
2416
2417         if (smu->ppt_funcs->notify_smu_enable_pwe)
2418                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2419
2420         mutex_unlock(&smu->mutex);
2421
2422         return ret;
2423 }
2424
2425 int smu_set_xgmi_pstate(struct smu_context *smu,
2426                         uint32_t pstate)
2427 {
2428         int ret = 0;
2429
2430         mutex_lock(&smu->mutex);
2431
2432         if (smu->ppt_funcs->set_xgmi_pstate)
2433                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2434
2435         mutex_unlock(&smu->mutex);
2436
2437         return ret;
2438 }
2439
2440 int smu_set_azalia_d3_pme(struct smu_context *smu)
2441 {
2442         int ret = 0;
2443
2444         mutex_lock(&smu->mutex);
2445
2446         if (smu->ppt_funcs->set_azalia_d3_pme)
2447                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2448
2449         mutex_unlock(&smu->mutex);
2450
2451         return ret;
2452 }
2453
2454 bool smu_baco_is_support(struct smu_context *smu)
2455 {
2456         bool ret = false;
2457
2458         mutex_lock(&smu->mutex);
2459
2460         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2461                 ret = smu->ppt_funcs->baco_is_support(smu);
2462
2463         mutex_unlock(&smu->mutex);
2464
2465         return ret;
2466 }
2467
2468 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2469 {
2470         if (smu->ppt_funcs->baco_get_state)
2471                 return -EINVAL;
2472
2473         mutex_lock(&smu->mutex);
2474         *state = smu->ppt_funcs->baco_get_state(smu);
2475         mutex_unlock(&smu->mutex);
2476
2477         return 0;
2478 }
2479
2480 int smu_baco_enter(struct smu_context *smu)
2481 {
2482         int ret = 0;
2483
2484         mutex_lock(&smu->mutex);
2485
2486         if (smu->ppt_funcs->baco_enter)
2487                 ret = smu->ppt_funcs->baco_enter(smu);
2488
2489         mutex_unlock(&smu->mutex);
2490
2491         return ret;
2492 }
2493
2494 int smu_baco_exit(struct smu_context *smu)
2495 {
2496         int ret = 0;
2497
2498         mutex_lock(&smu->mutex);
2499
2500         if (smu->ppt_funcs->baco_exit)
2501                 ret = smu->ppt_funcs->baco_exit(smu);
2502
2503         mutex_unlock(&smu->mutex);
2504
2505         return ret;
2506 }
2507
2508 int smu_mode2_reset(struct smu_context *smu)
2509 {
2510         int ret = 0;
2511
2512         mutex_lock(&smu->mutex);
2513
2514         if (smu->ppt_funcs->mode2_reset)
2515                 ret = smu->ppt_funcs->mode2_reset(smu);
2516
2517         mutex_unlock(&smu->mutex);
2518
2519         return ret;
2520 }
2521
2522 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2523                                          struct pp_smu_nv_clock_table *max_clocks)
2524 {
2525         int ret = 0;
2526
2527         mutex_lock(&smu->mutex);
2528
2529         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2530                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2531
2532         mutex_unlock(&smu->mutex);
2533
2534         return ret;
2535 }
2536
2537 int smu_get_uclk_dpm_states(struct smu_context *smu,
2538                             unsigned int *clock_values_in_khz,
2539                             unsigned int *num_states)
2540 {
2541         int ret = 0;
2542
2543         mutex_lock(&smu->mutex);
2544
2545         if (smu->ppt_funcs->get_uclk_dpm_states)
2546                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2547
2548         mutex_unlock(&smu->mutex);
2549
2550         return ret;
2551 }
2552
2553 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2554 {
2555         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2556
2557         mutex_lock(&smu->mutex);
2558
2559         if (smu->ppt_funcs->get_current_power_state)
2560                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2561
2562         mutex_unlock(&smu->mutex);
2563
2564         return pm_state;
2565 }
2566
2567 int smu_get_dpm_clock_table(struct smu_context *smu,
2568                             struct dpm_clocks *clock_table)
2569 {
2570         int ret = 0;
2571
2572         mutex_lock(&smu->mutex);
2573
2574         if (smu->ppt_funcs->get_dpm_clock_table)
2575                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2576
2577         mutex_unlock(&smu->mutex);
2578
2579         return ret;
2580 }
2581
2582 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2583 {
2584         uint32_t ret = 0;
2585
2586         if (smu->ppt_funcs->get_pptable_power_limit)
2587                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2588
2589         return ret;
2590 }
2591
2592 int smu_send_smc_msg(struct smu_context *smu,
2593                      enum smu_message_type msg)
2594 {
2595         int ret;
2596
2597         ret = smu_send_smc_msg_with_param(smu, msg, 0);
2598         return ret;
2599 }