drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "soc15_common.h"
  29 #include "smu_v11_0.h"
  30 #include "atom.h"
  31 #include "amd_pcie.h"
  32
  33 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
  34 {
  35         int ret = 0;
  36
  37         if (!if_version && !smu_version)
  38                 return -EINVAL;
  39
  40         if (if_version) {
  41                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
  42                 if (ret)
  43                         return ret;
  44
  45                 ret = smu_read_smc_arg(smu, if_version);
  46                 if (ret)
  47                         return ret;
  48         }
  49
  50         if (smu_version) {
  51                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
  52                 if (ret)
  53                         return ret;
  54
  55                 ret = smu_read_smc_arg(smu, smu_version);
  56                 if (ret)
  57                         return ret;
  58         }
  59
  60         return ret;
  61 }
  62
  63 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
  64                             uint32_t min, uint32_t max)
  65 {
  66         int ret = 0, clk_id = 0;
  67         uint32_t param;
  68
  69         if (min <= 0 && max <= 0)
  70                 return -EINVAL;
  71
  72         if (!smu_clk_dpm_is_enabled(smu, clk_type))
  73                 return 0;
  74
  75         clk_id = smu_clk_get_index(smu, clk_type);
  76         if (clk_id < 0)
  77                 return clk_id;
  78
  79         if (max > 0) {
  80                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
  81                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
  82                                                   param);
  83                 if (ret)
  84                         return ret;
  85         }
  86
  87         if (min > 0) {
  88                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
  89                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
  90                                                   param);
  91                 if (ret)
  92                         return ret;
  93         }
  94
  95
  96         return ret;
  97 }
  98
  99 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 100                             uint32_t min, uint32_t max)
 101 {
 102         int ret = 0, clk_id = 0;
 103         uint32_t param;
 104
 105         if (min <= 0 && max <= 0)
 106                 return -EINVAL;
 107
 108         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 109                 return 0;
 110
 111         clk_id = smu_clk_get_index(smu, clk_type);
 112         if (clk_id < 0)
 113                 return clk_id;
 114
 115         if (max > 0) {
 116                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 117                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 118                                                   param);
 119                 if (ret)
 120                         return ret;
 121         }
 122
 123         if (min > 0) {
 124                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 125                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 126                                                   param);
 127                 if (ret)
 128                         return ret;
 129         }
 130
 131
 132         return ret;
 133 }
 134
 135 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 136                            uint32_t *min, uint32_t *max)
 137 {
 138         int ret = 0, clk_id = 0;
 139         uint32_t param = 0;
 140         uint32_t clock_limit;
 141
 142         if (!min && !max)
 143                 return -EINVAL;
 144
 145         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 146                 switch (clk_type) {
 147                 case SMU_MCLK:
 148                 case SMU_UCLK:
 149                         clock_limit = smu->smu_table.boot_values.uclk;
 150                         break;
 151                 case SMU_GFXCLK:
 152                 case SMU_SCLK:
 153                         clock_limit = smu->smu_table.boot_values.gfxclk;
 154                         break;
 155                 case SMU_SOCCLK:
 156                         clock_limit = smu->smu_table.boot_values.socclk;
 157                         break;
 158                 default:
 159                         clock_limit = 0;
 160                         break;
 161                 }
 162
 163                 /* clock in Mhz unit */
 164                 if (min)
 165                         *min = clock_limit / 100;
 166                 if (max)
 167                         *max = clock_limit / 100;
 168
 169                 return 0;
 170         }
 171
 172         mutex_lock(&smu->mutex);
 173         clk_id = smu_clk_get_index(smu, clk_type);
 174         if (clk_id < 0) {
 175                 ret = -EINVAL;
 176                 goto failed;
 177         }
 178
 179         param = (clk_id & 0xffff) << 16;
 180
 181         if (max) {
 182                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
 183                 if (ret)
 184                         goto failed;
 185                 ret = smu_read_smc_arg(smu, max);
 186                 if (ret)
 187                         goto failed;
 188         }
 189
 190         if (min) {
 191                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
 192                 if (ret)
 193                         goto failed;
 194                 ret = smu_read_smc_arg(smu, min);
 195                 if (ret)
 196                         goto failed;
 197         }
 198
 199 failed:
 200         mutex_unlock(&smu->mutex);
 201         return ret;
 202 }
 203
 204 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 205                               uint16_t level, uint32_t *value)
 206 {
 207         int ret = 0, clk_id = 0;
 208         uint32_t param;
 209
 210         if (!value)
 211                 return -EINVAL;
 212
 213         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 214                 return 0;
 215
 216         clk_id = smu_clk_get_index(smu, clk_type);
 217         if (clk_id < 0)
 218                 return clk_id;
 219
 220         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 221
 222         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 223                                           param);
 224         if (ret)
 225                 return ret;
 226
 227         ret = smu_read_smc_arg(smu, &param);
 228         if (ret)
 229                 return ret;
 230
 231         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 232          * now, we un-support it */
 233         *value = param & 0x7fffffff;
 234
 235         return ret;
 236 }
 237
 238 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 239                             uint32_t *value)
 240 {
 241         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 242 }
 243
 244 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 245 {
 246         enum smu_feature_mask feature_id = 0;
 247
 248         switch (clk_type) {
 249         case SMU_MCLK:
 250         case SMU_UCLK:
 251                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 252                 break;
 253         case SMU_GFXCLK:
 254         case SMU_SCLK:
 255                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 256                 break;
 257         case SMU_SOCCLK:
 258                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 259                 break;
 260         default:
 261                 return true;
 262         }
 263
 264         if(!smu_feature_is_enabled(smu, feature_id)) {
 265                 pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id);
 266                 return false;
 267         }
 268
 269         return true;
 270 }
 271
 272
 273 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 274                            bool gate)
 275 {
 276         int ret = 0;
 277
 278         switch (block_type) {
 279         case AMD_IP_BLOCK_TYPE_UVD:
 280                 ret = smu_dpm_set_uvd_enable(smu, gate);
 281                 break;
 282         case AMD_IP_BLOCK_TYPE_VCE:
 283                 ret = smu_dpm_set_vce_enable(smu, gate);
 284                 break;
 285         case AMD_IP_BLOCK_TYPE_GFX:
 286                 ret = smu_gfx_off_control(smu, gate);
 287                 break;
 288         default:
 289                 break;
 290         }
 291
 292         return ret;
 293 }
 294
 295 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 296 {
 297         /* not support power state */
 298         return POWER_STATE_TYPE_DEFAULT;
 299 }
 300
 301 int smu_get_power_num_states(struct smu_context *smu,
 302                              struct pp_states_info *state_info)
 303 {
 304         if (!state_info)
 305                 return -EINVAL;
 306
 307         /* not support power state */
 308         memset(state_info, 0, sizeof(struct pp_states_info));
 309         state_info->nums = 0;
 310
 311         return 0;
 312 }
 313
 314 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 315                            void *data, uint32_t *size)
 316 {
 317         int ret = 0;
 318
 319         switch (sensor) {
 320         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 321                 *((uint32_t *)data) = smu->pstate_sclk;
 322                 *size = 4;
 323                 break;
 324         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 325                 *((uint32_t *)data) = smu->pstate_mclk;
 326                 *size = 4;
 327                 break;
 328         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 329                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 330                 *size = 8;
 331                 break;
 332         case AMDGPU_PP_SENSOR_UVD_POWER:
 333                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 334                 *size = 4;
 335                 break;
 336         case AMDGPU_PP_SENSOR_VCE_POWER:
 337                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 338                 *size = 4;
 339                 break;
 340         default:
 341                 ret = -EINVAL;
 342                 break;
 343         }
 344
 345         if (ret)
 346                 *size = 0;
 347
 348         return ret;
 349 }
 350
 351 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 352                      void *table_data, bool drv2smu)
 353 {
 354         struct smu_table_context *smu_table = &smu->smu_table;
 355         struct smu_table *table = NULL;
 356         int ret = 0;
 357         int table_id = smu_table_get_index(smu, table_index);
 358
 359         if (!table_data || table_id >= smu_table->table_count)
 360                 return -EINVAL;
 361
 362         table = &smu_table->tables[table_index];
 363
 364         if (drv2smu)
 365                 memcpy(table->cpu_addr, table_data, table->size);
 366
 367         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 368                                           upper_32_bits(table->mc_address));
 369         if (ret)
 370                 return ret;
 371         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 372                                           lower_32_bits(table->mc_address));
 373         if (ret)
 374                 return ret;
 375         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 376                                           SMU_MSG_TransferTableDram2Smu :
 377                                           SMU_MSG_TransferTableSmu2Dram,
 378                                           table_id | ((argument & 0xFFFF) << 16));
 379         if (ret)
 380                 return ret;
 381
 382         if (!drv2smu)
 383                 memcpy(table_data, table->cpu_addr, table->size);
 384
 385         return ret;
 386 }
 387
 388 bool is_support_sw_smu(struct amdgpu_device *adev)
 389 {
 390         if (adev->asic_type == CHIP_VEGA20)
 391                 return (amdgpu_dpm == 2) ? true : false;
 392         else if (adev->asic_type >= CHIP_NAVI10)
 393                 return true;
 394         else
 395                 return false;
 396 }
 397
 398 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 399 {
 400         struct smu_table_context *smu_table = &smu->smu_table;
 401
 402         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 403                 return -EINVAL;
 404
 405         if (smu_table->hardcode_pptable)
 406                 *table = smu_table->hardcode_pptable;
 407         else
 408                 *table = smu_table->power_play_table;
 409
 410         return smu_table->power_play_table_size;
 411 }
 412
 413 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 414 {
 415         struct smu_table_context *smu_table = &smu->smu_table;
 416         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 417         int ret = 0;
 418
 419         if (!smu->pm_enabled)
 420                 return -EINVAL;
 421         if (header->usStructureSize != size) {
 422                 pr_err("pp table size not matched !\n");
 423                 return -EIO;
 424         }
 425
 426         mutex_lock(&smu->mutex);
 427         if (!smu_table->hardcode_pptable)
 428                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 429         if (!smu_table->hardcode_pptable) {
 430                 ret = -ENOMEM;
 431                 goto failed;
 432         }
 433
 434         memcpy(smu_table->hardcode_pptable, buf, size);
 435         smu_table->power_play_table = smu_table->hardcode_pptable;
 436         smu_table->power_play_table_size = size;
 437         mutex_unlock(&smu->mutex);
 438
 439         ret = smu_reset(smu);
 440         if (ret)
 441                 pr_info("smu reset failed, ret = %d\n", ret);
 442
 443         return ret;
 444
 445 failed:
 446         mutex_unlock(&smu->mutex);
 447         return ret;
 448 }
 449
 450 int smu_feature_init_dpm(struct smu_context *smu)
 451 {
 452         struct smu_feature *feature = &smu->smu_feature;
 453         int ret = 0;
 454         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 455
 456         if (!smu->pm_enabled)
 457                 return ret;
 458         mutex_lock(&feature->mutex);
 459         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 460         mutex_unlock(&feature->mutex);
 461
 462         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 463                                              SMU_FEATURE_MAX/32);
 464         if (ret)
 465                 return ret;
 466
 467         mutex_lock(&feature->mutex);
 468         bitmap_or(feature->allowed, feature->allowed,
 469                       (unsigned long *)allowed_feature_mask,
 470                       feature->feature_num);
 471         mutex_unlock(&feature->mutex);
 472
 473         return ret;
 474 }
 475
 476 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 477 {
 478         struct smu_feature *feature = &smu->smu_feature;
 479         uint32_t feature_id;
 480         int ret = 0;
 481
 482         feature_id = smu_feature_get_index(smu, mask);
 483
 484         WARN_ON(feature_id > feature->feature_num);
 485
 486         mutex_lock(&feature->mutex);
 487         ret = test_bit(feature_id, feature->enabled);
 488         mutex_unlock(&feature->mutex);
 489
 490         return ret;
 491 }
 492
 493 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 494                             bool enable)
 495 {
 496         struct smu_feature *feature = &smu->smu_feature;
 497         uint32_t feature_id;
 498         int ret = 0;
 499
 500         feature_id = smu_feature_get_index(smu, mask);
 501
 502         WARN_ON(feature_id > feature->feature_num);
 503
 504         mutex_lock(&feature->mutex);
 505         ret = smu_feature_update_enable_state(smu, feature_id, enable);
 506         if (ret)
 507                 goto failed;
 508
 509         if (enable)
 510                 test_and_set_bit(feature_id, feature->enabled);
 511         else
 512                 test_and_clear_bit(feature_id, feature->enabled);
 513
 514 failed:
 515         mutex_unlock(&feature->mutex);
 516
 517         return ret;
 518 }
 519
 520 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 521 {
 522         struct smu_feature *feature = &smu->smu_feature;
 523         uint32_t feature_id;
 524         int ret = 0;
 525
 526         feature_id = smu_feature_get_index(smu, mask);
 527
 528         WARN_ON(feature_id > feature->feature_num);
 529
 530         mutex_lock(&feature->mutex);
 531         ret = test_bit(feature_id, feature->supported);
 532         mutex_unlock(&feature->mutex);
 533
 534         return ret;
 535 }
 536
 537 int smu_feature_set_supported(struct smu_context *smu,
 538                               enum smu_feature_mask mask,
 539                               bool enable)
 540 {
 541         struct smu_feature *feature = &smu->smu_feature;
 542         uint32_t feature_id;
 543         int ret = 0;
 544
 545         feature_id = smu_feature_get_index(smu, mask);
 546
 547         WARN_ON(feature_id > feature->feature_num);
 548
 549         mutex_lock(&feature->mutex);
 550         if (enable)
 551                 test_and_set_bit(feature_id, feature->supported);
 552         else
 553                 test_and_clear_bit(feature_id, feature->supported);
 554         mutex_unlock(&feature->mutex);
 555
 556         return ret;
 557 }
 558
 559 static int smu_set_funcs(struct amdgpu_device *adev)
 560 {
 561         struct smu_context *smu = &adev->smu;
 562
 563         switch (adev->asic_type) {
 564         case CHIP_VEGA20:
 565         case CHIP_NAVI10:
 566                 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 567                         smu->od_enabled = true;
 568                 smu_v11_0_set_smu_funcs(smu);
 569                 break;
 570         default:
 571                 return -EINVAL;
 572         }
 573
 574         return 0;
 575 }
 576
 577 static int smu_early_init(void *handle)
 578 {
 579         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 580         struct smu_context *smu = &adev->smu;
 581
 582         smu->adev = adev;
 583         smu->pm_enabled = !!amdgpu_dpm;
 584         mutex_init(&smu->mutex);
 585
 586         return smu_set_funcs(adev);
 587 }
 588
 589 static int smu_late_init(void *handle)
 590 {
 591         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 592         struct smu_context *smu = &adev->smu;
 593
 594         if (!smu->pm_enabled)
 595                 return 0;
 596         mutex_lock(&smu->mutex);
 597         smu_handle_task(&adev->smu,
 598                         smu->smu_dpm.dpm_level,
 599                         AMD_PP_TASK_COMPLETE_INIT);
 600         mutex_unlock(&smu->mutex);
 601
 602         return 0;
 603 }
 604
 605 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 606                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 607                             uint8_t **addr)
 608 {
 609         struct amdgpu_device *adev = smu->adev;
 610         uint16_t data_start;
 611
 612         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 613                                            size, frev, crev, &data_start))
 614                 return -EINVAL;
 615
 616         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 617
 618         return 0;
 619 }
 620
 621 static int smu_initialize_pptable(struct smu_context *smu)
 622 {
 623         /* TODO */
 624         return 0;
 625 }
 626
 627 static int smu_smc_table_sw_init(struct smu_context *smu)
 628 {
 629         int ret;
 630
 631         ret = smu_initialize_pptable(smu);
 632         if (ret) {
 633                 pr_err("Failed to init smu_initialize_pptable!\n");
 634                 return ret;
 635         }
 636
 637         /**
 638          * Create smu_table structure, and init smc tables such as
 639          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 640          */
 641         ret = smu_init_smc_tables(smu);
 642         if (ret) {
 643                 pr_err("Failed to init smc tables!\n");
 644                 return ret;
 645         }
 646
 647         /**
 648          * Create smu_power_context structure, and allocate smu_dpm_context and
 649          * context size to fill the smu_power_context data.
 650          */
 651         ret = smu_init_power(smu);
 652         if (ret) {
 653                 pr_err("Failed to init smu_init_power!\n");
 654                 return ret;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static int smu_smc_table_sw_fini(struct smu_context *smu)
 661 {
 662         int ret;
 663
 664         ret = smu_fini_smc_tables(smu);
 665         if (ret) {
 666                 pr_err("Failed to smu_fini_smc_tables!\n");
 667                 return ret;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int smu_sw_init(void *handle)
 674 {
 675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 676         struct smu_context *smu = &adev->smu;
 677         int ret;
 678
 679         smu->pool_size = adev->pm.smu_prv_buffer_size;
 680         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 681         mutex_init(&smu->smu_feature.mutex);
 682         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 683         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 684         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 685
 686         mutex_init(&smu->smu_baco.mutex);
 687         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 688         smu->smu_baco.platform_support = false;
 689
 690         smu->watermarks_bitmap = 0;
 691         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 692         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 693
 694         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 695         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 696         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 697         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 698         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 699         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 700         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 701         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 702
 703         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 704         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 705         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 706         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 707         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 708         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 709         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 710         smu->display_config = &adev->pm.pm_display_cfg;
 711
 712         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 713         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 714         ret = smu_init_microcode(smu);
 715         if (ret) {
 716                 pr_err("Failed to load smu firmware!\n");
 717                 return ret;
 718         }
 719
 720         ret = smu_smc_table_sw_init(smu);
 721         if (ret) {
 722                 pr_err("Failed to sw init smc table!\n");
 723                 return ret;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int smu_sw_fini(void *handle)
 730 {
 731         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 732         struct smu_context *smu = &adev->smu;
 733         int ret;
 734
 735         ret = smu_smc_table_sw_fini(smu);
 736         if (ret) {
 737                 pr_err("Failed to sw fini smc table!\n");
 738                 return ret;
 739         }
 740
 741         ret = smu_fini_power(smu);
 742         if (ret) {
 743                 pr_err("Failed to init smu_fini_power!\n");
 744                 return ret;
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int smu_init_fb_allocations(struct smu_context *smu)
 751 {
 752         struct amdgpu_device *adev = smu->adev;
 753         struct smu_table_context *smu_table = &smu->smu_table;
 754         struct smu_table *tables = smu_table->tables;
 755         uint32_t table_count = smu_table->table_count;
 756         uint32_t i = 0;
 757         int32_t ret = 0;
 758
 759         if (table_count <= 0)
 760                 return -EINVAL;
 761
 762         for (i = 0 ; i < table_count; i++) {
 763                 if (tables[i].size == 0)
 764                         continue;
 765                 ret = amdgpu_bo_create_kernel(adev,
 766                                               tables[i].size,
 767                                               tables[i].align,
 768                                               tables[i].domain,
 769                                               &tables[i].bo,
 770                                               &tables[i].mc_address,
 771                                               &tables[i].cpu_addr);
 772                 if (ret)
 773                         goto failed;
 774         }
 775
 776         return 0;
 777 failed:
 778         for (; i > 0; i--) {
 779                 if (tables[i].size == 0)
 780                         continue;
 781                 amdgpu_bo_free_kernel(&tables[i].bo,
 782                                       &tables[i].mc_address,
 783                                       &tables[i].cpu_addr);
 784
 785         }
 786         return ret;
 787 }
 788
 789 static int smu_fini_fb_allocations(struct smu_context *smu)
 790 {
 791         struct smu_table_context *smu_table = &smu->smu_table;
 792         struct smu_table *tables = smu_table->tables;
 793         uint32_t table_count = smu_table->table_count;
 794         uint32_t i = 0;
 795
 796         if (table_count == 0 || tables == NULL)
 797                 return 0;
 798
 799         for (i = 0 ; i < table_count; i++) {
 800                 if (tables[i].size == 0)
 801                         continue;
 802                 amdgpu_bo_free_kernel(&tables[i].bo,
 803                                       &tables[i].mc_address,
 804                                       &tables[i].cpu_addr);
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int smu_override_pcie_parameters(struct smu_context *smu)
 811 {
 812         struct amdgpu_device *adev = smu->adev;
 813         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 814         int ret;
 815
 816         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 817                 pcie_gen = 3;
 818         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 819                 pcie_gen = 2;
 820         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 821                 pcie_gen = 1;
 822         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 823                 pcie_gen = 0;
 824
 825         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 826          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 827          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 828          */
 829         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 830                 pcie_width = 6;
 831         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 832                 pcie_width = 5;
 833         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 834                 pcie_width = 4;
 835         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 836                 pcie_width = 3;
 837         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 838                 pcie_width = 2;
 839         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 840                 pcie_width = 1;
 841
 842         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 843         ret = smu_send_smc_msg_with_param(smu,
 844                                           SMU_MSG_OverridePcieParameters,
 845                                           smu_pcie_arg);
 846         if (ret)
 847                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
 848         return ret;
 849 }
 850
 851 static int smu_smc_table_hw_init(struct smu_context *smu,
 852                                  bool initialize)
 853 {
 854         struct amdgpu_device *adev = smu->adev;
 855         int ret;
 856
 857         if (smu_is_dpm_running(smu) && adev->in_suspend) {
 858                 pr_info("dpm has been enabled\n");
 859                 return 0;
 860         }
 861
 862         ret = smu_init_display_count(smu, 0);
 863         if (ret)
 864                 return ret;
 865
 866         if (initialize) {
 867                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
 868                 ret = smu_get_vbios_bootup_values(smu);
 869                 if (ret)
 870                         return ret;
 871
 872                 ret = smu_setup_pptable(smu);
 873                 if (ret)
 874                         return ret;
 875
 876                 ret = smu_get_clk_info_from_vbios(smu);
 877                 if (ret)
 878                         return ret;
 879
 880                 /*
 881                  * check if the format_revision in vbios is up to pptable header
 882                  * version, and the structure size is not 0.
 883                  */
 884                 ret = smu_check_pptable(smu);
 885                 if (ret)
 886                         return ret;
 887
 888                 /*
 889                  * allocate vram bos to store smc table contents.
 890                  */
 891                 ret = smu_init_fb_allocations(smu);
 892                 if (ret)
 893                         return ret;
 894
 895                 /*
 896                  * Parse pptable format and fill PPTable_t smc_pptable to
 897                  * smu_table_context structure. And read the smc_dpm_table from vbios,
 898                  * then fill it into smc_pptable.
 899                  */
 900                 ret = smu_parse_pptable(smu);
 901                 if (ret)
 902                         return ret;
 903
 904                 /*
 905                  * Send msg GetDriverIfVersion to check if the return value is equal
 906                  * with DRIVER_IF_VERSION of smc header.
 907                  */
 908                 ret = smu_check_fw_version(smu);
 909                 if (ret)
 910                         return ret;
 911         }
 912
 913         /*
 914          * Copy pptable bo in the vram to smc with SMU MSGs such as
 915          * SetDriverDramAddr and TransferTableDram2Smu.
 916          */
 917         ret = smu_write_pptable(smu);
 918         if (ret)
 919                 return ret;
 920
 921         /* issue RunAfllBtc msg */
 922         ret = smu_run_afll_btc(smu);
 923         if (ret)
 924                 return ret;
 925
 926         ret = smu_feature_set_allowed_mask(smu);
 927         if (ret)
 928                 return ret;
 929
 930         ret = smu_system_features_control(smu, true);
 931         if (ret)
 932                 return ret;
 933
 934         ret = smu_override_pcie_parameters(smu);
 935         if (ret)
 936                 return ret;
 937
 938         ret = smu_notify_display_change(smu);
 939         if (ret)
 940                 return ret;
 941
 942         /*
 943          * Set min deep sleep dce fclk with bootup value from vbios via
 944          * SetMinDeepSleepDcefclk MSG.
 945          */
 946         ret = smu_set_min_dcef_deep_sleep(smu);
 947         if (ret)
 948                 return ret;
 949
 950         /*
 951          * Set initialized values (get from vbios) to dpm tables context such as
 952          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 953          * type of clks.
 954          */
 955         if (initialize) {
 956                 ret = smu_populate_smc_pptable(smu);
 957                 if (ret)
 958                         return ret;
 959
 960                 ret = smu_init_max_sustainable_clocks(smu);
 961                 if (ret)
 962                         return ret;
 963         }
 964
 965         ret = smu_set_default_od_settings(smu, initialize);
 966         if (ret)
 967                 return ret;
 968
 969         if (initialize) {
 970                 ret = smu_populate_umd_state_clk(smu);
 971                 if (ret)
 972                         return ret;
 973
 974                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
 975                 if (ret)
 976                         return ret;
 977         }
 978
 979         /*
 980          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 981          */
 982         ret = smu_set_tool_table_location(smu);
 983
 984         if (!smu_is_dpm_running(smu))
 985                 pr_info("dpm has been disabled\n");
 986
 987         return ret;
 988 }
 989
 990 /**
 991  * smu_alloc_memory_pool - allocate memory pool in the system memory
 992  *
 993  * @smu: amdgpu_device pointer
 994  *
 995  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 996  * and DramLogSetDramAddr can notify it changed.
 997  *
 998  * Returns 0 on success, error on failure.
 999  */
1000 static int smu_alloc_memory_pool(struct smu_context *smu)
1001 {
1002         struct amdgpu_device *adev = smu->adev;
1003         struct smu_table_context *smu_table = &smu->smu_table;
1004         struct smu_table *memory_pool = &smu_table->memory_pool;
1005         uint64_t pool_size = smu->pool_size;
1006         int ret = 0;
1007
1008         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1009                 return ret;
1010
1011         memory_pool->size = pool_size;
1012         memory_pool->align = PAGE_SIZE;
1013         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1014
1015         switch (pool_size) {
1016         case SMU_MEMORY_POOL_SIZE_256_MB:
1017         case SMU_MEMORY_POOL_SIZE_512_MB:
1018         case SMU_MEMORY_POOL_SIZE_1_GB:
1019         case SMU_MEMORY_POOL_SIZE_2_GB:
1020                 ret = amdgpu_bo_create_kernel(adev,
1021                                               memory_pool->size,
1022                                               memory_pool->align,
1023                                               memory_pool->domain,
1024                                               &memory_pool->bo,
1025                                               &memory_pool->mc_address,
1026                                               &memory_pool->cpu_addr);
1027                 break;
1028         default:
1029                 break;
1030         }
1031
1032         return ret;
1033 }
1034
1035 static int smu_free_memory_pool(struct smu_context *smu)
1036 {
1037         struct smu_table_context *smu_table = &smu->smu_table;
1038         struct smu_table *memory_pool = &smu_table->memory_pool;
1039         int ret = 0;
1040
1041         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1042                 return ret;
1043
1044         amdgpu_bo_free_kernel(&memory_pool->bo,
1045                               &memory_pool->mc_address,
1046                               &memory_pool->cpu_addr);
1047
1048         memset(memory_pool, 0, sizeof(struct smu_table));
1049
1050         return ret;
1051 }
1052
1053 static int smu_hw_init(void *handle)
1054 {
1055         int ret;
1056         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1057         struct smu_context *smu = &adev->smu;
1058
1059         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1060                 ret = smu_check_fw_status(smu);
1061                 if (ret) {
1062                         pr_err("SMC firmware status is not correct\n");
1063                         return ret;
1064                 }
1065         }
1066
1067         ret = smu_feature_init_dpm(smu);
1068         if (ret)
1069                 goto failed;
1070
1071         ret = smu_smc_table_hw_init(smu, true);
1072         if (ret)
1073                 goto failed;
1074
1075         ret = smu_alloc_memory_pool(smu);
1076         if (ret)
1077                 goto failed;
1078
1079         /*
1080          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1081          * pool location.
1082          */
1083         ret = smu_notify_memory_pool_location(smu);
1084         if (ret)
1085                 goto failed;
1086
1087         ret = smu_start_thermal_control(smu);
1088         if (ret)
1089                 goto failed;
1090
1091         ret = smu_register_irq_handler(smu);
1092         if (ret)
1093                 goto failed;
1094
1095         if (!smu->pm_enabled)
1096                 adev->pm.dpm_enabled = false;
1097         else
1098                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1099
1100         pr_info("SMU is initialized successfully!\n");
1101
1102         return 0;
1103
1104 failed:
1105         return ret;
1106 }
1107
1108 static int smu_hw_fini(void *handle)
1109 {
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111         struct smu_context *smu = &adev->smu;
1112         struct smu_table_context *table_context = &smu->smu_table;
1113         int ret = 0;
1114
1115         kfree(table_context->driver_pptable);
1116         table_context->driver_pptable = NULL;
1117
1118         kfree(table_context->max_sustainable_clocks);
1119         table_context->max_sustainable_clocks = NULL;
1120
1121         kfree(table_context->overdrive_table);
1122         table_context->overdrive_table = NULL;
1123
1124         kfree(smu->irq_source);
1125         smu->irq_source = NULL;
1126
1127         ret = smu_fini_fb_allocations(smu);
1128         if (ret)
1129                 return ret;
1130
1131         ret = smu_free_memory_pool(smu);
1132         if (ret)
1133                 return ret;
1134
1135         return 0;
1136 }
1137
1138 int smu_reset(struct smu_context *smu)
1139 {
1140         struct amdgpu_device *adev = smu->adev;
1141         int ret = 0;
1142
1143         ret = smu_hw_fini(adev);
1144         if (ret)
1145                 return ret;
1146
1147         ret = smu_hw_init(adev);
1148         if (ret)
1149                 return ret;
1150
1151         return ret;
1152 }
1153
1154 static int smu_suspend(void *handle)
1155 {
1156         int ret;
1157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158         struct smu_context *smu = &adev->smu;
1159         bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1160
1161         ret = smu_system_features_control(smu, false);
1162         if (ret)
1163                 return ret;
1164
1165         if (adev->in_gpu_reset && baco_feature_is_enabled) {
1166                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1167                 if (ret) {
1168                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1169                         return ret;
1170                 }
1171         }
1172
1173         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1174
1175         if (adev->asic_type >= CHIP_NAVI10 &&
1176             adev->gfx.rlc.funcs->stop)
1177                 adev->gfx.rlc.funcs->stop(adev);
1178
1179         return 0;
1180 }
1181
1182 static int smu_resume(void *handle)
1183 {
1184         int ret;
1185         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186         struct smu_context *smu = &adev->smu;
1187
1188         pr_info("SMU is resuming...\n");
1189
1190         mutex_lock(&smu->mutex);
1191
1192         ret = smu_smc_table_hw_init(smu, false);
1193         if (ret)
1194                 goto failed;
1195
1196         ret = smu_start_thermal_control(smu);
1197         if (ret)
1198                 goto failed;
1199
1200         mutex_unlock(&smu->mutex);
1201
1202         pr_info("SMU is resumed successfully!\n");
1203
1204         return 0;
1205 failed:
1206         mutex_unlock(&smu->mutex);
1207         return ret;
1208 }
1209
1210 int smu_display_configuration_change(struct smu_context *smu,
1211                                      const struct amd_pp_display_configuration *display_config)
1212 {
1213         int index = 0;
1214         int num_of_active_display = 0;
1215
1216         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1217                 return -EINVAL;
1218
1219         if (!display_config)
1220                 return -EINVAL;
1221
1222         mutex_lock(&smu->mutex);
1223
1224         smu_set_deep_sleep_dcefclk(smu,
1225                                    display_config->min_dcef_deep_sleep_set_clk / 100);
1226
1227         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1228                 if (display_config->displays[index].controller_id != 0)
1229                         num_of_active_display++;
1230         }
1231
1232         smu_set_active_display_count(smu, num_of_active_display);
1233
1234         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1235                            display_config->cpu_cc6_disable,
1236                            display_config->cpu_pstate_disable,
1237                            display_config->nb_pstate_switch_disable);
1238
1239         mutex_unlock(&smu->mutex);
1240
1241         return 0;
1242 }
1243
1244 static int smu_get_clock_info(struct smu_context *smu,
1245                               struct smu_clock_info *clk_info,
1246                               enum smu_perf_level_designation designation)
1247 {
1248         int ret;
1249         struct smu_performance_level level = {0};
1250
1251         if (!clk_info)
1252                 return -EINVAL;
1253
1254         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1255         if (ret)
1256                 return -EINVAL;
1257
1258         clk_info->min_mem_clk = level.memory_clock;
1259         clk_info->min_eng_clk = level.core_clock;
1260         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1261
1262         ret = smu_get_perf_level(smu, designation, &level);
1263         if (ret)
1264                 return -EINVAL;
1265
1266         clk_info->min_mem_clk = level.memory_clock;
1267         clk_info->min_eng_clk = level.core_clock;
1268         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1269
1270         return 0;
1271 }
1272
1273 int smu_get_current_clocks(struct smu_context *smu,
1274                            struct amd_pp_clock_info *clocks)
1275 {
1276         struct amd_pp_simple_clock_info simple_clocks = {0};
1277         struct smu_clock_info hw_clocks;
1278         int ret = 0;
1279
1280         if (!is_support_sw_smu(smu->adev))
1281                 return -EINVAL;
1282
1283         mutex_lock(&smu->mutex);
1284
1285         smu_get_dal_power_level(smu, &simple_clocks);
1286
1287         if (smu->support_power_containment)
1288                 ret = smu_get_clock_info(smu, &hw_clocks,
1289                                          PERF_LEVEL_POWER_CONTAINMENT);
1290         else
1291                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1292
1293         if (ret) {
1294                 pr_err("Error in smu_get_clock_info\n");
1295                 goto failed;
1296         }
1297
1298         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1299         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1300         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1301         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1302         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1303         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1304         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1305         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1306
1307         if (simple_clocks.level == 0)
1308                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1309         else
1310                 clocks->max_clocks_state = simple_clocks.level;
1311
1312         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1313                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1314                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1315         }
1316
1317 failed:
1318         mutex_unlock(&smu->mutex);
1319         return ret;
1320 }
1321
1322 static int smu_set_clockgating_state(void *handle,
1323                                      enum amd_clockgating_state state)
1324 {
1325         return 0;
1326 }
1327
1328 static int smu_set_powergating_state(void *handle,
1329                                      enum amd_powergating_state state)
1330 {
1331         return 0;
1332 }
1333
1334 static int smu_enable_umd_pstate(void *handle,
1335                       enum amd_dpm_forced_level *level)
1336 {
1337         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1338                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1339                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1340                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1341
1342         struct smu_context *smu = (struct smu_context*)(handle);
1343         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1344         if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1345                 return -EINVAL;
1346
1347         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1348                 /* enter umd pstate, save current level, disable gfx cg*/
1349                 if (*level & profile_mode_mask) {
1350                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1351                         smu_dpm_ctx->enable_umd_pstate = true;
1352                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1353                                                                AMD_IP_BLOCK_TYPE_GFX,
1354                                                                AMD_CG_STATE_UNGATE);
1355                         amdgpu_device_ip_set_powergating_state(smu->adev,
1356                                                                AMD_IP_BLOCK_TYPE_GFX,
1357                                                                AMD_PG_STATE_UNGATE);
1358                 }
1359         } else {
1360                 /* exit umd pstate, restore level, enable gfx cg*/
1361                 if (!(*level & profile_mode_mask)) {
1362                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1363                                 *level = smu_dpm_ctx->saved_dpm_level;
1364                         smu_dpm_ctx->enable_umd_pstate = false;
1365                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1366                                                                AMD_IP_BLOCK_TYPE_GFX,
1367                                                                AMD_CG_STATE_GATE);
1368                         amdgpu_device_ip_set_powergating_state(smu->adev,
1369                                                                AMD_IP_BLOCK_TYPE_GFX,
1370                                                                AMD_PG_STATE_GATE);
1371                 }
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1378 {
1379         int ret = 0;
1380         uint32_t sclk_mask, mclk_mask, soc_mask;
1381
1382         switch (level) {
1383         case AMD_DPM_FORCED_LEVEL_HIGH:
1384                 ret = smu_force_dpm_limit_value(smu, true);
1385                 break;
1386         case AMD_DPM_FORCED_LEVEL_LOW:
1387                 ret = smu_force_dpm_limit_value(smu, false);
1388                 break;
1389         case AMD_DPM_FORCED_LEVEL_AUTO:
1390         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1391                 ret = smu_unforce_dpm_levels(smu);
1392                 break;
1393         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1394         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1395         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1396                 ret = smu_get_profiling_clk_mask(smu, level,
1397                                                  &sclk_mask,
1398                                                  &mclk_mask,
1399                                                  &soc_mask);
1400                 if (ret)
1401                         return ret;
1402                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1403                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1404                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1405                 break;
1406         case AMD_DPM_FORCED_LEVEL_MANUAL:
1407         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1408         default:
1409                 break;
1410         }
1411         return ret;
1412 }
1413
1414 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1415                                    enum amd_dpm_forced_level level,
1416                                    bool skip_display_settings)
1417 {
1418         int ret = 0;
1419         int index = 0;
1420         long workload;
1421         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1422
1423         if (!smu->pm_enabled)
1424                 return -EINVAL;
1425         if (!skip_display_settings) {
1426                 ret = smu_display_config_changed(smu);
1427                 if (ret) {
1428                         pr_err("Failed to change display config!");
1429                         return ret;
1430                 }
1431         }
1432
1433         if (!smu->pm_enabled)
1434                 return -EINVAL;
1435         ret = smu_apply_clocks_adjust_rules(smu);
1436         if (ret) {
1437                 pr_err("Failed to apply clocks adjust rules!");
1438                 return ret;
1439         }
1440
1441         if (!skip_display_settings) {
1442                 ret = smu_notify_smc_dispaly_config(smu);
1443                 if (ret) {
1444                         pr_err("Failed to notify smc display config!");
1445                         return ret;
1446                 }
1447         }
1448
1449         if (smu_dpm_ctx->dpm_level != level) {
1450                 ret = smu_asic_set_performance_level(smu, level);
1451                 if (ret) {
1452                         ret = smu_default_set_performance_level(smu, level);
1453                 }
1454                 if (!ret)
1455                         smu_dpm_ctx->dpm_level = level;
1456         }
1457
1458         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1459                 index = fls(smu->workload_mask);
1460                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1461                 workload = smu->workload_setting[index];
1462
1463                 if (smu->power_profile_mode != workload)
1464                         smu_set_power_profile_mode(smu, &workload, 0);
1465         }
1466
1467         return ret;
1468 }
1469
1470 int smu_handle_task(struct smu_context *smu,
1471                     enum amd_dpm_forced_level level,
1472                     enum amd_pp_task task_id)
1473 {
1474         int ret = 0;
1475
1476         switch (task_id) {
1477         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1478                 ret = smu_pre_display_config_changed(smu);
1479                 if (ret)
1480                         return ret;
1481                 ret = smu_set_cpu_power_state(smu);
1482                 if (ret)
1483                         return ret;
1484                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1485                 break;
1486         case AMD_PP_TASK_COMPLETE_INIT:
1487         case AMD_PP_TASK_READJUST_POWER_STATE:
1488                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1489                 break;
1490         default:
1491                 break;
1492         }
1493
1494         return ret;
1495 }
1496
1497 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1498 {
1499         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1500         enum amd_dpm_forced_level level;
1501
1502         if (!smu_dpm_ctx->dpm_context)
1503                 return -EINVAL;
1504
1505         mutex_lock(&(smu->mutex));
1506         level = smu_dpm_ctx->dpm_level;
1507         mutex_unlock(&(smu->mutex));
1508
1509         return level;
1510 }
1511
1512 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1513 {
1514         int ret = 0;
1515         int i;
1516         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1517
1518         if (!smu_dpm_ctx->dpm_context)
1519                 return -EINVAL;
1520
1521         for (i = 0; i < smu->adev->num_ip_blocks; i++) {
1522                 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
1523                         break;
1524         }
1525
1526
1527         smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
1528         ret = smu_handle_task(smu, level,
1529                               AMD_PP_TASK_READJUST_POWER_STATE);
1530         if (ret)
1531                 return ret;
1532
1533         mutex_lock(&smu->mutex);
1534         smu_dpm_ctx->dpm_level = level;
1535         mutex_unlock(&smu->mutex);
1536
1537         return ret;
1538 }
1539
1540 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1541 {
1542         int ret = 0;
1543
1544         mutex_lock(&smu->mutex);
1545         ret = smu_init_display_count(smu, count);
1546         mutex_unlock(&smu->mutex);
1547
1548         return ret;
1549 }
1550
1551 const struct amd_ip_funcs smu_ip_funcs = {
1552         .name = "smu",
1553         .early_init = smu_early_init,
1554         .late_init = smu_late_init,
1555         .sw_init = smu_sw_init,
1556         .sw_fini = smu_sw_fini,
1557         .hw_init = smu_hw_init,
1558         .hw_fini = smu_hw_fini,
1559         .suspend = smu_suspend,
1560         .resume = smu_resume,
1561         .is_idle = NULL,
1562         .check_soft_reset = NULL,
1563         .wait_for_idle = NULL,
1564         .soft_reset = NULL,
1565         .set_clockgating_state = smu_set_clockgating_state,
1566         .set_powergating_state = smu_set_powergating_state,
1567         .enable_umd_pstate = smu_enable_umd_pstate,
1568 };
1569
1570 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1571 {
1572         .type = AMD_IP_BLOCK_TYPE_SMC,
1573         .major = 11,
1574         .minor = 0,
1575         .rev = 0,
1576         .funcs = &smu_ip_funcs,
1577 };