2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "soc15_common.h"
30 #include "smu_v11_0.h"
31 #include "smu_v12_0.h"
34 #include "vega20_ppt.h"
35 #include "arcturus_ppt.h"
36 #include "navi10_ppt.h"
37 #include "renoir_ppt.h"
39 #undef __SMU_DUMMY_MAP
40 #define __SMU_DUMMY_MAP(type) #type
41 static const char* __smu_message_names[] = {
45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
47 if (type < 0 || type >= SMU_MSG_MAX_COUNT)
48 return "unknown smu message";
49 return __smu_message_names[type];
52 #undef __SMU_DUMMY_MAP
53 #define __SMU_DUMMY_MAP(fea) #fea
54 static const char* __smu_feature_names[] = {
58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
60 if (feature < 0 || feature >= SMU_FEATURE_COUNT)
61 return "unknown smu feature";
62 return __smu_feature_names[feature];
65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
69 uint32_t feature_mask[2] = { 0 };
70 int32_t feature_index = 0;
72 uint32_t sort_feature[SMU_FEATURE_COUNT];
73 uint64_t hw_feature_count = 0;
75 mutex_lock(&smu->mutex);
77 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
81 size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
82 feature_mask[1], feature_mask[0]);
84 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
85 feature_index = smu_feature_get_index(smu, i);
86 if (feature_index < 0)
88 sort_feature[feature_index] = i;
92 for (i = 0; i < hw_feature_count; i++) {
93 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
95 smu_get_feature_name(smu, sort_feature[i]),
97 !!smu_feature_is_enabled(smu, sort_feature[i]) ?
98 "enabled" : "disabled");
102 mutex_unlock(&smu->mutex);
107 static int smu_feature_update_enable_state(struct smu_context *smu,
108 uint64_t feature_mask,
111 struct smu_feature *feature = &smu->smu_feature;
112 uint32_t feature_low = 0, feature_high = 0;
115 if (!smu->pm_enabled)
118 feature_low = (feature_mask >> 0 ) & 0xffffffff;
119 feature_high = (feature_mask >> 32) & 0xffffffff;
122 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
126 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
131 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
135 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
141 mutex_lock(&feature->mutex);
143 bitmap_or(feature->enabled, feature->enabled,
144 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
146 bitmap_andnot(feature->enabled, feature->enabled,
147 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
148 mutex_unlock(&feature->mutex);
153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
156 uint32_t feature_mask[2] = { 0 };
157 uint64_t feature_2_enabled = 0;
158 uint64_t feature_2_disabled = 0;
159 uint64_t feature_enables = 0;
161 mutex_lock(&smu->mutex);
163 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
167 feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
169 feature_2_enabled = ~feature_enables & new_mask;
170 feature_2_disabled = feature_enables & ~new_mask;
172 if (feature_2_enabled) {
173 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
177 if (feature_2_disabled) {
178 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
184 mutex_unlock(&smu->mutex);
189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
193 if (!if_version && !smu_version)
197 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
201 ret = smu_read_smc_arg(smu, if_version);
207 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
211 ret = smu_read_smc_arg(smu, smu_version);
219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
220 uint32_t min, uint32_t max)
224 if (min <= 0 && max <= 0)
227 if (!smu_clk_dpm_is_enabled(smu, clk_type))
230 ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
235 uint32_t min, uint32_t max)
237 int ret = 0, clk_id = 0;
240 if (min <= 0 && max <= 0)
243 if (!smu_clk_dpm_is_enabled(smu, clk_type))
246 clk_id = smu_clk_get_index(smu, clk_type);
251 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
252 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
259 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
260 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
271 uint32_t *min, uint32_t *max, bool lock_needed)
273 uint32_t clock_limit;
280 mutex_lock(&smu->mutex);
282 if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
286 clock_limit = smu->smu_table.boot_values.uclk;
290 clock_limit = smu->smu_table.boot_values.gfxclk;
293 clock_limit = smu->smu_table.boot_values.socclk;
300 /* clock in Mhz unit */
302 *min = clock_limit / 100;
304 *max = clock_limit / 100;
307 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
308 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
310 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
314 mutex_unlock(&smu->mutex);
319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
320 uint16_t level, uint32_t *value)
322 int ret = 0, clk_id = 0;
328 if (!smu_clk_dpm_is_enabled(smu, clk_type))
331 clk_id = smu_clk_get_index(smu, clk_type);
335 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
337 ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
342 ret = smu_read_smc_arg(smu, ¶m);
346 /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
347 * now, we un-support it */
348 *value = param & 0x7fffffff;
353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
356 return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
359 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
361 enum smu_feature_mask feature_id = 0;
366 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
370 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
373 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
379 if(!smu_feature_is_enabled(smu, feature_id)) {
387 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
389 * @smu: smu_context pointer
390 * @block_type: the IP block to power gate/ungate
391 * @gate: to power gate if true, ungate otherwise
393 * This API uses no smu->mutex lock protection due to:
394 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
395 * This is guarded to be race condition free by the caller.
396 * 2. Or get called on user setting request of power_dpm_force_performance_level.
397 * Under this case, the smu->mutex lock protection is already enforced on
398 * the parent API smu_force_performance_level of the call path.
400 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
405 switch (block_type) {
406 case AMD_IP_BLOCK_TYPE_UVD:
407 ret = smu_dpm_set_uvd_enable(smu, gate);
409 case AMD_IP_BLOCK_TYPE_VCE:
410 ret = smu_dpm_set_vce_enable(smu, gate);
412 case AMD_IP_BLOCK_TYPE_GFX:
413 ret = smu_gfx_off_control(smu, gate);
415 case AMD_IP_BLOCK_TYPE_SDMA:
416 ret = smu_powergate_sdma(smu, gate);
418 case AMD_IP_BLOCK_TYPE_JPEG:
419 ret = smu_dpm_set_jpeg_enable(smu, gate);
428 int smu_get_power_num_states(struct smu_context *smu,
429 struct pp_states_info *state_info)
434 /* not support power state */
435 memset(state_info, 0, sizeof(struct pp_states_info));
436 state_info->nums = 1;
437 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
442 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
443 void *data, uint32_t *size)
445 struct smu_power_context *smu_power = &smu->smu_power;
446 struct smu_power_gate *power_gate = &smu_power->power_gate;
453 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
454 *((uint32_t *)data) = smu->pstate_sclk;
457 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
458 *((uint32_t *)data) = smu->pstate_mclk;
461 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
462 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
465 case AMDGPU_PP_SENSOR_UVD_POWER:
466 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
469 case AMDGPU_PP_SENSOR_VCE_POWER:
470 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
473 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
474 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
488 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
489 void *table_data, bool drv2smu)
491 struct smu_table_context *smu_table = &smu->smu_table;
492 struct amdgpu_device *adev = smu->adev;
493 struct smu_table *table = NULL;
495 int table_id = smu_table_get_index(smu, table_index);
497 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
500 table = &smu_table->tables[table_index];
503 memcpy(table->cpu_addr, table_data, table->size);
505 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
506 upper_32_bits(table->mc_address));
509 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
510 lower_32_bits(table->mc_address));
513 ret = smu_send_smc_msg_with_param(smu, drv2smu ?
514 SMU_MSG_TransferTableDram2Smu :
515 SMU_MSG_TransferTableSmu2Dram,
516 table_id | ((argument & 0xFFFF) << 16));
520 /* flush hdp cache */
521 adev->nbio.funcs->hdp_flush(adev, NULL);
524 memcpy(table_data, table->cpu_addr, table->size);
529 bool is_support_sw_smu(struct amdgpu_device *adev)
531 if (adev->asic_type == CHIP_VEGA20)
532 return (amdgpu_dpm == 2) ? true : false;
533 else if (adev->asic_type >= CHIP_ARCTURUS) {
534 if (amdgpu_sriov_vf(adev))
542 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
544 if (!is_support_sw_smu(adev))
547 if (adev->asic_type == CHIP_VEGA20)
553 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
555 struct smu_table_context *smu_table = &smu->smu_table;
556 uint32_t powerplay_table_size;
558 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
561 mutex_lock(&smu->mutex);
563 if (smu_table->hardcode_pptable)
564 *table = smu_table->hardcode_pptable;
566 *table = smu_table->power_play_table;
568 powerplay_table_size = smu_table->power_play_table_size;
570 mutex_unlock(&smu->mutex);
572 return powerplay_table_size;
575 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
577 struct smu_table_context *smu_table = &smu->smu_table;
578 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
581 if (!smu->pm_enabled)
583 if (header->usStructureSize != size) {
584 pr_err("pp table size not matched !\n");
588 mutex_lock(&smu->mutex);
589 if (!smu_table->hardcode_pptable)
590 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
591 if (!smu_table->hardcode_pptable) {
596 memcpy(smu_table->hardcode_pptable, buf, size);
597 smu_table->power_play_table = smu_table->hardcode_pptable;
598 smu_table->power_play_table_size = size;
601 * Special hw_fini action(for Navi1x, the DPMs disablement will be
602 * skipped) may be needed for custom pptable uploading.
604 smu->uploading_custom_pp_table = true;
606 ret = smu_reset(smu);
608 pr_info("smu reset failed, ret = %d\n", ret);
610 smu->uploading_custom_pp_table = false;
613 mutex_unlock(&smu->mutex);
617 int smu_feature_init_dpm(struct smu_context *smu)
619 struct smu_feature *feature = &smu->smu_feature;
621 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
623 if (!smu->pm_enabled)
625 mutex_lock(&feature->mutex);
626 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
627 mutex_unlock(&feature->mutex);
629 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
634 mutex_lock(&feature->mutex);
635 bitmap_or(feature->allowed, feature->allowed,
636 (unsigned long *)allowed_feature_mask,
637 feature->feature_num);
638 mutex_unlock(&feature->mutex);
644 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
646 struct amdgpu_device *adev = smu->adev;
647 struct smu_feature *feature = &smu->smu_feature;
651 if (adev->flags & AMD_IS_APU)
654 feature_id = smu_feature_get_index(smu, mask);
658 WARN_ON(feature_id > feature->feature_num);
660 mutex_lock(&feature->mutex);
661 ret = test_bit(feature_id, feature->enabled);
662 mutex_unlock(&feature->mutex);
667 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
670 struct smu_feature *feature = &smu->smu_feature;
673 feature_id = smu_feature_get_index(smu, mask);
677 WARN_ON(feature_id > feature->feature_num);
679 return smu_feature_update_enable_state(smu,
684 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
686 struct smu_feature *feature = &smu->smu_feature;
690 feature_id = smu_feature_get_index(smu, mask);
694 WARN_ON(feature_id > feature->feature_num);
696 mutex_lock(&feature->mutex);
697 ret = test_bit(feature_id, feature->supported);
698 mutex_unlock(&feature->mutex);
703 int smu_feature_set_supported(struct smu_context *smu,
704 enum smu_feature_mask mask,
707 struct smu_feature *feature = &smu->smu_feature;
711 feature_id = smu_feature_get_index(smu, mask);
715 WARN_ON(feature_id > feature->feature_num);
717 mutex_lock(&feature->mutex);
719 test_and_set_bit(feature_id, feature->supported);
721 test_and_clear_bit(feature_id, feature->supported);
722 mutex_unlock(&feature->mutex);
727 static int smu_set_funcs(struct amdgpu_device *adev)
729 struct smu_context *smu = &adev->smu;
731 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
732 smu->od_enabled = true;
734 switch (adev->asic_type) {
736 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
737 vega20_set_ppt_funcs(smu);
742 navi10_set_ppt_funcs(smu);
745 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
746 arcturus_set_ppt_funcs(smu);
747 /* OD is not supported on Arcturus */
748 smu->od_enabled =false;
751 renoir_set_ppt_funcs(smu);
760 static int smu_early_init(void *handle)
762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
763 struct smu_context *smu = &adev->smu;
766 smu->pm_enabled = !!amdgpu_dpm;
768 mutex_init(&smu->mutex);
770 return smu_set_funcs(adev);
773 static int smu_late_init(void *handle)
775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
776 struct smu_context *smu = &adev->smu;
778 if (!smu->pm_enabled)
781 smu_handle_task(&adev->smu,
782 smu->smu_dpm.dpm_level,
783 AMD_PP_TASK_COMPLETE_INIT,
789 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
790 uint16_t *size, uint8_t *frev, uint8_t *crev,
793 struct amdgpu_device *adev = smu->adev;
796 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
797 size, frev, crev, &data_start))
800 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
805 static int smu_initialize_pptable(struct smu_context *smu)
811 static int smu_smc_table_sw_init(struct smu_context *smu)
815 ret = smu_initialize_pptable(smu);
817 pr_err("Failed to init smu_initialize_pptable!\n");
822 * Create smu_table structure, and init smc tables such as
823 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
825 ret = smu_init_smc_tables(smu);
827 pr_err("Failed to init smc tables!\n");
832 * Create smu_power_context structure, and allocate smu_dpm_context and
833 * context size to fill the smu_power_context data.
835 ret = smu_init_power(smu);
837 pr_err("Failed to init smu_init_power!\n");
844 static int smu_smc_table_sw_fini(struct smu_context *smu)
848 ret = smu_fini_smc_tables(smu);
850 pr_err("Failed to smu_fini_smc_tables!\n");
857 static int smu_sw_init(void *handle)
859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
860 struct smu_context *smu = &adev->smu;
863 smu->pool_size = adev->pm.smu_prv_buffer_size;
864 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
865 mutex_init(&smu->smu_feature.mutex);
866 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
867 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
868 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
870 mutex_init(&smu->smu_baco.mutex);
871 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
872 smu->smu_baco.platform_support = false;
874 mutex_init(&smu->sensor_lock);
875 mutex_init(&smu->metrics_lock);
877 smu->watermarks_bitmap = 0;
878 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
879 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
881 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
882 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
883 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
884 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
885 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
886 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
887 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
888 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
890 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
891 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
892 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
893 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
894 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
895 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
896 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
897 smu->display_config = &adev->pm.pm_display_cfg;
899 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
900 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
901 ret = smu_init_microcode(smu);
903 pr_err("Failed to load smu firmware!\n");
907 ret = smu_smc_table_sw_init(smu);
909 pr_err("Failed to sw init smc table!\n");
913 ret = smu_register_irq_handler(smu);
915 pr_err("Failed to register smc irq handler!\n");
922 static int smu_sw_fini(void *handle)
924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
925 struct smu_context *smu = &adev->smu;
928 kfree(smu->irq_source);
929 smu->irq_source = NULL;
931 ret = smu_smc_table_sw_fini(smu);
933 pr_err("Failed to sw fini smc table!\n");
937 ret = smu_fini_power(smu);
939 pr_err("Failed to init smu_fini_power!\n");
946 static int smu_init_fb_allocations(struct smu_context *smu)
948 struct amdgpu_device *adev = smu->adev;
949 struct smu_table_context *smu_table = &smu->smu_table;
950 struct smu_table *tables = smu_table->tables;
953 for (i = 0; i < SMU_TABLE_COUNT; i++) {
954 if (tables[i].size == 0)
956 ret = amdgpu_bo_create_kernel(adev,
961 &tables[i].mc_address,
962 &tables[i].cpu_addr);
970 if (tables[i].size == 0)
972 amdgpu_bo_free_kernel(&tables[i].bo,
973 &tables[i].mc_address,
974 &tables[i].cpu_addr);
980 static int smu_fini_fb_allocations(struct smu_context *smu)
982 struct smu_table_context *smu_table = &smu->smu_table;
983 struct smu_table *tables = smu_table->tables;
989 for (i = 0; i < SMU_TABLE_COUNT; i++) {
990 if (tables[i].size == 0)
992 amdgpu_bo_free_kernel(&tables[i].bo,
993 &tables[i].mc_address,
994 &tables[i].cpu_addr);
1000 static int smu_smc_table_hw_init(struct smu_context *smu,
1003 struct amdgpu_device *adev = smu->adev;
1006 if (smu_is_dpm_running(smu) && adev->in_suspend) {
1007 pr_info("dpm has been enabled\n");
1011 if (adev->asic_type != CHIP_ARCTURUS) {
1012 ret = smu_init_display_count(smu, 0);
1018 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1019 ret = smu_get_vbios_bootup_values(smu);
1023 ret = smu_setup_pptable(smu);
1027 ret = smu_get_clk_info_from_vbios(smu);
1032 * check if the format_revision in vbios is up to pptable header
1033 * version, and the structure size is not 0.
1035 ret = smu_check_pptable(smu);
1040 * allocate vram bos to store smc table contents.
1042 ret = smu_init_fb_allocations(smu);
1047 * Parse pptable format and fill PPTable_t smc_pptable to
1048 * smu_table_context structure. And read the smc_dpm_table from vbios,
1049 * then fill it into smc_pptable.
1051 ret = smu_parse_pptable(smu);
1056 * Send msg GetDriverIfVersion to check if the return value is equal
1057 * with DRIVER_IF_VERSION of smc header.
1059 ret = smu_check_fw_version(smu);
1064 /* smu_dump_pptable(smu); */
1067 * Copy pptable bo in the vram to smc with SMU MSGs such as
1068 * SetDriverDramAddr and TransferTableDram2Smu.
1070 ret = smu_write_pptable(smu);
1074 /* issue Run*Btc msg */
1075 ret = smu_run_btc(smu);
1079 ret = smu_feature_set_allowed_mask(smu);
1083 ret = smu_system_features_control(smu, true);
1087 if (adev->asic_type != CHIP_ARCTURUS) {
1088 ret = smu_notify_display_change(smu);
1093 * Set min deep sleep dce fclk with bootup value from vbios via
1094 * SetMinDeepSleepDcefclk MSG.
1096 ret = smu_set_min_dcef_deep_sleep(smu);
1102 * Set initialized values (get from vbios) to dpm tables context such as
1103 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1107 ret = smu_populate_smc_tables(smu);
1111 ret = smu_init_max_sustainable_clocks(smu);
1116 if (adev->asic_type != CHIP_ARCTURUS) {
1117 ret = smu_override_pcie_parameters(smu);
1122 ret = smu_set_default_od_settings(smu, initialize);
1127 ret = smu_populate_umd_state_clk(smu);
1131 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1137 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1139 ret = smu_set_tool_table_location(smu);
1141 if (!smu_is_dpm_running(smu))
1142 pr_info("dpm has been disabled\n");
1148 * smu_alloc_memory_pool - allocate memory pool in the system memory
1150 * @smu: amdgpu_device pointer
1152 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1153 * and DramLogSetDramAddr can notify it changed.
1155 * Returns 0 on success, error on failure.
1157 static int smu_alloc_memory_pool(struct smu_context *smu)
1159 struct amdgpu_device *adev = smu->adev;
1160 struct smu_table_context *smu_table = &smu->smu_table;
1161 struct smu_table *memory_pool = &smu_table->memory_pool;
1162 uint64_t pool_size = smu->pool_size;
1165 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1168 memory_pool->size = pool_size;
1169 memory_pool->align = PAGE_SIZE;
1170 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1172 switch (pool_size) {
1173 case SMU_MEMORY_POOL_SIZE_256_MB:
1174 case SMU_MEMORY_POOL_SIZE_512_MB:
1175 case SMU_MEMORY_POOL_SIZE_1_GB:
1176 case SMU_MEMORY_POOL_SIZE_2_GB:
1177 ret = amdgpu_bo_create_kernel(adev,
1180 memory_pool->domain,
1182 &memory_pool->mc_address,
1183 &memory_pool->cpu_addr);
1192 static int smu_free_memory_pool(struct smu_context *smu)
1194 struct smu_table_context *smu_table = &smu->smu_table;
1195 struct smu_table *memory_pool = &smu_table->memory_pool;
1197 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1200 amdgpu_bo_free_kernel(&memory_pool->bo,
1201 &memory_pool->mc_address,
1202 &memory_pool->cpu_addr);
1204 memset(memory_pool, 0, sizeof(struct smu_table));
1209 static int smu_start_smc_engine(struct smu_context *smu)
1211 struct amdgpu_device *adev = smu->adev;
1214 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1215 if (adev->asic_type < CHIP_NAVI10) {
1216 if (smu->ppt_funcs->load_microcode) {
1217 ret = smu->ppt_funcs->load_microcode(smu);
1224 if (smu->ppt_funcs->check_fw_status) {
1225 ret = smu->ppt_funcs->check_fw_status(smu);
1227 pr_err("SMC is not ready\n");
1233 static int smu_hw_init(void *handle)
1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237 struct smu_context *smu = &adev->smu;
1239 ret = smu_start_smc_engine(smu);
1241 pr_err("SMU is not ready yet!\n");
1245 if (adev->flags & AMD_IS_APU) {
1246 smu_powergate_sdma(&adev->smu, false);
1247 smu_powergate_vcn(&adev->smu, false);
1248 smu_powergate_jpeg(&adev->smu, false);
1249 smu_set_gfx_cgpg(&adev->smu, true);
1252 if (!smu->pm_enabled)
1255 ret = smu_feature_init_dpm(smu);
1259 ret = smu_smc_table_hw_init(smu, true);
1263 ret = smu_alloc_memory_pool(smu);
1268 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1271 ret = smu_notify_memory_pool_location(smu);
1275 ret = smu_start_thermal_control(smu);
1279 if (!smu->pm_enabled)
1280 adev->pm.dpm_enabled = false;
1282 adev->pm.dpm_enabled = true; /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1284 pr_info("SMU is initialized successfully!\n");
1292 static int smu_stop_dpms(struct smu_context *smu)
1294 return smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
1297 static int smu_hw_fini(void *handle)
1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300 struct smu_context *smu = &adev->smu;
1301 struct smu_table_context *table_context = &smu->smu_table;
1304 if (adev->flags & AMD_IS_APU) {
1305 smu_powergate_sdma(&adev->smu, true);
1306 smu_powergate_vcn(&adev->smu, true);
1307 smu_powergate_jpeg(&adev->smu, true);
1310 ret = smu_stop_thermal_control(smu);
1312 pr_warn("Fail to stop thermal control!\n");
1317 * For custom pptable uploading, skip the DPM features
1318 * disable process on Navi1x ASICs.
1319 * - As the gfx related features are under control of
1320 * RLC on those ASICs. RLC reinitialization will be
1321 * needed to reenable them. That will cost much more
1324 * - SMU firmware can handle the DPM reenablement
1327 if (!smu->uploading_custom_pp_table ||
1328 !((adev->asic_type >= CHIP_NAVI10) &&
1329 (adev->asic_type <= CHIP_NAVI12))) {
1330 ret = smu_stop_dpms(smu);
1332 pr_warn("Fail to stop Dpms!\n");
1337 kfree(table_context->driver_pptable);
1338 table_context->driver_pptable = NULL;
1340 kfree(table_context->max_sustainable_clocks);
1341 table_context->max_sustainable_clocks = NULL;
1343 kfree(table_context->overdrive_table);
1344 table_context->overdrive_table = NULL;
1346 ret = smu_fini_fb_allocations(smu);
1350 ret = smu_free_memory_pool(smu);
1357 int smu_reset(struct smu_context *smu)
1359 struct amdgpu_device *adev = smu->adev;
1362 ret = smu_hw_fini(adev);
1366 ret = smu_hw_init(adev);
1373 static int smu_suspend(void *handle)
1376 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1377 struct smu_context *smu = &adev->smu;
1378 bool baco_feature_is_enabled = false;
1380 if(!(adev->flags & AMD_IS_APU))
1381 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1383 ret = smu_system_features_control(smu, false);
1387 if (baco_feature_is_enabled) {
1388 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1390 pr_warn("set BACO feature enabled failed, return %d\n", ret);
1395 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1397 if (adev->asic_type >= CHIP_NAVI10 &&
1398 adev->gfx.rlc.funcs->stop)
1399 adev->gfx.rlc.funcs->stop(adev);
1401 smu_set_gfx_cgpg(&adev->smu, false);
1406 static int smu_resume(void *handle)
1409 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410 struct smu_context *smu = &adev->smu;
1412 pr_info("SMU is resuming...\n");
1414 ret = smu_start_smc_engine(smu);
1416 pr_err("SMU is not ready yet!\n");
1420 ret = smu_smc_table_hw_init(smu, false);
1424 ret = smu_start_thermal_control(smu);
1429 smu_set_gfx_cgpg(&adev->smu, true);
1431 smu->disable_uclk_switch = 0;
1433 pr_info("SMU is resumed successfully!\n");
1441 int smu_display_configuration_change(struct smu_context *smu,
1442 const struct amd_pp_display_configuration *display_config)
1445 int num_of_active_display = 0;
1447 if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1450 if (!display_config)
1453 mutex_lock(&smu->mutex);
1455 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1456 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1457 display_config->min_dcef_deep_sleep_set_clk / 100);
1459 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1460 if (display_config->displays[index].controller_id != 0)
1461 num_of_active_display++;
1464 smu_set_active_display_count(smu, num_of_active_display);
1466 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1467 display_config->cpu_cc6_disable,
1468 display_config->cpu_pstate_disable,
1469 display_config->nb_pstate_switch_disable);
1471 mutex_unlock(&smu->mutex);
1476 static int smu_get_clock_info(struct smu_context *smu,
1477 struct smu_clock_info *clk_info,
1478 enum smu_perf_level_designation designation)
1481 struct smu_performance_level level = {0};
1486 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1490 clk_info->min_mem_clk = level.memory_clock;
1491 clk_info->min_eng_clk = level.core_clock;
1492 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1494 ret = smu_get_perf_level(smu, designation, &level);
1498 clk_info->min_mem_clk = level.memory_clock;
1499 clk_info->min_eng_clk = level.core_clock;
1500 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1505 int smu_get_current_clocks(struct smu_context *smu,
1506 struct amd_pp_clock_info *clocks)
1508 struct amd_pp_simple_clock_info simple_clocks = {0};
1509 struct smu_clock_info hw_clocks;
1512 if (!is_support_sw_smu(smu->adev))
1515 mutex_lock(&smu->mutex);
1517 smu_get_dal_power_level(smu, &simple_clocks);
1519 if (smu->support_power_containment)
1520 ret = smu_get_clock_info(smu, &hw_clocks,
1521 PERF_LEVEL_POWER_CONTAINMENT);
1523 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1526 pr_err("Error in smu_get_clock_info\n");
1530 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1531 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1532 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1533 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1534 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1535 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1536 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1537 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1539 if (simple_clocks.level == 0)
1540 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1542 clocks->max_clocks_state = simple_clocks.level;
1544 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1545 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1546 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1550 mutex_unlock(&smu->mutex);
1554 static int smu_set_clockgating_state(void *handle,
1555 enum amd_clockgating_state state)
1560 static int smu_set_powergating_state(void *handle,
1561 enum amd_powergating_state state)
1566 static int smu_enable_umd_pstate(void *handle,
1567 enum amd_dpm_forced_level *level)
1569 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1570 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1571 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1572 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1574 struct smu_context *smu = (struct smu_context*)(handle);
1575 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1577 if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1580 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1581 /* enter umd pstate, save current level, disable gfx cg*/
1582 if (*level & profile_mode_mask) {
1583 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1584 smu_dpm_ctx->enable_umd_pstate = true;
1585 amdgpu_device_ip_set_clockgating_state(smu->adev,
1586 AMD_IP_BLOCK_TYPE_GFX,
1587 AMD_CG_STATE_UNGATE);
1588 amdgpu_device_ip_set_powergating_state(smu->adev,
1589 AMD_IP_BLOCK_TYPE_GFX,
1590 AMD_PG_STATE_UNGATE);
1593 /* exit umd pstate, restore level, enable gfx cg*/
1594 if (!(*level & profile_mode_mask)) {
1595 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1596 *level = smu_dpm_ctx->saved_dpm_level;
1597 smu_dpm_ctx->enable_umd_pstate = false;
1598 amdgpu_device_ip_set_clockgating_state(smu->adev,
1599 AMD_IP_BLOCK_TYPE_GFX,
1601 amdgpu_device_ip_set_powergating_state(smu->adev,
1602 AMD_IP_BLOCK_TYPE_GFX,
1610 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1611 enum amd_dpm_forced_level level,
1612 bool skip_display_settings)
1617 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1619 if (!smu->pm_enabled)
1622 if (!skip_display_settings) {
1623 ret = smu_display_config_changed(smu);
1625 pr_err("Failed to change display config!");
1630 ret = smu_apply_clocks_adjust_rules(smu);
1632 pr_err("Failed to apply clocks adjust rules!");
1636 if (!skip_display_settings) {
1637 ret = smu_notify_smc_display_config(smu);
1639 pr_err("Failed to notify smc display config!");
1644 if (smu_dpm_ctx->dpm_level != level) {
1645 ret = smu_asic_set_performance_level(smu, level);
1647 pr_err("Failed to set performance level!");
1651 /* update the saved copy */
1652 smu_dpm_ctx->dpm_level = level;
1655 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1656 index = fls(smu->workload_mask);
1657 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1658 workload = smu->workload_setting[index];
1660 if (smu->power_profile_mode != workload)
1661 smu_set_power_profile_mode(smu, &workload, 0, false);
1667 int smu_handle_task(struct smu_context *smu,
1668 enum amd_dpm_forced_level level,
1669 enum amd_pp_task task_id,
1675 mutex_lock(&smu->mutex);
1678 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1679 ret = smu_pre_display_config_changed(smu);
1682 ret = smu_set_cpu_power_state(smu);
1685 ret = smu_adjust_power_state_dynamic(smu, level, false);
1687 case AMD_PP_TASK_COMPLETE_INIT:
1688 case AMD_PP_TASK_READJUST_POWER_STATE:
1689 ret = smu_adjust_power_state_dynamic(smu, level, true);
1697 mutex_unlock(&smu->mutex);
1702 int smu_switch_power_profile(struct smu_context *smu,
1703 enum PP_SMC_POWER_PROFILE type,
1706 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1710 if (!smu->pm_enabled)
1713 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1716 mutex_lock(&smu->mutex);
1719 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1720 index = fls(smu->workload_mask);
1721 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1722 workload = smu->workload_setting[index];
1724 smu->workload_mask |= (1 << smu->workload_prority[type]);
1725 index = fls(smu->workload_mask);
1726 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1727 workload = smu->workload_setting[index];
1730 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1731 smu_set_power_profile_mode(smu, &workload, 0, false);
1733 mutex_unlock(&smu->mutex);
1738 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1740 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1741 enum amd_dpm_forced_level level;
1743 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1746 mutex_lock(&(smu->mutex));
1747 level = smu_dpm_ctx->dpm_level;
1748 mutex_unlock(&(smu->mutex));
1753 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1755 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1758 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1761 mutex_lock(&smu->mutex);
1763 ret = smu_enable_umd_pstate(smu, &level);
1765 mutex_unlock(&smu->mutex);
1769 ret = smu_handle_task(smu, level,
1770 AMD_PP_TASK_READJUST_POWER_STATE,
1773 mutex_unlock(&smu->mutex);
1778 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1782 mutex_lock(&smu->mutex);
1783 ret = smu_init_display_count(smu, count);
1784 mutex_unlock(&smu->mutex);
1789 int smu_force_clk_levels(struct smu_context *smu,
1790 enum smu_clk_type clk_type,
1794 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1797 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1798 pr_debug("force clock level is for dpm manual mode only.\n");
1803 mutex_lock(&smu->mutex);
1805 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1806 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1809 mutex_unlock(&smu->mutex);
1814 int smu_set_mp1_state(struct smu_context *smu,
1815 enum pp_mp1_state mp1_state)
1821 * The SMC is not fully ready. That may be
1822 * expected as the IP may be masked.
1823 * So, just return without error.
1825 if (!smu->pm_enabled)
1828 mutex_lock(&smu->mutex);
1830 switch (mp1_state) {
1831 case PP_MP1_STATE_SHUTDOWN:
1832 msg = SMU_MSG_PrepareMp1ForShutdown;
1834 case PP_MP1_STATE_UNLOAD:
1835 msg = SMU_MSG_PrepareMp1ForUnload;
1837 case PP_MP1_STATE_RESET:
1838 msg = SMU_MSG_PrepareMp1ForReset;
1840 case PP_MP1_STATE_NONE:
1842 mutex_unlock(&smu->mutex);
1846 /* some asics may not support those messages */
1847 if (smu_msg_get_index(smu, msg) < 0) {
1848 mutex_unlock(&smu->mutex);
1852 ret = smu_send_smc_msg(smu, msg);
1854 pr_err("[PrepareMp1] Failed!\n");
1856 mutex_unlock(&smu->mutex);
1861 int smu_set_df_cstate(struct smu_context *smu,
1862 enum pp_df_cstate state)
1867 * The SMC is not fully ready. That may be
1868 * expected as the IP may be masked.
1869 * So, just return without error.
1871 if (!smu->pm_enabled)
1874 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1877 mutex_lock(&smu->mutex);
1879 ret = smu->ppt_funcs->set_df_cstate(smu, state);
1881 pr_err("[SetDfCstate] failed!\n");
1883 mutex_unlock(&smu->mutex);
1888 int smu_write_watermarks_table(struct smu_context *smu)
1891 struct smu_table_context *smu_table = &smu->smu_table;
1892 struct smu_table *table = NULL;
1894 table = &smu_table->tables[SMU_TABLE_WATERMARKS];
1896 if (!table->cpu_addr)
1899 ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
1905 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1906 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1908 struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1909 void *table = watermarks->cpu_addr;
1911 mutex_lock(&smu->mutex);
1913 if (!smu->disable_watermark &&
1914 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1915 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1916 smu_set_watermarks_table(smu, table, clock_ranges);
1917 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1918 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1921 mutex_unlock(&smu->mutex);
1926 const struct amd_ip_funcs smu_ip_funcs = {
1928 .early_init = smu_early_init,
1929 .late_init = smu_late_init,
1930 .sw_init = smu_sw_init,
1931 .sw_fini = smu_sw_fini,
1932 .hw_init = smu_hw_init,
1933 .hw_fini = smu_hw_fini,
1934 .suspend = smu_suspend,
1935 .resume = smu_resume,
1937 .check_soft_reset = NULL,
1938 .wait_for_idle = NULL,
1940 .set_clockgating_state = smu_set_clockgating_state,
1941 .set_powergating_state = smu_set_powergating_state,
1942 .enable_umd_pstate = smu_enable_umd_pstate,
1945 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1947 .type = AMD_IP_BLOCK_TYPE_SMC,
1951 .funcs = &smu_ip_funcs,
1954 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1956 .type = AMD_IP_BLOCK_TYPE_SMC,
1960 .funcs = &smu_ip_funcs,
1963 int smu_load_microcode(struct smu_context *smu)
1967 mutex_lock(&smu->mutex);
1969 if (smu->ppt_funcs->load_microcode)
1970 ret = smu->ppt_funcs->load_microcode(smu);
1972 mutex_unlock(&smu->mutex);
1977 int smu_check_fw_status(struct smu_context *smu)
1981 mutex_lock(&smu->mutex);
1983 if (smu->ppt_funcs->check_fw_status)
1984 ret = smu->ppt_funcs->check_fw_status(smu);
1986 mutex_unlock(&smu->mutex);
1991 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1995 mutex_lock(&smu->mutex);
1997 if (smu->ppt_funcs->set_gfx_cgpg)
1998 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2000 mutex_unlock(&smu->mutex);
2005 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2009 mutex_lock(&smu->mutex);
2011 if (smu->ppt_funcs->set_fan_speed_rpm)
2012 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2014 mutex_unlock(&smu->mutex);
2019 int smu_get_power_limit(struct smu_context *smu,
2027 mutex_lock(&smu->mutex);
2029 if (smu->ppt_funcs->get_power_limit)
2030 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2033 mutex_unlock(&smu->mutex);
2038 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2042 mutex_lock(&smu->mutex);
2044 if (smu->ppt_funcs->set_power_limit)
2045 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2047 mutex_unlock(&smu->mutex);
2052 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2056 mutex_lock(&smu->mutex);
2058 if (smu->ppt_funcs->print_clk_levels)
2059 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2061 mutex_unlock(&smu->mutex);
2066 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2070 mutex_lock(&smu->mutex);
2072 if (smu->ppt_funcs->get_od_percentage)
2073 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2075 mutex_unlock(&smu->mutex);
2080 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2084 mutex_lock(&smu->mutex);
2086 if (smu->ppt_funcs->set_od_percentage)
2087 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2089 mutex_unlock(&smu->mutex);
2094 int smu_od_edit_dpm_table(struct smu_context *smu,
2095 enum PP_OD_DPM_TABLE_COMMAND type,
2096 long *input, uint32_t size)
2100 mutex_lock(&smu->mutex);
2102 if (smu->ppt_funcs->od_edit_dpm_table)
2103 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2105 mutex_unlock(&smu->mutex);
2110 int smu_read_sensor(struct smu_context *smu,
2111 enum amd_pp_sensors sensor,
2112 void *data, uint32_t *size)
2116 mutex_lock(&smu->mutex);
2118 if (smu->ppt_funcs->read_sensor)
2119 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2121 mutex_unlock(&smu->mutex);
2126 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2130 mutex_lock(&smu->mutex);
2132 if (smu->ppt_funcs->get_power_profile_mode)
2133 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2135 mutex_unlock(&smu->mutex);
2140 int smu_set_power_profile_mode(struct smu_context *smu,
2142 uint32_t param_size,
2148 mutex_lock(&smu->mutex);
2150 if (smu->ppt_funcs->set_power_profile_mode)
2151 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2154 mutex_unlock(&smu->mutex);
2160 int smu_get_fan_control_mode(struct smu_context *smu)
2164 mutex_lock(&smu->mutex);
2166 if (smu->ppt_funcs->get_fan_control_mode)
2167 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2169 mutex_unlock(&smu->mutex);
2174 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2178 mutex_lock(&smu->mutex);
2180 if (smu->ppt_funcs->set_fan_control_mode)
2181 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2183 mutex_unlock(&smu->mutex);
2188 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2192 mutex_lock(&smu->mutex);
2194 if (smu->ppt_funcs->get_fan_speed_percent)
2195 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2197 mutex_unlock(&smu->mutex);
2202 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2206 mutex_lock(&smu->mutex);
2208 if (smu->ppt_funcs->set_fan_speed_percent)
2209 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2211 mutex_unlock(&smu->mutex);
2216 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2220 mutex_lock(&smu->mutex);
2222 if (smu->ppt_funcs->get_fan_speed_rpm)
2223 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2225 mutex_unlock(&smu->mutex);
2230 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2234 mutex_lock(&smu->mutex);
2236 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2237 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2239 mutex_unlock(&smu->mutex);
2244 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2248 mutex_lock(&smu->mutex);
2250 if (smu->ppt_funcs->set_active_display_count)
2251 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2253 mutex_unlock(&smu->mutex);
2258 int smu_get_clock_by_type(struct smu_context *smu,
2259 enum amd_pp_clock_type type,
2260 struct amd_pp_clocks *clocks)
2264 mutex_lock(&smu->mutex);
2266 if (smu->ppt_funcs->get_clock_by_type)
2267 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2269 mutex_unlock(&smu->mutex);
2274 int smu_get_max_high_clocks(struct smu_context *smu,
2275 struct amd_pp_simple_clock_info *clocks)
2279 mutex_lock(&smu->mutex);
2281 if (smu->ppt_funcs->get_max_high_clocks)
2282 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2284 mutex_unlock(&smu->mutex);
2289 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2290 enum smu_clk_type clk_type,
2291 struct pp_clock_levels_with_latency *clocks)
2295 mutex_lock(&smu->mutex);
2297 if (smu->ppt_funcs->get_clock_by_type_with_latency)
2298 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2300 mutex_unlock(&smu->mutex);
2305 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2306 enum amd_pp_clock_type type,
2307 struct pp_clock_levels_with_voltage *clocks)
2311 mutex_lock(&smu->mutex);
2313 if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2314 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2316 mutex_unlock(&smu->mutex);
2322 int smu_display_clock_voltage_request(struct smu_context *smu,
2323 struct pp_display_clock_request *clock_req)
2327 mutex_lock(&smu->mutex);
2329 if (smu->ppt_funcs->display_clock_voltage_request)
2330 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2332 mutex_unlock(&smu->mutex);
2338 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2342 mutex_lock(&smu->mutex);
2344 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2345 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2347 mutex_unlock(&smu->mutex);
2352 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2356 mutex_lock(&smu->mutex);
2358 if (smu->ppt_funcs->notify_smu_enable_pwe)
2359 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2361 mutex_unlock(&smu->mutex);
2366 int smu_set_xgmi_pstate(struct smu_context *smu,
2371 mutex_lock(&smu->mutex);
2373 if (smu->ppt_funcs->set_xgmi_pstate)
2374 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2376 mutex_unlock(&smu->mutex);
2381 int smu_set_azalia_d3_pme(struct smu_context *smu)
2385 mutex_lock(&smu->mutex);
2387 if (smu->ppt_funcs->set_azalia_d3_pme)
2388 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2390 mutex_unlock(&smu->mutex);
2395 bool smu_baco_is_support(struct smu_context *smu)
2399 mutex_lock(&smu->mutex);
2401 if (smu->ppt_funcs->baco_is_support)
2402 ret = smu->ppt_funcs->baco_is_support(smu);
2404 mutex_unlock(&smu->mutex);
2409 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2411 if (smu->ppt_funcs->baco_get_state)
2414 mutex_lock(&smu->mutex);
2415 *state = smu->ppt_funcs->baco_get_state(smu);
2416 mutex_unlock(&smu->mutex);
2421 int smu_baco_enter(struct smu_context *smu)
2425 mutex_lock(&smu->mutex);
2427 if (smu->ppt_funcs->baco_enter)
2428 ret = smu->ppt_funcs->baco_enter(smu);
2430 mutex_unlock(&smu->mutex);
2435 int smu_baco_exit(struct smu_context *smu)
2439 mutex_lock(&smu->mutex);
2441 if (smu->ppt_funcs->baco_exit)
2442 ret = smu->ppt_funcs->baco_exit(smu);
2444 mutex_unlock(&smu->mutex);
2449 int smu_mode2_reset(struct smu_context *smu)
2453 mutex_lock(&smu->mutex);
2455 if (smu->ppt_funcs->mode2_reset)
2456 ret = smu->ppt_funcs->mode2_reset(smu);
2458 mutex_unlock(&smu->mutex);
2463 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2464 struct pp_smu_nv_clock_table *max_clocks)
2468 mutex_lock(&smu->mutex);
2470 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2471 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2473 mutex_unlock(&smu->mutex);
2478 int smu_get_uclk_dpm_states(struct smu_context *smu,
2479 unsigned int *clock_values_in_khz,
2480 unsigned int *num_states)
2484 mutex_lock(&smu->mutex);
2486 if (smu->ppt_funcs->get_uclk_dpm_states)
2487 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2489 mutex_unlock(&smu->mutex);
2494 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2496 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2498 mutex_lock(&smu->mutex);
2500 if (smu->ppt_funcs->get_current_power_state)
2501 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2503 mutex_unlock(&smu->mutex);
2508 int smu_get_dpm_clock_table(struct smu_context *smu,
2509 struct dpm_clocks *clock_table)
2513 mutex_lock(&smu->mutex);
2515 if (smu->ppt_funcs->get_dpm_clock_table)
2516 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2518 mutex_unlock(&smu->mutex);
2523 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2527 if (smu->ppt_funcs->get_pptable_power_limit)
2528 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2533 int smu_send_smc_msg(struct smu_context *smu,
2534 enum smu_message_type msg)
2538 ret = smu_send_smc_msg_with_param(smu, msg, 0);