drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "soc15_common.h"
  30 #include "smu_v11_0.h"
  31 #include "smu_v12_0.h"
  32 #include "atom.h"
  33 #include "amd_pcie.h"
  34 #include "vega20_ppt.h"
  35 #include "arcturus_ppt.h"
  36 #include "navi10_ppt.h"
  37 #include "renoir_ppt.h"
  38
  39 #undef __SMU_DUMMY_MAP
  40 #define __SMU_DUMMY_MAP(type)   #type
  41 static const char* __smu_message_names[] = {
  42         SMU_MESSAGE_TYPES
  43 };
  44
  45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  46 {
  47         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  48                 return "unknown smu message";
  49         return __smu_message_names[type];
  50 }
  51
  52 #undef __SMU_DUMMY_MAP
  53 #define __SMU_DUMMY_MAP(fea)    #fea
  54 static const char* __smu_feature_names[] = {
  55         SMU_FEATURE_MASKS
  56 };
  57
  58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  59 {
  60         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  61                 return "unknown smu feature";
  62         return __smu_feature_names[feature];
  63 }
  64
  65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  66 {
  67         size_t size = 0;
  68         int ret = 0, i = 0;
  69         uint32_t feature_mask[2] = { 0 };
  70         int32_t feature_index = 0;
  71         uint32_t count = 0;
  72         uint32_t sort_feature[SMU_FEATURE_COUNT];
  73         uint64_t hw_feature_count = 0;
  74
  75         mutex_lock(&smu->mutex);
  76
  77         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  78         if (ret)
  79                 goto failed;
  80
  81         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  82                         feature_mask[1], feature_mask[0]);
  83
  84         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  85                 feature_index = smu_feature_get_index(smu, i);
  86                 if (feature_index < 0)
  87                         continue;
  88                 sort_feature[feature_index] = i;
  89                 hw_feature_count++;
  90         }
  91
  92         for (i = 0; i < hw_feature_count; i++) {
  93                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  94                                count++,
  95                                smu_get_feature_name(smu, sort_feature[i]),
  96                                i,
  97                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  98                                "enabled" : "disabled");
  99         }
 100
 101 failed:
 102         mutex_unlock(&smu->mutex);
 103
 104         return size;
 105 }
 106
 107 static int smu_feature_update_enable_state(struct smu_context *smu,
 108                                            uint64_t feature_mask,
 109                                            bool enabled)
 110 {
 111         struct smu_feature *feature = &smu->smu_feature;
 112         uint32_t feature_low = 0, feature_high = 0;
 113         int ret = 0;
 114
 115         if (!smu->pm_enabled)
 116                 return ret;
 117
 118         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 119         feature_high = (feature_mask >> 32) & 0xffffffff;
 120
 121         if (enabled) {
 122                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 123                                                   feature_low);
 124                 if (ret)
 125                         return ret;
 126                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 127                                                   feature_high);
 128                 if (ret)
 129                         return ret;
 130         } else {
 131                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 132                                                   feature_low);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 136                                                   feature_high);
 137                 if (ret)
 138                         return ret;
 139         }
 140
 141         mutex_lock(&feature->mutex);
 142         if (enabled)
 143                 bitmap_or(feature->enabled, feature->enabled,
 144                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 145         else
 146                 bitmap_andnot(feature->enabled, feature->enabled,
 147                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 148         mutex_unlock(&feature->mutex);
 149
 150         return ret;
 151 }
 152
 153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 154 {
 155         int ret = 0;
 156         uint32_t feature_mask[2] = { 0 };
 157         uint64_t feature_2_enabled = 0;
 158         uint64_t feature_2_disabled = 0;
 159         uint64_t feature_enables = 0;
 160
 161         mutex_lock(&smu->mutex);
 162
 163         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 164         if (ret)
 165                 goto out;
 166
 167         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 168
 169         feature_2_enabled  = ~feature_enables & new_mask;
 170         feature_2_disabled = feature_enables & ~new_mask;
 171
 172         if (feature_2_enabled) {
 173                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 174                 if (ret)
 175                         goto out;
 176         }
 177         if (feature_2_disabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 179                 if (ret)
 180                         goto out;
 181         }
 182
 183 out:
 184         mutex_unlock(&smu->mutex);
 185
 186         return ret;
 187 }
 188
 189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 190 {
 191         int ret = 0;
 192
 193         if (!if_version && !smu_version)
 194                 return -EINVAL;
 195
 196         if (if_version) {
 197                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 198                 if (ret)
 199                         return ret;
 200
 201                 ret = smu_read_smc_arg(smu, if_version);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         if (smu_version) {
 207                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 208                 if (ret)
 209                         return ret;
 210
 211                 ret = smu_read_smc_arg(smu, smu_version);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return ret;
 217 }
 218
 219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 220                             uint32_t min, uint32_t max)
 221 {
 222         int ret = 0;
 223
 224         if (min <= 0 && max <= 0)
 225                 return -EINVAL;
 226
 227         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 228                 return 0;
 229
 230         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 231         return ret;
 232 }
 233
 234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 235                             uint32_t min, uint32_t max)
 236 {
 237         int ret = 0, clk_id = 0;
 238         uint32_t param;
 239
 240         if (min <= 0 && max <= 0)
 241                 return -EINVAL;
 242
 243         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 244                 return 0;
 245
 246         clk_id = smu_clk_get_index(smu, clk_type);
 247         if (clk_id < 0)
 248                 return clk_id;
 249
 250         if (max > 0) {
 251                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 252                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 253                                                   param);
 254                 if (ret)
 255                         return ret;
 256         }
 257
 258         if (min > 0) {
 259                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 260                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 261                                                   param);
 262                 if (ret)
 263                         return ret;
 264         }
 265
 266
 267         return ret;
 268 }
 269
 270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 271                            uint32_t *min, uint32_t *max, bool lock_needed)
 272 {
 273         uint32_t clock_limit;
 274         int ret = 0;
 275
 276         if (!min && !max)
 277                 return -EINVAL;
 278
 279         if (lock_needed)
 280                 mutex_lock(&smu->mutex);
 281
 282         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 283                 switch (clk_type) {
 284                 case SMU_MCLK:
 285                 case SMU_UCLK:
 286                         clock_limit = smu->smu_table.boot_values.uclk;
 287                         break;
 288                 case SMU_GFXCLK:
 289                 case SMU_SCLK:
 290                         clock_limit = smu->smu_table.boot_values.gfxclk;
 291                         break;
 292                 case SMU_SOCCLK:
 293                         clock_limit = smu->smu_table.boot_values.socclk;
 294                         break;
 295                 default:
 296                         clock_limit = 0;
 297                         break;
 298                 }
 299
 300                 /* clock in Mhz unit */
 301                 if (min)
 302                         *min = clock_limit / 100;
 303                 if (max)
 304                         *max = clock_limit / 100;
 305         } else {
 306                 /*
 307                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 308                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 309                  */
 310                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 311         }
 312
 313         if (lock_needed)
 314                 mutex_unlock(&smu->mutex);
 315
 316         return ret;
 317 }
 318
 319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 320                               uint16_t level, uint32_t *value)
 321 {
 322         int ret = 0, clk_id = 0;
 323         uint32_t param;
 324
 325         if (!value)
 326                 return -EINVAL;
 327
 328         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 329                 return 0;
 330
 331         clk_id = smu_clk_get_index(smu, clk_type);
 332         if (clk_id < 0)
 333                 return clk_id;
 334
 335         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 336
 337         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 338                                           param);
 339         if (ret)
 340                 return ret;
 341
 342         ret = smu_read_smc_arg(smu, &param);
 343         if (ret)
 344                 return ret;
 345
 346         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 347          * now, we un-support it */
 348         *value = param & 0x7fffffff;
 349
 350         return ret;
 351 }
 352
 353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 354                             uint32_t *value)
 355 {
 356         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 357 }
 358
 359 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 360 {
 361         enum smu_feature_mask feature_id = 0;
 362
 363         switch (clk_type) {
 364         case SMU_MCLK:
 365         case SMU_UCLK:
 366                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 367                 break;
 368         case SMU_GFXCLK:
 369         case SMU_SCLK:
 370                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 371                 break;
 372         case SMU_SOCCLK:
 373                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 374                 break;
 375         default:
 376                 return true;
 377         }
 378
 379         if(!smu_feature_is_enabled(smu, feature_id)) {
 380                 return false;
 381         }
 382
 383         return true;
 384 }
 385
 386 /**
 387  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 388  *
 389  * @smu:        smu_context pointer
 390  * @block_type: the IP block to power gate/ungate
 391  * @gate:       to power gate if true, ungate otherwise
 392  *
 393  * This API uses no smu->mutex lock protection due to:
 394  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 395  *    This is guarded to be race condition free by the caller.
 396  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 397  *    Under this case, the smu->mutex lock protection is already enforced on
 398  *    the parent API smu_force_performance_level of the call path.
 399  */
 400 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 401                            bool gate)
 402 {
 403         int ret = 0;
 404
 405         switch (block_type) {
 406         case AMD_IP_BLOCK_TYPE_UVD:
 407                 ret = smu_dpm_set_uvd_enable(smu, gate);
 408                 break;
 409         case AMD_IP_BLOCK_TYPE_VCE:
 410                 ret = smu_dpm_set_vce_enable(smu, gate);
 411                 break;
 412         case AMD_IP_BLOCK_TYPE_GFX:
 413                 ret = smu_gfx_off_control(smu, gate);
 414                 break;
 415         case AMD_IP_BLOCK_TYPE_SDMA:
 416                 ret = smu_powergate_sdma(smu, gate);
 417                 break;
 418         default:
 419                 break;
 420         }
 421
 422         return ret;
 423 }
 424
 425 int smu_get_power_num_states(struct smu_context *smu,
 426                              struct pp_states_info *state_info)
 427 {
 428         if (!state_info)
 429                 return -EINVAL;
 430
 431         /* not support power state */
 432         memset(state_info, 0, sizeof(struct pp_states_info));
 433         state_info->nums = 1;
 434         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 435
 436         return 0;
 437 }
 438
 439 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 440                            void *data, uint32_t *size)
 441 {
 442         struct smu_power_context *smu_power = &smu->smu_power;
 443         struct smu_power_gate *power_gate = &smu_power->power_gate;
 444         int ret = 0;
 445
 446         if(!data || !size)
 447                 return -EINVAL;
 448
 449         switch (sensor) {
 450         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 451                 *((uint32_t *)data) = smu->pstate_sclk;
 452                 *size = 4;
 453                 break;
 454         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 455                 *((uint32_t *)data) = smu->pstate_mclk;
 456                 *size = 4;
 457                 break;
 458         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 459                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 460                 *size = 8;
 461                 break;
 462         case AMDGPU_PP_SENSOR_UVD_POWER:
 463                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 464                 *size = 4;
 465                 break;
 466         case AMDGPU_PP_SENSOR_VCE_POWER:
 467                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 468                 *size = 4;
 469                 break;
 470         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 471                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 472                 *size = 4;
 473                 break;
 474         default:
 475                 ret = -EINVAL;
 476                 break;
 477         }
 478
 479         if (ret)
 480                 *size = 0;
 481
 482         return ret;
 483 }
 484
 485 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 486                      void *table_data, bool drv2smu)
 487 {
 488         struct smu_table_context *smu_table = &smu->smu_table;
 489         struct amdgpu_device *adev = smu->adev;
 490         struct smu_table *table = NULL;
 491         int ret = 0;
 492         int table_id = smu_table_get_index(smu, table_index);
 493
 494         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 495                 return -EINVAL;
 496
 497         table = &smu_table->tables[table_index];
 498
 499         if (drv2smu)
 500                 memcpy(table->cpu_addr, table_data, table->size);
 501
 502         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 503                                           upper_32_bits(table->mc_address));
 504         if (ret)
 505                 return ret;
 506         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 507                                           lower_32_bits(table->mc_address));
 508         if (ret)
 509                 return ret;
 510         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 511                                           SMU_MSG_TransferTableDram2Smu :
 512                                           SMU_MSG_TransferTableSmu2Dram,
 513                                           table_id | ((argument & 0xFFFF) << 16));
 514         if (ret)
 515                 return ret;
 516
 517         /* flush hdp cache */
 518         adev->nbio.funcs->hdp_flush(adev, NULL);
 519
 520         if (!drv2smu)
 521                 memcpy(table_data, table->cpu_addr, table->size);
 522
 523         return ret;
 524 }
 525
 526 bool is_support_sw_smu(struct amdgpu_device *adev)
 527 {
 528         if (adev->asic_type == CHIP_VEGA20)
 529                 return (amdgpu_dpm == 2) ? true : false;
 530         else if (adev->asic_type >= CHIP_ARCTURUS)
 531                 return true;
 532         else
 533                 return false;
 534 }
 535
 536 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 537 {
 538         if (!is_support_sw_smu(adev))
 539                 return false;
 540
 541         if (adev->asic_type == CHIP_VEGA20)
 542                 return true;
 543
 544         return false;
 545 }
 546
 547 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 548 {
 549         struct smu_table_context *smu_table = &smu->smu_table;
 550         uint32_t powerplay_table_size;
 551
 552         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 553                 return -EINVAL;
 554
 555         mutex_lock(&smu->mutex);
 556
 557         if (smu_table->hardcode_pptable)
 558                 *table = smu_table->hardcode_pptable;
 559         else
 560                 *table = smu_table->power_play_table;
 561
 562         powerplay_table_size = smu_table->power_play_table_size;
 563
 564         mutex_unlock(&smu->mutex);
 565
 566         return powerplay_table_size;
 567 }
 568
 569 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 570 {
 571         struct smu_table_context *smu_table = &smu->smu_table;
 572         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 573         int ret = 0;
 574
 575         if (!smu->pm_enabled)
 576                 return -EINVAL;
 577         if (header->usStructureSize != size) {
 578                 pr_err("pp table size not matched !\n");
 579                 return -EIO;
 580         }
 581
 582         mutex_lock(&smu->mutex);
 583         if (!smu_table->hardcode_pptable)
 584                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 585         if (!smu_table->hardcode_pptable) {
 586                 ret = -ENOMEM;
 587                 goto failed;
 588         }
 589
 590         memcpy(smu_table->hardcode_pptable, buf, size);
 591         smu_table->power_play_table = smu_table->hardcode_pptable;
 592         smu_table->power_play_table_size = size;
 593
 594         /*
 595          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 596          * skipped) may be needed for custom pptable uploading.
 597          */
 598         smu->uploading_custom_pp_table = true;
 599
 600         ret = smu_reset(smu);
 601         if (ret)
 602                 pr_info("smu reset failed, ret = %d\n", ret);
 603
 604         smu->uploading_custom_pp_table = false;
 605
 606 failed:
 607         mutex_unlock(&smu->mutex);
 608         return ret;
 609 }
 610
 611 int smu_feature_init_dpm(struct smu_context *smu)
 612 {
 613         struct smu_feature *feature = &smu->smu_feature;
 614         int ret = 0;
 615         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 616
 617         if (!smu->pm_enabled)
 618                 return ret;
 619         mutex_lock(&feature->mutex);
 620         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 621         mutex_unlock(&feature->mutex);
 622
 623         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 624                                              SMU_FEATURE_MAX/32);
 625         if (ret)
 626                 return ret;
 627
 628         mutex_lock(&feature->mutex);
 629         bitmap_or(feature->allowed, feature->allowed,
 630                       (unsigned long *)allowed_feature_mask,
 631                       feature->feature_num);
 632         mutex_unlock(&feature->mutex);
 633
 634         return ret;
 635 }
 636
 637
 638 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 639 {
 640         struct amdgpu_device *adev = smu->adev;
 641         struct smu_feature *feature = &smu->smu_feature;
 642         int feature_id;
 643         int ret = 0;
 644
 645         if (adev->flags & AMD_IS_APU)
 646                 return 1;
 647
 648         feature_id = smu_feature_get_index(smu, mask);
 649         if (feature_id < 0)
 650                 return 0;
 651
 652         WARN_ON(feature_id > feature->feature_num);
 653
 654         mutex_lock(&feature->mutex);
 655         ret = test_bit(feature_id, feature->enabled);
 656         mutex_unlock(&feature->mutex);
 657
 658         return ret;
 659 }
 660
 661 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 662                             bool enable)
 663 {
 664         struct smu_feature *feature = &smu->smu_feature;
 665         int feature_id;
 666
 667         feature_id = smu_feature_get_index(smu, mask);
 668         if (feature_id < 0)
 669                 return -EINVAL;
 670
 671         WARN_ON(feature_id > feature->feature_num);
 672
 673         return smu_feature_update_enable_state(smu,
 674                                                1ULL << feature_id,
 675                                                enable);
 676 }
 677
 678 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 679 {
 680         struct smu_feature *feature = &smu->smu_feature;
 681         int feature_id;
 682         int ret = 0;
 683
 684         feature_id = smu_feature_get_index(smu, mask);
 685         if (feature_id < 0)
 686                 return 0;
 687
 688         WARN_ON(feature_id > feature->feature_num);
 689
 690         mutex_lock(&feature->mutex);
 691         ret = test_bit(feature_id, feature->supported);
 692         mutex_unlock(&feature->mutex);
 693
 694         return ret;
 695 }
 696
 697 int smu_feature_set_supported(struct smu_context *smu,
 698                               enum smu_feature_mask mask,
 699                               bool enable)
 700 {
 701         struct smu_feature *feature = &smu->smu_feature;
 702         int feature_id;
 703         int ret = 0;
 704
 705         feature_id = smu_feature_get_index(smu, mask);
 706         if (feature_id < 0)
 707                 return -EINVAL;
 708
 709         WARN_ON(feature_id > feature->feature_num);
 710
 711         mutex_lock(&feature->mutex);
 712         if (enable)
 713                 test_and_set_bit(feature_id, feature->supported);
 714         else
 715                 test_and_clear_bit(feature_id, feature->supported);
 716         mutex_unlock(&feature->mutex);
 717
 718         return ret;
 719 }
 720
 721 static int smu_set_funcs(struct amdgpu_device *adev)
 722 {
 723         struct smu_context *smu = &adev->smu;
 724
 725         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 726                 smu->od_enabled = true;
 727
 728         switch (adev->asic_type) {
 729         case CHIP_VEGA20:
 730                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 731                 vega20_set_ppt_funcs(smu);
 732                 break;
 733         case CHIP_NAVI10:
 734         case CHIP_NAVI14:
 735         case CHIP_NAVI12:
 736                 navi10_set_ppt_funcs(smu);
 737                 break;
 738         case CHIP_ARCTURUS:
 739                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 740                 arcturus_set_ppt_funcs(smu);
 741                 /* OD is not supported on Arcturus */
 742                 smu->od_enabled =false;
 743                 break;
 744         case CHIP_RENOIR:
 745                 renoir_set_ppt_funcs(smu);
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int smu_early_init(void *handle)
 755 {
 756         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 757         struct smu_context *smu = &adev->smu;
 758
 759         smu->adev = adev;
 760         smu->pm_enabled = !!amdgpu_dpm;
 761         smu->is_apu = false;
 762         mutex_init(&smu->mutex);
 763
 764         return smu_set_funcs(adev);
 765 }
 766
 767 static int smu_late_init(void *handle)
 768 {
 769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 770         struct smu_context *smu = &adev->smu;
 771
 772         if (!smu->pm_enabled)
 773                 return 0;
 774
 775         smu_handle_task(&adev->smu,
 776                         smu->smu_dpm.dpm_level,
 777                         AMD_PP_TASK_COMPLETE_INIT,
 778                         false);
 779
 780         return 0;
 781 }
 782
 783 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 784                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 785                             uint8_t **addr)
 786 {
 787         struct amdgpu_device *adev = smu->adev;
 788         uint16_t data_start;
 789
 790         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 791                                            size, frev, crev, &data_start))
 792                 return -EINVAL;
 793
 794         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 795
 796         return 0;
 797 }
 798
 799 static int smu_initialize_pptable(struct smu_context *smu)
 800 {
 801         /* TODO */
 802         return 0;
 803 }
 804
 805 static int smu_smc_table_sw_init(struct smu_context *smu)
 806 {
 807         int ret;
 808
 809         ret = smu_initialize_pptable(smu);
 810         if (ret) {
 811                 pr_err("Failed to init smu_initialize_pptable!\n");
 812                 return ret;
 813         }
 814
 815         /**
 816          * Create smu_table structure, and init smc tables such as
 817          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 818          */
 819         ret = smu_init_smc_tables(smu);
 820         if (ret) {
 821                 pr_err("Failed to init smc tables!\n");
 822                 return ret;
 823         }
 824
 825         /**
 826          * Create smu_power_context structure, and allocate smu_dpm_context and
 827          * context size to fill the smu_power_context data.
 828          */
 829         ret = smu_init_power(smu);
 830         if (ret) {
 831                 pr_err("Failed to init smu_init_power!\n");
 832                 return ret;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int smu_smc_table_sw_fini(struct smu_context *smu)
 839 {
 840         int ret;
 841
 842         ret = smu_fini_smc_tables(smu);
 843         if (ret) {
 844                 pr_err("Failed to smu_fini_smc_tables!\n");
 845                 return ret;
 846         }
 847
 848         return 0;
 849 }
 850
 851 static int smu_sw_init(void *handle)
 852 {
 853         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 854         struct smu_context *smu = &adev->smu;
 855         int ret;
 856
 857         smu->pool_size = adev->pm.smu_prv_buffer_size;
 858         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 859         mutex_init(&smu->smu_feature.mutex);
 860         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 861         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 862         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 863
 864         mutex_init(&smu->smu_baco.mutex);
 865         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 866         smu->smu_baco.platform_support = false;
 867
 868         mutex_init(&smu->sensor_lock);
 869
 870         smu->watermarks_bitmap = 0;
 871         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 872         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 873
 874         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 875         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 876         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 877         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 878         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 879         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 880         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 881         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 882
 883         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 884         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 885         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 886         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 887         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 888         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 889         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 890         smu->display_config = &adev->pm.pm_display_cfg;
 891
 892         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 893         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 894         ret = smu_init_microcode(smu);
 895         if (ret) {
 896                 pr_err("Failed to load smu firmware!\n");
 897                 return ret;
 898         }
 899
 900         ret = smu_smc_table_sw_init(smu);
 901         if (ret) {
 902                 pr_err("Failed to sw init smc table!\n");
 903                 return ret;
 904         }
 905
 906         ret = smu_register_irq_handler(smu);
 907         if (ret) {
 908                 pr_err("Failed to register smc irq handler!\n");
 909                 return ret;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int smu_sw_fini(void *handle)
 916 {
 917         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 918         struct smu_context *smu = &adev->smu;
 919         int ret;
 920
 921         kfree(smu->irq_source);
 922         smu->irq_source = NULL;
 923
 924         ret = smu_smc_table_sw_fini(smu);
 925         if (ret) {
 926                 pr_err("Failed to sw fini smc table!\n");
 927                 return ret;
 928         }
 929
 930         ret = smu_fini_power(smu);
 931         if (ret) {
 932                 pr_err("Failed to init smu_fini_power!\n");
 933                 return ret;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int smu_init_fb_allocations(struct smu_context *smu)
 940 {
 941         struct amdgpu_device *adev = smu->adev;
 942         struct smu_table_context *smu_table = &smu->smu_table;
 943         struct smu_table *tables = smu_table->tables;
 944         int ret, i;
 945
 946         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 947                 if (tables[i].size == 0)
 948                         continue;
 949                 ret = amdgpu_bo_create_kernel(adev,
 950                                               tables[i].size,
 951                                               tables[i].align,
 952                                               tables[i].domain,
 953                                               &tables[i].bo,
 954                                               &tables[i].mc_address,
 955                                               &tables[i].cpu_addr);
 956                 if (ret)
 957                         goto failed;
 958         }
 959
 960         return 0;
 961 failed:
 962         while (--i >= 0) {
 963                 if (tables[i].size == 0)
 964                         continue;
 965                 amdgpu_bo_free_kernel(&tables[i].bo,
 966                                       &tables[i].mc_address,
 967                                       &tables[i].cpu_addr);
 968
 969         }
 970         return ret;
 971 }
 972
 973 static int smu_fini_fb_allocations(struct smu_context *smu)
 974 {
 975         struct smu_table_context *smu_table = &smu->smu_table;
 976         struct smu_table *tables = smu_table->tables;
 977         uint32_t i = 0;
 978
 979         if (!tables)
 980                 return 0;
 981
 982         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 983                 if (tables[i].size == 0)
 984                         continue;
 985                 amdgpu_bo_free_kernel(&tables[i].bo,
 986                                       &tables[i].mc_address,
 987                                       &tables[i].cpu_addr);
 988         }
 989
 990         return 0;
 991 }
 992
 993 static int smu_smc_table_hw_init(struct smu_context *smu,
 994                                  bool initialize)
 995 {
 996         struct amdgpu_device *adev = smu->adev;
 997         int ret;
 998
 999         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1000                 pr_info("dpm has been enabled\n");
1001                 return 0;
1002         }
1003
1004         if (adev->asic_type != CHIP_ARCTURUS) {
1005                 ret = smu_init_display_count(smu, 0);
1006                 if (ret)
1007                         return ret;
1008         }
1009
1010         if (initialize) {
1011                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1012                 ret = smu_get_vbios_bootup_values(smu);
1013                 if (ret)
1014                         return ret;
1015
1016                 ret = smu_setup_pptable(smu);
1017                 if (ret)
1018                         return ret;
1019
1020                 ret = smu_get_clk_info_from_vbios(smu);
1021                 if (ret)
1022                         return ret;
1023
1024                 /*
1025                  * check if the format_revision in vbios is up to pptable header
1026                  * version, and the structure size is not 0.
1027                  */
1028                 ret = smu_check_pptable(smu);
1029                 if (ret)
1030                         return ret;
1031
1032                 /*
1033                  * allocate vram bos to store smc table contents.
1034                  */
1035                 ret = smu_init_fb_allocations(smu);
1036                 if (ret)
1037                         return ret;
1038
1039                 /*
1040                  * Parse pptable format and fill PPTable_t smc_pptable to
1041                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1042                  * then fill it into smc_pptable.
1043                  */
1044                 ret = smu_parse_pptable(smu);
1045                 if (ret)
1046                         return ret;
1047
1048                 /*
1049                  * Send msg GetDriverIfVersion to check if the return value is equal
1050                  * with DRIVER_IF_VERSION of smc header.
1051                  */
1052                 ret = smu_check_fw_version(smu);
1053                 if (ret)
1054                         return ret;
1055         }
1056
1057         /* smu_dump_pptable(smu); */
1058
1059         /*
1060          * Copy pptable bo in the vram to smc with SMU MSGs such as
1061          * SetDriverDramAddr and TransferTableDram2Smu.
1062          */
1063         ret = smu_write_pptable(smu);
1064         if (ret)
1065                 return ret;
1066
1067         /* issue Run*Btc msg */
1068         ret = smu_run_btc(smu);
1069         if (ret)
1070                 return ret;
1071
1072         ret = smu_feature_set_allowed_mask(smu);
1073         if (ret)
1074                 return ret;
1075
1076         ret = smu_system_features_control(smu, true);
1077         if (ret)
1078                 return ret;
1079
1080         if (adev->asic_type != CHIP_ARCTURUS) {
1081                 ret = smu_notify_display_change(smu);
1082                 if (ret)
1083                         return ret;
1084
1085                 /*
1086                  * Set min deep sleep dce fclk with bootup value from vbios via
1087                  * SetMinDeepSleepDcefclk MSG.
1088                  */
1089                 ret = smu_set_min_dcef_deep_sleep(smu);
1090                 if (ret)
1091                         return ret;
1092         }
1093
1094         /*
1095          * Set initialized values (get from vbios) to dpm tables context such as
1096          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1097          * type of clks.
1098          */
1099         if (initialize) {
1100                 ret = smu_populate_smc_tables(smu);
1101                 if (ret)
1102                         return ret;
1103
1104                 ret = smu_init_max_sustainable_clocks(smu);
1105                 if (ret)
1106                         return ret;
1107         }
1108
1109         if (adev->asic_type != CHIP_ARCTURUS) {
1110                 ret = smu_override_pcie_parameters(smu);
1111                 if (ret)
1112                         return ret;
1113         }
1114
1115         ret = smu_set_default_od_settings(smu, initialize);
1116         if (ret)
1117                 return ret;
1118
1119         if (initialize) {
1120                 ret = smu_populate_umd_state_clk(smu);
1121                 if (ret)
1122                         return ret;
1123
1124                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1125                 if (ret)
1126                         return ret;
1127         }
1128
1129         /*
1130          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1131          */
1132         ret = smu_set_tool_table_location(smu);
1133
1134         if (!smu_is_dpm_running(smu))
1135                 pr_info("dpm has been disabled\n");
1136
1137         return ret;
1138 }
1139
1140 /**
1141  * smu_alloc_memory_pool - allocate memory pool in the system memory
1142  *
1143  * @smu: amdgpu_device pointer
1144  *
1145  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1146  * and DramLogSetDramAddr can notify it changed.
1147  *
1148  * Returns 0 on success, error on failure.
1149  */
1150 static int smu_alloc_memory_pool(struct smu_context *smu)
1151 {
1152         struct amdgpu_device *adev = smu->adev;
1153         struct smu_table_context *smu_table = &smu->smu_table;
1154         struct smu_table *memory_pool = &smu_table->memory_pool;
1155         uint64_t pool_size = smu->pool_size;
1156         int ret = 0;
1157
1158         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1159                 return ret;
1160
1161         memory_pool->size = pool_size;
1162         memory_pool->align = PAGE_SIZE;
1163         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1164
1165         switch (pool_size) {
1166         case SMU_MEMORY_POOL_SIZE_256_MB:
1167         case SMU_MEMORY_POOL_SIZE_512_MB:
1168         case SMU_MEMORY_POOL_SIZE_1_GB:
1169         case SMU_MEMORY_POOL_SIZE_2_GB:
1170                 ret = amdgpu_bo_create_kernel(adev,
1171                                               memory_pool->size,
1172                                               memory_pool->align,
1173                                               memory_pool->domain,
1174                                               &memory_pool->bo,
1175                                               &memory_pool->mc_address,
1176                                               &memory_pool->cpu_addr);
1177                 break;
1178         default:
1179                 break;
1180         }
1181
1182         return ret;
1183 }
1184
1185 static int smu_free_memory_pool(struct smu_context *smu)
1186 {
1187         struct smu_table_context *smu_table = &smu->smu_table;
1188         struct smu_table *memory_pool = &smu_table->memory_pool;
1189         int ret = 0;
1190
1191         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1192                 return ret;
1193
1194         amdgpu_bo_free_kernel(&memory_pool->bo,
1195                               &memory_pool->mc_address,
1196                               &memory_pool->cpu_addr);
1197
1198         memset(memory_pool, 0, sizeof(struct smu_table));
1199
1200         return ret;
1201 }
1202
1203 static int smu_start_smc_engine(struct smu_context *smu)
1204 {
1205         struct amdgpu_device *adev = smu->adev;
1206         int ret = 0;
1207
1208         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1209                 if (adev->asic_type < CHIP_NAVI10) {
1210                         if (smu->ppt_funcs->load_microcode) {
1211                                 ret = smu->ppt_funcs->load_microcode(smu);
1212                                 if (ret)
1213                                         return ret;
1214                         }
1215                 }
1216         }
1217
1218         if (smu->ppt_funcs->check_fw_status) {
1219                 ret = smu->ppt_funcs->check_fw_status(smu);
1220                 if (ret)
1221                         pr_err("SMC is not ready\n");
1222         }
1223
1224         return ret;
1225 }
1226
1227 static int smu_hw_init(void *handle)
1228 {
1229         int ret;
1230         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231         struct smu_context *smu = &adev->smu;
1232
1233         ret = smu_start_smc_engine(smu);
1234         if (ret) {
1235                 pr_err("SMU is not ready yet!\n");
1236                 return ret;
1237         }
1238
1239         if (adev->flags & AMD_IS_APU) {
1240                 smu_powergate_sdma(&adev->smu, false);
1241                 smu_powergate_vcn(&adev->smu, false);
1242                 smu_set_gfx_cgpg(&adev->smu, true);
1243         }
1244
1245         if (!smu->pm_enabled)
1246                 return 0;
1247
1248         ret = smu_feature_init_dpm(smu);
1249         if (ret)
1250                 goto failed;
1251
1252         ret = smu_smc_table_hw_init(smu, true);
1253         if (ret)
1254                 goto failed;
1255
1256         ret = smu_alloc_memory_pool(smu);
1257         if (ret)
1258                 goto failed;
1259
1260         /*
1261          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1262          * pool location.
1263          */
1264         ret = smu_notify_memory_pool_location(smu);
1265         if (ret)
1266                 goto failed;
1267
1268         ret = smu_start_thermal_control(smu);
1269         if (ret)
1270                 goto failed;
1271
1272         if (!smu->pm_enabled)
1273                 adev->pm.dpm_enabled = false;
1274         else
1275                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1276
1277         pr_info("SMU is initialized successfully!\n");
1278
1279         return 0;
1280
1281 failed:
1282         return ret;
1283 }
1284
1285 static int smu_stop_dpms(struct smu_context *smu)
1286 {
1287         return smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
1288 }
1289
1290 static int smu_hw_fini(void *handle)
1291 {
1292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293         struct smu_context *smu = &adev->smu;
1294         struct smu_table_context *table_context = &smu->smu_table;
1295         int ret = 0;
1296
1297         if (adev->flags & AMD_IS_APU) {
1298                 smu_powergate_sdma(&adev->smu, true);
1299                 smu_powergate_vcn(&adev->smu, true);
1300         }
1301
1302         ret = smu_stop_thermal_control(smu);
1303         if (ret) {
1304                 pr_warn("Fail to stop thermal control!\n");
1305                 return ret;
1306         }
1307
1308         /*
1309          * For custom pptable uploading, skip the DPM features
1310          * disable process on Navi1x ASICs.
1311          *   - As the gfx related features are under control of
1312          *     RLC on those ASICs. RLC reinitialization will be
1313          *     needed to reenable them. That will cost much more
1314          *     efforts.
1315          *
1316          *   - SMU firmware can handle the DPM reenablement
1317          *     properly.
1318          */
1319         if (!smu->uploading_custom_pp_table ||
1320             !((adev->asic_type >= CHIP_NAVI10) &&
1321               (adev->asic_type <= CHIP_NAVI12))) {
1322                 ret = smu_stop_dpms(smu);
1323                 if (ret) {
1324                         pr_warn("Fail to stop Dpms!\n");
1325                         return ret;
1326                 }
1327         }
1328
1329         kfree(table_context->driver_pptable);
1330         table_context->driver_pptable = NULL;
1331
1332         kfree(table_context->max_sustainable_clocks);
1333         table_context->max_sustainable_clocks = NULL;
1334
1335         kfree(table_context->overdrive_table);
1336         table_context->overdrive_table = NULL;
1337
1338         ret = smu_fini_fb_allocations(smu);
1339         if (ret)
1340                 return ret;
1341
1342         ret = smu_free_memory_pool(smu);
1343         if (ret)
1344                 return ret;
1345
1346         return 0;
1347 }
1348
1349 int smu_reset(struct smu_context *smu)
1350 {
1351         struct amdgpu_device *adev = smu->adev;
1352         int ret = 0;
1353
1354         ret = smu_hw_fini(adev);
1355         if (ret)
1356                 return ret;
1357
1358         ret = smu_hw_init(adev);
1359         if (ret)
1360                 return ret;
1361
1362         return ret;
1363 }
1364
1365 static int smu_suspend(void *handle)
1366 {
1367         int ret;
1368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369         struct smu_context *smu = &adev->smu;
1370         bool baco_feature_is_enabled = false;
1371
1372         if(!(adev->flags & AMD_IS_APU))
1373                 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1374
1375         ret = smu_system_features_control(smu, false);
1376         if (ret)
1377                 return ret;
1378
1379         if (adev->in_gpu_reset && baco_feature_is_enabled) {
1380                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1381                 if (ret) {
1382                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1383                         return ret;
1384                 }
1385         }
1386
1387         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1388
1389         if (adev->asic_type >= CHIP_NAVI10 &&
1390             adev->gfx.rlc.funcs->stop)
1391                 adev->gfx.rlc.funcs->stop(adev);
1392         if (smu->is_apu)
1393                 smu_set_gfx_cgpg(&adev->smu, false);
1394
1395         return 0;
1396 }
1397
1398 static int smu_resume(void *handle)
1399 {
1400         int ret;
1401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1402         struct smu_context *smu = &adev->smu;
1403
1404         pr_info("SMU is resuming...\n");
1405
1406         ret = smu_start_smc_engine(smu);
1407         if (ret) {
1408                 pr_err("SMU is not ready yet!\n");
1409                 goto failed;
1410         }
1411
1412         ret = smu_smc_table_hw_init(smu, false);
1413         if (ret)
1414                 goto failed;
1415
1416         ret = smu_start_thermal_control(smu);
1417         if (ret)
1418                 goto failed;
1419
1420         if (smu->is_apu)
1421                 smu_set_gfx_cgpg(&adev->smu, true);
1422
1423         smu->disable_uclk_switch = 0;
1424
1425         pr_info("SMU is resumed successfully!\n");
1426
1427         return 0;
1428
1429 failed:
1430         return ret;
1431 }
1432
1433 int smu_display_configuration_change(struct smu_context *smu,
1434                                      const struct amd_pp_display_configuration *display_config)
1435 {
1436         int index = 0;
1437         int num_of_active_display = 0;
1438
1439         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1440                 return -EINVAL;
1441
1442         if (!display_config)
1443                 return -EINVAL;
1444
1445         mutex_lock(&smu->mutex);
1446
1447         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1448                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1449                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1450
1451         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1452                 if (display_config->displays[index].controller_id != 0)
1453                         num_of_active_display++;
1454         }
1455
1456         smu_set_active_display_count(smu, num_of_active_display);
1457
1458         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1459                            display_config->cpu_cc6_disable,
1460                            display_config->cpu_pstate_disable,
1461                            display_config->nb_pstate_switch_disable);
1462
1463         mutex_unlock(&smu->mutex);
1464
1465         return 0;
1466 }
1467
1468 static int smu_get_clock_info(struct smu_context *smu,
1469                               struct smu_clock_info *clk_info,
1470                               enum smu_perf_level_designation designation)
1471 {
1472         int ret;
1473         struct smu_performance_level level = {0};
1474
1475         if (!clk_info)
1476                 return -EINVAL;
1477
1478         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1479         if (ret)
1480                 return -EINVAL;
1481
1482         clk_info->min_mem_clk = level.memory_clock;
1483         clk_info->min_eng_clk = level.core_clock;
1484         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1485
1486         ret = smu_get_perf_level(smu, designation, &level);
1487         if (ret)
1488                 return -EINVAL;
1489
1490         clk_info->min_mem_clk = level.memory_clock;
1491         clk_info->min_eng_clk = level.core_clock;
1492         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1493
1494         return 0;
1495 }
1496
1497 int smu_get_current_clocks(struct smu_context *smu,
1498                            struct amd_pp_clock_info *clocks)
1499 {
1500         struct amd_pp_simple_clock_info simple_clocks = {0};
1501         struct smu_clock_info hw_clocks;
1502         int ret = 0;
1503
1504         if (!is_support_sw_smu(smu->adev))
1505                 return -EINVAL;
1506
1507         mutex_lock(&smu->mutex);
1508
1509         smu_get_dal_power_level(smu, &simple_clocks);
1510
1511         if (smu->support_power_containment)
1512                 ret = smu_get_clock_info(smu, &hw_clocks,
1513                                          PERF_LEVEL_POWER_CONTAINMENT);
1514         else
1515                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1516
1517         if (ret) {
1518                 pr_err("Error in smu_get_clock_info\n");
1519                 goto failed;
1520         }
1521
1522         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1523         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1524         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1525         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1526         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1527         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1528         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1529         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1530
1531         if (simple_clocks.level == 0)
1532                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1533         else
1534                 clocks->max_clocks_state = simple_clocks.level;
1535
1536         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1537                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1538                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1539         }
1540
1541 failed:
1542         mutex_unlock(&smu->mutex);
1543         return ret;
1544 }
1545
1546 static int smu_set_clockgating_state(void *handle,
1547                                      enum amd_clockgating_state state)
1548 {
1549         return 0;
1550 }
1551
1552 static int smu_set_powergating_state(void *handle,
1553                                      enum amd_powergating_state state)
1554 {
1555         return 0;
1556 }
1557
1558 static int smu_enable_umd_pstate(void *handle,
1559                       enum amd_dpm_forced_level *level)
1560 {
1561         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1562                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1563                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1564                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1565
1566         struct smu_context *smu = (struct smu_context*)(handle);
1567         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1568
1569         if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1570                 return -EINVAL;
1571
1572         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1573                 /* enter umd pstate, save current level, disable gfx cg*/
1574                 if (*level & profile_mode_mask) {
1575                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1576                         smu_dpm_ctx->enable_umd_pstate = true;
1577                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1578                                                                AMD_IP_BLOCK_TYPE_GFX,
1579                                                                AMD_CG_STATE_UNGATE);
1580                         amdgpu_device_ip_set_powergating_state(smu->adev,
1581                                                                AMD_IP_BLOCK_TYPE_GFX,
1582                                                                AMD_PG_STATE_UNGATE);
1583                 }
1584         } else {
1585                 /* exit umd pstate, restore level, enable gfx cg*/
1586                 if (!(*level & profile_mode_mask)) {
1587                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1588                                 *level = smu_dpm_ctx->saved_dpm_level;
1589                         smu_dpm_ctx->enable_umd_pstate = false;
1590                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1591                                                                AMD_IP_BLOCK_TYPE_GFX,
1592                                                                AMD_CG_STATE_GATE);
1593                         amdgpu_device_ip_set_powergating_state(smu->adev,
1594                                                                AMD_IP_BLOCK_TYPE_GFX,
1595                                                                AMD_PG_STATE_GATE);
1596                 }
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1603 {
1604         int ret = 0;
1605         uint32_t sclk_mask, mclk_mask, soc_mask;
1606
1607         switch (level) {
1608         case AMD_DPM_FORCED_LEVEL_HIGH:
1609                 ret = smu_force_dpm_limit_value(smu, true);
1610                 break;
1611         case AMD_DPM_FORCED_LEVEL_LOW:
1612                 ret = smu_force_dpm_limit_value(smu, false);
1613                 break;
1614         case AMD_DPM_FORCED_LEVEL_AUTO:
1615         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1616                 ret = smu_unforce_dpm_levels(smu);
1617                 break;
1618         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1619         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1620         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1621                 ret = smu_get_profiling_clk_mask(smu, level,
1622                                                  &sclk_mask,
1623                                                  &mclk_mask,
1624                                                  &soc_mask);
1625                 if (ret)
1626                         return ret;
1627                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1628                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1629                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1630                 break;
1631         case AMD_DPM_FORCED_LEVEL_MANUAL:
1632         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1633         default:
1634                 break;
1635         }
1636         return ret;
1637 }
1638
1639 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1640                                    enum amd_dpm_forced_level level,
1641                                    bool skip_display_settings)
1642 {
1643         int ret = 0;
1644         int index = 0;
1645         long workload;
1646         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1647
1648         if (!smu->pm_enabled)
1649                 return -EINVAL;
1650
1651         if (!skip_display_settings) {
1652                 ret = smu_display_config_changed(smu);
1653                 if (ret) {
1654                         pr_err("Failed to change display config!");
1655                         return ret;
1656                 }
1657         }
1658
1659         ret = smu_apply_clocks_adjust_rules(smu);
1660         if (ret) {
1661                 pr_err("Failed to apply clocks adjust rules!");
1662                 return ret;
1663         }
1664
1665         if (!skip_display_settings) {
1666                 ret = smu_notify_smc_dispaly_config(smu);
1667                 if (ret) {
1668                         pr_err("Failed to notify smc display config!");
1669                         return ret;
1670                 }
1671         }
1672
1673         if (smu_dpm_ctx->dpm_level != level) {
1674                 ret = smu_asic_set_performance_level(smu, level);
1675                 if (ret) {
1676                         ret = smu_default_set_performance_level(smu, level);
1677                         if (ret) {
1678                                 pr_err("Failed to set performance level!");
1679                                 return ret;
1680                         }
1681                 }
1682
1683                 /* update the saved copy */
1684                 smu_dpm_ctx->dpm_level = level;
1685         }
1686
1687         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1688                 index = fls(smu->workload_mask);
1689                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1690                 workload = smu->workload_setting[index];
1691
1692                 if (smu->power_profile_mode != workload)
1693                         smu_set_power_profile_mode(smu, &workload, 0, false);
1694         }
1695
1696         return ret;
1697 }
1698
1699 int smu_handle_task(struct smu_context *smu,
1700                     enum amd_dpm_forced_level level,
1701                     enum amd_pp_task task_id,
1702                     bool lock_needed)
1703 {
1704         int ret = 0;
1705
1706         if (lock_needed)
1707                 mutex_lock(&smu->mutex);
1708
1709         switch (task_id) {
1710         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1711                 ret = smu_pre_display_config_changed(smu);
1712                 if (ret)
1713                         goto out;
1714                 ret = smu_set_cpu_power_state(smu);
1715                 if (ret)
1716                         goto out;
1717                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1718                 break;
1719         case AMD_PP_TASK_COMPLETE_INIT:
1720         case AMD_PP_TASK_READJUST_POWER_STATE:
1721                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1722                 break;
1723         default:
1724                 break;
1725         }
1726
1727 out:
1728         if (lock_needed)
1729                 mutex_unlock(&smu->mutex);
1730
1731         return ret;
1732 }
1733
1734 int smu_switch_power_profile(struct smu_context *smu,
1735                              enum PP_SMC_POWER_PROFILE type,
1736                              bool en)
1737 {
1738         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1739         long workload;
1740         uint32_t index;
1741
1742         if (!smu->pm_enabled)
1743                 return -EINVAL;
1744
1745         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1746                 return -EINVAL;
1747
1748         mutex_lock(&smu->mutex);
1749
1750         if (!en) {
1751                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1752                 index = fls(smu->workload_mask);
1753                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1754                 workload = smu->workload_setting[index];
1755         } else {
1756                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1757                 index = fls(smu->workload_mask);
1758                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1759                 workload = smu->workload_setting[index];
1760         }
1761
1762         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1763                 smu_set_power_profile_mode(smu, &workload, 0, false);
1764
1765         mutex_unlock(&smu->mutex);
1766
1767         return 0;
1768 }
1769
1770 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1771 {
1772         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1773         enum amd_dpm_forced_level level;
1774
1775         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1776                 return -EINVAL;
1777
1778         mutex_lock(&(smu->mutex));
1779         level = smu_dpm_ctx->dpm_level;
1780         mutex_unlock(&(smu->mutex));
1781
1782         return level;
1783 }
1784
1785 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1786 {
1787         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1788         int ret = 0;
1789
1790         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1791                 return -EINVAL;
1792
1793         mutex_lock(&smu->mutex);
1794
1795         ret = smu_enable_umd_pstate(smu, &level);
1796         if (ret) {
1797                 mutex_unlock(&smu->mutex);
1798                 return ret;
1799         }
1800
1801         ret = smu_handle_task(smu, level,
1802                               AMD_PP_TASK_READJUST_POWER_STATE,
1803                               false);
1804
1805         mutex_unlock(&smu->mutex);
1806
1807         return ret;
1808 }
1809
1810 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1811 {
1812         int ret = 0;
1813
1814         mutex_lock(&smu->mutex);
1815         ret = smu_init_display_count(smu, count);
1816         mutex_unlock(&smu->mutex);
1817
1818         return ret;
1819 }
1820
1821 int smu_force_clk_levels(struct smu_context *smu,
1822                          enum smu_clk_type clk_type,
1823                          uint32_t mask,
1824                          bool lock_needed)
1825 {
1826         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1827         int ret = 0;
1828
1829         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1830                 pr_debug("force clock level is for dpm manual mode only.\n");
1831                 return -EINVAL;
1832         }
1833
1834         if (lock_needed)
1835                 mutex_lock(&smu->mutex);
1836
1837         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1838                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1839
1840         if (lock_needed)
1841                 mutex_unlock(&smu->mutex);
1842
1843         return ret;
1844 }
1845
1846 int smu_set_mp1_state(struct smu_context *smu,
1847                       enum pp_mp1_state mp1_state)
1848 {
1849         uint16_t msg;
1850         int ret;
1851
1852         /*
1853          * The SMC is not fully ready. That may be
1854          * expected as the IP may be masked.
1855          * So, just return without error.
1856          */
1857         if (!smu->pm_enabled)
1858                 return 0;
1859
1860         mutex_lock(&smu->mutex);
1861
1862         switch (mp1_state) {
1863         case PP_MP1_STATE_SHUTDOWN:
1864                 msg = SMU_MSG_PrepareMp1ForShutdown;
1865                 break;
1866         case PP_MP1_STATE_UNLOAD:
1867                 msg = SMU_MSG_PrepareMp1ForUnload;
1868                 break;
1869         case PP_MP1_STATE_RESET:
1870                 msg = SMU_MSG_PrepareMp1ForReset;
1871                 break;
1872         case PP_MP1_STATE_NONE:
1873         default:
1874                 mutex_unlock(&smu->mutex);
1875                 return 0;
1876         }
1877
1878         /* some asics may not support those messages */
1879         if (smu_msg_get_index(smu, msg) < 0) {
1880                 mutex_unlock(&smu->mutex);
1881                 return 0;
1882         }
1883
1884         ret = smu_send_smc_msg(smu, msg);
1885         if (ret)
1886                 pr_err("[PrepareMp1] Failed!\n");
1887
1888         mutex_unlock(&smu->mutex);
1889
1890         return ret;
1891 }
1892
1893 int smu_set_df_cstate(struct smu_context *smu,
1894                       enum pp_df_cstate state)
1895 {
1896         int ret = 0;
1897
1898         /*
1899          * The SMC is not fully ready. That may be
1900          * expected as the IP may be masked.
1901          * So, just return without error.
1902          */
1903         if (!smu->pm_enabled)
1904                 return 0;
1905
1906         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1907                 return 0;
1908
1909         mutex_lock(&smu->mutex);
1910
1911         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1912         if (ret)
1913                 pr_err("[SetDfCstate] failed!\n");
1914
1915         mutex_unlock(&smu->mutex);
1916
1917         return ret;
1918 }
1919
1920 int smu_write_watermarks_table(struct smu_context *smu)
1921 {
1922         int ret = 0;
1923         struct smu_table_context *smu_table = &smu->smu_table;
1924         struct smu_table *table = NULL;
1925
1926         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
1927
1928         if (!table->cpu_addr)
1929                 return -EINVAL;
1930
1931         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
1932                                 true);
1933
1934         return ret;
1935 }
1936
1937 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1938                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1939 {
1940         int ret = 0;
1941         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1942         void *table = watermarks->cpu_addr;
1943
1944         mutex_lock(&smu->mutex);
1945
1946         if (!smu->disable_watermark &&
1947                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1948                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1949                 smu_set_watermarks_table(smu, table, clock_ranges);
1950                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1951                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1952         }
1953
1954         mutex_unlock(&smu->mutex);
1955
1956         return ret;
1957 }
1958
1959 const struct amd_ip_funcs smu_ip_funcs = {
1960         .name = "smu",
1961         .early_init = smu_early_init,
1962         .late_init = smu_late_init,
1963         .sw_init = smu_sw_init,
1964         .sw_fini = smu_sw_fini,
1965         .hw_init = smu_hw_init,
1966         .hw_fini = smu_hw_fini,
1967         .suspend = smu_suspend,
1968         .resume = smu_resume,
1969         .is_idle = NULL,
1970         .check_soft_reset = NULL,
1971         .wait_for_idle = NULL,
1972         .soft_reset = NULL,
1973         .set_clockgating_state = smu_set_clockgating_state,
1974         .set_powergating_state = smu_set_powergating_state,
1975         .enable_umd_pstate = smu_enable_umd_pstate,
1976 };
1977
1978 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1979 {
1980         .type = AMD_IP_BLOCK_TYPE_SMC,
1981         .major = 11,
1982         .minor = 0,
1983         .rev = 0,
1984         .funcs = &smu_ip_funcs,
1985 };
1986
1987 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1988 {
1989         .type = AMD_IP_BLOCK_TYPE_SMC,
1990         .major = 12,
1991         .minor = 0,
1992         .rev = 0,
1993         .funcs = &smu_ip_funcs,
1994 };
1995
1996 int smu_load_microcode(struct smu_context *smu)
1997 {
1998         int ret = 0;
1999
2000         mutex_lock(&smu->mutex);
2001
2002         if (smu->ppt_funcs->load_microcode)
2003                 ret = smu->ppt_funcs->load_microcode(smu);
2004
2005         mutex_unlock(&smu->mutex);
2006
2007         return ret;
2008 }
2009
2010 int smu_check_fw_status(struct smu_context *smu)
2011 {
2012         int ret = 0;
2013
2014         mutex_lock(&smu->mutex);
2015
2016         if (smu->ppt_funcs->check_fw_status)
2017                 ret = smu->ppt_funcs->check_fw_status(smu);
2018
2019         mutex_unlock(&smu->mutex);
2020
2021         return ret;
2022 }
2023
2024 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2025 {
2026         int ret = 0;
2027
2028         mutex_lock(&smu->mutex);
2029
2030         if (smu->ppt_funcs->set_gfx_cgpg)
2031                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2032
2033         mutex_unlock(&smu->mutex);
2034
2035         return ret;
2036 }
2037
2038 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2039 {
2040         int ret = 0;
2041
2042         mutex_lock(&smu->mutex);
2043
2044         if (smu->ppt_funcs->set_fan_speed_rpm)
2045                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2046
2047         mutex_unlock(&smu->mutex);
2048
2049         return ret;
2050 }
2051
2052 int smu_get_power_limit(struct smu_context *smu,
2053                         uint32_t *limit,
2054                         bool def,
2055                         bool lock_needed)
2056 {
2057         int ret = 0;
2058
2059         if (lock_needed)
2060                 mutex_lock(&smu->mutex);
2061
2062         if (smu->ppt_funcs->get_power_limit)
2063                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2064
2065         if (lock_needed)
2066                 mutex_unlock(&smu->mutex);
2067
2068         return ret;
2069 }
2070
2071 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2072 {
2073         int ret = 0;
2074
2075         mutex_lock(&smu->mutex);
2076
2077         if (smu->ppt_funcs->set_power_limit)
2078                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2079
2080         mutex_unlock(&smu->mutex);
2081
2082         return ret;
2083 }
2084
2085 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2086 {
2087         int ret = 0;
2088
2089         mutex_lock(&smu->mutex);
2090
2091         if (smu->ppt_funcs->print_clk_levels)
2092                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2093
2094         mutex_unlock(&smu->mutex);
2095
2096         return ret;
2097 }
2098
2099 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2100 {
2101         int ret = 0;
2102
2103         mutex_lock(&smu->mutex);
2104
2105         if (smu->ppt_funcs->get_od_percentage)
2106                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2107
2108         mutex_unlock(&smu->mutex);
2109
2110         return ret;
2111 }
2112
2113 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2114 {
2115         int ret = 0;
2116
2117         mutex_lock(&smu->mutex);
2118
2119         if (smu->ppt_funcs->set_od_percentage)
2120                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2121
2122         mutex_unlock(&smu->mutex);
2123
2124         return ret;
2125 }
2126
2127 int smu_od_edit_dpm_table(struct smu_context *smu,
2128                           enum PP_OD_DPM_TABLE_COMMAND type,
2129                           long *input, uint32_t size)
2130 {
2131         int ret = 0;
2132
2133         mutex_lock(&smu->mutex);
2134
2135         if (smu->ppt_funcs->od_edit_dpm_table)
2136                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2137
2138         mutex_unlock(&smu->mutex);
2139
2140         return ret;
2141 }
2142
2143 int smu_read_sensor(struct smu_context *smu,
2144                     enum amd_pp_sensors sensor,
2145                     void *data, uint32_t *size)
2146 {
2147         int ret = 0;
2148
2149         mutex_lock(&smu->mutex);
2150
2151         if (smu->ppt_funcs->read_sensor)
2152                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2153
2154         mutex_unlock(&smu->mutex);
2155
2156         return ret;
2157 }
2158
2159 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2160 {
2161         int ret = 0;
2162
2163         mutex_lock(&smu->mutex);
2164
2165         if (smu->ppt_funcs->get_power_profile_mode)
2166                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2167
2168         mutex_unlock(&smu->mutex);
2169
2170         return ret;
2171 }
2172
2173 int smu_set_power_profile_mode(struct smu_context *smu,
2174                                long *param,
2175                                uint32_t param_size,
2176                                bool lock_needed)
2177 {
2178         int ret = 0;
2179
2180         if (lock_needed)
2181                 mutex_lock(&smu->mutex);
2182
2183         if (smu->ppt_funcs->set_power_profile_mode)
2184                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2185
2186         if (lock_needed)
2187                 mutex_unlock(&smu->mutex);
2188
2189         return ret;
2190 }
2191
2192
2193 int smu_get_fan_control_mode(struct smu_context *smu)
2194 {
2195         int ret = 0;
2196
2197         mutex_lock(&smu->mutex);
2198
2199         if (smu->ppt_funcs->get_fan_control_mode)
2200                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2201
2202         mutex_unlock(&smu->mutex);
2203
2204         return ret;
2205 }
2206
2207 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2208 {
2209         int ret = 0;
2210
2211         mutex_lock(&smu->mutex);
2212
2213         if (smu->ppt_funcs->set_fan_control_mode)
2214                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2215
2216         mutex_unlock(&smu->mutex);
2217
2218         return ret;
2219 }
2220
2221 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2222 {
2223         int ret = 0;
2224
2225         mutex_lock(&smu->mutex);
2226
2227         if (smu->ppt_funcs->get_fan_speed_percent)
2228                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2229
2230         mutex_unlock(&smu->mutex);
2231
2232         return ret;
2233 }
2234
2235 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2236 {
2237         int ret = 0;
2238
2239         mutex_lock(&smu->mutex);
2240
2241         if (smu->ppt_funcs->set_fan_speed_percent)
2242                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2243
2244         mutex_unlock(&smu->mutex);
2245
2246         return ret;
2247 }
2248
2249 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2250 {
2251         int ret = 0;
2252
2253         mutex_lock(&smu->mutex);
2254
2255         if (smu->ppt_funcs->get_fan_speed_rpm)
2256                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2257
2258         mutex_unlock(&smu->mutex);
2259
2260         return ret;
2261 }
2262
2263 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2264 {
2265         int ret = 0;
2266
2267         mutex_lock(&smu->mutex);
2268
2269         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2270                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2271
2272         mutex_unlock(&smu->mutex);
2273
2274         return ret;
2275 }
2276
2277 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2278 {
2279         int ret = 0;
2280
2281         mutex_lock(&smu->mutex);
2282
2283         if (smu->ppt_funcs->set_active_display_count)
2284                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2285
2286         mutex_unlock(&smu->mutex);
2287
2288         return ret;
2289 }
2290
2291 int smu_get_clock_by_type(struct smu_context *smu,
2292                           enum amd_pp_clock_type type,
2293                           struct amd_pp_clocks *clocks)
2294 {
2295         int ret = 0;
2296
2297         mutex_lock(&smu->mutex);
2298
2299         if (smu->ppt_funcs->get_clock_by_type)
2300                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2301
2302         mutex_unlock(&smu->mutex);
2303
2304         return ret;
2305 }
2306
2307 int smu_get_max_high_clocks(struct smu_context *smu,
2308                             struct amd_pp_simple_clock_info *clocks)
2309 {
2310         int ret = 0;
2311
2312         mutex_lock(&smu->mutex);
2313
2314         if (smu->ppt_funcs->get_max_high_clocks)
2315                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2316
2317         mutex_unlock(&smu->mutex);
2318
2319         return ret;
2320 }
2321
2322 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2323                                        enum smu_clk_type clk_type,
2324                                        struct pp_clock_levels_with_latency *clocks)
2325 {
2326         int ret = 0;
2327
2328         mutex_lock(&smu->mutex);
2329
2330         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2331                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2332
2333         mutex_unlock(&smu->mutex);
2334
2335         return ret;
2336 }
2337
2338 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2339                                        enum amd_pp_clock_type type,
2340                                        struct pp_clock_levels_with_voltage *clocks)
2341 {
2342         int ret = 0;
2343
2344         mutex_lock(&smu->mutex);
2345
2346         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2347                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2348
2349         mutex_unlock(&smu->mutex);
2350
2351         return ret;
2352 }
2353
2354
2355 int smu_display_clock_voltage_request(struct smu_context *smu,
2356                                       struct pp_display_clock_request *clock_req)
2357 {
2358         int ret = 0;
2359
2360         mutex_lock(&smu->mutex);
2361
2362         if (smu->ppt_funcs->display_clock_voltage_request)
2363                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2364
2365         mutex_unlock(&smu->mutex);
2366
2367         return ret;
2368 }
2369
2370
2371 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2372 {
2373         int ret = -EINVAL;
2374
2375         mutex_lock(&smu->mutex);
2376
2377         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2378                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2379
2380         mutex_unlock(&smu->mutex);
2381
2382         return ret;
2383 }
2384
2385 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2386 {
2387         int ret = 0;
2388
2389         mutex_lock(&smu->mutex);
2390
2391         if (smu->ppt_funcs->notify_smu_enable_pwe)
2392                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2393
2394         mutex_unlock(&smu->mutex);
2395
2396         return ret;
2397 }
2398
2399 int smu_set_xgmi_pstate(struct smu_context *smu,
2400                         uint32_t pstate)
2401 {
2402         int ret = 0;
2403
2404         mutex_lock(&smu->mutex);
2405
2406         if (smu->ppt_funcs->set_xgmi_pstate)
2407                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2408
2409         mutex_unlock(&smu->mutex);
2410
2411         return ret;
2412 }
2413
2414 int smu_set_azalia_d3_pme(struct smu_context *smu)
2415 {
2416         int ret = 0;
2417
2418         mutex_lock(&smu->mutex);
2419
2420         if (smu->ppt_funcs->set_azalia_d3_pme)
2421                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2422
2423         mutex_unlock(&smu->mutex);
2424
2425         return ret;
2426 }
2427
2428 bool smu_baco_is_support(struct smu_context *smu)
2429 {
2430         bool ret = false;
2431
2432         mutex_lock(&smu->mutex);
2433
2434         if (smu->ppt_funcs->baco_is_support)
2435                 ret = smu->ppt_funcs->baco_is_support(smu);
2436
2437         mutex_unlock(&smu->mutex);
2438
2439         return ret;
2440 }
2441
2442 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2443 {
2444         if (smu->ppt_funcs->baco_get_state)
2445                 return -EINVAL;
2446
2447         mutex_lock(&smu->mutex);
2448         *state = smu->ppt_funcs->baco_get_state(smu);
2449         mutex_unlock(&smu->mutex);
2450
2451         return 0;
2452 }
2453
2454 int smu_baco_reset(struct smu_context *smu)
2455 {
2456         int ret = 0;
2457
2458         mutex_lock(&smu->mutex);
2459
2460         if (smu->ppt_funcs->baco_reset)
2461                 ret = smu->ppt_funcs->baco_reset(smu);
2462
2463         mutex_unlock(&smu->mutex);
2464
2465         return ret;
2466 }
2467
2468 int smu_mode2_reset(struct smu_context *smu)
2469 {
2470         int ret = 0;
2471
2472         mutex_lock(&smu->mutex);
2473
2474         if (smu->ppt_funcs->mode2_reset)
2475                 ret = smu->ppt_funcs->mode2_reset(smu);
2476
2477         mutex_unlock(&smu->mutex);
2478
2479         return ret;
2480 }
2481
2482 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2483                                          struct pp_smu_nv_clock_table *max_clocks)
2484 {
2485         int ret = 0;
2486
2487         mutex_lock(&smu->mutex);
2488
2489         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2490                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2491
2492         mutex_unlock(&smu->mutex);
2493
2494         return ret;
2495 }
2496
2497 int smu_get_uclk_dpm_states(struct smu_context *smu,
2498                             unsigned int *clock_values_in_khz,
2499                             unsigned int *num_states)
2500 {
2501         int ret = 0;
2502
2503         mutex_lock(&smu->mutex);
2504
2505         if (smu->ppt_funcs->get_uclk_dpm_states)
2506                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2507
2508         mutex_unlock(&smu->mutex);
2509
2510         return ret;
2511 }
2512
2513 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2514 {
2515         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2516
2517         mutex_lock(&smu->mutex);
2518
2519         if (smu->ppt_funcs->get_current_power_state)
2520                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2521
2522         mutex_unlock(&smu->mutex);
2523
2524         return pm_state;
2525 }
2526
2527 int smu_get_dpm_clock_table(struct smu_context *smu,
2528                             struct dpm_clocks *clock_table)
2529 {
2530         int ret = 0;
2531
2532         mutex_lock(&smu->mutex);
2533
2534         if (smu->ppt_funcs->get_dpm_clock_table)
2535                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2536
2537         mutex_unlock(&smu->mutex);
2538
2539         return ret;
2540 }
2541
2542 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2543 {
2544         uint32_t ret = 0;
2545
2546         if (smu->ppt_funcs->get_pptable_power_limit)
2547                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2548
2549         return ret;
2550 }
2551
2552 int smu_send_smc_msg(struct smu_context *smu,
2553                      enum smu_message_type msg)
2554 {
2555         int ret;
2556
2557         ret = smu_send_smc_msg_with_param(smu, msg, 0);
2558         return ret;
2559 }