drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "soc15_common.h"
  30 #include "smu_v11_0.h"
  31 #include "smu_v12_0.h"
  32 #include "atom.h"
  33 #include "amd_pcie.h"
  34 #include "vega20_ppt.h"
  35 #include "arcturus_ppt.h"
  36 #include "navi10_ppt.h"
  37 #include "renoir_ppt.h"
  38
  39 #undef __SMU_DUMMY_MAP
  40 #define __SMU_DUMMY_MAP(type)   #type
  41 static const char* __smu_message_names[] = {
  42         SMU_MESSAGE_TYPES
  43 };
  44
  45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  46 {
  47         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  48                 return "unknown smu message";
  49         return __smu_message_names[type];
  50 }
  51
  52 #undef __SMU_DUMMY_MAP
  53 #define __SMU_DUMMY_MAP(fea)    #fea
  54 static const char* __smu_feature_names[] = {
  55         SMU_FEATURE_MASKS
  56 };
  57
  58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  59 {
  60         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  61                 return "unknown smu feature";
  62         return __smu_feature_names[feature];
  63 }
  64
  65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  66 {
  67         size_t size = 0;
  68         int ret = 0, i = 0;
  69         uint32_t feature_mask[2] = { 0 };
  70         int32_t feature_index = 0;
  71         uint32_t count = 0;
  72         uint32_t sort_feature[SMU_FEATURE_COUNT];
  73         uint64_t hw_feature_count = 0;
  74
  75         mutex_lock(&smu->mutex);
  76
  77         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  78         if (ret)
  79                 goto failed;
  80
  81         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  82                         feature_mask[1], feature_mask[0]);
  83
  84         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  85                 feature_index = smu_feature_get_index(smu, i);
  86                 if (feature_index < 0)
  87                         continue;
  88                 sort_feature[feature_index] = i;
  89                 hw_feature_count++;
  90         }
  91
  92         for (i = 0; i < hw_feature_count; i++) {
  93                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  94                                count++,
  95                                smu_get_feature_name(smu, sort_feature[i]),
  96                                i,
  97                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  98                                "enabled" : "disabled");
  99         }
 100
 101 failed:
 102         mutex_unlock(&smu->mutex);
 103
 104         return size;
 105 }
 106
 107 static int smu_feature_update_enable_state(struct smu_context *smu,
 108                                            uint64_t feature_mask,
 109                                            bool enabled)
 110 {
 111         struct smu_feature *feature = &smu->smu_feature;
 112         uint32_t feature_low = 0, feature_high = 0;
 113         int ret = 0;
 114
 115         if (!smu->pm_enabled)
 116                 return ret;
 117
 118         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 119         feature_high = (feature_mask >> 32) & 0xffffffff;
 120
 121         if (enabled) {
 122                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 123                                                   feature_low);
 124                 if (ret)
 125                         return ret;
 126                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 127                                                   feature_high);
 128                 if (ret)
 129                         return ret;
 130         } else {
 131                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 132                                                   feature_low);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 136                                                   feature_high);
 137                 if (ret)
 138                         return ret;
 139         }
 140
 141         mutex_lock(&feature->mutex);
 142         if (enabled)
 143                 bitmap_or(feature->enabled, feature->enabled,
 144                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 145         else
 146                 bitmap_andnot(feature->enabled, feature->enabled,
 147                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 148         mutex_unlock(&feature->mutex);
 149
 150         return ret;
 151 }
 152
 153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 154 {
 155         int ret = 0;
 156         uint32_t feature_mask[2] = { 0 };
 157         uint64_t feature_2_enabled = 0;
 158         uint64_t feature_2_disabled = 0;
 159         uint64_t feature_enables = 0;
 160
 161         mutex_lock(&smu->mutex);
 162
 163         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 164         if (ret)
 165                 goto out;
 166
 167         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 168
 169         feature_2_enabled  = ~feature_enables & new_mask;
 170         feature_2_disabled = feature_enables & ~new_mask;
 171
 172         if (feature_2_enabled) {
 173                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 174                 if (ret)
 175                         goto out;
 176         }
 177         if (feature_2_disabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 179                 if (ret)
 180                         goto out;
 181         }
 182
 183 out:
 184         mutex_unlock(&smu->mutex);
 185
 186         return ret;
 187 }
 188
 189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 190 {
 191         int ret = 0;
 192
 193         if (!if_version && !smu_version)
 194                 return -EINVAL;
 195
 196         if (if_version) {
 197                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 198                 if (ret)
 199                         return ret;
 200
 201                 ret = smu_read_smc_arg(smu, if_version);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         if (smu_version) {
 207                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 208                 if (ret)
 209                         return ret;
 210
 211                 ret = smu_read_smc_arg(smu, smu_version);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return ret;
 217 }
 218
 219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 220                             uint32_t min, uint32_t max)
 221 {
 222         int ret = 0;
 223
 224         if (min <= 0 && max <= 0)
 225                 return -EINVAL;
 226
 227         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 228                 return 0;
 229
 230         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 231         return ret;
 232 }
 233
 234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 235                             uint32_t min, uint32_t max)
 236 {
 237         int ret = 0, clk_id = 0;
 238         uint32_t param;
 239
 240         if (min <= 0 && max <= 0)
 241                 return -EINVAL;
 242
 243         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 244                 return 0;
 245
 246         clk_id = smu_clk_get_index(smu, clk_type);
 247         if (clk_id < 0)
 248                 return clk_id;
 249
 250         if (max > 0) {
 251                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 252                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 253                                                   param);
 254                 if (ret)
 255                         return ret;
 256         }
 257
 258         if (min > 0) {
 259                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 260                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 261                                                   param);
 262                 if (ret)
 263                         return ret;
 264         }
 265
 266
 267         return ret;
 268 }
 269
 270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 271                            uint32_t *min, uint32_t *max, bool lock_needed)
 272 {
 273         uint32_t clock_limit;
 274         int ret = 0;
 275
 276         if (!min && !max)
 277                 return -EINVAL;
 278
 279         if (lock_needed)
 280                 mutex_lock(&smu->mutex);
 281
 282         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 283                 switch (clk_type) {
 284                 case SMU_MCLK:
 285                 case SMU_UCLK:
 286                         clock_limit = smu->smu_table.boot_values.uclk;
 287                         break;
 288                 case SMU_GFXCLK:
 289                 case SMU_SCLK:
 290                         clock_limit = smu->smu_table.boot_values.gfxclk;
 291                         break;
 292                 case SMU_SOCCLK:
 293                         clock_limit = smu->smu_table.boot_values.socclk;
 294                         break;
 295                 default:
 296                         clock_limit = 0;
 297                         break;
 298                 }
 299
 300                 /* clock in Mhz unit */
 301                 if (min)
 302                         *min = clock_limit / 100;
 303                 if (max)
 304                         *max = clock_limit / 100;
 305         } else {
 306                 /*
 307                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 308                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 309                  */
 310                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 311         }
 312
 313         if (lock_needed)
 314                 mutex_unlock(&smu->mutex);
 315
 316         return ret;
 317 }
 318
 319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 320                               uint16_t level, uint32_t *value)
 321 {
 322         int ret = 0, clk_id = 0;
 323         uint32_t param;
 324
 325         if (!value)
 326                 return -EINVAL;
 327
 328         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 329                 return 0;
 330
 331         clk_id = smu_clk_get_index(smu, clk_type);
 332         if (clk_id < 0)
 333                 return clk_id;
 334
 335         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 336
 337         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 338                                           param);
 339         if (ret)
 340                 return ret;
 341
 342         ret = smu_read_smc_arg(smu, &param);
 343         if (ret)
 344                 return ret;
 345
 346         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 347          * now, we un-support it */
 348         *value = param & 0x7fffffff;
 349
 350         return ret;
 351 }
 352
 353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 354                             uint32_t *value)
 355 {
 356         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 357 }
 358
 359 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 360 {
 361         enum smu_feature_mask feature_id = 0;
 362
 363         switch (clk_type) {
 364         case SMU_MCLK:
 365         case SMU_UCLK:
 366                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 367                 break;
 368         case SMU_GFXCLK:
 369         case SMU_SCLK:
 370                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 371                 break;
 372         case SMU_SOCCLK:
 373                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 374                 break;
 375         default:
 376                 return true;
 377         }
 378
 379         if(!smu_feature_is_enabled(smu, feature_id)) {
 380                 return false;
 381         }
 382
 383         return true;
 384 }
 385
 386 /**
 387  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 388  *
 389  * @smu:        smu_context pointer
 390  * @block_type: the IP block to power gate/ungate
 391  * @gate:       to power gate if true, ungate otherwise
 392  *
 393  * This API uses no smu->mutex lock protection due to:
 394  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 395  *    This is guarded to be race condition free by the caller.
 396  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 397  *    Under this case, the smu->mutex lock protection is already enforced on
 398  *    the parent API smu_force_performance_level of the call path.
 399  */
 400 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 401                            bool gate)
 402 {
 403         int ret = 0;
 404
 405         switch (block_type) {
 406         case AMD_IP_BLOCK_TYPE_UVD:
 407                 ret = smu_dpm_set_uvd_enable(smu, gate);
 408                 break;
 409         case AMD_IP_BLOCK_TYPE_VCE:
 410                 ret = smu_dpm_set_vce_enable(smu, gate);
 411                 break;
 412         case AMD_IP_BLOCK_TYPE_GFX:
 413                 ret = smu_gfx_off_control(smu, gate);
 414                 break;
 415         case AMD_IP_BLOCK_TYPE_SDMA:
 416                 ret = smu_powergate_sdma(smu, gate);
 417                 break;
 418         case AMD_IP_BLOCK_TYPE_JPEG:
 419                 ret = smu_dpm_set_jpeg_enable(smu, gate);
 420                 break;
 421         default:
 422                 break;
 423         }
 424
 425         return ret;
 426 }
 427
 428 int smu_get_power_num_states(struct smu_context *smu,
 429                              struct pp_states_info *state_info)
 430 {
 431         if (!state_info)
 432                 return -EINVAL;
 433
 434         /* not support power state */
 435         memset(state_info, 0, sizeof(struct pp_states_info));
 436         state_info->nums = 1;
 437         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 438
 439         return 0;
 440 }
 441
 442 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 443                            void *data, uint32_t *size)
 444 {
 445         struct smu_power_context *smu_power = &smu->smu_power;
 446         struct smu_power_gate *power_gate = &smu_power->power_gate;
 447         int ret = 0;
 448
 449         if(!data || !size)
 450                 return -EINVAL;
 451
 452         switch (sensor) {
 453         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 454                 *((uint32_t *)data) = smu->pstate_sclk;
 455                 *size = 4;
 456                 break;
 457         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 458                 *((uint32_t *)data) = smu->pstate_mclk;
 459                 *size = 4;
 460                 break;
 461         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 462                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 463                 *size = 8;
 464                 break;
 465         case AMDGPU_PP_SENSOR_UVD_POWER:
 466                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 467                 *size = 4;
 468                 break;
 469         case AMDGPU_PP_SENSOR_VCE_POWER:
 470                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 471                 *size = 4;
 472                 break;
 473         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 474                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 475                 *size = 4;
 476                 break;
 477         default:
 478                 ret = -EINVAL;
 479                 break;
 480         }
 481
 482         if (ret)
 483                 *size = 0;
 484
 485         return ret;
 486 }
 487
 488 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 489                      void *table_data, bool drv2smu)
 490 {
 491         struct smu_table_context *smu_table = &smu->smu_table;
 492         struct amdgpu_device *adev = smu->adev;
 493         struct smu_table *table = NULL;
 494         int ret = 0;
 495         int table_id = smu_table_get_index(smu, table_index);
 496
 497         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 498                 return -EINVAL;
 499
 500         table = &smu_table->tables[table_index];
 501
 502         if (drv2smu)
 503                 memcpy(table->cpu_addr, table_data, table->size);
 504
 505         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 506                                           upper_32_bits(table->mc_address));
 507         if (ret)
 508                 return ret;
 509         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 510                                           lower_32_bits(table->mc_address));
 511         if (ret)
 512                 return ret;
 513         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 514                                           SMU_MSG_TransferTableDram2Smu :
 515                                           SMU_MSG_TransferTableSmu2Dram,
 516                                           table_id | ((argument & 0xFFFF) << 16));
 517         if (ret)
 518                 return ret;
 519
 520         /* flush hdp cache */
 521         adev->nbio.funcs->hdp_flush(adev, NULL);
 522
 523         if (!drv2smu)
 524                 memcpy(table_data, table->cpu_addr, table->size);
 525
 526         return ret;
 527 }
 528
 529 bool is_support_sw_smu(struct amdgpu_device *adev)
 530 {
 531         if (adev->asic_type == CHIP_VEGA20)
 532                 return (amdgpu_dpm == 2) ? true : false;
 533         else if (adev->asic_type >= CHIP_ARCTURUS) {
 534                 if (amdgpu_sriov_vf(adev))
 535                         return false;
 536                 else
 537                         return true;
 538         } else
 539                 return false;
 540 }
 541
 542 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 543 {
 544         if (!is_support_sw_smu(adev))
 545                 return false;
 546
 547         if (adev->asic_type == CHIP_VEGA20)
 548                 return true;
 549
 550         return false;
 551 }
 552
 553 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 554 {
 555         struct smu_table_context *smu_table = &smu->smu_table;
 556         uint32_t powerplay_table_size;
 557
 558         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 559                 return -EINVAL;
 560
 561         mutex_lock(&smu->mutex);
 562
 563         if (smu_table->hardcode_pptable)
 564                 *table = smu_table->hardcode_pptable;
 565         else
 566                 *table = smu_table->power_play_table;
 567
 568         powerplay_table_size = smu_table->power_play_table_size;
 569
 570         mutex_unlock(&smu->mutex);
 571
 572         return powerplay_table_size;
 573 }
 574
 575 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 576 {
 577         struct smu_table_context *smu_table = &smu->smu_table;
 578         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 579         int ret = 0;
 580
 581         if (!smu->pm_enabled)
 582                 return -EINVAL;
 583         if (header->usStructureSize != size) {
 584                 pr_err("pp table size not matched !\n");
 585                 return -EIO;
 586         }
 587
 588         mutex_lock(&smu->mutex);
 589         if (!smu_table->hardcode_pptable)
 590                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 591         if (!smu_table->hardcode_pptable) {
 592                 ret = -ENOMEM;
 593                 goto failed;
 594         }
 595
 596         memcpy(smu_table->hardcode_pptable, buf, size);
 597         smu_table->power_play_table = smu_table->hardcode_pptable;
 598         smu_table->power_play_table_size = size;
 599
 600         /*
 601          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 602          * skipped) may be needed for custom pptable uploading.
 603          */
 604         smu->uploading_custom_pp_table = true;
 605
 606         ret = smu_reset(smu);
 607         if (ret)
 608                 pr_info("smu reset failed, ret = %d\n", ret);
 609
 610         smu->uploading_custom_pp_table = false;
 611
 612 failed:
 613         mutex_unlock(&smu->mutex);
 614         return ret;
 615 }
 616
 617 int smu_feature_init_dpm(struct smu_context *smu)
 618 {
 619         struct smu_feature *feature = &smu->smu_feature;
 620         int ret = 0;
 621         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 622
 623         if (!smu->pm_enabled)
 624                 return ret;
 625         mutex_lock(&feature->mutex);
 626         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 627         mutex_unlock(&feature->mutex);
 628
 629         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 630                                              SMU_FEATURE_MAX/32);
 631         if (ret)
 632                 return ret;
 633
 634         mutex_lock(&feature->mutex);
 635         bitmap_or(feature->allowed, feature->allowed,
 636                       (unsigned long *)allowed_feature_mask,
 637                       feature->feature_num);
 638         mutex_unlock(&feature->mutex);
 639
 640         return ret;
 641 }
 642
 643
 644 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 645 {
 646         struct amdgpu_device *adev = smu->adev;
 647         struct smu_feature *feature = &smu->smu_feature;
 648         int feature_id;
 649         int ret = 0;
 650
 651         if (adev->flags & AMD_IS_APU)
 652                 return 1;
 653
 654         feature_id = smu_feature_get_index(smu, mask);
 655         if (feature_id < 0)
 656                 return 0;
 657
 658         WARN_ON(feature_id > feature->feature_num);
 659
 660         mutex_lock(&feature->mutex);
 661         ret = test_bit(feature_id, feature->enabled);
 662         mutex_unlock(&feature->mutex);
 663
 664         return ret;
 665 }
 666
 667 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 668                             bool enable)
 669 {
 670         struct smu_feature *feature = &smu->smu_feature;
 671         int feature_id;
 672
 673         feature_id = smu_feature_get_index(smu, mask);
 674         if (feature_id < 0)
 675                 return -EINVAL;
 676
 677         WARN_ON(feature_id > feature->feature_num);
 678
 679         return smu_feature_update_enable_state(smu,
 680                                                1ULL << feature_id,
 681                                                enable);
 682 }
 683
 684 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 685 {
 686         struct smu_feature *feature = &smu->smu_feature;
 687         int feature_id;
 688         int ret = 0;
 689
 690         feature_id = smu_feature_get_index(smu, mask);
 691         if (feature_id < 0)
 692                 return 0;
 693
 694         WARN_ON(feature_id > feature->feature_num);
 695
 696         mutex_lock(&feature->mutex);
 697         ret = test_bit(feature_id, feature->supported);
 698         mutex_unlock(&feature->mutex);
 699
 700         return ret;
 701 }
 702
 703 int smu_feature_set_supported(struct smu_context *smu,
 704                               enum smu_feature_mask mask,
 705                               bool enable)
 706 {
 707         struct smu_feature *feature = &smu->smu_feature;
 708         int feature_id;
 709         int ret = 0;
 710
 711         feature_id = smu_feature_get_index(smu, mask);
 712         if (feature_id < 0)
 713                 return -EINVAL;
 714
 715         WARN_ON(feature_id > feature->feature_num);
 716
 717         mutex_lock(&feature->mutex);
 718         if (enable)
 719                 test_and_set_bit(feature_id, feature->supported);
 720         else
 721                 test_and_clear_bit(feature_id, feature->supported);
 722         mutex_unlock(&feature->mutex);
 723
 724         return ret;
 725 }
 726
 727 static int smu_set_funcs(struct amdgpu_device *adev)
 728 {
 729         struct smu_context *smu = &adev->smu;
 730
 731         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 732                 smu->od_enabled = true;
 733
 734         switch (adev->asic_type) {
 735         case CHIP_VEGA20:
 736                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 737                 vega20_set_ppt_funcs(smu);
 738                 break;
 739         case CHIP_NAVI10:
 740         case CHIP_NAVI14:
 741         case CHIP_NAVI12:
 742                 navi10_set_ppt_funcs(smu);
 743                 break;
 744         case CHIP_ARCTURUS:
 745                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 746                 arcturus_set_ppt_funcs(smu);
 747                 /* OD is not supported on Arcturus */
 748                 smu->od_enabled =false;
 749                 break;
 750         case CHIP_RENOIR:
 751                 renoir_set_ppt_funcs(smu);
 752                 break;
 753         default:
 754                 return -EINVAL;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int smu_early_init(void *handle)
 761 {
 762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 763         struct smu_context *smu = &adev->smu;
 764
 765         smu->adev = adev;
 766         smu->pm_enabled = !!amdgpu_dpm;
 767         smu->is_apu = false;
 768         mutex_init(&smu->mutex);
 769
 770         return smu_set_funcs(adev);
 771 }
 772
 773 static int smu_late_init(void *handle)
 774 {
 775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 776         struct smu_context *smu = &adev->smu;
 777
 778         if (!smu->pm_enabled)
 779                 return 0;
 780
 781         smu_handle_task(&adev->smu,
 782                         smu->smu_dpm.dpm_level,
 783                         AMD_PP_TASK_COMPLETE_INIT,
 784                         false);
 785
 786         return 0;
 787 }
 788
 789 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 790                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 791                             uint8_t **addr)
 792 {
 793         struct amdgpu_device *adev = smu->adev;
 794         uint16_t data_start;
 795
 796         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 797                                            size, frev, crev, &data_start))
 798                 return -EINVAL;
 799
 800         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 801
 802         return 0;
 803 }
 804
 805 static int smu_initialize_pptable(struct smu_context *smu)
 806 {
 807         /* TODO */
 808         return 0;
 809 }
 810
 811 static int smu_smc_table_sw_init(struct smu_context *smu)
 812 {
 813         int ret;
 814
 815         ret = smu_initialize_pptable(smu);
 816         if (ret) {
 817                 pr_err("Failed to init smu_initialize_pptable!\n");
 818                 return ret;
 819         }
 820
 821         /**
 822          * Create smu_table structure, and init smc tables such as
 823          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 824          */
 825         ret = smu_init_smc_tables(smu);
 826         if (ret) {
 827                 pr_err("Failed to init smc tables!\n");
 828                 return ret;
 829         }
 830
 831         /**
 832          * Create smu_power_context structure, and allocate smu_dpm_context and
 833          * context size to fill the smu_power_context data.
 834          */
 835         ret = smu_init_power(smu);
 836         if (ret) {
 837                 pr_err("Failed to init smu_init_power!\n");
 838                 return ret;
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int smu_smc_table_sw_fini(struct smu_context *smu)
 845 {
 846         int ret;
 847
 848         ret = smu_fini_smc_tables(smu);
 849         if (ret) {
 850                 pr_err("Failed to smu_fini_smc_tables!\n");
 851                 return ret;
 852         }
 853
 854         return 0;
 855 }
 856
 857 static int smu_sw_init(void *handle)
 858 {
 859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 860         struct smu_context *smu = &adev->smu;
 861         int ret;
 862
 863         smu->pool_size = adev->pm.smu_prv_buffer_size;
 864         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 865         mutex_init(&smu->smu_feature.mutex);
 866         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 867         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 868         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 869
 870         mutex_init(&smu->smu_baco.mutex);
 871         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 872         smu->smu_baco.platform_support = false;
 873
 874         mutex_init(&smu->sensor_lock);
 875
 876         smu->watermarks_bitmap = 0;
 877         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 878         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 879
 880         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 881         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 882         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 883         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 884         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 885         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 886         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 887         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 888
 889         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 890         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 891         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 892         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 893         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 894         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 895         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 896         smu->display_config = &adev->pm.pm_display_cfg;
 897
 898         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 899         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 900         ret = smu_init_microcode(smu);
 901         if (ret) {
 902                 pr_err("Failed to load smu firmware!\n");
 903                 return ret;
 904         }
 905
 906         ret = smu_smc_table_sw_init(smu);
 907         if (ret) {
 908                 pr_err("Failed to sw init smc table!\n");
 909                 return ret;
 910         }
 911
 912         ret = smu_register_irq_handler(smu);
 913         if (ret) {
 914                 pr_err("Failed to register smc irq handler!\n");
 915                 return ret;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int smu_sw_fini(void *handle)
 922 {
 923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 924         struct smu_context *smu = &adev->smu;
 925         int ret;
 926
 927         kfree(smu->irq_source);
 928         smu->irq_source = NULL;
 929
 930         ret = smu_smc_table_sw_fini(smu);
 931         if (ret) {
 932                 pr_err("Failed to sw fini smc table!\n");
 933                 return ret;
 934         }
 935
 936         ret = smu_fini_power(smu);
 937         if (ret) {
 938                 pr_err("Failed to init smu_fini_power!\n");
 939                 return ret;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int smu_init_fb_allocations(struct smu_context *smu)
 946 {
 947         struct amdgpu_device *adev = smu->adev;
 948         struct smu_table_context *smu_table = &smu->smu_table;
 949         struct smu_table *tables = smu_table->tables;
 950         int ret, i;
 951
 952         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 953                 if (tables[i].size == 0)
 954                         continue;
 955                 ret = amdgpu_bo_create_kernel(adev,
 956                                               tables[i].size,
 957                                               tables[i].align,
 958                                               tables[i].domain,
 959                                               &tables[i].bo,
 960                                               &tables[i].mc_address,
 961                                               &tables[i].cpu_addr);
 962                 if (ret)
 963                         goto failed;
 964         }
 965
 966         return 0;
 967 failed:
 968         while (--i >= 0) {
 969                 if (tables[i].size == 0)
 970                         continue;
 971                 amdgpu_bo_free_kernel(&tables[i].bo,
 972                                       &tables[i].mc_address,
 973                                       &tables[i].cpu_addr);
 974
 975         }
 976         return ret;
 977 }
 978
 979 static int smu_fini_fb_allocations(struct smu_context *smu)
 980 {
 981         struct smu_table_context *smu_table = &smu->smu_table;
 982         struct smu_table *tables = smu_table->tables;
 983         uint32_t i = 0;
 984
 985         if (!tables)
 986                 return 0;
 987
 988         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 989                 if (tables[i].size == 0)
 990                         continue;
 991                 amdgpu_bo_free_kernel(&tables[i].bo,
 992                                       &tables[i].mc_address,
 993                                       &tables[i].cpu_addr);
 994         }
 995
 996         return 0;
 997 }
 998
 999 static int smu_smc_table_hw_init(struct smu_context *smu,
1000                                  bool initialize)
1001 {
1002         struct amdgpu_device *adev = smu->adev;
1003         int ret;
1004
1005         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1006                 pr_info("dpm has been enabled\n");
1007                 return 0;
1008         }
1009
1010         if (adev->asic_type != CHIP_ARCTURUS) {
1011                 ret = smu_init_display_count(smu, 0);
1012                 if (ret)
1013                         return ret;
1014         }
1015
1016         if (initialize) {
1017                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1018                 ret = smu_get_vbios_bootup_values(smu);
1019                 if (ret)
1020                         return ret;
1021
1022                 ret = smu_setup_pptable(smu);
1023                 if (ret)
1024                         return ret;
1025
1026                 ret = smu_get_clk_info_from_vbios(smu);
1027                 if (ret)
1028                         return ret;
1029
1030                 /*
1031                  * check if the format_revision in vbios is up to pptable header
1032                  * version, and the structure size is not 0.
1033                  */
1034                 ret = smu_check_pptable(smu);
1035                 if (ret)
1036                         return ret;
1037
1038                 /*
1039                  * allocate vram bos to store smc table contents.
1040                  */
1041                 ret = smu_init_fb_allocations(smu);
1042                 if (ret)
1043                         return ret;
1044
1045                 /*
1046                  * Parse pptable format and fill PPTable_t smc_pptable to
1047                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1048                  * then fill it into smc_pptable.
1049                  */
1050                 ret = smu_parse_pptable(smu);
1051                 if (ret)
1052                         return ret;
1053
1054                 /*
1055                  * Send msg GetDriverIfVersion to check if the return value is equal
1056                  * with DRIVER_IF_VERSION of smc header.
1057                  */
1058                 ret = smu_check_fw_version(smu);
1059                 if (ret)
1060                         return ret;
1061         }
1062
1063         /* smu_dump_pptable(smu); */
1064
1065         /*
1066          * Copy pptable bo in the vram to smc with SMU MSGs such as
1067          * SetDriverDramAddr and TransferTableDram2Smu.
1068          */
1069         ret = smu_write_pptable(smu);
1070         if (ret)
1071                 return ret;
1072
1073         /* issue Run*Btc msg */
1074         ret = smu_run_btc(smu);
1075         if (ret)
1076                 return ret;
1077
1078         ret = smu_feature_set_allowed_mask(smu);
1079         if (ret)
1080                 return ret;
1081
1082         ret = smu_system_features_control(smu, true);
1083         if (ret)
1084                 return ret;
1085
1086         if (adev->asic_type != CHIP_ARCTURUS) {
1087                 ret = smu_notify_display_change(smu);
1088                 if (ret)
1089                         return ret;
1090
1091                 /*
1092                  * Set min deep sleep dce fclk with bootup value from vbios via
1093                  * SetMinDeepSleepDcefclk MSG.
1094                  */
1095                 ret = smu_set_min_dcef_deep_sleep(smu);
1096                 if (ret)
1097                         return ret;
1098         }
1099
1100         /*
1101          * Set initialized values (get from vbios) to dpm tables context such as
1102          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1103          * type of clks.
1104          */
1105         if (initialize) {
1106                 ret = smu_populate_smc_tables(smu);
1107                 if (ret)
1108                         return ret;
1109
1110                 ret = smu_init_max_sustainable_clocks(smu);
1111                 if (ret)
1112                         return ret;
1113         }
1114
1115         if (adev->asic_type != CHIP_ARCTURUS) {
1116                 ret = smu_override_pcie_parameters(smu);
1117                 if (ret)
1118                         return ret;
1119         }
1120
1121         ret = smu_set_default_od_settings(smu, initialize);
1122         if (ret)
1123                 return ret;
1124
1125         if (initialize) {
1126                 ret = smu_populate_umd_state_clk(smu);
1127                 if (ret)
1128                         return ret;
1129
1130                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1131                 if (ret)
1132                         return ret;
1133         }
1134
1135         /*
1136          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1137          */
1138         ret = smu_set_tool_table_location(smu);
1139
1140         if (!smu_is_dpm_running(smu))
1141                 pr_info("dpm has been disabled\n");
1142
1143         return ret;
1144 }
1145
1146 /**
1147  * smu_alloc_memory_pool - allocate memory pool in the system memory
1148  *
1149  * @smu: amdgpu_device pointer
1150  *
1151  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1152  * and DramLogSetDramAddr can notify it changed.
1153  *
1154  * Returns 0 on success, error on failure.
1155  */
1156 static int smu_alloc_memory_pool(struct smu_context *smu)
1157 {
1158         struct amdgpu_device *adev = smu->adev;
1159         struct smu_table_context *smu_table = &smu->smu_table;
1160         struct smu_table *memory_pool = &smu_table->memory_pool;
1161         uint64_t pool_size = smu->pool_size;
1162         int ret = 0;
1163
1164         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1165                 return ret;
1166
1167         memory_pool->size = pool_size;
1168         memory_pool->align = PAGE_SIZE;
1169         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1170
1171         switch (pool_size) {
1172         case SMU_MEMORY_POOL_SIZE_256_MB:
1173         case SMU_MEMORY_POOL_SIZE_512_MB:
1174         case SMU_MEMORY_POOL_SIZE_1_GB:
1175         case SMU_MEMORY_POOL_SIZE_2_GB:
1176                 ret = amdgpu_bo_create_kernel(adev,
1177                                               memory_pool->size,
1178                                               memory_pool->align,
1179                                               memory_pool->domain,
1180                                               &memory_pool->bo,
1181                                               &memory_pool->mc_address,
1182                                               &memory_pool->cpu_addr);
1183                 break;
1184         default:
1185                 break;
1186         }
1187
1188         return ret;
1189 }
1190
1191 static int smu_free_memory_pool(struct smu_context *smu)
1192 {
1193         struct smu_table_context *smu_table = &smu->smu_table;
1194         struct smu_table *memory_pool = &smu_table->memory_pool;
1195
1196         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1197                 return 0;
1198
1199         amdgpu_bo_free_kernel(&memory_pool->bo,
1200                               &memory_pool->mc_address,
1201                               &memory_pool->cpu_addr);
1202
1203         memset(memory_pool, 0, sizeof(struct smu_table));
1204
1205         return 0;
1206 }
1207
1208 static int smu_start_smc_engine(struct smu_context *smu)
1209 {
1210         struct amdgpu_device *adev = smu->adev;
1211         int ret = 0;
1212
1213         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1214                 if (adev->asic_type < CHIP_NAVI10) {
1215                         if (smu->ppt_funcs->load_microcode) {
1216                                 ret = smu->ppt_funcs->load_microcode(smu);
1217                                 if (ret)
1218                                         return ret;
1219                         }
1220                 }
1221         }
1222
1223         if (smu->ppt_funcs->check_fw_status) {
1224                 ret = smu->ppt_funcs->check_fw_status(smu);
1225                 if (ret)
1226                         pr_err("SMC is not ready\n");
1227         }
1228
1229         return ret;
1230 }
1231
1232 static int smu_hw_init(void *handle)
1233 {
1234         int ret;
1235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1236         struct smu_context *smu = &adev->smu;
1237
1238         ret = smu_start_smc_engine(smu);
1239         if (ret) {
1240                 pr_err("SMU is not ready yet!\n");
1241                 return ret;
1242         }
1243
1244         if (adev->flags & AMD_IS_APU) {
1245                 smu_powergate_sdma(&adev->smu, false);
1246                 smu_powergate_vcn(&adev->smu, false);
1247                 smu_powergate_jpeg(&adev->smu, false);
1248                 smu_set_gfx_cgpg(&adev->smu, true);
1249         }
1250
1251         if (!smu->pm_enabled)
1252                 return 0;
1253
1254         ret = smu_feature_init_dpm(smu);
1255         if (ret)
1256                 goto failed;
1257
1258         ret = smu_smc_table_hw_init(smu, true);
1259         if (ret)
1260                 goto failed;
1261
1262         ret = smu_alloc_memory_pool(smu);
1263         if (ret)
1264                 goto failed;
1265
1266         /*
1267          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1268          * pool location.
1269          */
1270         ret = smu_notify_memory_pool_location(smu);
1271         if (ret)
1272                 goto failed;
1273
1274         ret = smu_start_thermal_control(smu);
1275         if (ret)
1276                 goto failed;
1277
1278         if (!smu->pm_enabled)
1279                 adev->pm.dpm_enabled = false;
1280         else
1281                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1282
1283         pr_info("SMU is initialized successfully!\n");
1284
1285         return 0;
1286
1287 failed:
1288         return ret;
1289 }
1290
1291 static int smu_stop_dpms(struct smu_context *smu)
1292 {
1293         return smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
1294 }
1295
1296 static int smu_hw_fini(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         struct smu_context *smu = &adev->smu;
1300         struct smu_table_context *table_context = &smu->smu_table;
1301         int ret = 0;
1302
1303         if (adev->flags & AMD_IS_APU) {
1304                 smu_powergate_sdma(&adev->smu, true);
1305                 smu_powergate_vcn(&adev->smu, true);
1306                 smu_powergate_jpeg(&adev->smu, true);
1307         }
1308
1309         ret = smu_stop_thermal_control(smu);
1310         if (ret) {
1311                 pr_warn("Fail to stop thermal control!\n");
1312                 return ret;
1313         }
1314
1315         /*
1316          * For custom pptable uploading, skip the DPM features
1317          * disable process on Navi1x ASICs.
1318          *   - As the gfx related features are under control of
1319          *     RLC on those ASICs. RLC reinitialization will be
1320          *     needed to reenable them. That will cost much more
1321          *     efforts.
1322          *
1323          *   - SMU firmware can handle the DPM reenablement
1324          *     properly.
1325          */
1326         if (!smu->uploading_custom_pp_table ||
1327             !((adev->asic_type >= CHIP_NAVI10) &&
1328               (adev->asic_type <= CHIP_NAVI12))) {
1329                 ret = smu_stop_dpms(smu);
1330                 if (ret) {
1331                         pr_warn("Fail to stop Dpms!\n");
1332                         return ret;
1333                 }
1334         }
1335
1336         kfree(table_context->driver_pptable);
1337         table_context->driver_pptable = NULL;
1338
1339         kfree(table_context->max_sustainable_clocks);
1340         table_context->max_sustainable_clocks = NULL;
1341
1342         kfree(table_context->overdrive_table);
1343         table_context->overdrive_table = NULL;
1344
1345         ret = smu_fini_fb_allocations(smu);
1346         if (ret)
1347                 return ret;
1348
1349         ret = smu_free_memory_pool(smu);
1350         if (ret)
1351                 return ret;
1352
1353         return 0;
1354 }
1355
1356 int smu_reset(struct smu_context *smu)
1357 {
1358         struct amdgpu_device *adev = smu->adev;
1359         int ret = 0;
1360
1361         ret = smu_hw_fini(adev);
1362         if (ret)
1363                 return ret;
1364
1365         ret = smu_hw_init(adev);
1366         if (ret)
1367                 return ret;
1368
1369         return ret;
1370 }
1371
1372 static int smu_suspend(void *handle)
1373 {
1374         int ret;
1375         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1376         struct smu_context *smu = &adev->smu;
1377         bool baco_feature_is_enabled = false;
1378
1379         if(!(adev->flags & AMD_IS_APU))
1380                 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1381
1382         ret = smu_system_features_control(smu, false);
1383         if (ret)
1384                 return ret;
1385
1386         if (baco_feature_is_enabled) {
1387                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1388                 if (ret) {
1389                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1390                         return ret;
1391                 }
1392         }
1393
1394         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1395
1396         if (adev->asic_type >= CHIP_NAVI10 &&
1397             adev->gfx.rlc.funcs->stop)
1398                 adev->gfx.rlc.funcs->stop(adev);
1399         if (smu->is_apu)
1400                 smu_set_gfx_cgpg(&adev->smu, false);
1401
1402         return 0;
1403 }
1404
1405 static int smu_resume(void *handle)
1406 {
1407         int ret;
1408         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1409         struct smu_context *smu = &adev->smu;
1410
1411         pr_info("SMU is resuming...\n");
1412
1413         ret = smu_start_smc_engine(smu);
1414         if (ret) {
1415                 pr_err("SMU is not ready yet!\n");
1416                 goto failed;
1417         }
1418
1419         ret = smu_smc_table_hw_init(smu, false);
1420         if (ret)
1421                 goto failed;
1422
1423         ret = smu_start_thermal_control(smu);
1424         if (ret)
1425                 goto failed;
1426
1427         if (smu->is_apu)
1428                 smu_set_gfx_cgpg(&adev->smu, true);
1429
1430         smu->disable_uclk_switch = 0;
1431
1432         pr_info("SMU is resumed successfully!\n");
1433
1434         return 0;
1435
1436 failed:
1437         return ret;
1438 }
1439
1440 int smu_display_configuration_change(struct smu_context *smu,
1441                                      const struct amd_pp_display_configuration *display_config)
1442 {
1443         int index = 0;
1444         int num_of_active_display = 0;
1445
1446         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1447                 return -EINVAL;
1448
1449         if (!display_config)
1450                 return -EINVAL;
1451
1452         mutex_lock(&smu->mutex);
1453
1454         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1455                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1456                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1457
1458         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1459                 if (display_config->displays[index].controller_id != 0)
1460                         num_of_active_display++;
1461         }
1462
1463         smu_set_active_display_count(smu, num_of_active_display);
1464
1465         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1466                            display_config->cpu_cc6_disable,
1467                            display_config->cpu_pstate_disable,
1468                            display_config->nb_pstate_switch_disable);
1469
1470         mutex_unlock(&smu->mutex);
1471
1472         return 0;
1473 }
1474
1475 static int smu_get_clock_info(struct smu_context *smu,
1476                               struct smu_clock_info *clk_info,
1477                               enum smu_perf_level_designation designation)
1478 {
1479         int ret;
1480         struct smu_performance_level level = {0};
1481
1482         if (!clk_info)
1483                 return -EINVAL;
1484
1485         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1486         if (ret)
1487                 return -EINVAL;
1488
1489         clk_info->min_mem_clk = level.memory_clock;
1490         clk_info->min_eng_clk = level.core_clock;
1491         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1492
1493         ret = smu_get_perf_level(smu, designation, &level);
1494         if (ret)
1495                 return -EINVAL;
1496
1497         clk_info->min_mem_clk = level.memory_clock;
1498         clk_info->min_eng_clk = level.core_clock;
1499         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1500
1501         return 0;
1502 }
1503
1504 int smu_get_current_clocks(struct smu_context *smu,
1505                            struct amd_pp_clock_info *clocks)
1506 {
1507         struct amd_pp_simple_clock_info simple_clocks = {0};
1508         struct smu_clock_info hw_clocks;
1509         int ret = 0;
1510
1511         if (!is_support_sw_smu(smu->adev))
1512                 return -EINVAL;
1513
1514         mutex_lock(&smu->mutex);
1515
1516         smu_get_dal_power_level(smu, &simple_clocks);
1517
1518         if (smu->support_power_containment)
1519                 ret = smu_get_clock_info(smu, &hw_clocks,
1520                                          PERF_LEVEL_POWER_CONTAINMENT);
1521         else
1522                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1523
1524         if (ret) {
1525                 pr_err("Error in smu_get_clock_info\n");
1526                 goto failed;
1527         }
1528
1529         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1530         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1531         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1532         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1533         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1534         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1535         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1536         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1537
1538         if (simple_clocks.level == 0)
1539                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1540         else
1541                 clocks->max_clocks_state = simple_clocks.level;
1542
1543         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1544                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1545                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1546         }
1547
1548 failed:
1549         mutex_unlock(&smu->mutex);
1550         return ret;
1551 }
1552
1553 static int smu_set_clockgating_state(void *handle,
1554                                      enum amd_clockgating_state state)
1555 {
1556         return 0;
1557 }
1558
1559 static int smu_set_powergating_state(void *handle,
1560                                      enum amd_powergating_state state)
1561 {
1562         return 0;
1563 }
1564
1565 static int smu_enable_umd_pstate(void *handle,
1566                       enum amd_dpm_forced_level *level)
1567 {
1568         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1569                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1570                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1571                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1572
1573         struct smu_context *smu = (struct smu_context*)(handle);
1574         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1575
1576         if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1577                 return -EINVAL;
1578
1579         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1580                 /* enter umd pstate, save current level, disable gfx cg*/
1581                 if (*level & profile_mode_mask) {
1582                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1583                         smu_dpm_ctx->enable_umd_pstate = true;
1584                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1585                                                                AMD_IP_BLOCK_TYPE_GFX,
1586                                                                AMD_CG_STATE_UNGATE);
1587                         amdgpu_device_ip_set_powergating_state(smu->adev,
1588                                                                AMD_IP_BLOCK_TYPE_GFX,
1589                                                                AMD_PG_STATE_UNGATE);
1590                 }
1591         } else {
1592                 /* exit umd pstate, restore level, enable gfx cg*/
1593                 if (!(*level & profile_mode_mask)) {
1594                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1595                                 *level = smu_dpm_ctx->saved_dpm_level;
1596                         smu_dpm_ctx->enable_umd_pstate = false;
1597                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1598                                                                AMD_IP_BLOCK_TYPE_GFX,
1599                                                                AMD_CG_STATE_GATE);
1600                         amdgpu_device_ip_set_powergating_state(smu->adev,
1601                                                                AMD_IP_BLOCK_TYPE_GFX,
1602                                                                AMD_PG_STATE_GATE);
1603                 }
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1610 {
1611         int ret = 0;
1612         uint32_t sclk_mask, mclk_mask, soc_mask;
1613
1614         switch (level) {
1615         case AMD_DPM_FORCED_LEVEL_HIGH:
1616                 ret = smu_force_dpm_limit_value(smu, true);
1617                 break;
1618         case AMD_DPM_FORCED_LEVEL_LOW:
1619                 ret = smu_force_dpm_limit_value(smu, false);
1620                 break;
1621         case AMD_DPM_FORCED_LEVEL_AUTO:
1622         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1623                 ret = smu_unforce_dpm_levels(smu);
1624                 break;
1625         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1626         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1627         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1628                 ret = smu_get_profiling_clk_mask(smu, level,
1629                                                  &sclk_mask,
1630                                                  &mclk_mask,
1631                                                  &soc_mask);
1632                 if (ret)
1633                         return ret;
1634                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1635                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1636                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1637                 break;
1638         case AMD_DPM_FORCED_LEVEL_MANUAL:
1639         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1640         default:
1641                 break;
1642         }
1643         return ret;
1644 }
1645
1646 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1647                                    enum amd_dpm_forced_level level,
1648                                    bool skip_display_settings)
1649 {
1650         int ret = 0;
1651         int index = 0;
1652         long workload;
1653         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1654
1655         if (!smu->pm_enabled)
1656                 return -EINVAL;
1657
1658         if (!skip_display_settings) {
1659                 ret = smu_display_config_changed(smu);
1660                 if (ret) {
1661                         pr_err("Failed to change display config!");
1662                         return ret;
1663                 }
1664         }
1665
1666         ret = smu_apply_clocks_adjust_rules(smu);
1667         if (ret) {
1668                 pr_err("Failed to apply clocks adjust rules!");
1669                 return ret;
1670         }
1671
1672         if (!skip_display_settings) {
1673                 ret = smu_notify_smc_dispaly_config(smu);
1674                 if (ret) {
1675                         pr_err("Failed to notify smc display config!");
1676                         return ret;
1677                 }
1678         }
1679
1680         if (smu_dpm_ctx->dpm_level != level) {
1681                 ret = smu_asic_set_performance_level(smu, level);
1682                 if (ret) {
1683                         ret = smu_default_set_performance_level(smu, level);
1684                         if (ret) {
1685                                 pr_err("Failed to set performance level!");
1686                                 return ret;
1687                         }
1688                 }
1689
1690                 /* update the saved copy */
1691                 smu_dpm_ctx->dpm_level = level;
1692         }
1693
1694         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1695                 index = fls(smu->workload_mask);
1696                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1697                 workload = smu->workload_setting[index];
1698
1699                 if (smu->power_profile_mode != workload)
1700                         smu_set_power_profile_mode(smu, &workload, 0, false);
1701         }
1702
1703         return ret;
1704 }
1705
1706 int smu_handle_task(struct smu_context *smu,
1707                     enum amd_dpm_forced_level level,
1708                     enum amd_pp_task task_id,
1709                     bool lock_needed)
1710 {
1711         int ret = 0;
1712
1713         if (lock_needed)
1714                 mutex_lock(&smu->mutex);
1715
1716         switch (task_id) {
1717         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1718                 ret = smu_pre_display_config_changed(smu);
1719                 if (ret)
1720                         goto out;
1721                 ret = smu_set_cpu_power_state(smu);
1722                 if (ret)
1723                         goto out;
1724                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1725                 break;
1726         case AMD_PP_TASK_COMPLETE_INIT:
1727         case AMD_PP_TASK_READJUST_POWER_STATE:
1728                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1729                 break;
1730         default:
1731                 break;
1732         }
1733
1734 out:
1735         if (lock_needed)
1736                 mutex_unlock(&smu->mutex);
1737
1738         return ret;
1739 }
1740
1741 int smu_switch_power_profile(struct smu_context *smu,
1742                              enum PP_SMC_POWER_PROFILE type,
1743                              bool en)
1744 {
1745         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1746         long workload;
1747         uint32_t index;
1748
1749         if (!smu->pm_enabled)
1750                 return -EINVAL;
1751
1752         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1753                 return -EINVAL;
1754
1755         mutex_lock(&smu->mutex);
1756
1757         if (!en) {
1758                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1759                 index = fls(smu->workload_mask);
1760                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1761                 workload = smu->workload_setting[index];
1762         } else {
1763                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1764                 index = fls(smu->workload_mask);
1765                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1766                 workload = smu->workload_setting[index];
1767         }
1768
1769         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1770                 smu_set_power_profile_mode(smu, &workload, 0, false);
1771
1772         mutex_unlock(&smu->mutex);
1773
1774         return 0;
1775 }
1776
1777 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1778 {
1779         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1780         enum amd_dpm_forced_level level;
1781
1782         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1783                 return -EINVAL;
1784
1785         mutex_lock(&(smu->mutex));
1786         level = smu_dpm_ctx->dpm_level;
1787         mutex_unlock(&(smu->mutex));
1788
1789         return level;
1790 }
1791
1792 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1793 {
1794         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1795         int ret = 0;
1796
1797         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1798                 return -EINVAL;
1799
1800         mutex_lock(&smu->mutex);
1801
1802         ret = smu_enable_umd_pstate(smu, &level);
1803         if (ret) {
1804                 mutex_unlock(&smu->mutex);
1805                 return ret;
1806         }
1807
1808         ret = smu_handle_task(smu, level,
1809                               AMD_PP_TASK_READJUST_POWER_STATE,
1810                               false);
1811
1812         mutex_unlock(&smu->mutex);
1813
1814         return ret;
1815 }
1816
1817 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1818 {
1819         int ret = 0;
1820
1821         mutex_lock(&smu->mutex);
1822         ret = smu_init_display_count(smu, count);
1823         mutex_unlock(&smu->mutex);
1824
1825         return ret;
1826 }
1827
1828 int smu_force_clk_levels(struct smu_context *smu,
1829                          enum smu_clk_type clk_type,
1830                          uint32_t mask,
1831                          bool lock_needed)
1832 {
1833         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1834         int ret = 0;
1835
1836         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1837                 pr_debug("force clock level is for dpm manual mode only.\n");
1838                 return -EINVAL;
1839         }
1840
1841         if (lock_needed)
1842                 mutex_lock(&smu->mutex);
1843
1844         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1845                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1846
1847         if (lock_needed)
1848                 mutex_unlock(&smu->mutex);
1849
1850         return ret;
1851 }
1852
1853 int smu_set_mp1_state(struct smu_context *smu,
1854                       enum pp_mp1_state mp1_state)
1855 {
1856         uint16_t msg;
1857         int ret;
1858
1859         /*
1860          * The SMC is not fully ready. That may be
1861          * expected as the IP may be masked.
1862          * So, just return without error.
1863          */
1864         if (!smu->pm_enabled)
1865                 return 0;
1866
1867         mutex_lock(&smu->mutex);
1868
1869         switch (mp1_state) {
1870         case PP_MP1_STATE_SHUTDOWN:
1871                 msg = SMU_MSG_PrepareMp1ForShutdown;
1872                 break;
1873         case PP_MP1_STATE_UNLOAD:
1874                 msg = SMU_MSG_PrepareMp1ForUnload;
1875                 break;
1876         case PP_MP1_STATE_RESET:
1877                 msg = SMU_MSG_PrepareMp1ForReset;
1878                 break;
1879         case PP_MP1_STATE_NONE:
1880         default:
1881                 mutex_unlock(&smu->mutex);
1882                 return 0;
1883         }
1884
1885         /* some asics may not support those messages */
1886         if (smu_msg_get_index(smu, msg) < 0) {
1887                 mutex_unlock(&smu->mutex);
1888                 return 0;
1889         }
1890
1891         ret = smu_send_smc_msg(smu, msg);
1892         if (ret)
1893                 pr_err("[PrepareMp1] Failed!\n");
1894
1895         mutex_unlock(&smu->mutex);
1896
1897         return ret;
1898 }
1899
1900 int smu_set_df_cstate(struct smu_context *smu,
1901                       enum pp_df_cstate state)
1902 {
1903         int ret = 0;
1904
1905         /*
1906          * The SMC is not fully ready. That may be
1907          * expected as the IP may be masked.
1908          * So, just return without error.
1909          */
1910         if (!smu->pm_enabled)
1911                 return 0;
1912
1913         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1914                 return 0;
1915
1916         mutex_lock(&smu->mutex);
1917
1918         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1919         if (ret)
1920                 pr_err("[SetDfCstate] failed!\n");
1921
1922         mutex_unlock(&smu->mutex);
1923
1924         return ret;
1925 }
1926
1927 int smu_write_watermarks_table(struct smu_context *smu)
1928 {
1929         int ret = 0;
1930         struct smu_table_context *smu_table = &smu->smu_table;
1931         struct smu_table *table = NULL;
1932
1933         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
1934
1935         if (!table->cpu_addr)
1936                 return -EINVAL;
1937
1938         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
1939                                 true);
1940
1941         return ret;
1942 }
1943
1944 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1945                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1946 {
1947         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1948         void *table = watermarks->cpu_addr;
1949
1950         mutex_lock(&smu->mutex);
1951
1952         if (!smu->disable_watermark &&
1953                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1954                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1955                 smu_set_watermarks_table(smu, table, clock_ranges);
1956                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1957                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1958         }
1959
1960         mutex_unlock(&smu->mutex);
1961
1962         return 0;
1963 }
1964
1965 const struct amd_ip_funcs smu_ip_funcs = {
1966         .name = "smu",
1967         .early_init = smu_early_init,
1968         .late_init = smu_late_init,
1969         .sw_init = smu_sw_init,
1970         .sw_fini = smu_sw_fini,
1971         .hw_init = smu_hw_init,
1972         .hw_fini = smu_hw_fini,
1973         .suspend = smu_suspend,
1974         .resume = smu_resume,
1975         .is_idle = NULL,
1976         .check_soft_reset = NULL,
1977         .wait_for_idle = NULL,
1978         .soft_reset = NULL,
1979         .set_clockgating_state = smu_set_clockgating_state,
1980         .set_powergating_state = smu_set_powergating_state,
1981         .enable_umd_pstate = smu_enable_umd_pstate,
1982 };
1983
1984 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1985 {
1986         .type = AMD_IP_BLOCK_TYPE_SMC,
1987         .major = 11,
1988         .minor = 0,
1989         .rev = 0,
1990         .funcs = &smu_ip_funcs,
1991 };
1992
1993 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1994 {
1995         .type = AMD_IP_BLOCK_TYPE_SMC,
1996         .major = 12,
1997         .minor = 0,
1998         .rev = 0,
1999         .funcs = &smu_ip_funcs,
2000 };
2001
2002 int smu_load_microcode(struct smu_context *smu)
2003 {
2004         int ret = 0;
2005
2006         mutex_lock(&smu->mutex);
2007
2008         if (smu->ppt_funcs->load_microcode)
2009                 ret = smu->ppt_funcs->load_microcode(smu);
2010
2011         mutex_unlock(&smu->mutex);
2012
2013         return ret;
2014 }
2015
2016 int smu_check_fw_status(struct smu_context *smu)
2017 {
2018         int ret = 0;
2019
2020         mutex_lock(&smu->mutex);
2021
2022         if (smu->ppt_funcs->check_fw_status)
2023                 ret = smu->ppt_funcs->check_fw_status(smu);
2024
2025         mutex_unlock(&smu->mutex);
2026
2027         return ret;
2028 }
2029
2030 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2031 {
2032         int ret = 0;
2033
2034         mutex_lock(&smu->mutex);
2035
2036         if (smu->ppt_funcs->set_gfx_cgpg)
2037                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2038
2039         mutex_unlock(&smu->mutex);
2040
2041         return ret;
2042 }
2043
2044 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2045 {
2046         int ret = 0;
2047
2048         mutex_lock(&smu->mutex);
2049
2050         if (smu->ppt_funcs->set_fan_speed_rpm)
2051                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2052
2053         mutex_unlock(&smu->mutex);
2054
2055         return ret;
2056 }
2057
2058 int smu_get_power_limit(struct smu_context *smu,
2059                         uint32_t *limit,
2060                         bool def,
2061                         bool lock_needed)
2062 {
2063         int ret = 0;
2064
2065         if (lock_needed)
2066                 mutex_lock(&smu->mutex);
2067
2068         if (smu->ppt_funcs->get_power_limit)
2069                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2070
2071         if (lock_needed)
2072                 mutex_unlock(&smu->mutex);
2073
2074         return ret;
2075 }
2076
2077 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2078 {
2079         int ret = 0;
2080
2081         mutex_lock(&smu->mutex);
2082
2083         if (smu->ppt_funcs->set_power_limit)
2084                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2085
2086         mutex_unlock(&smu->mutex);
2087
2088         return ret;
2089 }
2090
2091 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2092 {
2093         int ret = 0;
2094
2095         mutex_lock(&smu->mutex);
2096
2097         if (smu->ppt_funcs->print_clk_levels)
2098                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2099
2100         mutex_unlock(&smu->mutex);
2101
2102         return ret;
2103 }
2104
2105 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2106 {
2107         int ret = 0;
2108
2109         mutex_lock(&smu->mutex);
2110
2111         if (smu->ppt_funcs->get_od_percentage)
2112                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2113
2114         mutex_unlock(&smu->mutex);
2115
2116         return ret;
2117 }
2118
2119 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2120 {
2121         int ret = 0;
2122
2123         mutex_lock(&smu->mutex);
2124
2125         if (smu->ppt_funcs->set_od_percentage)
2126                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2127
2128         mutex_unlock(&smu->mutex);
2129
2130         return ret;
2131 }
2132
2133 int smu_od_edit_dpm_table(struct smu_context *smu,
2134                           enum PP_OD_DPM_TABLE_COMMAND type,
2135                           long *input, uint32_t size)
2136 {
2137         int ret = 0;
2138
2139         mutex_lock(&smu->mutex);
2140
2141         if (smu->ppt_funcs->od_edit_dpm_table)
2142                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2143
2144         mutex_unlock(&smu->mutex);
2145
2146         return ret;
2147 }
2148
2149 int smu_read_sensor(struct smu_context *smu,
2150                     enum amd_pp_sensors sensor,
2151                     void *data, uint32_t *size)
2152 {
2153         int ret = 0;
2154
2155         mutex_lock(&smu->mutex);
2156
2157         if (smu->ppt_funcs->read_sensor)
2158                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2159
2160         mutex_unlock(&smu->mutex);
2161
2162         return ret;
2163 }
2164
2165 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2166 {
2167         int ret = 0;
2168
2169         mutex_lock(&smu->mutex);
2170
2171         if (smu->ppt_funcs->get_power_profile_mode)
2172                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2173
2174         mutex_unlock(&smu->mutex);
2175
2176         return ret;
2177 }
2178
2179 int smu_set_power_profile_mode(struct smu_context *smu,
2180                                long *param,
2181                                uint32_t param_size,
2182                                bool lock_needed)
2183 {
2184         int ret = 0;
2185
2186         if (lock_needed)
2187                 mutex_lock(&smu->mutex);
2188
2189         if (smu->ppt_funcs->set_power_profile_mode)
2190                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2191
2192         if (lock_needed)
2193                 mutex_unlock(&smu->mutex);
2194
2195         return ret;
2196 }
2197
2198
2199 int smu_get_fan_control_mode(struct smu_context *smu)
2200 {
2201         int ret = 0;
2202
2203         mutex_lock(&smu->mutex);
2204
2205         if (smu->ppt_funcs->get_fan_control_mode)
2206                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2207
2208         mutex_unlock(&smu->mutex);
2209
2210         return ret;
2211 }
2212
2213 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2214 {
2215         int ret = 0;
2216
2217         mutex_lock(&smu->mutex);
2218
2219         if (smu->ppt_funcs->set_fan_control_mode)
2220                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2221
2222         mutex_unlock(&smu->mutex);
2223
2224         return ret;
2225 }
2226
2227 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2228 {
2229         int ret = 0;
2230
2231         mutex_lock(&smu->mutex);
2232
2233         if (smu->ppt_funcs->get_fan_speed_percent)
2234                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2235
2236         mutex_unlock(&smu->mutex);
2237
2238         return ret;
2239 }
2240
2241 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2242 {
2243         int ret = 0;
2244
2245         mutex_lock(&smu->mutex);
2246
2247         if (smu->ppt_funcs->set_fan_speed_percent)
2248                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2249
2250         mutex_unlock(&smu->mutex);
2251
2252         return ret;
2253 }
2254
2255 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2256 {
2257         int ret = 0;
2258
2259         mutex_lock(&smu->mutex);
2260
2261         if (smu->ppt_funcs->get_fan_speed_rpm)
2262                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2263
2264         mutex_unlock(&smu->mutex);
2265
2266         return ret;
2267 }
2268
2269 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2270 {
2271         int ret = 0;
2272
2273         mutex_lock(&smu->mutex);
2274
2275         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2276                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2277
2278         mutex_unlock(&smu->mutex);
2279
2280         return ret;
2281 }
2282
2283 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2284 {
2285         int ret = 0;
2286
2287         mutex_lock(&smu->mutex);
2288
2289         if (smu->ppt_funcs->set_active_display_count)
2290                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2291
2292         mutex_unlock(&smu->mutex);
2293
2294         return ret;
2295 }
2296
2297 int smu_get_clock_by_type(struct smu_context *smu,
2298                           enum amd_pp_clock_type type,
2299                           struct amd_pp_clocks *clocks)
2300 {
2301         int ret = 0;
2302
2303         mutex_lock(&smu->mutex);
2304
2305         if (smu->ppt_funcs->get_clock_by_type)
2306                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2307
2308         mutex_unlock(&smu->mutex);
2309
2310         return ret;
2311 }
2312
2313 int smu_get_max_high_clocks(struct smu_context *smu,
2314                             struct amd_pp_simple_clock_info *clocks)
2315 {
2316         int ret = 0;
2317
2318         mutex_lock(&smu->mutex);
2319
2320         if (smu->ppt_funcs->get_max_high_clocks)
2321                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2322
2323         mutex_unlock(&smu->mutex);
2324
2325         return ret;
2326 }
2327
2328 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2329                                        enum smu_clk_type clk_type,
2330                                        struct pp_clock_levels_with_latency *clocks)
2331 {
2332         int ret = 0;
2333
2334         mutex_lock(&smu->mutex);
2335
2336         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2337                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2338
2339         mutex_unlock(&smu->mutex);
2340
2341         return ret;
2342 }
2343
2344 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2345                                        enum amd_pp_clock_type type,
2346                                        struct pp_clock_levels_with_voltage *clocks)
2347 {
2348         int ret = 0;
2349
2350         mutex_lock(&smu->mutex);
2351
2352         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2353                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2354
2355         mutex_unlock(&smu->mutex);
2356
2357         return ret;
2358 }
2359
2360
2361 int smu_display_clock_voltage_request(struct smu_context *smu,
2362                                       struct pp_display_clock_request *clock_req)
2363 {
2364         int ret = 0;
2365
2366         mutex_lock(&smu->mutex);
2367
2368         if (smu->ppt_funcs->display_clock_voltage_request)
2369                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2370
2371         mutex_unlock(&smu->mutex);
2372
2373         return ret;
2374 }
2375
2376
2377 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2378 {
2379         int ret = -EINVAL;
2380
2381         mutex_lock(&smu->mutex);
2382
2383         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2384                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2385
2386         mutex_unlock(&smu->mutex);
2387
2388         return ret;
2389 }
2390
2391 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2392 {
2393         int ret = 0;
2394
2395         mutex_lock(&smu->mutex);
2396
2397         if (smu->ppt_funcs->notify_smu_enable_pwe)
2398                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2399
2400         mutex_unlock(&smu->mutex);
2401
2402         return ret;
2403 }
2404
2405 int smu_set_xgmi_pstate(struct smu_context *smu,
2406                         uint32_t pstate)
2407 {
2408         int ret = 0;
2409
2410         mutex_lock(&smu->mutex);
2411
2412         if (smu->ppt_funcs->set_xgmi_pstate)
2413                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2414
2415         mutex_unlock(&smu->mutex);
2416
2417         return ret;
2418 }
2419
2420 int smu_set_azalia_d3_pme(struct smu_context *smu)
2421 {
2422         int ret = 0;
2423
2424         mutex_lock(&smu->mutex);
2425
2426         if (smu->ppt_funcs->set_azalia_d3_pme)
2427                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2428
2429         mutex_unlock(&smu->mutex);
2430
2431         return ret;
2432 }
2433
2434 bool smu_baco_is_support(struct smu_context *smu)
2435 {
2436         bool ret = false;
2437
2438         mutex_lock(&smu->mutex);
2439
2440         if (smu->ppt_funcs->baco_is_support)
2441                 ret = smu->ppt_funcs->baco_is_support(smu);
2442
2443         mutex_unlock(&smu->mutex);
2444
2445         return ret;
2446 }
2447
2448 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2449 {
2450         if (smu->ppt_funcs->baco_get_state)
2451                 return -EINVAL;
2452
2453         mutex_lock(&smu->mutex);
2454         *state = smu->ppt_funcs->baco_get_state(smu);
2455         mutex_unlock(&smu->mutex);
2456
2457         return 0;
2458 }
2459
2460 int smu_baco_enter(struct smu_context *smu)
2461 {
2462         int ret = 0;
2463
2464         mutex_lock(&smu->mutex);
2465
2466         if (smu->ppt_funcs->baco_enter)
2467                 ret = smu->ppt_funcs->baco_enter(smu);
2468
2469         mutex_unlock(&smu->mutex);
2470
2471         return ret;
2472 }
2473
2474 int smu_baco_exit(struct smu_context *smu)
2475 {
2476         int ret = 0;
2477
2478         mutex_lock(&smu->mutex);
2479
2480         if (smu->ppt_funcs->baco_exit)
2481                 ret = smu->ppt_funcs->baco_exit(smu);
2482
2483         mutex_unlock(&smu->mutex);
2484
2485         return ret;
2486 }
2487
2488 int smu_mode2_reset(struct smu_context *smu)
2489 {
2490         int ret = 0;
2491
2492         mutex_lock(&smu->mutex);
2493
2494         if (smu->ppt_funcs->mode2_reset)
2495                 ret = smu->ppt_funcs->mode2_reset(smu);
2496
2497         mutex_unlock(&smu->mutex);
2498
2499         return ret;
2500 }
2501
2502 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2503                                          struct pp_smu_nv_clock_table *max_clocks)
2504 {
2505         int ret = 0;
2506
2507         mutex_lock(&smu->mutex);
2508
2509         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2510                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2511
2512         mutex_unlock(&smu->mutex);
2513
2514         return ret;
2515 }
2516
2517 int smu_get_uclk_dpm_states(struct smu_context *smu,
2518                             unsigned int *clock_values_in_khz,
2519                             unsigned int *num_states)
2520 {
2521         int ret = 0;
2522
2523         mutex_lock(&smu->mutex);
2524
2525         if (smu->ppt_funcs->get_uclk_dpm_states)
2526                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2527
2528         mutex_unlock(&smu->mutex);
2529
2530         return ret;
2531 }
2532
2533 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2534 {
2535         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2536
2537         mutex_lock(&smu->mutex);
2538
2539         if (smu->ppt_funcs->get_current_power_state)
2540                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2541
2542         mutex_unlock(&smu->mutex);
2543
2544         return pm_state;
2545 }
2546
2547 int smu_get_dpm_clock_table(struct smu_context *smu,
2548                             struct dpm_clocks *clock_table)
2549 {
2550         int ret = 0;
2551
2552         mutex_lock(&smu->mutex);
2553
2554         if (smu->ppt_funcs->get_dpm_clock_table)
2555                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2556
2557         mutex_unlock(&smu->mutex);
2558
2559         return ret;
2560 }
2561
2562 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2563 {
2564         uint32_t ret = 0;
2565
2566         if (smu->ppt_funcs->get_pptable_power_limit)
2567                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2568
2569         return ret;
2570 }
2571
2572 int smu_send_smc_msg(struct smu_context *smu,
2573                      enum smu_message_type msg)
2574 {
2575         int ret;
2576
2577         ret = smu_send_smc_msg_with_param(smu, msg, 0);
2578         return ret;
2579 }