2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "soc15_common.h"
29 #include "smu_v11_0.h"
30 #include "smu_v12_0.h"
34 #undef __SMU_DUMMY_MAP
35 #define __SMU_DUMMY_MAP(type) #type
36 static const char* __smu_message_names[] = {
40 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
42 if (type < 0 || type >= SMU_MSG_MAX_COUNT)
43 return "unknown smu message";
44 return __smu_message_names[type];
47 #undef __SMU_DUMMY_MAP
48 #define __SMU_DUMMY_MAP(fea) #fea
49 static const char* __smu_feature_names[] = {
53 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
55 if (feature < 0 || feature >= SMU_FEATURE_COUNT)
56 return "unknown smu feature";
57 return __smu_feature_names[feature];
60 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
64 uint32_t feature_mask[2] = { 0 };
65 int32_t feature_index = 0;
67 uint32_t sort_feature[SMU_FEATURE_COUNT];
68 uint64_t hw_feature_count = 0;
70 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
74 size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
75 feature_mask[1], feature_mask[0]);
77 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
78 feature_index = smu_feature_get_index(smu, i);
79 if (feature_index < 0)
81 sort_feature[feature_index] = i;
85 for (i = 0; i < hw_feature_count; i++) {
86 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
88 smu_get_feature_name(smu, sort_feature[i]),
90 !!smu_feature_is_enabled(smu, sort_feature[i]) ?
91 "enabled" : "disabled");
98 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
101 uint32_t feature_mask[2] = { 0 };
102 uint64_t feature_2_enabled = 0;
103 uint64_t feature_2_disabled = 0;
104 uint64_t feature_enables = 0;
106 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
110 feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
112 feature_2_enabled = ~feature_enables & new_mask;
113 feature_2_disabled = feature_enables & ~new_mask;
115 if (feature_2_enabled) {
116 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
120 if (feature_2_disabled) {
121 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
129 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
133 if (!if_version && !smu_version)
137 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
141 ret = smu_read_smc_arg(smu, if_version);
147 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
151 ret = smu_read_smc_arg(smu, smu_version);
159 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
160 uint32_t min, uint32_t max)
162 int ret = 0, clk_id = 0;
165 if (min <= 0 && max <= 0)
168 if (!smu_clk_dpm_is_enabled(smu, clk_type))
171 clk_id = smu_clk_get_index(smu, clk_type);
176 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
177 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
184 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
185 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
195 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
196 uint32_t min, uint32_t max)
198 int ret = 0, clk_id = 0;
201 if (min <= 0 && max <= 0)
204 if (!smu_clk_dpm_is_enabled(smu, clk_type))
207 clk_id = smu_clk_get_index(smu, clk_type);
212 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
213 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
220 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
221 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
231 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
232 uint32_t *min, uint32_t *max)
234 uint32_t clock_limit;
240 if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
244 clock_limit = smu->smu_table.boot_values.uclk;
248 clock_limit = smu->smu_table.boot_values.gfxclk;
251 clock_limit = smu->smu_table.boot_values.socclk;
258 /* clock in Mhz unit */
260 *min = clock_limit / 100;
262 *max = clock_limit / 100;
267 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
268 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
270 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
274 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
275 uint16_t level, uint32_t *value)
277 int ret = 0, clk_id = 0;
283 if (!smu_clk_dpm_is_enabled(smu, clk_type))
286 clk_id = smu_clk_get_index(smu, clk_type);
290 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
292 ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
297 ret = smu_read_smc_arg(smu, ¶m);
301 /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
302 * now, we un-support it */
303 *value = param & 0x7fffffff;
308 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
311 return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
314 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
316 enum smu_feature_mask feature_id = 0;
321 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
325 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
328 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
334 if(!smu_feature_is_enabled(smu, feature_id)) {
342 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
347 switch (block_type) {
348 case AMD_IP_BLOCK_TYPE_UVD:
349 ret = smu_dpm_set_uvd_enable(smu, gate);
351 case AMD_IP_BLOCK_TYPE_VCE:
352 ret = smu_dpm_set_vce_enable(smu, gate);
354 case AMD_IP_BLOCK_TYPE_GFX:
355 ret = smu_gfx_off_control(smu, gate);
357 case AMD_IP_BLOCK_TYPE_SDMA:
358 ret = smu_powergate_sdma(smu, gate);
367 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
369 /* not support power state */
370 return POWER_STATE_TYPE_DEFAULT;
373 int smu_get_power_num_states(struct smu_context *smu,
374 struct pp_states_info *state_info)
379 /* not support power state */
380 memset(state_info, 0, sizeof(struct pp_states_info));
381 state_info->nums = 1;
382 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
387 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
388 void *data, uint32_t *size)
390 struct smu_power_context *smu_power = &smu->smu_power;
391 struct smu_power_gate *power_gate = &smu_power->power_gate;
398 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
399 *((uint32_t *)data) = smu->pstate_sclk;
402 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
403 *((uint32_t *)data) = smu->pstate_mclk;
406 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
407 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
410 case AMDGPU_PP_SENSOR_UVD_POWER:
411 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
414 case AMDGPU_PP_SENSOR_VCE_POWER:
415 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
418 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
419 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
433 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
434 void *table_data, bool drv2smu)
436 struct smu_table_context *smu_table = &smu->smu_table;
437 struct amdgpu_device *adev = smu->adev;
438 struct smu_table *table = NULL;
440 int table_id = smu_table_get_index(smu, table_index);
442 if (!table_data || table_id >= smu_table->table_count || table_id < 0)
445 table = &smu_table->tables[table_index];
448 memcpy(table->cpu_addr, table_data, table->size);
450 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
451 upper_32_bits(table->mc_address));
454 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
455 lower_32_bits(table->mc_address));
458 ret = smu_send_smc_msg_with_param(smu, drv2smu ?
459 SMU_MSG_TransferTableDram2Smu :
460 SMU_MSG_TransferTableSmu2Dram,
461 table_id | ((argument & 0xFFFF) << 16));
465 /* flush hdp cache */
466 adev->nbio_funcs->hdp_flush(adev, NULL);
469 memcpy(table_data, table->cpu_addr, table->size);
474 bool is_support_sw_smu(struct amdgpu_device *adev)
476 if (adev->asic_type == CHIP_VEGA20)
477 return (amdgpu_dpm == 2) ? true : false;
478 else if (adev->asic_type >= CHIP_ARCTURUS)
484 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
489 if (adev->asic_type == CHIP_VEGA20)
495 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
497 struct smu_table_context *smu_table = &smu->smu_table;
499 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
502 if (smu_table->hardcode_pptable)
503 *table = smu_table->hardcode_pptable;
505 *table = smu_table->power_play_table;
507 return smu_table->power_play_table_size;
510 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
512 struct smu_table_context *smu_table = &smu->smu_table;
513 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
516 if (!smu->pm_enabled)
518 if (header->usStructureSize != size) {
519 pr_err("pp table size not matched !\n");
523 mutex_lock(&smu->mutex);
524 if (!smu_table->hardcode_pptable)
525 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
526 if (!smu_table->hardcode_pptable) {
531 memcpy(smu_table->hardcode_pptable, buf, size);
532 smu_table->power_play_table = smu_table->hardcode_pptable;
533 smu_table->power_play_table_size = size;
534 mutex_unlock(&smu->mutex);
536 ret = smu_reset(smu);
538 pr_info("smu reset failed, ret = %d\n", ret);
543 mutex_unlock(&smu->mutex);
547 int smu_feature_init_dpm(struct smu_context *smu)
549 struct smu_feature *feature = &smu->smu_feature;
551 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
553 if (!smu->pm_enabled)
555 mutex_lock(&feature->mutex);
556 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
557 mutex_unlock(&feature->mutex);
559 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
564 mutex_lock(&feature->mutex);
565 bitmap_or(feature->allowed, feature->allowed,
566 (unsigned long *)allowed_feature_mask,
567 feature->feature_num);
568 mutex_unlock(&feature->mutex);
572 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
574 uint32_t feature_low = 0, feature_high = 0;
577 if (!smu->pm_enabled)
580 feature_low = (feature_mask >> 0 ) & 0xffffffff;
581 feature_high = (feature_mask >> 32) & 0xffffffff;
584 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
588 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
594 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
598 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
608 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
610 struct amdgpu_device *adev = smu->adev;
611 struct smu_feature *feature = &smu->smu_feature;
615 if (adev->flags & AMD_IS_APU)
618 feature_id = smu_feature_get_index(smu, mask);
622 WARN_ON(feature_id > feature->feature_num);
624 mutex_lock(&feature->mutex);
625 ret = test_bit(feature_id, feature->enabled);
626 mutex_unlock(&feature->mutex);
631 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
634 struct smu_feature *feature = &smu->smu_feature;
636 uint64_t feature_mask = 0;
639 feature_id = smu_feature_get_index(smu, mask);
643 WARN_ON(feature_id > feature->feature_num);
645 feature_mask = 1ULL << feature_id;
647 mutex_lock(&feature->mutex);
648 ret = smu_feature_update_enable_state(smu, feature_mask, enable);
653 test_and_set_bit(feature_id, feature->enabled);
655 test_and_clear_bit(feature_id, feature->enabled);
658 mutex_unlock(&feature->mutex);
663 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
665 struct smu_feature *feature = &smu->smu_feature;
669 feature_id = smu_feature_get_index(smu, mask);
673 WARN_ON(feature_id > feature->feature_num);
675 mutex_lock(&feature->mutex);
676 ret = test_bit(feature_id, feature->supported);
677 mutex_unlock(&feature->mutex);
682 int smu_feature_set_supported(struct smu_context *smu,
683 enum smu_feature_mask mask,
686 struct smu_feature *feature = &smu->smu_feature;
690 feature_id = smu_feature_get_index(smu, mask);
694 WARN_ON(feature_id > feature->feature_num);
696 mutex_lock(&feature->mutex);
698 test_and_set_bit(feature_id, feature->supported);
700 test_and_clear_bit(feature_id, feature->supported);
701 mutex_unlock(&feature->mutex);
706 static int smu_set_funcs(struct amdgpu_device *adev)
708 struct smu_context *smu = &adev->smu;
710 switch (adev->asic_type) {
716 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
717 smu->od_enabled = true;
718 smu_v11_0_set_smu_funcs(smu);
721 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
722 smu->od_enabled = true;
723 smu_v12_0_set_smu_funcs(smu);
732 static int smu_early_init(void *handle)
734 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
735 struct smu_context *smu = &adev->smu;
738 smu->pm_enabled = !!amdgpu_dpm;
739 mutex_init(&smu->mutex);
741 return smu_set_funcs(adev);
744 static int smu_late_init(void *handle)
746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
747 struct smu_context *smu = &adev->smu;
749 if (!smu->pm_enabled)
752 mutex_lock(&smu->mutex);
753 smu_handle_task(&adev->smu,
754 smu->smu_dpm.dpm_level,
755 AMD_PP_TASK_COMPLETE_INIT);
756 mutex_unlock(&smu->mutex);
761 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
762 uint16_t *size, uint8_t *frev, uint8_t *crev,
765 struct amdgpu_device *adev = smu->adev;
768 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
769 size, frev, crev, &data_start))
772 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
777 static int smu_initialize_pptable(struct smu_context *smu)
783 static int smu_smc_table_sw_init(struct smu_context *smu)
787 ret = smu_initialize_pptable(smu);
789 pr_err("Failed to init smu_initialize_pptable!\n");
794 * Create smu_table structure, and init smc tables such as
795 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
797 ret = smu_init_smc_tables(smu);
799 pr_err("Failed to init smc tables!\n");
804 * Create smu_power_context structure, and allocate smu_dpm_context and
805 * context size to fill the smu_power_context data.
807 ret = smu_init_power(smu);
809 pr_err("Failed to init smu_init_power!\n");
816 static int smu_smc_table_sw_fini(struct smu_context *smu)
820 ret = smu_fini_smc_tables(smu);
822 pr_err("Failed to smu_fini_smc_tables!\n");
829 static int smu_sw_init(void *handle)
831 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
832 struct smu_context *smu = &adev->smu;
835 smu->pool_size = adev->pm.smu_prv_buffer_size;
836 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
837 mutex_init(&smu->smu_feature.mutex);
838 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
839 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
840 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
842 mutex_init(&smu->smu_baco.mutex);
843 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
844 smu->smu_baco.platform_support = false;
846 mutex_init(&smu->sensor_lock);
848 smu->watermarks_bitmap = 0;
849 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
850 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
852 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
853 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
854 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
855 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
856 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
857 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
858 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
859 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
861 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
862 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
863 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
864 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
865 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
866 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
867 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
868 smu->display_config = &adev->pm.pm_display_cfg;
870 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
871 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
872 ret = smu_init_microcode(smu);
874 pr_err("Failed to load smu firmware!\n");
878 ret = smu_smc_table_sw_init(smu);
880 pr_err("Failed to sw init smc table!\n");
884 ret = smu_register_irq_handler(smu);
886 pr_err("Failed to register smc irq handler!\n");
893 static int smu_sw_fini(void *handle)
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896 struct smu_context *smu = &adev->smu;
899 kfree(smu->irq_source);
900 smu->irq_source = NULL;
902 ret = smu_smc_table_sw_fini(smu);
904 pr_err("Failed to sw fini smc table!\n");
908 ret = smu_fini_power(smu);
910 pr_err("Failed to init smu_fini_power!\n");
917 static int smu_init_fb_allocations(struct smu_context *smu)
919 struct amdgpu_device *adev = smu->adev;
920 struct smu_table_context *smu_table = &smu->smu_table;
921 struct smu_table *tables = smu_table->tables;
922 uint32_t table_count = smu_table->table_count;
926 if (table_count <= 0)
929 for (i = 0 ; i < table_count; i++) {
930 if (tables[i].size == 0)
932 ret = amdgpu_bo_create_kernel(adev,
937 &tables[i].mc_address,
938 &tables[i].cpu_addr);
946 if (tables[i].size == 0)
948 amdgpu_bo_free_kernel(&tables[i].bo,
949 &tables[i].mc_address,
950 &tables[i].cpu_addr);
956 static int smu_fini_fb_allocations(struct smu_context *smu)
958 struct smu_table_context *smu_table = &smu->smu_table;
959 struct smu_table *tables = smu_table->tables;
960 uint32_t table_count = smu_table->table_count;
963 if (table_count == 0 || tables == NULL)
966 for (i = 0 ; i < table_count; i++) {
967 if (tables[i].size == 0)
969 amdgpu_bo_free_kernel(&tables[i].bo,
970 &tables[i].mc_address,
971 &tables[i].cpu_addr);
977 static int smu_override_pcie_parameters(struct smu_context *smu)
979 struct amdgpu_device *adev = smu->adev;
980 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
983 if (adev->flags & AMD_IS_APU)
986 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
988 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
990 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
992 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
995 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
996 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
997 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
999 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1001 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1003 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1005 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1007 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1009 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1012 smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
1013 ret = smu_send_smc_msg_with_param(smu,
1014 SMU_MSG_OverridePcieParameters,
1017 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1021 static int smu_smc_table_hw_init(struct smu_context *smu,
1024 struct amdgpu_device *adev = smu->adev;
1027 if (smu_is_dpm_running(smu) && adev->in_suspend) {
1028 pr_info("dpm has been enabled\n");
1032 if (adev->asic_type != CHIP_ARCTURUS) {
1033 ret = smu_init_display_count(smu, 0);
1039 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1040 ret = smu_get_vbios_bootup_values(smu);
1044 ret = smu_setup_pptable(smu);
1048 ret = smu_get_clk_info_from_vbios(smu);
1053 * check if the format_revision in vbios is up to pptable header
1054 * version, and the structure size is not 0.
1056 ret = smu_check_pptable(smu);
1061 * allocate vram bos to store smc table contents.
1063 ret = smu_init_fb_allocations(smu);
1068 * Parse pptable format and fill PPTable_t smc_pptable to
1069 * smu_table_context structure. And read the smc_dpm_table from vbios,
1070 * then fill it into smc_pptable.
1072 ret = smu_parse_pptable(smu);
1077 * Send msg GetDriverIfVersion to check if the return value is equal
1078 * with DRIVER_IF_VERSION of smc header.
1080 ret = smu_check_fw_version(smu);
1085 /* smu_dump_pptable(smu); */
1088 * Copy pptable bo in the vram to smc with SMU MSGs such as
1089 * SetDriverDramAddr and TransferTableDram2Smu.
1091 ret = smu_write_pptable(smu);
1095 /* issue RunAfllBtc msg */
1096 ret = smu_run_afll_btc(smu);
1100 ret = smu_feature_set_allowed_mask(smu);
1104 ret = smu_system_features_control(smu, true);
1108 if (adev->asic_type != CHIP_ARCTURUS) {
1109 ret = smu_override_pcie_parameters(smu);
1113 ret = smu_notify_display_change(smu);
1118 * Set min deep sleep dce fclk with bootup value from vbios via
1119 * SetMinDeepSleepDcefclk MSG.
1121 ret = smu_set_min_dcef_deep_sleep(smu);
1127 * Set initialized values (get from vbios) to dpm tables context such as
1128 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1132 ret = smu_populate_smc_tables(smu);
1136 ret = smu_init_max_sustainable_clocks(smu);
1141 ret = smu_set_default_od_settings(smu, initialize);
1146 ret = smu_populate_umd_state_clk(smu);
1150 ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
1156 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1158 ret = smu_set_tool_table_location(smu);
1160 if (!smu_is_dpm_running(smu))
1161 pr_info("dpm has been disabled\n");
1167 * smu_alloc_memory_pool - allocate memory pool in the system memory
1169 * @smu: amdgpu_device pointer
1171 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1172 * and DramLogSetDramAddr can notify it changed.
1174 * Returns 0 on success, error on failure.
1176 static int smu_alloc_memory_pool(struct smu_context *smu)
1178 struct amdgpu_device *adev = smu->adev;
1179 struct smu_table_context *smu_table = &smu->smu_table;
1180 struct smu_table *memory_pool = &smu_table->memory_pool;
1181 uint64_t pool_size = smu->pool_size;
1184 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1187 memory_pool->size = pool_size;
1188 memory_pool->align = PAGE_SIZE;
1189 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1191 switch (pool_size) {
1192 case SMU_MEMORY_POOL_SIZE_256_MB:
1193 case SMU_MEMORY_POOL_SIZE_512_MB:
1194 case SMU_MEMORY_POOL_SIZE_1_GB:
1195 case SMU_MEMORY_POOL_SIZE_2_GB:
1196 ret = amdgpu_bo_create_kernel(adev,
1199 memory_pool->domain,
1201 &memory_pool->mc_address,
1202 &memory_pool->cpu_addr);
1211 static int smu_free_memory_pool(struct smu_context *smu)
1213 struct smu_table_context *smu_table = &smu->smu_table;
1214 struct smu_table *memory_pool = &smu_table->memory_pool;
1217 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1220 amdgpu_bo_free_kernel(&memory_pool->bo,
1221 &memory_pool->mc_address,
1222 &memory_pool->cpu_addr);
1224 memset(memory_pool, 0, sizeof(struct smu_table));
1229 static int smu_hw_init(void *handle)
1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233 struct smu_context *smu = &adev->smu;
1235 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1236 if (adev->asic_type < CHIP_NAVI10) {
1237 ret = smu_load_microcode(smu);
1243 ret = smu_check_fw_status(smu);
1245 pr_err("SMC firmware status is not correct\n");
1249 if (adev->flags & AMD_IS_APU) {
1250 smu_powergate_sdma(&adev->smu, false);
1251 smu_powergate_vcn(&adev->smu, false);
1254 if (!smu->pm_enabled)
1257 ret = smu_feature_init_dpm(smu);
1261 ret = smu_smc_table_hw_init(smu, true);
1265 ret = smu_alloc_memory_pool(smu);
1270 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1273 ret = smu_notify_memory_pool_location(smu);
1277 ret = smu_start_thermal_control(smu);
1281 if (!smu->pm_enabled)
1282 adev->pm.dpm_enabled = false;
1284 adev->pm.dpm_enabled = true; /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1286 pr_info("SMU is initialized successfully!\n");
1294 static int smu_hw_fini(void *handle)
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297 struct smu_context *smu = &adev->smu;
1298 struct smu_table_context *table_context = &smu->smu_table;
1301 if (adev->flags & AMD_IS_APU) {
1302 smu_powergate_sdma(&adev->smu, true);
1303 smu_powergate_vcn(&adev->smu, true);
1306 kfree(table_context->driver_pptable);
1307 table_context->driver_pptable = NULL;
1309 kfree(table_context->max_sustainable_clocks);
1310 table_context->max_sustainable_clocks = NULL;
1312 kfree(table_context->overdrive_table);
1313 table_context->overdrive_table = NULL;
1315 ret = smu_fini_fb_allocations(smu);
1319 ret = smu_free_memory_pool(smu);
1326 int smu_reset(struct smu_context *smu)
1328 struct amdgpu_device *adev = smu->adev;
1331 ret = smu_hw_fini(adev);
1335 ret = smu_hw_init(adev);
1342 static int smu_suspend(void *handle)
1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346 struct smu_context *smu = &adev->smu;
1347 bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1349 ret = smu_system_features_control(smu, false);
1353 if (adev->in_gpu_reset && baco_feature_is_enabled) {
1354 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1356 pr_warn("set BACO feature enabled failed, return %d\n", ret);
1361 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1363 if (adev->asic_type >= CHIP_NAVI10 &&
1364 adev->gfx.rlc.funcs->stop)
1365 adev->gfx.rlc.funcs->stop(adev);
1370 static int smu_resume(void *handle)
1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374 struct smu_context *smu = &adev->smu;
1376 pr_info("SMU is resuming...\n");
1378 mutex_lock(&smu->mutex);
1380 ret = smu_smc_table_hw_init(smu, false);
1384 ret = smu_start_thermal_control(smu);
1388 mutex_unlock(&smu->mutex);
1390 pr_info("SMU is resumed successfully!\n");
1394 mutex_unlock(&smu->mutex);
1398 int smu_display_configuration_change(struct smu_context *smu,
1399 const struct amd_pp_display_configuration *display_config)
1402 int num_of_active_display = 0;
1404 if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1407 if (!display_config)
1410 mutex_lock(&smu->mutex);
1412 smu_set_deep_sleep_dcefclk(smu,
1413 display_config->min_dcef_deep_sleep_set_clk / 100);
1415 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1416 if (display_config->displays[index].controller_id != 0)
1417 num_of_active_display++;
1420 smu_set_active_display_count(smu, num_of_active_display);
1422 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1423 display_config->cpu_cc6_disable,
1424 display_config->cpu_pstate_disable,
1425 display_config->nb_pstate_switch_disable);
1427 mutex_unlock(&smu->mutex);
1432 static int smu_get_clock_info(struct smu_context *smu,
1433 struct smu_clock_info *clk_info,
1434 enum smu_perf_level_designation designation)
1437 struct smu_performance_level level = {0};
1442 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1446 clk_info->min_mem_clk = level.memory_clock;
1447 clk_info->min_eng_clk = level.core_clock;
1448 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1450 ret = smu_get_perf_level(smu, designation, &level);
1454 clk_info->min_mem_clk = level.memory_clock;
1455 clk_info->min_eng_clk = level.core_clock;
1456 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1461 int smu_get_current_clocks(struct smu_context *smu,
1462 struct amd_pp_clock_info *clocks)
1464 struct amd_pp_simple_clock_info simple_clocks = {0};
1465 struct smu_clock_info hw_clocks;
1468 if (!is_support_sw_smu(smu->adev))
1471 mutex_lock(&smu->mutex);
1473 smu_get_dal_power_level(smu, &simple_clocks);
1475 if (smu->support_power_containment)
1476 ret = smu_get_clock_info(smu, &hw_clocks,
1477 PERF_LEVEL_POWER_CONTAINMENT);
1479 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1482 pr_err("Error in smu_get_clock_info\n");
1486 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1487 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1488 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1489 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1490 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1491 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1492 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1493 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1495 if (simple_clocks.level == 0)
1496 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1498 clocks->max_clocks_state = simple_clocks.level;
1500 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1501 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1502 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1506 mutex_unlock(&smu->mutex);
1510 static int smu_set_clockgating_state(void *handle,
1511 enum amd_clockgating_state state)
1516 static int smu_set_powergating_state(void *handle,
1517 enum amd_powergating_state state)
1522 static int smu_enable_umd_pstate(void *handle,
1523 enum amd_dpm_forced_level *level)
1525 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1526 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1527 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1528 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1530 struct smu_context *smu = (struct smu_context*)(handle);
1531 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1532 if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
1535 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1536 /* enter umd pstate, save current level, disable gfx cg*/
1537 if (*level & profile_mode_mask) {
1538 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1539 smu_dpm_ctx->enable_umd_pstate = true;
1540 amdgpu_device_ip_set_clockgating_state(smu->adev,
1541 AMD_IP_BLOCK_TYPE_GFX,
1542 AMD_CG_STATE_UNGATE);
1543 amdgpu_device_ip_set_powergating_state(smu->adev,
1544 AMD_IP_BLOCK_TYPE_GFX,
1545 AMD_PG_STATE_UNGATE);
1548 /* exit umd pstate, restore level, enable gfx cg*/
1549 if (!(*level & profile_mode_mask)) {
1550 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1551 *level = smu_dpm_ctx->saved_dpm_level;
1552 smu_dpm_ctx->enable_umd_pstate = false;
1553 amdgpu_device_ip_set_clockgating_state(smu->adev,
1554 AMD_IP_BLOCK_TYPE_GFX,
1556 amdgpu_device_ip_set_powergating_state(smu->adev,
1557 AMD_IP_BLOCK_TYPE_GFX,
1565 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1568 uint32_t sclk_mask, mclk_mask, soc_mask;
1571 case AMD_DPM_FORCED_LEVEL_HIGH:
1572 ret = smu_force_dpm_limit_value(smu, true);
1574 case AMD_DPM_FORCED_LEVEL_LOW:
1575 ret = smu_force_dpm_limit_value(smu, false);
1577 case AMD_DPM_FORCED_LEVEL_AUTO:
1578 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1579 ret = smu_unforce_dpm_levels(smu);
1581 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1582 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1583 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1584 ret = smu_get_profiling_clk_mask(smu, level,
1590 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1591 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1592 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1594 case AMD_DPM_FORCED_LEVEL_MANUAL:
1595 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1602 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1603 enum amd_dpm_forced_level level,
1604 bool skip_display_settings)
1609 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1611 if (!smu->pm_enabled)
1614 if (!skip_display_settings) {
1615 ret = smu_display_config_changed(smu);
1617 pr_err("Failed to change display config!");
1622 ret = smu_apply_clocks_adjust_rules(smu);
1624 pr_err("Failed to apply clocks adjust rules!");
1628 if (!skip_display_settings) {
1629 ret = smu_notify_smc_dispaly_config(smu);
1631 pr_err("Failed to notify smc display config!");
1636 if (smu_dpm_ctx->dpm_level != level) {
1637 ret = smu_asic_set_performance_level(smu, level);
1639 ret = smu_default_set_performance_level(smu, level);
1641 pr_err("Failed to set performance level!");
1646 /* update the saved copy */
1647 smu_dpm_ctx->dpm_level = level;
1650 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1651 index = fls(smu->workload_mask);
1652 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1653 workload = smu->workload_setting[index];
1655 if (smu->power_profile_mode != workload)
1656 smu_set_power_profile_mode(smu, &workload, 0);
1662 int smu_handle_task(struct smu_context *smu,
1663 enum amd_dpm_forced_level level,
1664 enum amd_pp_task task_id)
1669 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1670 ret = smu_pre_display_config_changed(smu);
1673 ret = smu_set_cpu_power_state(smu);
1676 ret = smu_adjust_power_state_dynamic(smu, level, false);
1678 case AMD_PP_TASK_COMPLETE_INIT:
1679 case AMD_PP_TASK_READJUST_POWER_STATE:
1680 ret = smu_adjust_power_state_dynamic(smu, level, true);
1689 int smu_switch_power_profile(struct smu_context *smu,
1690 enum PP_SMC_POWER_PROFILE type,
1693 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1697 if (!smu->pm_enabled)
1700 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1703 mutex_lock(&smu->mutex);
1706 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1707 index = fls(smu->workload_mask);
1708 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1709 workload = smu->workload_setting[index];
1711 smu->workload_mask |= (1 << smu->workload_prority[type]);
1712 index = fls(smu->workload_mask);
1713 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1714 workload = smu->workload_setting[index];
1717 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1718 smu_set_power_profile_mode(smu, &workload, 0);
1720 mutex_unlock(&smu->mutex);
1725 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1727 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1728 enum amd_dpm_forced_level level;
1730 if (!smu_dpm_ctx->dpm_context)
1733 mutex_lock(&(smu->mutex));
1734 level = smu_dpm_ctx->dpm_level;
1735 mutex_unlock(&(smu->mutex));
1740 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1742 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1745 if (!smu_dpm_ctx->dpm_context)
1748 ret = smu_enable_umd_pstate(smu, &level);
1752 ret = smu_handle_task(smu, level,
1753 AMD_PP_TASK_READJUST_POWER_STATE);
1758 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1762 mutex_lock(&smu->mutex);
1763 ret = smu_init_display_count(smu, count);
1764 mutex_unlock(&smu->mutex);
1769 const struct amd_ip_funcs smu_ip_funcs = {
1771 .early_init = smu_early_init,
1772 .late_init = smu_late_init,
1773 .sw_init = smu_sw_init,
1774 .sw_fini = smu_sw_fini,
1775 .hw_init = smu_hw_init,
1776 .hw_fini = smu_hw_fini,
1777 .suspend = smu_suspend,
1778 .resume = smu_resume,
1780 .check_soft_reset = NULL,
1781 .wait_for_idle = NULL,
1783 .set_clockgating_state = smu_set_clockgating_state,
1784 .set_powergating_state = smu_set_powergating_state,
1785 .enable_umd_pstate = smu_enable_umd_pstate,
1788 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1790 .type = AMD_IP_BLOCK_TYPE_SMC,
1794 .funcs = &smu_ip_funcs,
1797 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1799 .type = AMD_IP_BLOCK_TYPE_SMC,
1803 .funcs = &smu_ip_funcs,