2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "soc15_common.h"
30 #include "smu_v11_0.h"
31 #include "smu_v12_0.h"
34 #include "vega20_ppt.h"
35 #include "arcturus_ppt.h"
36 #include "navi10_ppt.h"
37 #include "renoir_ppt.h"
39 #undef __SMU_DUMMY_MAP
40 #define __SMU_DUMMY_MAP(type) #type
41 static const char* __smu_message_names[] = {
45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
47 if (type < 0 || type >= SMU_MSG_MAX_COUNT)
48 return "unknown smu message";
49 return __smu_message_names[type];
52 #undef __SMU_DUMMY_MAP
53 #define __SMU_DUMMY_MAP(fea) #fea
54 static const char* __smu_feature_names[] = {
58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
60 if (feature < 0 || feature >= SMU_FEATURE_COUNT)
61 return "unknown smu feature";
62 return __smu_feature_names[feature];
65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
69 uint32_t feature_mask[2] = { 0 };
70 int32_t feature_index = 0;
72 uint32_t sort_feature[SMU_FEATURE_COUNT];
73 uint64_t hw_feature_count = 0;
75 mutex_lock(&smu->mutex);
77 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
81 size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
82 feature_mask[1], feature_mask[0]);
84 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
85 feature_index = smu_feature_get_index(smu, i);
86 if (feature_index < 0)
88 sort_feature[feature_index] = i;
92 for (i = 0; i < hw_feature_count; i++) {
93 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
95 smu_get_feature_name(smu, sort_feature[i]),
97 !!smu_feature_is_enabled(smu, sort_feature[i]) ?
98 "enabled" : "disabled");
102 mutex_unlock(&smu->mutex);
107 static int smu_feature_update_enable_state(struct smu_context *smu,
108 uint64_t feature_mask,
111 struct smu_feature *feature = &smu->smu_feature;
112 uint32_t feature_low = 0, feature_high = 0;
115 if (!smu->pm_enabled)
118 feature_low = (feature_mask >> 0 ) & 0xffffffff;
119 feature_high = (feature_mask >> 32) & 0xffffffff;
122 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
126 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
131 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
135 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
141 mutex_lock(&feature->mutex);
143 bitmap_or(feature->enabled, feature->enabled,
144 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
146 bitmap_andnot(feature->enabled, feature->enabled,
147 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
148 mutex_unlock(&feature->mutex);
153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
156 uint32_t feature_mask[2] = { 0 };
157 uint64_t feature_2_enabled = 0;
158 uint64_t feature_2_disabled = 0;
159 uint64_t feature_enables = 0;
161 mutex_lock(&smu->mutex);
163 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
167 feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
169 feature_2_enabled = ~feature_enables & new_mask;
170 feature_2_disabled = feature_enables & ~new_mask;
172 if (feature_2_enabled) {
173 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
177 if (feature_2_disabled) {
178 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
184 mutex_unlock(&smu->mutex);
189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
193 if (!if_version && !smu_version)
197 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
201 ret = smu_read_smc_arg(smu, if_version);
207 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
211 ret = smu_read_smc_arg(smu, smu_version);
219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
220 uint32_t min, uint32_t max)
224 if (min <= 0 && max <= 0)
227 if (!smu_clk_dpm_is_enabled(smu, clk_type))
230 ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
235 uint32_t min, uint32_t max)
237 int ret = 0, clk_id = 0;
240 if (min <= 0 && max <= 0)
243 if (!smu_clk_dpm_is_enabled(smu, clk_type))
246 clk_id = smu_clk_get_index(smu, clk_type);
251 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
252 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
259 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
260 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
271 uint32_t *min, uint32_t *max, bool lock_needed)
273 uint32_t clock_limit;
280 mutex_lock(&smu->mutex);
282 if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
286 clock_limit = smu->smu_table.boot_values.uclk;
290 clock_limit = smu->smu_table.boot_values.gfxclk;
293 clock_limit = smu->smu_table.boot_values.socclk;
300 /* clock in Mhz unit */
302 *min = clock_limit / 100;
304 *max = clock_limit / 100;
307 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
308 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
310 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
314 mutex_unlock(&smu->mutex);
319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
320 uint16_t level, uint32_t *value)
322 int ret = 0, clk_id = 0;
328 if (!smu_clk_dpm_is_enabled(smu, clk_type))
331 clk_id = smu_clk_get_index(smu, clk_type);
335 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
337 ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
342 ret = smu_read_smc_arg(smu, ¶m);
346 /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
347 * now, we un-support it */
348 *value = param & 0x7fffffff;
353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
356 return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
359 int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
360 uint32_t *min_value, uint32_t *max_value)
363 uint32_t level_count = 0;
365 if (!min_value && !max_value)
369 /* by default, level 0 clock value as min value */
370 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
376 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
380 ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count - 1, max_value);
388 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
390 enum smu_feature_mask feature_id = 0;
395 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
399 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
402 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
408 if(!smu_feature_is_enabled(smu, feature_id)) {
416 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
418 * @smu: smu_context pointer
419 * @block_type: the IP block to power gate/ungate
420 * @gate: to power gate if true, ungate otherwise
422 * This API uses no smu->mutex lock protection due to:
423 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
424 * This is guarded to be race condition free by the caller.
425 * 2. Or get called on user setting request of power_dpm_force_performance_level.
426 * Under this case, the smu->mutex lock protection is already enforced on
427 * the parent API smu_force_performance_level of the call path.
429 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
434 switch (block_type) {
435 case AMD_IP_BLOCK_TYPE_UVD:
436 ret = smu_dpm_set_uvd_enable(smu, gate);
438 case AMD_IP_BLOCK_TYPE_VCE:
439 ret = smu_dpm_set_vce_enable(smu, gate);
441 case AMD_IP_BLOCK_TYPE_GFX:
442 ret = smu_gfx_off_control(smu, gate);
444 case AMD_IP_BLOCK_TYPE_SDMA:
445 ret = smu_powergate_sdma(smu, gate);
447 case AMD_IP_BLOCK_TYPE_JPEG:
448 ret = smu_dpm_set_jpeg_enable(smu, gate);
457 int smu_get_power_num_states(struct smu_context *smu,
458 struct pp_states_info *state_info)
463 /* not support power state */
464 memset(state_info, 0, sizeof(struct pp_states_info));
465 state_info->nums = 1;
466 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
471 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
472 void *data, uint32_t *size)
474 struct smu_power_context *smu_power = &smu->smu_power;
475 struct smu_power_gate *power_gate = &smu_power->power_gate;
482 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
483 *((uint32_t *)data) = smu->pstate_sclk;
486 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
487 *((uint32_t *)data) = smu->pstate_mclk;
490 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
491 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
494 case AMDGPU_PP_SENSOR_UVD_POWER:
495 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
498 case AMDGPU_PP_SENSOR_VCE_POWER:
499 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
502 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
503 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
517 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
518 void *table_data, bool drv2smu)
520 struct smu_table_context *smu_table = &smu->smu_table;
521 struct amdgpu_device *adev = smu->adev;
522 struct smu_table *table = &smu_table->driver_table;
523 int table_id = smu_table_get_index(smu, table_index);
527 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
530 table_size = smu_table->tables[table_index].size;
533 memcpy(table->cpu_addr, table_data, table_size);
535 ret = smu_send_smc_msg_with_param(smu, drv2smu ?
536 SMU_MSG_TransferTableDram2Smu :
537 SMU_MSG_TransferTableSmu2Dram,
538 table_id | ((argument & 0xFFFF) << 16));
542 /* flush hdp cache */
543 adev->nbio.funcs->hdp_flush(adev, NULL);
546 memcpy(table_data, table->cpu_addr, table_size);
551 bool is_support_sw_smu(struct amdgpu_device *adev)
553 if (adev->asic_type == CHIP_VEGA20)
554 return (amdgpu_dpm == 2) ? true : false;
555 else if (adev->asic_type >= CHIP_ARCTURUS) {
556 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
564 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
566 if (!is_support_sw_smu(adev))
569 if (adev->asic_type == CHIP_VEGA20)
575 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
577 struct smu_table_context *smu_table = &smu->smu_table;
578 uint32_t powerplay_table_size;
580 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
583 mutex_lock(&smu->mutex);
585 if (smu_table->hardcode_pptable)
586 *table = smu_table->hardcode_pptable;
588 *table = smu_table->power_play_table;
590 powerplay_table_size = smu_table->power_play_table_size;
592 mutex_unlock(&smu->mutex);
594 return powerplay_table_size;
597 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
599 struct smu_table_context *smu_table = &smu->smu_table;
600 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
603 if (!smu->pm_enabled)
605 if (header->usStructureSize != size) {
606 pr_err("pp table size not matched !\n");
610 mutex_lock(&smu->mutex);
611 if (!smu_table->hardcode_pptable)
612 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
613 if (!smu_table->hardcode_pptable) {
618 memcpy(smu_table->hardcode_pptable, buf, size);
619 smu_table->power_play_table = smu_table->hardcode_pptable;
620 smu_table->power_play_table_size = size;
623 * Special hw_fini action(for Navi1x, the DPMs disablement will be
624 * skipped) may be needed for custom pptable uploading.
626 smu->uploading_custom_pp_table = true;
628 ret = smu_reset(smu);
630 pr_info("smu reset failed, ret = %d\n", ret);
632 smu->uploading_custom_pp_table = false;
635 mutex_unlock(&smu->mutex);
639 int smu_feature_init_dpm(struct smu_context *smu)
641 struct smu_feature *feature = &smu->smu_feature;
643 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
645 if (!smu->pm_enabled)
647 mutex_lock(&feature->mutex);
648 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
649 mutex_unlock(&feature->mutex);
651 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
656 mutex_lock(&feature->mutex);
657 bitmap_or(feature->allowed, feature->allowed,
658 (unsigned long *)allowed_feature_mask,
659 feature->feature_num);
660 mutex_unlock(&feature->mutex);
666 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
668 struct smu_feature *feature = &smu->smu_feature;
675 feature_id = smu_feature_get_index(smu, mask);
679 WARN_ON(feature_id > feature->feature_num);
681 mutex_lock(&feature->mutex);
682 ret = test_bit(feature_id, feature->enabled);
683 mutex_unlock(&feature->mutex);
688 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
691 struct smu_feature *feature = &smu->smu_feature;
694 feature_id = smu_feature_get_index(smu, mask);
698 WARN_ON(feature_id > feature->feature_num);
700 return smu_feature_update_enable_state(smu,
705 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
707 struct smu_feature *feature = &smu->smu_feature;
711 feature_id = smu_feature_get_index(smu, mask);
715 WARN_ON(feature_id > feature->feature_num);
717 mutex_lock(&feature->mutex);
718 ret = test_bit(feature_id, feature->supported);
719 mutex_unlock(&feature->mutex);
724 int smu_feature_set_supported(struct smu_context *smu,
725 enum smu_feature_mask mask,
728 struct smu_feature *feature = &smu->smu_feature;
732 feature_id = smu_feature_get_index(smu, mask);
736 WARN_ON(feature_id > feature->feature_num);
738 mutex_lock(&feature->mutex);
740 test_and_set_bit(feature_id, feature->supported);
742 test_and_clear_bit(feature_id, feature->supported);
743 mutex_unlock(&feature->mutex);
748 static int smu_set_funcs(struct amdgpu_device *adev)
750 struct smu_context *smu = &adev->smu;
752 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
753 smu->od_enabled = true;
755 switch (adev->asic_type) {
757 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
758 vega20_set_ppt_funcs(smu);
763 navi10_set_ppt_funcs(smu);
766 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
767 arcturus_set_ppt_funcs(smu);
768 /* OD is not supported on Arcturus */
769 smu->od_enabled =false;
772 renoir_set_ppt_funcs(smu);
781 static int smu_early_init(void *handle)
783 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
784 struct smu_context *smu = &adev->smu;
787 smu->pm_enabled = !!amdgpu_dpm;
789 mutex_init(&smu->mutex);
791 return smu_set_funcs(adev);
794 static int smu_late_init(void *handle)
796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
797 struct smu_context *smu = &adev->smu;
799 if (!smu->pm_enabled)
802 smu_handle_task(&adev->smu,
803 smu->smu_dpm.dpm_level,
804 AMD_PP_TASK_COMPLETE_INIT,
810 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
811 uint16_t *size, uint8_t *frev, uint8_t *crev,
814 struct amdgpu_device *adev = smu->adev;
817 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
818 size, frev, crev, &data_start))
821 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
826 static int smu_initialize_pptable(struct smu_context *smu)
832 static int smu_smc_table_sw_init(struct smu_context *smu)
836 ret = smu_initialize_pptable(smu);
838 pr_err("Failed to init smu_initialize_pptable!\n");
843 * Create smu_table structure, and init smc tables such as
844 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
846 ret = smu_init_smc_tables(smu);
848 pr_err("Failed to init smc tables!\n");
853 * Create smu_power_context structure, and allocate smu_dpm_context and
854 * context size to fill the smu_power_context data.
856 ret = smu_init_power(smu);
858 pr_err("Failed to init smu_init_power!\n");
865 static int smu_smc_table_sw_fini(struct smu_context *smu)
869 ret = smu_fini_smc_tables(smu);
871 pr_err("Failed to smu_fini_smc_tables!\n");
878 static int smu_sw_init(void *handle)
880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881 struct smu_context *smu = &adev->smu;
884 smu->pool_size = adev->pm.smu_prv_buffer_size;
885 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
886 mutex_init(&smu->smu_feature.mutex);
887 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
888 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
889 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
891 mutex_init(&smu->smu_baco.mutex);
892 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
893 smu->smu_baco.platform_support = false;
895 mutex_init(&smu->sensor_lock);
896 mutex_init(&smu->metrics_lock);
898 smu->watermarks_bitmap = 0;
899 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
900 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
902 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
903 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
904 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
905 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
906 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
907 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
908 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
909 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
911 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
912 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
913 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
914 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
915 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
916 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
917 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
918 smu->display_config = &adev->pm.pm_display_cfg;
920 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
921 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
922 ret = smu_init_microcode(smu);
924 pr_err("Failed to load smu firmware!\n");
928 ret = smu_smc_table_sw_init(smu);
930 pr_err("Failed to sw init smc table!\n");
934 ret = smu_register_irq_handler(smu);
936 pr_err("Failed to register smc irq handler!\n");
943 static int smu_sw_fini(void *handle)
945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
946 struct smu_context *smu = &adev->smu;
949 kfree(smu->irq_source);
950 smu->irq_source = NULL;
952 ret = smu_smc_table_sw_fini(smu);
954 pr_err("Failed to sw fini smc table!\n");
958 ret = smu_fini_power(smu);
960 pr_err("Failed to init smu_fini_power!\n");
967 static int smu_init_fb_allocations(struct smu_context *smu)
969 struct amdgpu_device *adev = smu->adev;
970 struct smu_table_context *smu_table = &smu->smu_table;
971 struct smu_table *tables = smu_table->tables;
972 struct smu_table *driver_table = &(smu_table->driver_table);
973 uint32_t max_table_size = 0;
976 /* VRAM allocation for tool table */
977 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
978 ret = amdgpu_bo_create_kernel(adev,
979 tables[SMU_TABLE_PMSTATUSLOG].size,
980 tables[SMU_TABLE_PMSTATUSLOG].align,
981 tables[SMU_TABLE_PMSTATUSLOG].domain,
982 &tables[SMU_TABLE_PMSTATUSLOG].bo,
983 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
984 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
986 pr_err("VRAM allocation for tool table failed!\n");
991 /* VRAM allocation for driver table */
992 for (i = 0; i < SMU_TABLE_COUNT; i++) {
993 if (tables[i].size == 0)
996 if (i == SMU_TABLE_PMSTATUSLOG)
999 if (max_table_size < tables[i].size)
1000 max_table_size = tables[i].size;
1003 driver_table->size = max_table_size;
1004 driver_table->align = PAGE_SIZE;
1005 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
1007 ret = amdgpu_bo_create_kernel(adev,
1009 driver_table->align,
1010 driver_table->domain,
1012 &driver_table->mc_address,
1013 &driver_table->cpu_addr);
1015 pr_err("VRAM allocation for driver table failed!\n");
1016 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1017 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1018 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1019 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1025 static int smu_fini_fb_allocations(struct smu_context *smu)
1027 struct smu_table_context *smu_table = &smu->smu_table;
1028 struct smu_table *tables = smu_table->tables;
1029 struct smu_table *driver_table = &(smu_table->driver_table);
1034 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1035 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1036 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1037 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1039 amdgpu_bo_free_kernel(&driver_table->bo,
1040 &driver_table->mc_address,
1041 &driver_table->cpu_addr);
1046 static int smu_smc_table_hw_init(struct smu_context *smu,
1049 struct amdgpu_device *adev = smu->adev;
1052 if (smu_is_dpm_running(smu) && adev->in_suspend) {
1053 pr_info("dpm has been enabled\n");
1057 if (adev->asic_type != CHIP_ARCTURUS) {
1058 ret = smu_init_display_count(smu, 0);
1064 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1065 ret = smu_get_vbios_bootup_values(smu);
1069 ret = smu_setup_pptable(smu);
1073 ret = smu_get_clk_info_from_vbios(smu);
1078 * check if the format_revision in vbios is up to pptable header
1079 * version, and the structure size is not 0.
1081 ret = smu_check_pptable(smu);
1086 * allocate vram bos to store smc table contents.
1088 ret = smu_init_fb_allocations(smu);
1093 * Parse pptable format and fill PPTable_t smc_pptable to
1094 * smu_table_context structure. And read the smc_dpm_table from vbios,
1095 * then fill it into smc_pptable.
1097 ret = smu_parse_pptable(smu);
1102 * Send msg GetDriverIfVersion to check if the return value is equal
1103 * with DRIVER_IF_VERSION of smc header.
1105 ret = smu_check_fw_version(smu);
1110 /* smu_dump_pptable(smu); */
1111 if (!amdgpu_sriov_vf(adev)) {
1112 ret = smu_set_driver_table_location(smu);
1117 * Copy pptable bo in the vram to smc with SMU MSGs such as
1118 * SetDriverDramAddr and TransferTableDram2Smu.
1120 ret = smu_write_pptable(smu);
1124 /* issue Run*Btc msg */
1125 ret = smu_run_btc(smu);
1128 ret = smu_feature_set_allowed_mask(smu);
1132 ret = smu_system_features_control(smu, true);
1136 if (adev->asic_type != CHIP_ARCTURUS) {
1137 ret = smu_notify_display_change(smu);
1142 * Set min deep sleep dce fclk with bootup value from vbios via
1143 * SetMinDeepSleepDcefclk MSG.
1145 ret = smu_set_min_dcef_deep_sleep(smu);
1151 * Set initialized values (get from vbios) to dpm tables context such as
1152 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1156 ret = smu_populate_smc_tables(smu);
1160 ret = smu_init_max_sustainable_clocks(smu);
1165 if (adev->asic_type != CHIP_ARCTURUS) {
1166 ret = smu_override_pcie_parameters(smu);
1171 ret = smu_set_default_od_settings(smu, initialize);
1176 ret = smu_populate_umd_state_clk(smu);
1180 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1186 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1188 if (!amdgpu_sriov_vf(adev)) {
1189 ret = smu_set_tool_table_location(smu);
1191 if (!smu_is_dpm_running(smu))
1192 pr_info("dpm has been disabled\n");
1198 * smu_alloc_memory_pool - allocate memory pool in the system memory
1200 * @smu: amdgpu_device pointer
1202 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1203 * and DramLogSetDramAddr can notify it changed.
1205 * Returns 0 on success, error on failure.
1207 static int smu_alloc_memory_pool(struct smu_context *smu)
1209 struct amdgpu_device *adev = smu->adev;
1210 struct smu_table_context *smu_table = &smu->smu_table;
1211 struct smu_table *memory_pool = &smu_table->memory_pool;
1212 uint64_t pool_size = smu->pool_size;
1215 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1218 memory_pool->size = pool_size;
1219 memory_pool->align = PAGE_SIZE;
1220 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1222 switch (pool_size) {
1223 case SMU_MEMORY_POOL_SIZE_256_MB:
1224 case SMU_MEMORY_POOL_SIZE_512_MB:
1225 case SMU_MEMORY_POOL_SIZE_1_GB:
1226 case SMU_MEMORY_POOL_SIZE_2_GB:
1227 ret = amdgpu_bo_create_kernel(adev,
1230 memory_pool->domain,
1232 &memory_pool->mc_address,
1233 &memory_pool->cpu_addr);
1242 static int smu_free_memory_pool(struct smu_context *smu)
1244 struct smu_table_context *smu_table = &smu->smu_table;
1245 struct smu_table *memory_pool = &smu_table->memory_pool;
1247 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1250 amdgpu_bo_free_kernel(&memory_pool->bo,
1251 &memory_pool->mc_address,
1252 &memory_pool->cpu_addr);
1254 memset(memory_pool, 0, sizeof(struct smu_table));
1259 static int smu_start_smc_engine(struct smu_context *smu)
1261 struct amdgpu_device *adev = smu->adev;
1264 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1265 if (adev->asic_type < CHIP_NAVI10) {
1266 if (smu->ppt_funcs->load_microcode) {
1267 ret = smu->ppt_funcs->load_microcode(smu);
1274 if (smu->ppt_funcs->check_fw_status) {
1275 ret = smu->ppt_funcs->check_fw_status(smu);
1277 pr_err("SMC is not ready\n");
1283 static int smu_hw_init(void *handle)
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 struct smu_context *smu = &adev->smu;
1289 ret = smu_start_smc_engine(smu);
1291 pr_err("SMU is not ready yet!\n");
1296 smu_powergate_sdma(&adev->smu, false);
1297 smu_powergate_vcn(&adev->smu, false);
1298 smu_powergate_jpeg(&adev->smu, false);
1299 smu_set_gfx_cgpg(&adev->smu, true);
1302 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1305 if (!smu->pm_enabled)
1308 ret = smu_feature_init_dpm(smu);
1312 ret = smu_smc_table_hw_init(smu, true);
1316 ret = smu_alloc_memory_pool(smu);
1321 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1324 ret = smu_notify_memory_pool_location(smu);
1328 ret = smu_start_thermal_control(smu);
1332 if (!smu->pm_enabled)
1333 adev->pm.dpm_enabled = false;
1335 adev->pm.dpm_enabled = true; /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1337 pr_info("SMU is initialized successfully!\n");
1345 static int smu_stop_dpms(struct smu_context *smu)
1347 return smu_system_features_control(smu, false);
1350 static int smu_hw_fini(void *handle)
1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353 struct smu_context *smu = &adev->smu;
1354 struct smu_table_context *table_context = &smu->smu_table;
1357 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1361 smu_powergate_sdma(&adev->smu, true);
1362 smu_powergate_vcn(&adev->smu, true);
1363 smu_powergate_jpeg(&adev->smu, true);
1366 if (!amdgpu_sriov_vf(adev)){
1367 ret = smu_stop_thermal_control(smu);
1369 pr_warn("Fail to stop thermal control!\n");
1374 * For custom pptable uploading, skip the DPM features
1375 * disable process on Navi1x ASICs.
1376 * - As the gfx related features are under control of
1377 * RLC on those ASICs. RLC reinitialization will be
1378 * needed to reenable them. That will cost much more
1381 * - SMU firmware can handle the DPM reenablement
1384 if (!smu->uploading_custom_pp_table ||
1385 !((adev->asic_type >= CHIP_NAVI10) &&
1386 (adev->asic_type <= CHIP_NAVI12))) {
1387 ret = smu_stop_dpms(smu);
1389 pr_warn("Fail to stop Dpms!\n");
1395 kfree(table_context->driver_pptable);
1396 table_context->driver_pptable = NULL;
1398 kfree(table_context->max_sustainable_clocks);
1399 table_context->max_sustainable_clocks = NULL;
1401 kfree(table_context->overdrive_table);
1402 table_context->overdrive_table = NULL;
1404 ret = smu_fini_fb_allocations(smu);
1408 ret = smu_free_memory_pool(smu);
1415 int smu_reset(struct smu_context *smu)
1417 struct amdgpu_device *adev = smu->adev;
1420 ret = smu_hw_fini(adev);
1424 ret = smu_hw_init(adev);
1431 static int smu_suspend(void *handle)
1434 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1435 struct smu_context *smu = &adev->smu;
1436 bool baco_feature_is_enabled = false;
1439 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1441 ret = smu_system_features_control(smu, false);
1445 if (baco_feature_is_enabled) {
1446 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1448 pr_warn("set BACO feature enabled failed, return %d\n", ret);
1453 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1455 if (adev->asic_type >= CHIP_NAVI10 &&
1456 adev->gfx.rlc.funcs->stop)
1457 adev->gfx.rlc.funcs->stop(adev);
1459 smu_set_gfx_cgpg(&adev->smu, false);
1464 static int smu_resume(void *handle)
1467 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468 struct smu_context *smu = &adev->smu;
1470 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1473 if (!smu->pm_enabled)
1476 pr_info("SMU is resuming...\n");
1478 ret = smu_start_smc_engine(smu);
1480 pr_err("SMU is not ready yet!\n");
1484 ret = smu_smc_table_hw_init(smu, false);
1488 ret = smu_start_thermal_control(smu);
1493 smu_set_gfx_cgpg(&adev->smu, true);
1495 smu->disable_uclk_switch = 0;
1497 pr_info("SMU is resumed successfully!\n");
1505 int smu_display_configuration_change(struct smu_context *smu,
1506 const struct amd_pp_display_configuration *display_config)
1509 int num_of_active_display = 0;
1511 if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1514 if (!display_config)
1517 mutex_lock(&smu->mutex);
1519 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1520 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1521 display_config->min_dcef_deep_sleep_set_clk / 100);
1523 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1524 if (display_config->displays[index].controller_id != 0)
1525 num_of_active_display++;
1528 smu_set_active_display_count(smu, num_of_active_display);
1530 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1531 display_config->cpu_cc6_disable,
1532 display_config->cpu_pstate_disable,
1533 display_config->nb_pstate_switch_disable);
1535 mutex_unlock(&smu->mutex);
1540 static int smu_get_clock_info(struct smu_context *smu,
1541 struct smu_clock_info *clk_info,
1542 enum smu_perf_level_designation designation)
1545 struct smu_performance_level level = {0};
1550 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1554 clk_info->min_mem_clk = level.memory_clock;
1555 clk_info->min_eng_clk = level.core_clock;
1556 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1558 ret = smu_get_perf_level(smu, designation, &level);
1562 clk_info->min_mem_clk = level.memory_clock;
1563 clk_info->min_eng_clk = level.core_clock;
1564 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1569 int smu_get_current_clocks(struct smu_context *smu,
1570 struct amd_pp_clock_info *clocks)
1572 struct amd_pp_simple_clock_info simple_clocks = {0};
1573 struct smu_clock_info hw_clocks;
1576 if (!is_support_sw_smu(smu->adev))
1579 mutex_lock(&smu->mutex);
1581 smu_get_dal_power_level(smu, &simple_clocks);
1583 if (smu->support_power_containment)
1584 ret = smu_get_clock_info(smu, &hw_clocks,
1585 PERF_LEVEL_POWER_CONTAINMENT);
1587 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1590 pr_err("Error in smu_get_clock_info\n");
1594 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1595 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1596 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1597 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1598 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1599 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1600 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1601 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1603 if (simple_clocks.level == 0)
1604 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1606 clocks->max_clocks_state = simple_clocks.level;
1608 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1609 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1610 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1614 mutex_unlock(&smu->mutex);
1618 static int smu_set_clockgating_state(void *handle,
1619 enum amd_clockgating_state state)
1624 static int smu_set_powergating_state(void *handle,
1625 enum amd_powergating_state state)
1630 static int smu_enable_umd_pstate(void *handle,
1631 enum amd_dpm_forced_level *level)
1633 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1634 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1635 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1636 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1638 struct smu_context *smu = (struct smu_context*)(handle);
1639 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1641 if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1644 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1645 /* enter umd pstate, save current level, disable gfx cg*/
1646 if (*level & profile_mode_mask) {
1647 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1648 smu_dpm_ctx->enable_umd_pstate = true;
1649 amdgpu_device_ip_set_clockgating_state(smu->adev,
1650 AMD_IP_BLOCK_TYPE_GFX,
1651 AMD_CG_STATE_UNGATE);
1652 amdgpu_device_ip_set_powergating_state(smu->adev,
1653 AMD_IP_BLOCK_TYPE_GFX,
1654 AMD_PG_STATE_UNGATE);
1657 /* exit umd pstate, restore level, enable gfx cg*/
1658 if (!(*level & profile_mode_mask)) {
1659 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1660 *level = smu_dpm_ctx->saved_dpm_level;
1661 smu_dpm_ctx->enable_umd_pstate = false;
1662 amdgpu_device_ip_set_clockgating_state(smu->adev,
1663 AMD_IP_BLOCK_TYPE_GFX,
1665 amdgpu_device_ip_set_powergating_state(smu->adev,
1666 AMD_IP_BLOCK_TYPE_GFX,
1674 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1675 enum amd_dpm_forced_level level,
1676 bool skip_display_settings)
1681 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1683 if (!smu->pm_enabled)
1686 if (!skip_display_settings) {
1687 ret = smu_display_config_changed(smu);
1689 pr_err("Failed to change display config!");
1694 ret = smu_apply_clocks_adjust_rules(smu);
1696 pr_err("Failed to apply clocks adjust rules!");
1700 if (!skip_display_settings) {
1701 ret = smu_notify_smc_display_config(smu);
1703 pr_err("Failed to notify smc display config!");
1708 if (smu_dpm_ctx->dpm_level != level) {
1709 ret = smu_asic_set_performance_level(smu, level);
1711 pr_err("Failed to set performance level!");
1715 /* update the saved copy */
1716 smu_dpm_ctx->dpm_level = level;
1719 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1720 index = fls(smu->workload_mask);
1721 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1722 workload = smu->workload_setting[index];
1724 if (smu->power_profile_mode != workload)
1725 smu_set_power_profile_mode(smu, &workload, 0, false);
1731 int smu_handle_task(struct smu_context *smu,
1732 enum amd_dpm_forced_level level,
1733 enum amd_pp_task task_id,
1739 mutex_lock(&smu->mutex);
1742 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1743 ret = smu_pre_display_config_changed(smu);
1746 ret = smu_set_cpu_power_state(smu);
1749 ret = smu_adjust_power_state_dynamic(smu, level, false);
1751 case AMD_PP_TASK_COMPLETE_INIT:
1752 case AMD_PP_TASK_READJUST_POWER_STATE:
1753 ret = smu_adjust_power_state_dynamic(smu, level, true);
1761 mutex_unlock(&smu->mutex);
1766 int smu_switch_power_profile(struct smu_context *smu,
1767 enum PP_SMC_POWER_PROFILE type,
1770 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1774 if (!smu->pm_enabled)
1777 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1780 mutex_lock(&smu->mutex);
1783 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1784 index = fls(smu->workload_mask);
1785 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1786 workload = smu->workload_setting[index];
1788 smu->workload_mask |= (1 << smu->workload_prority[type]);
1789 index = fls(smu->workload_mask);
1790 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1791 workload = smu->workload_setting[index];
1794 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1795 smu_set_power_profile_mode(smu, &workload, 0, false);
1797 mutex_unlock(&smu->mutex);
1802 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1804 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1805 enum amd_dpm_forced_level level;
1807 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1810 mutex_lock(&(smu->mutex));
1811 level = smu_dpm_ctx->dpm_level;
1812 mutex_unlock(&(smu->mutex));
1817 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1819 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1822 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1825 mutex_lock(&smu->mutex);
1827 ret = smu_enable_umd_pstate(smu, &level);
1829 mutex_unlock(&smu->mutex);
1833 ret = smu_handle_task(smu, level,
1834 AMD_PP_TASK_READJUST_POWER_STATE,
1837 mutex_unlock(&smu->mutex);
1842 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1846 mutex_lock(&smu->mutex);
1847 ret = smu_init_display_count(smu, count);
1848 mutex_unlock(&smu->mutex);
1853 int smu_force_clk_levels(struct smu_context *smu,
1854 enum smu_clk_type clk_type,
1858 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1861 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1862 pr_debug("force clock level is for dpm manual mode only.\n");
1867 mutex_lock(&smu->mutex);
1869 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1870 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1873 mutex_unlock(&smu->mutex);
1878 int smu_set_mp1_state(struct smu_context *smu,
1879 enum pp_mp1_state mp1_state)
1885 * The SMC is not fully ready. That may be
1886 * expected as the IP may be masked.
1887 * So, just return without error.
1889 if (!smu->pm_enabled)
1892 mutex_lock(&smu->mutex);
1894 switch (mp1_state) {
1895 case PP_MP1_STATE_SHUTDOWN:
1896 msg = SMU_MSG_PrepareMp1ForShutdown;
1898 case PP_MP1_STATE_UNLOAD:
1899 msg = SMU_MSG_PrepareMp1ForUnload;
1901 case PP_MP1_STATE_RESET:
1902 msg = SMU_MSG_PrepareMp1ForReset;
1904 case PP_MP1_STATE_NONE:
1906 mutex_unlock(&smu->mutex);
1910 /* some asics may not support those messages */
1911 if (smu_msg_get_index(smu, msg) < 0) {
1912 mutex_unlock(&smu->mutex);
1916 ret = smu_send_smc_msg(smu, msg);
1918 pr_err("[PrepareMp1] Failed!\n");
1920 mutex_unlock(&smu->mutex);
1925 int smu_set_df_cstate(struct smu_context *smu,
1926 enum pp_df_cstate state)
1931 * The SMC is not fully ready. That may be
1932 * expected as the IP may be masked.
1933 * So, just return without error.
1935 if (!smu->pm_enabled)
1938 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1941 mutex_lock(&smu->mutex);
1943 ret = smu->ppt_funcs->set_df_cstate(smu, state);
1945 pr_err("[SetDfCstate] failed!\n");
1947 mutex_unlock(&smu->mutex);
1952 int smu_write_watermarks_table(struct smu_context *smu)
1954 void *watermarks_table = smu->smu_table.watermarks_table;
1956 if (!watermarks_table)
1959 return smu_update_table(smu,
1960 SMU_TABLE_WATERMARKS,
1966 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1967 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1969 void *table = smu->smu_table.watermarks_table;
1974 mutex_lock(&smu->mutex);
1976 if (!smu->disable_watermark &&
1977 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1978 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1979 smu_set_watermarks_table(smu, table, clock_ranges);
1980 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1981 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1984 mutex_unlock(&smu->mutex);
1989 const struct amd_ip_funcs smu_ip_funcs = {
1991 .early_init = smu_early_init,
1992 .late_init = smu_late_init,
1993 .sw_init = smu_sw_init,
1994 .sw_fini = smu_sw_fini,
1995 .hw_init = smu_hw_init,
1996 .hw_fini = smu_hw_fini,
1997 .suspend = smu_suspend,
1998 .resume = smu_resume,
2000 .check_soft_reset = NULL,
2001 .wait_for_idle = NULL,
2003 .set_clockgating_state = smu_set_clockgating_state,
2004 .set_powergating_state = smu_set_powergating_state,
2005 .enable_umd_pstate = smu_enable_umd_pstate,
2008 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2010 .type = AMD_IP_BLOCK_TYPE_SMC,
2014 .funcs = &smu_ip_funcs,
2017 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2019 .type = AMD_IP_BLOCK_TYPE_SMC,
2023 .funcs = &smu_ip_funcs,
2026 int smu_load_microcode(struct smu_context *smu)
2030 mutex_lock(&smu->mutex);
2032 if (smu->ppt_funcs->load_microcode)
2033 ret = smu->ppt_funcs->load_microcode(smu);
2035 mutex_unlock(&smu->mutex);
2040 int smu_check_fw_status(struct smu_context *smu)
2044 mutex_lock(&smu->mutex);
2046 if (smu->ppt_funcs->check_fw_status)
2047 ret = smu->ppt_funcs->check_fw_status(smu);
2049 mutex_unlock(&smu->mutex);
2054 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2058 mutex_lock(&smu->mutex);
2060 if (smu->ppt_funcs->set_gfx_cgpg)
2061 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2063 mutex_unlock(&smu->mutex);
2068 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2072 mutex_lock(&smu->mutex);
2074 if (smu->ppt_funcs->set_fan_speed_rpm)
2075 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2077 mutex_unlock(&smu->mutex);
2082 int smu_get_power_limit(struct smu_context *smu,
2090 mutex_lock(&smu->mutex);
2092 if (smu->ppt_funcs->get_power_limit)
2093 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2096 mutex_unlock(&smu->mutex);
2101 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2105 mutex_lock(&smu->mutex);
2107 if (smu->ppt_funcs->set_power_limit)
2108 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2110 mutex_unlock(&smu->mutex);
2115 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2119 mutex_lock(&smu->mutex);
2121 if (smu->ppt_funcs->print_clk_levels)
2122 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2124 mutex_unlock(&smu->mutex);
2129 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2133 mutex_lock(&smu->mutex);
2135 if (smu->ppt_funcs->get_od_percentage)
2136 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2138 mutex_unlock(&smu->mutex);
2143 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2147 mutex_lock(&smu->mutex);
2149 if (smu->ppt_funcs->set_od_percentage)
2150 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2152 mutex_unlock(&smu->mutex);
2157 int smu_od_edit_dpm_table(struct smu_context *smu,
2158 enum PP_OD_DPM_TABLE_COMMAND type,
2159 long *input, uint32_t size)
2163 mutex_lock(&smu->mutex);
2165 if (smu->ppt_funcs->od_edit_dpm_table)
2166 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2168 mutex_unlock(&smu->mutex);
2173 int smu_read_sensor(struct smu_context *smu,
2174 enum amd_pp_sensors sensor,
2175 void *data, uint32_t *size)
2179 mutex_lock(&smu->mutex);
2181 if (smu->ppt_funcs->read_sensor)
2182 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2184 mutex_unlock(&smu->mutex);
2189 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2193 mutex_lock(&smu->mutex);
2195 if (smu->ppt_funcs->get_power_profile_mode)
2196 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2198 mutex_unlock(&smu->mutex);
2203 int smu_set_power_profile_mode(struct smu_context *smu,
2205 uint32_t param_size,
2211 mutex_lock(&smu->mutex);
2213 if (smu->ppt_funcs->set_power_profile_mode)
2214 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2217 mutex_unlock(&smu->mutex);
2223 int smu_get_fan_control_mode(struct smu_context *smu)
2227 mutex_lock(&smu->mutex);
2229 if (smu->ppt_funcs->get_fan_control_mode)
2230 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2232 mutex_unlock(&smu->mutex);
2237 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2241 mutex_lock(&smu->mutex);
2243 if (smu->ppt_funcs->set_fan_control_mode)
2244 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2246 mutex_unlock(&smu->mutex);
2251 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2255 mutex_lock(&smu->mutex);
2257 if (smu->ppt_funcs->get_fan_speed_percent)
2258 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2260 mutex_unlock(&smu->mutex);
2265 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2269 mutex_lock(&smu->mutex);
2271 if (smu->ppt_funcs->set_fan_speed_percent)
2272 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2274 mutex_unlock(&smu->mutex);
2279 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2283 mutex_lock(&smu->mutex);
2285 if (smu->ppt_funcs->get_fan_speed_rpm)
2286 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2288 mutex_unlock(&smu->mutex);
2293 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2297 mutex_lock(&smu->mutex);
2299 if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2300 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2302 mutex_unlock(&smu->mutex);
2307 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2311 if (smu->ppt_funcs->set_active_display_count)
2312 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2317 int smu_get_clock_by_type(struct smu_context *smu,
2318 enum amd_pp_clock_type type,
2319 struct amd_pp_clocks *clocks)
2323 mutex_lock(&smu->mutex);
2325 if (smu->ppt_funcs->get_clock_by_type)
2326 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2328 mutex_unlock(&smu->mutex);
2333 int smu_get_max_high_clocks(struct smu_context *smu,
2334 struct amd_pp_simple_clock_info *clocks)
2338 mutex_lock(&smu->mutex);
2340 if (smu->ppt_funcs->get_max_high_clocks)
2341 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2343 mutex_unlock(&smu->mutex);
2348 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2349 enum smu_clk_type clk_type,
2350 struct pp_clock_levels_with_latency *clocks)
2354 mutex_lock(&smu->mutex);
2356 if (smu->ppt_funcs->get_clock_by_type_with_latency)
2357 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2359 mutex_unlock(&smu->mutex);
2364 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2365 enum amd_pp_clock_type type,
2366 struct pp_clock_levels_with_voltage *clocks)
2370 mutex_lock(&smu->mutex);
2372 if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2373 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2375 mutex_unlock(&smu->mutex);
2381 int smu_display_clock_voltage_request(struct smu_context *smu,
2382 struct pp_display_clock_request *clock_req)
2386 mutex_lock(&smu->mutex);
2388 if (smu->ppt_funcs->display_clock_voltage_request)
2389 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2391 mutex_unlock(&smu->mutex);
2397 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2401 mutex_lock(&smu->mutex);
2403 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2404 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2406 mutex_unlock(&smu->mutex);
2411 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2415 mutex_lock(&smu->mutex);
2417 if (smu->ppt_funcs->notify_smu_enable_pwe)
2418 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2420 mutex_unlock(&smu->mutex);
2425 int smu_set_xgmi_pstate(struct smu_context *smu,
2430 mutex_lock(&smu->mutex);
2432 if (smu->ppt_funcs->set_xgmi_pstate)
2433 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2435 mutex_unlock(&smu->mutex);
2440 int smu_set_azalia_d3_pme(struct smu_context *smu)
2444 mutex_lock(&smu->mutex);
2446 if (smu->ppt_funcs->set_azalia_d3_pme)
2447 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2449 mutex_unlock(&smu->mutex);
2454 bool smu_baco_is_support(struct smu_context *smu)
2458 mutex_lock(&smu->mutex);
2460 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2461 ret = smu->ppt_funcs->baco_is_support(smu);
2463 mutex_unlock(&smu->mutex);
2468 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2470 if (smu->ppt_funcs->baco_get_state)
2473 mutex_lock(&smu->mutex);
2474 *state = smu->ppt_funcs->baco_get_state(smu);
2475 mutex_unlock(&smu->mutex);
2480 int smu_baco_enter(struct smu_context *smu)
2484 mutex_lock(&smu->mutex);
2486 if (smu->ppt_funcs->baco_enter)
2487 ret = smu->ppt_funcs->baco_enter(smu);
2489 mutex_unlock(&smu->mutex);
2494 int smu_baco_exit(struct smu_context *smu)
2498 mutex_lock(&smu->mutex);
2500 if (smu->ppt_funcs->baco_exit)
2501 ret = smu->ppt_funcs->baco_exit(smu);
2503 mutex_unlock(&smu->mutex);
2508 int smu_mode2_reset(struct smu_context *smu)
2512 mutex_lock(&smu->mutex);
2514 if (smu->ppt_funcs->mode2_reset)
2515 ret = smu->ppt_funcs->mode2_reset(smu);
2517 mutex_unlock(&smu->mutex);
2522 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2523 struct pp_smu_nv_clock_table *max_clocks)
2527 mutex_lock(&smu->mutex);
2529 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2530 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2532 mutex_unlock(&smu->mutex);
2537 int smu_get_uclk_dpm_states(struct smu_context *smu,
2538 unsigned int *clock_values_in_khz,
2539 unsigned int *num_states)
2543 mutex_lock(&smu->mutex);
2545 if (smu->ppt_funcs->get_uclk_dpm_states)
2546 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2548 mutex_unlock(&smu->mutex);
2553 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2555 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2557 mutex_lock(&smu->mutex);
2559 if (smu->ppt_funcs->get_current_power_state)
2560 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2562 mutex_unlock(&smu->mutex);
2567 int smu_get_dpm_clock_table(struct smu_context *smu,
2568 struct dpm_clocks *clock_table)
2572 mutex_lock(&smu->mutex);
2574 if (smu->ppt_funcs->get_dpm_clock_table)
2575 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2577 mutex_unlock(&smu->mutex);
2582 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2586 if (smu->ppt_funcs->get_pptable_power_limit)
2587 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2592 int smu_send_smc_msg(struct smu_context *smu,
2593 enum smu_message_type msg)
2597 ret = smu_send_smc_msg_with_param(smu, msg, 0);