drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24
  25 #include "pp_debug.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "soc15_common.h"
  30 #include "smu_v11_0.h"
  31 #include "smu_v12_0.h"
  32 #include "atom.h"
  33 #include "amd_pcie.h"
  34 #include "vega20_ppt.h"
  35 #include "arcturus_ppt.h"
  36 #include "navi10_ppt.h"
  37 #include "renoir_ppt.h"
  38
  39 #undef __SMU_DUMMY_MAP
  40 #define __SMU_DUMMY_MAP(type)   #type
  41 static const char* __smu_message_names[] = {
  42         SMU_MESSAGE_TYPES
  43 };
  44
  45 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
  46 {
  47         if (type < 0 || type >= SMU_MSG_MAX_COUNT)
  48                 return "unknown smu message";
  49         return __smu_message_names[type];
  50 }
  51
  52 #undef __SMU_DUMMY_MAP
  53 #define __SMU_DUMMY_MAP(fea)    #fea
  54 static const char* __smu_feature_names[] = {
  55         SMU_FEATURE_MASKS
  56 };
  57
  58 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
  59 {
  60         if (feature < 0 || feature >= SMU_FEATURE_COUNT)
  61                 return "unknown smu feature";
  62         return __smu_feature_names[feature];
  63 }
  64
  65 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  66 {
  67         size_t size = 0;
  68         int ret = 0, i = 0;
  69         uint32_t feature_mask[2] = { 0 };
  70         int32_t feature_index = 0;
  71         uint32_t count = 0;
  72         uint32_t sort_feature[SMU_FEATURE_COUNT];
  73         uint64_t hw_feature_count = 0;
  74
  75         mutex_lock(&smu->mutex);
  76
  77         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
  78         if (ret)
  79                 goto failed;
  80
  81         size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
  82                         feature_mask[1], feature_mask[0]);
  83
  84         for (i = 0; i < SMU_FEATURE_COUNT; i++) {
  85                 feature_index = smu_feature_get_index(smu, i);
  86                 if (feature_index < 0)
  87                         continue;
  88                 sort_feature[feature_index] = i;
  89                 hw_feature_count++;
  90         }
  91
  92         for (i = 0; i < hw_feature_count; i++) {
  93                 size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
  94                                count++,
  95                                smu_get_feature_name(smu, sort_feature[i]),
  96                                i,
  97                                !!smu_feature_is_enabled(smu, sort_feature[i]) ?
  98                                "enabled" : "disabled");
  99         }
 100
 101 failed:
 102         mutex_unlock(&smu->mutex);
 103
 104         return size;
 105 }
 106
 107 static int smu_feature_update_enable_state(struct smu_context *smu,
 108                                            uint64_t feature_mask,
 109                                            bool enabled)
 110 {
 111         struct smu_feature *feature = &smu->smu_feature;
 112         uint32_t feature_low = 0, feature_high = 0;
 113         int ret = 0;
 114
 115         if (!smu->pm_enabled)
 116                 return ret;
 117
 118         feature_low = (feature_mask >> 0 ) & 0xffffffff;
 119         feature_high = (feature_mask >> 32) & 0xffffffff;
 120
 121         if (enabled) {
 122                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 123                                                   feature_low);
 124                 if (ret)
 125                         return ret;
 126                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 127                                                   feature_high);
 128                 if (ret)
 129                         return ret;
 130         } else {
 131                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 132                                                   feature_low);
 133                 if (ret)
 134                         return ret;
 135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 136                                                   feature_high);
 137                 if (ret)
 138                         return ret;
 139         }
 140
 141         mutex_lock(&feature->mutex);
 142         if (enabled)
 143                 bitmap_or(feature->enabled, feature->enabled,
 144                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 145         else
 146                 bitmap_andnot(feature->enabled, feature->enabled,
 147                                 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
 148         mutex_unlock(&feature->mutex);
 149
 150         return ret;
 151 }
 152
 153 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 154 {
 155         int ret = 0;
 156         uint32_t feature_mask[2] = { 0 };
 157         uint64_t feature_2_enabled = 0;
 158         uint64_t feature_2_disabled = 0;
 159         uint64_t feature_enables = 0;
 160
 161         mutex_lock(&smu->mutex);
 162
 163         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 164         if (ret)
 165                 goto out;
 166
 167         feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
 168
 169         feature_2_enabled  = ~feature_enables & new_mask;
 170         feature_2_disabled = feature_enables & ~new_mask;
 171
 172         if (feature_2_enabled) {
 173                 ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 174                 if (ret)
 175                         goto out;
 176         }
 177         if (feature_2_disabled) {
 178                 ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 179                 if (ret)
 180                         goto out;
 181         }
 182
 183 out:
 184         mutex_unlock(&smu->mutex);
 185
 186         return ret;
 187 }
 188
 189 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 190 {
 191         int ret = 0;
 192
 193         if (!if_version && !smu_version)
 194                 return -EINVAL;
 195
 196         if (if_version) {
 197                 ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
 198                 if (ret)
 199                         return ret;
 200
 201                 ret = smu_read_smc_arg(smu, if_version);
 202                 if (ret)
 203                         return ret;
 204         }
 205
 206         if (smu_version) {
 207                 ret = smu_send_smc_msg(smu, SMU_MSG_GetSmuVersion);
 208                 if (ret)
 209                         return ret;
 210
 211                 ret = smu_read_smc_arg(smu, smu_version);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return ret;
 217 }
 218
 219 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 220                             uint32_t min, uint32_t max)
 221 {
 222         int ret = 0;
 223
 224         if (min <= 0 && max <= 0)
 225                 return -EINVAL;
 226
 227         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 228                 return 0;
 229
 230         ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
 231         return ret;
 232 }
 233
 234 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 235                             uint32_t min, uint32_t max)
 236 {
 237         int ret = 0, clk_id = 0;
 238         uint32_t param;
 239
 240         if (min <= 0 && max <= 0)
 241                 return -EINVAL;
 242
 243         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 244                 return 0;
 245
 246         clk_id = smu_clk_get_index(smu, clk_type);
 247         if (clk_id < 0)
 248                 return clk_id;
 249
 250         if (max > 0) {
 251                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
 252                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
 253                                                   param);
 254                 if (ret)
 255                         return ret;
 256         }
 257
 258         if (min > 0) {
 259                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
 260                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
 261                                                   param);
 262                 if (ret)
 263                         return ret;
 264         }
 265
 266
 267         return ret;
 268 }
 269
 270 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 271                            uint32_t *min, uint32_t *max, bool lock_needed)
 272 {
 273         uint32_t clock_limit;
 274         int ret = 0;
 275
 276         if (!min && !max)
 277                 return -EINVAL;
 278
 279         if (lock_needed)
 280                 mutex_lock(&smu->mutex);
 281
 282         if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
 283                 switch (clk_type) {
 284                 case SMU_MCLK:
 285                 case SMU_UCLK:
 286                         clock_limit = smu->smu_table.boot_values.uclk;
 287                         break;
 288                 case SMU_GFXCLK:
 289                 case SMU_SCLK:
 290                         clock_limit = smu->smu_table.boot_values.gfxclk;
 291                         break;
 292                 case SMU_SOCCLK:
 293                         clock_limit = smu->smu_table.boot_values.socclk;
 294                         break;
 295                 default:
 296                         clock_limit = 0;
 297                         break;
 298                 }
 299
 300                 /* clock in Mhz unit */
 301                 if (min)
 302                         *min = clock_limit / 100;
 303                 if (max)
 304                         *max = clock_limit / 100;
 305         } else {
 306                 /*
 307                  * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
 308                  * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
 309                  */
 310                 ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
 311         }
 312
 313         if (lock_needed)
 314                 mutex_unlock(&smu->mutex);
 315
 316         return ret;
 317 }
 318
 319 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
 320                               uint16_t level, uint32_t *value)
 321 {
 322         int ret = 0, clk_id = 0;
 323         uint32_t param;
 324
 325         if (!value)
 326                 return -EINVAL;
 327
 328         if (!smu_clk_dpm_is_enabled(smu, clk_type))
 329                 return 0;
 330
 331         clk_id = smu_clk_get_index(smu, clk_type);
 332         if (clk_id < 0)
 333                 return clk_id;
 334
 335         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
 336
 337         ret = smu_send_smc_msg_with_param(smu,SMU_MSG_GetDpmFreqByIndex,
 338                                           param);
 339         if (ret)
 340                 return ret;
 341
 342         ret = smu_read_smc_arg(smu, &param);
 343         if (ret)
 344                 return ret;
 345
 346         /* BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
 347          * now, we un-support it */
 348         *value = param & 0x7fffffff;
 349
 350         return ret;
 351 }
 352
 353 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 354                             uint32_t *value)
 355 {
 356         return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 357 }
 358
 359 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 360 {
 361         enum smu_feature_mask feature_id = 0;
 362
 363         switch (clk_type) {
 364         case SMU_MCLK:
 365         case SMU_UCLK:
 366                 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 367                 break;
 368         case SMU_GFXCLK:
 369         case SMU_SCLK:
 370                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 371                 break;
 372         case SMU_SOCCLK:
 373                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 374                 break;
 375         default:
 376                 return true;
 377         }
 378
 379         if(!smu_feature_is_enabled(smu, feature_id)) {
 380                 return false;
 381         }
 382
 383         return true;
 384 }
 385
 386 /**
 387  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 388  *
 389  * @smu:        smu_context pointer
 390  * @block_type: the IP block to power gate/ungate
 391  * @gate:       to power gate if true, ungate otherwise
 392  *
 393  * This API uses no smu->mutex lock protection due to:
 394  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 395  *    This is guarded to be race condition free by the caller.
 396  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 397  *    Under this case, the smu->mutex lock protection is already enforced on
 398  *    the parent API smu_force_performance_level of the call path.
 399  */
 400 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 401                            bool gate)
 402 {
 403         int ret = 0;
 404
 405         switch (block_type) {
 406         case AMD_IP_BLOCK_TYPE_UVD:
 407                 ret = smu_dpm_set_uvd_enable(smu, gate);
 408                 break;
 409         case AMD_IP_BLOCK_TYPE_VCE:
 410                 ret = smu_dpm_set_vce_enable(smu, gate);
 411                 break;
 412         case AMD_IP_BLOCK_TYPE_GFX:
 413                 ret = smu_gfx_off_control(smu, gate);
 414                 break;
 415         case AMD_IP_BLOCK_TYPE_SDMA:
 416                 ret = smu_powergate_sdma(smu, gate);
 417                 break;
 418         case AMD_IP_BLOCK_TYPE_JPEG:
 419                 ret = smu_dpm_set_jpeg_enable(smu, gate);
 420                 break;
 421         default:
 422                 break;
 423         }
 424
 425         return ret;
 426 }
 427
 428 int smu_get_power_num_states(struct smu_context *smu,
 429                              struct pp_states_info *state_info)
 430 {
 431         if (!state_info)
 432                 return -EINVAL;
 433
 434         /* not support power state */
 435         memset(state_info, 0, sizeof(struct pp_states_info));
 436         state_info->nums = 1;
 437         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 438
 439         return 0;
 440 }
 441
 442 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
 443                            void *data, uint32_t *size)
 444 {
 445         struct smu_power_context *smu_power = &smu->smu_power;
 446         struct smu_power_gate *power_gate = &smu_power->power_gate;
 447         int ret = 0;
 448
 449         if(!data || !size)
 450                 return -EINVAL;
 451
 452         switch (sensor) {
 453         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 454                 *((uint32_t *)data) = smu->pstate_sclk;
 455                 *size = 4;
 456                 break;
 457         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 458                 *((uint32_t *)data) = smu->pstate_mclk;
 459                 *size = 4;
 460                 break;
 461         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
 462                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
 463                 *size = 8;
 464                 break;
 465         case AMDGPU_PP_SENSOR_UVD_POWER:
 466                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
 467                 *size = 4;
 468                 break;
 469         case AMDGPU_PP_SENSOR_VCE_POWER:
 470                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
 471                 *size = 4;
 472                 break;
 473         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
 474                 *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
 475                 *size = 4;
 476                 break;
 477         default:
 478                 ret = -EINVAL;
 479                 break;
 480         }
 481
 482         if (ret)
 483                 *size = 0;
 484
 485         return ret;
 486 }
 487
 488 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
 489                      void *table_data, bool drv2smu)
 490 {
 491         struct smu_table_context *smu_table = &smu->smu_table;
 492         struct amdgpu_device *adev = smu->adev;
 493         struct smu_table *table = NULL;
 494         int ret = 0;
 495         int table_id = smu_table_get_index(smu, table_index);
 496
 497         if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
 498                 return -EINVAL;
 499
 500         table = &smu_table->tables[table_index];
 501
 502         if (drv2smu)
 503                 memcpy(table->cpu_addr, table_data, table->size);
 504
 505         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
 506                                           upper_32_bits(table->mc_address));
 507         if (ret)
 508                 return ret;
 509         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
 510                                           lower_32_bits(table->mc_address));
 511         if (ret)
 512                 return ret;
 513         ret = smu_send_smc_msg_with_param(smu, drv2smu ?
 514                                           SMU_MSG_TransferTableDram2Smu :
 515                                           SMU_MSG_TransferTableSmu2Dram,
 516                                           table_id | ((argument & 0xFFFF) << 16));
 517         if (ret)
 518                 return ret;
 519
 520         /* flush hdp cache */
 521         adev->nbio.funcs->hdp_flush(adev, NULL);
 522
 523         if (!drv2smu)
 524                 memcpy(table_data, table->cpu_addr, table->size);
 525
 526         return ret;
 527 }
 528
 529 bool is_support_sw_smu(struct amdgpu_device *adev)
 530 {
 531         if (adev->asic_type == CHIP_VEGA20)
 532                 return (amdgpu_dpm == 2) ? true : false;
 533         else if (adev->asic_type >= CHIP_ARCTURUS) {
 534                 if (amdgpu_sriov_vf(adev))
 535                         return false;
 536                 else
 537                         return true;
 538         } else
 539                 return false;
 540 }
 541
 542 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
 543 {
 544         if (!is_support_sw_smu(adev))
 545                 return false;
 546
 547         if (adev->asic_type == CHIP_VEGA20)
 548                 return true;
 549
 550         return false;
 551 }
 552
 553 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 554 {
 555         struct smu_table_context *smu_table = &smu->smu_table;
 556         uint32_t powerplay_table_size;
 557
 558         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 559                 return -EINVAL;
 560
 561         mutex_lock(&smu->mutex);
 562
 563         if (smu_table->hardcode_pptable)
 564                 *table = smu_table->hardcode_pptable;
 565         else
 566                 *table = smu_table->power_play_table;
 567
 568         powerplay_table_size = smu_table->power_play_table_size;
 569
 570         mutex_unlock(&smu->mutex);
 571
 572         return powerplay_table_size;
 573 }
 574
 575 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 576 {
 577         struct smu_table_context *smu_table = &smu->smu_table;
 578         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 579         int ret = 0;
 580
 581         if (!smu->pm_enabled)
 582                 return -EINVAL;
 583         if (header->usStructureSize != size) {
 584                 pr_err("pp table size not matched !\n");
 585                 return -EIO;
 586         }
 587
 588         mutex_lock(&smu->mutex);
 589         if (!smu_table->hardcode_pptable)
 590                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 591         if (!smu_table->hardcode_pptable) {
 592                 ret = -ENOMEM;
 593                 goto failed;
 594         }
 595
 596         memcpy(smu_table->hardcode_pptable, buf, size);
 597         smu_table->power_play_table = smu_table->hardcode_pptable;
 598         smu_table->power_play_table_size = size;
 599
 600         /*
 601          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 602          * skipped) may be needed for custom pptable uploading.
 603          */
 604         smu->uploading_custom_pp_table = true;
 605
 606         ret = smu_reset(smu);
 607         if (ret)
 608                 pr_info("smu reset failed, ret = %d\n", ret);
 609
 610         smu->uploading_custom_pp_table = false;
 611
 612 failed:
 613         mutex_unlock(&smu->mutex);
 614         return ret;
 615 }
 616
 617 int smu_feature_init_dpm(struct smu_context *smu)
 618 {
 619         struct smu_feature *feature = &smu->smu_feature;
 620         int ret = 0;
 621         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 622
 623         if (!smu->pm_enabled)
 624                 return ret;
 625         mutex_lock(&feature->mutex);
 626         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 627         mutex_unlock(&feature->mutex);
 628
 629         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 630                                              SMU_FEATURE_MAX/32);
 631         if (ret)
 632                 return ret;
 633
 634         mutex_lock(&feature->mutex);
 635         bitmap_or(feature->allowed, feature->allowed,
 636                       (unsigned long *)allowed_feature_mask,
 637                       feature->feature_num);
 638         mutex_unlock(&feature->mutex);
 639
 640         return ret;
 641 }
 642
 643
 644 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 645 {
 646         struct amdgpu_device *adev = smu->adev;
 647         struct smu_feature *feature = &smu->smu_feature;
 648         int feature_id;
 649         int ret = 0;
 650
 651         if (adev->flags & AMD_IS_APU)
 652                 return 1;
 653
 654         feature_id = smu_feature_get_index(smu, mask);
 655         if (feature_id < 0)
 656                 return 0;
 657
 658         WARN_ON(feature_id > feature->feature_num);
 659
 660         mutex_lock(&feature->mutex);
 661         ret = test_bit(feature_id, feature->enabled);
 662         mutex_unlock(&feature->mutex);
 663
 664         return ret;
 665 }
 666
 667 int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 668                             bool enable)
 669 {
 670         struct smu_feature *feature = &smu->smu_feature;
 671         int feature_id;
 672
 673         feature_id = smu_feature_get_index(smu, mask);
 674         if (feature_id < 0)
 675                 return -EINVAL;
 676
 677         WARN_ON(feature_id > feature->feature_num);
 678
 679         return smu_feature_update_enable_state(smu,
 680                                                1ULL << feature_id,
 681                                                enable);
 682 }
 683
 684 int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
 685 {
 686         struct smu_feature *feature = &smu->smu_feature;
 687         int feature_id;
 688         int ret = 0;
 689
 690         feature_id = smu_feature_get_index(smu, mask);
 691         if (feature_id < 0)
 692                 return 0;
 693
 694         WARN_ON(feature_id > feature->feature_num);
 695
 696         mutex_lock(&feature->mutex);
 697         ret = test_bit(feature_id, feature->supported);
 698         mutex_unlock(&feature->mutex);
 699
 700         return ret;
 701 }
 702
 703 int smu_feature_set_supported(struct smu_context *smu,
 704                               enum smu_feature_mask mask,
 705                               bool enable)
 706 {
 707         struct smu_feature *feature = &smu->smu_feature;
 708         int feature_id;
 709         int ret = 0;
 710
 711         feature_id = smu_feature_get_index(smu, mask);
 712         if (feature_id < 0)
 713                 return -EINVAL;
 714
 715         WARN_ON(feature_id > feature->feature_num);
 716
 717         mutex_lock(&feature->mutex);
 718         if (enable)
 719                 test_and_set_bit(feature_id, feature->supported);
 720         else
 721                 test_and_clear_bit(feature_id, feature->supported);
 722         mutex_unlock(&feature->mutex);
 723
 724         return ret;
 725 }
 726
 727 static int smu_set_funcs(struct amdgpu_device *adev)
 728 {
 729         struct smu_context *smu = &adev->smu;
 730
 731         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 732                 smu->od_enabled = true;
 733
 734         switch (adev->asic_type) {
 735         case CHIP_VEGA20:
 736                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 737                 vega20_set_ppt_funcs(smu);
 738                 break;
 739         case CHIP_NAVI10:
 740         case CHIP_NAVI14:
 741         case CHIP_NAVI12:
 742                 navi10_set_ppt_funcs(smu);
 743                 break;
 744         case CHIP_ARCTURUS:
 745                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 746                 arcturus_set_ppt_funcs(smu);
 747                 /* OD is not supported on Arcturus */
 748                 smu->od_enabled =false;
 749                 break;
 750         case CHIP_RENOIR:
 751                 renoir_set_ppt_funcs(smu);
 752                 break;
 753         default:
 754                 return -EINVAL;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int smu_early_init(void *handle)
 761 {
 762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 763         struct smu_context *smu = &adev->smu;
 764
 765         smu->adev = adev;
 766         smu->pm_enabled = !!amdgpu_dpm;
 767         smu->is_apu = false;
 768         mutex_init(&smu->mutex);
 769
 770         return smu_set_funcs(adev);
 771 }
 772
 773 static int smu_late_init(void *handle)
 774 {
 775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 776         struct smu_context *smu = &adev->smu;
 777
 778         if (!smu->pm_enabled)
 779                 return 0;
 780
 781         smu_handle_task(&adev->smu,
 782                         smu->smu_dpm.dpm_level,
 783                         AMD_PP_TASK_COMPLETE_INIT,
 784                         false);
 785
 786         return 0;
 787 }
 788
 789 int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
 790                             uint16_t *size, uint8_t *frev, uint8_t *crev,
 791                             uint8_t **addr)
 792 {
 793         struct amdgpu_device *adev = smu->adev;
 794         uint16_t data_start;
 795
 796         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
 797                                            size, frev, crev, &data_start))
 798                 return -EINVAL;
 799
 800         *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
 801
 802         return 0;
 803 }
 804
 805 static int smu_initialize_pptable(struct smu_context *smu)
 806 {
 807         /* TODO */
 808         return 0;
 809 }
 810
 811 static int smu_smc_table_sw_init(struct smu_context *smu)
 812 {
 813         int ret;
 814
 815         ret = smu_initialize_pptable(smu);
 816         if (ret) {
 817                 pr_err("Failed to init smu_initialize_pptable!\n");
 818                 return ret;
 819         }
 820
 821         /**
 822          * Create smu_table structure, and init smc tables such as
 823          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 824          */
 825         ret = smu_init_smc_tables(smu);
 826         if (ret) {
 827                 pr_err("Failed to init smc tables!\n");
 828                 return ret;
 829         }
 830
 831         /**
 832          * Create smu_power_context structure, and allocate smu_dpm_context and
 833          * context size to fill the smu_power_context data.
 834          */
 835         ret = smu_init_power(smu);
 836         if (ret) {
 837                 pr_err("Failed to init smu_init_power!\n");
 838                 return ret;
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int smu_smc_table_sw_fini(struct smu_context *smu)
 845 {
 846         int ret;
 847
 848         ret = smu_fini_smc_tables(smu);
 849         if (ret) {
 850                 pr_err("Failed to smu_fini_smc_tables!\n");
 851                 return ret;
 852         }
 853
 854         return 0;
 855 }
 856
 857 static int smu_sw_init(void *handle)
 858 {
 859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 860         struct smu_context *smu = &adev->smu;
 861         int ret;
 862
 863         smu->pool_size = adev->pm.smu_prv_buffer_size;
 864         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 865         mutex_init(&smu->smu_feature.mutex);
 866         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 867         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 868         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 869
 870         mutex_init(&smu->smu_baco.mutex);
 871         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 872         smu->smu_baco.platform_support = false;
 873
 874         mutex_init(&smu->sensor_lock);
 875         mutex_init(&smu->metrics_lock);
 876
 877         smu->watermarks_bitmap = 0;
 878         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 879         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 880
 881         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 882         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 883         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 884         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 885         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 886         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 887         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 888         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 889
 890         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 891         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 892         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 893         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 894         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 895         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 896         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 897         smu->display_config = &adev->pm.pm_display_cfg;
 898
 899         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 900         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 901         ret = smu_init_microcode(smu);
 902         if (ret) {
 903                 pr_err("Failed to load smu firmware!\n");
 904                 return ret;
 905         }
 906
 907         ret = smu_smc_table_sw_init(smu);
 908         if (ret) {
 909                 pr_err("Failed to sw init smc table!\n");
 910                 return ret;
 911         }
 912
 913         ret = smu_register_irq_handler(smu);
 914         if (ret) {
 915                 pr_err("Failed to register smc irq handler!\n");
 916                 return ret;
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int smu_sw_fini(void *handle)
 923 {
 924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 925         struct smu_context *smu = &adev->smu;
 926         int ret;
 927
 928         kfree(smu->irq_source);
 929         smu->irq_source = NULL;
 930
 931         ret = smu_smc_table_sw_fini(smu);
 932         if (ret) {
 933                 pr_err("Failed to sw fini smc table!\n");
 934                 return ret;
 935         }
 936
 937         ret = smu_fini_power(smu);
 938         if (ret) {
 939                 pr_err("Failed to init smu_fini_power!\n");
 940                 return ret;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int smu_init_fb_allocations(struct smu_context *smu)
 947 {
 948         struct amdgpu_device *adev = smu->adev;
 949         struct smu_table_context *smu_table = &smu->smu_table;
 950         struct smu_table *tables = smu_table->tables;
 951         int ret, i;
 952
 953         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 954                 if (tables[i].size == 0)
 955                         continue;
 956                 ret = amdgpu_bo_create_kernel(adev,
 957                                               tables[i].size,
 958                                               tables[i].align,
 959                                               tables[i].domain,
 960                                               &tables[i].bo,
 961                                               &tables[i].mc_address,
 962                                               &tables[i].cpu_addr);
 963                 if (ret)
 964                         goto failed;
 965         }
 966
 967         return 0;
 968 failed:
 969         while (--i >= 0) {
 970                 if (tables[i].size == 0)
 971                         continue;
 972                 amdgpu_bo_free_kernel(&tables[i].bo,
 973                                       &tables[i].mc_address,
 974                                       &tables[i].cpu_addr);
 975
 976         }
 977         return ret;
 978 }
 979
 980 static int smu_fini_fb_allocations(struct smu_context *smu)
 981 {
 982         struct smu_table_context *smu_table = &smu->smu_table;
 983         struct smu_table *tables = smu_table->tables;
 984         uint32_t i = 0;
 985
 986         if (!tables)
 987                 return 0;
 988
 989         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 990                 if (tables[i].size == 0)
 991                         continue;
 992                 amdgpu_bo_free_kernel(&tables[i].bo,
 993                                       &tables[i].mc_address,
 994                                       &tables[i].cpu_addr);
 995         }
 996
 997         return 0;
 998 }
 999
1000 static int smu_smc_table_hw_init(struct smu_context *smu,
1001                                  bool initialize)
1002 {
1003         struct amdgpu_device *adev = smu->adev;
1004         int ret;
1005
1006         if (smu_is_dpm_running(smu) && adev->in_suspend) {
1007                 pr_info("dpm has been enabled\n");
1008                 return 0;
1009         }
1010
1011         if (adev->asic_type != CHIP_ARCTURUS) {
1012                 ret = smu_init_display_count(smu, 0);
1013                 if (ret)
1014                         return ret;
1015         }
1016
1017         if (initialize) {
1018                 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1019                 ret = smu_get_vbios_bootup_values(smu);
1020                 if (ret)
1021                         return ret;
1022
1023                 ret = smu_setup_pptable(smu);
1024                 if (ret)
1025                         return ret;
1026
1027                 ret = smu_get_clk_info_from_vbios(smu);
1028                 if (ret)
1029                         return ret;
1030
1031                 /*
1032                  * check if the format_revision in vbios is up to pptable header
1033                  * version, and the structure size is not 0.
1034                  */
1035                 ret = smu_check_pptable(smu);
1036                 if (ret)
1037                         return ret;
1038
1039                 /*
1040                  * allocate vram bos to store smc table contents.
1041                  */
1042                 ret = smu_init_fb_allocations(smu);
1043                 if (ret)
1044                         return ret;
1045
1046                 /*
1047                  * Parse pptable format and fill PPTable_t smc_pptable to
1048                  * smu_table_context structure. And read the smc_dpm_table from vbios,
1049                  * then fill it into smc_pptable.
1050                  */
1051                 ret = smu_parse_pptable(smu);
1052                 if (ret)
1053                         return ret;
1054
1055                 /*
1056                  * Send msg GetDriverIfVersion to check if the return value is equal
1057                  * with DRIVER_IF_VERSION of smc header.
1058                  */
1059                 ret = smu_check_fw_version(smu);
1060                 if (ret)
1061                         return ret;
1062         }
1063
1064         /* smu_dump_pptable(smu); */
1065
1066         /*
1067          * Copy pptable bo in the vram to smc with SMU MSGs such as
1068          * SetDriverDramAddr and TransferTableDram2Smu.
1069          */
1070         ret = smu_write_pptable(smu);
1071         if (ret)
1072                 return ret;
1073
1074         /* issue Run*Btc msg */
1075         ret = smu_run_btc(smu);
1076         if (ret)
1077                 return ret;
1078
1079         ret = smu_feature_set_allowed_mask(smu);
1080         if (ret)
1081                 return ret;
1082
1083         ret = smu_system_features_control(smu, true);
1084         if (ret)
1085                 return ret;
1086
1087         if (adev->asic_type != CHIP_ARCTURUS) {
1088                 ret = smu_notify_display_change(smu);
1089                 if (ret)
1090                         return ret;
1091
1092                 /*
1093                  * Set min deep sleep dce fclk with bootup value from vbios via
1094                  * SetMinDeepSleepDcefclk MSG.
1095                  */
1096                 ret = smu_set_min_dcef_deep_sleep(smu);
1097                 if (ret)
1098                         return ret;
1099         }
1100
1101         /*
1102          * Set initialized values (get from vbios) to dpm tables context such as
1103          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1104          * type of clks.
1105          */
1106         if (initialize) {
1107                 ret = smu_populate_smc_tables(smu);
1108                 if (ret)
1109                         return ret;
1110
1111                 ret = smu_init_max_sustainable_clocks(smu);
1112                 if (ret)
1113                         return ret;
1114         }
1115
1116         if (adev->asic_type != CHIP_ARCTURUS) {
1117                 ret = smu_override_pcie_parameters(smu);
1118                 if (ret)
1119                         return ret;
1120         }
1121
1122         ret = smu_set_default_od_settings(smu, initialize);
1123         if (ret)
1124                 return ret;
1125
1126         if (initialize) {
1127                 ret = smu_populate_umd_state_clk(smu);
1128                 if (ret)
1129                         return ret;
1130
1131                 ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
1132                 if (ret)
1133                         return ret;
1134         }
1135
1136         /*
1137          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1138          */
1139         ret = smu_set_tool_table_location(smu);
1140
1141         if (!smu_is_dpm_running(smu))
1142                 pr_info("dpm has been disabled\n");
1143
1144         return ret;
1145 }
1146
1147 /**
1148  * smu_alloc_memory_pool - allocate memory pool in the system memory
1149  *
1150  * @smu: amdgpu_device pointer
1151  *
1152  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1153  * and DramLogSetDramAddr can notify it changed.
1154  *
1155  * Returns 0 on success, error on failure.
1156  */
1157 static int smu_alloc_memory_pool(struct smu_context *smu)
1158 {
1159         struct amdgpu_device *adev = smu->adev;
1160         struct smu_table_context *smu_table = &smu->smu_table;
1161         struct smu_table *memory_pool = &smu_table->memory_pool;
1162         uint64_t pool_size = smu->pool_size;
1163         int ret = 0;
1164
1165         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1166                 return ret;
1167
1168         memory_pool->size = pool_size;
1169         memory_pool->align = PAGE_SIZE;
1170         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1171
1172         switch (pool_size) {
1173         case SMU_MEMORY_POOL_SIZE_256_MB:
1174         case SMU_MEMORY_POOL_SIZE_512_MB:
1175         case SMU_MEMORY_POOL_SIZE_1_GB:
1176         case SMU_MEMORY_POOL_SIZE_2_GB:
1177                 ret = amdgpu_bo_create_kernel(adev,
1178                                               memory_pool->size,
1179                                               memory_pool->align,
1180                                               memory_pool->domain,
1181                                               &memory_pool->bo,
1182                                               &memory_pool->mc_address,
1183                                               &memory_pool->cpu_addr);
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         return ret;
1190 }
1191
1192 static int smu_free_memory_pool(struct smu_context *smu)
1193 {
1194         struct smu_table_context *smu_table = &smu->smu_table;
1195         struct smu_table *memory_pool = &smu_table->memory_pool;
1196
1197         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1198                 return 0;
1199
1200         amdgpu_bo_free_kernel(&memory_pool->bo,
1201                               &memory_pool->mc_address,
1202                               &memory_pool->cpu_addr);
1203
1204         memset(memory_pool, 0, sizeof(struct smu_table));
1205
1206         return 0;
1207 }
1208
1209 static int smu_start_smc_engine(struct smu_context *smu)
1210 {
1211         struct amdgpu_device *adev = smu->adev;
1212         int ret = 0;
1213
1214         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1215                 if (adev->asic_type < CHIP_NAVI10) {
1216                         if (smu->ppt_funcs->load_microcode) {
1217                                 ret = smu->ppt_funcs->load_microcode(smu);
1218                                 if (ret)
1219                                         return ret;
1220                         }
1221                 }
1222         }
1223
1224         if (smu->ppt_funcs->check_fw_status) {
1225                 ret = smu->ppt_funcs->check_fw_status(smu);
1226                 if (ret)
1227                         pr_err("SMC is not ready\n");
1228         }
1229
1230         return ret;
1231 }
1232
1233 static int smu_hw_init(void *handle)
1234 {
1235         int ret;
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237         struct smu_context *smu = &adev->smu;
1238
1239         ret = smu_start_smc_engine(smu);
1240         if (ret) {
1241                 pr_err("SMU is not ready yet!\n");
1242                 return ret;
1243         }
1244
1245         if (adev->flags & AMD_IS_APU) {
1246                 smu_powergate_sdma(&adev->smu, false);
1247                 smu_powergate_vcn(&adev->smu, false);
1248                 smu_powergate_jpeg(&adev->smu, false);
1249                 smu_set_gfx_cgpg(&adev->smu, true);
1250         }
1251
1252         if (!smu->pm_enabled)
1253                 return 0;
1254
1255         ret = smu_feature_init_dpm(smu);
1256         if (ret)
1257                 goto failed;
1258
1259         ret = smu_smc_table_hw_init(smu, true);
1260         if (ret)
1261                 goto failed;
1262
1263         ret = smu_alloc_memory_pool(smu);
1264         if (ret)
1265                 goto failed;
1266
1267         /*
1268          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1269          * pool location.
1270          */
1271         ret = smu_notify_memory_pool_location(smu);
1272         if (ret)
1273                 goto failed;
1274
1275         ret = smu_start_thermal_control(smu);
1276         if (ret)
1277                 goto failed;
1278
1279         if (!smu->pm_enabled)
1280                 adev->pm.dpm_enabled = false;
1281         else
1282                 adev->pm.dpm_enabled = true;    /* TODO: will set dpm_enabled flag while VCN and DAL DPM is workable */
1283
1284         pr_info("SMU is initialized successfully!\n");
1285
1286         return 0;
1287
1288 failed:
1289         return ret;
1290 }
1291
1292 static int smu_stop_dpms(struct smu_context *smu)
1293 {
1294         return smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
1295 }
1296
1297 static int smu_hw_fini(void *handle)
1298 {
1299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300         struct smu_context *smu = &adev->smu;
1301         struct smu_table_context *table_context = &smu->smu_table;
1302         int ret = 0;
1303
1304         if (adev->flags & AMD_IS_APU) {
1305                 smu_powergate_sdma(&adev->smu, true);
1306                 smu_powergate_vcn(&adev->smu, true);
1307                 smu_powergate_jpeg(&adev->smu, true);
1308         }
1309
1310         ret = smu_stop_thermal_control(smu);
1311         if (ret) {
1312                 pr_warn("Fail to stop thermal control!\n");
1313                 return ret;
1314         }
1315
1316         /*
1317          * For custom pptable uploading, skip the DPM features
1318          * disable process on Navi1x ASICs.
1319          *   - As the gfx related features are under control of
1320          *     RLC on those ASICs. RLC reinitialization will be
1321          *     needed to reenable them. That will cost much more
1322          *     efforts.
1323          *
1324          *   - SMU firmware can handle the DPM reenablement
1325          *     properly.
1326          */
1327         if (!smu->uploading_custom_pp_table ||
1328             !((adev->asic_type >= CHIP_NAVI10) &&
1329               (adev->asic_type <= CHIP_NAVI12))) {
1330                 ret = smu_stop_dpms(smu);
1331                 if (ret) {
1332                         pr_warn("Fail to stop Dpms!\n");
1333                         return ret;
1334                 }
1335         }
1336
1337         kfree(table_context->driver_pptable);
1338         table_context->driver_pptable = NULL;
1339
1340         kfree(table_context->max_sustainable_clocks);
1341         table_context->max_sustainable_clocks = NULL;
1342
1343         kfree(table_context->overdrive_table);
1344         table_context->overdrive_table = NULL;
1345
1346         ret = smu_fini_fb_allocations(smu);
1347         if (ret)
1348                 return ret;
1349
1350         ret = smu_free_memory_pool(smu);
1351         if (ret)
1352                 return ret;
1353
1354         return 0;
1355 }
1356
1357 int smu_reset(struct smu_context *smu)
1358 {
1359         struct amdgpu_device *adev = smu->adev;
1360         int ret = 0;
1361
1362         ret = smu_hw_fini(adev);
1363         if (ret)
1364                 return ret;
1365
1366         ret = smu_hw_init(adev);
1367         if (ret)
1368                 return ret;
1369
1370         return ret;
1371 }
1372
1373 static int smu_suspend(void *handle)
1374 {
1375         int ret;
1376         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1377         struct smu_context *smu = &adev->smu;
1378         bool baco_feature_is_enabled = false;
1379
1380         if(!(adev->flags & AMD_IS_APU))
1381                 baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
1382
1383         ret = smu_system_features_control(smu, false);
1384         if (ret)
1385                 return ret;
1386
1387         if (baco_feature_is_enabled) {
1388                 ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
1389                 if (ret) {
1390                         pr_warn("set BACO feature enabled failed, return %d\n", ret);
1391                         return ret;
1392                 }
1393         }
1394
1395         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1396
1397         if (adev->asic_type >= CHIP_NAVI10 &&
1398             adev->gfx.rlc.funcs->stop)
1399                 adev->gfx.rlc.funcs->stop(adev);
1400         if (smu->is_apu)
1401                 smu_set_gfx_cgpg(&adev->smu, false);
1402
1403         return 0;
1404 }
1405
1406 static int smu_resume(void *handle)
1407 {
1408         int ret;
1409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410         struct smu_context *smu = &adev->smu;
1411
1412         pr_info("SMU is resuming...\n");
1413
1414         ret = smu_start_smc_engine(smu);
1415         if (ret) {
1416                 pr_err("SMU is not ready yet!\n");
1417                 goto failed;
1418         }
1419
1420         ret = smu_smc_table_hw_init(smu, false);
1421         if (ret)
1422                 goto failed;
1423
1424         ret = smu_start_thermal_control(smu);
1425         if (ret)
1426                 goto failed;
1427
1428         if (smu->is_apu)
1429                 smu_set_gfx_cgpg(&adev->smu, true);
1430
1431         smu->disable_uclk_switch = 0;
1432
1433         pr_info("SMU is resumed successfully!\n");
1434
1435         return 0;
1436
1437 failed:
1438         return ret;
1439 }
1440
1441 int smu_display_configuration_change(struct smu_context *smu,
1442                                      const struct amd_pp_display_configuration *display_config)
1443 {
1444         int index = 0;
1445         int num_of_active_display = 0;
1446
1447         if (!smu->pm_enabled || !is_support_sw_smu(smu->adev))
1448                 return -EINVAL;
1449
1450         if (!display_config)
1451                 return -EINVAL;
1452
1453         mutex_lock(&smu->mutex);
1454
1455         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
1456                 smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
1457                                 display_config->min_dcef_deep_sleep_set_clk / 100);
1458
1459         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1460                 if (display_config->displays[index].controller_id != 0)
1461                         num_of_active_display++;
1462         }
1463
1464         smu_set_active_display_count(smu, num_of_active_display);
1465
1466         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1467                            display_config->cpu_cc6_disable,
1468                            display_config->cpu_pstate_disable,
1469                            display_config->nb_pstate_switch_disable);
1470
1471         mutex_unlock(&smu->mutex);
1472
1473         return 0;
1474 }
1475
1476 static int smu_get_clock_info(struct smu_context *smu,
1477                               struct smu_clock_info *clk_info,
1478                               enum smu_perf_level_designation designation)
1479 {
1480         int ret;
1481         struct smu_performance_level level = {0};
1482
1483         if (!clk_info)
1484                 return -EINVAL;
1485
1486         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1487         if (ret)
1488                 return -EINVAL;
1489
1490         clk_info->min_mem_clk = level.memory_clock;
1491         clk_info->min_eng_clk = level.core_clock;
1492         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1493
1494         ret = smu_get_perf_level(smu, designation, &level);
1495         if (ret)
1496                 return -EINVAL;
1497
1498         clk_info->min_mem_clk = level.memory_clock;
1499         clk_info->min_eng_clk = level.core_clock;
1500         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1501
1502         return 0;
1503 }
1504
1505 int smu_get_current_clocks(struct smu_context *smu,
1506                            struct amd_pp_clock_info *clocks)
1507 {
1508         struct amd_pp_simple_clock_info simple_clocks = {0};
1509         struct smu_clock_info hw_clocks;
1510         int ret = 0;
1511
1512         if (!is_support_sw_smu(smu->adev))
1513                 return -EINVAL;
1514
1515         mutex_lock(&smu->mutex);
1516
1517         smu_get_dal_power_level(smu, &simple_clocks);
1518
1519         if (smu->support_power_containment)
1520                 ret = smu_get_clock_info(smu, &hw_clocks,
1521                                          PERF_LEVEL_POWER_CONTAINMENT);
1522         else
1523                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1524
1525         if (ret) {
1526                 pr_err("Error in smu_get_clock_info\n");
1527                 goto failed;
1528         }
1529
1530         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1531         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1532         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1533         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1534         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1535         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1536         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1537         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1538
1539         if (simple_clocks.level == 0)
1540                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1541         else
1542                 clocks->max_clocks_state = simple_clocks.level;
1543
1544         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1545                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1546                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1547         }
1548
1549 failed:
1550         mutex_unlock(&smu->mutex);
1551         return ret;
1552 }
1553
1554 static int smu_set_clockgating_state(void *handle,
1555                                      enum amd_clockgating_state state)
1556 {
1557         return 0;
1558 }
1559
1560 static int smu_set_powergating_state(void *handle,
1561                                      enum amd_powergating_state state)
1562 {
1563         return 0;
1564 }
1565
1566 static int smu_enable_umd_pstate(void *handle,
1567                       enum amd_dpm_forced_level *level)
1568 {
1569         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1570                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1571                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1572                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1573
1574         struct smu_context *smu = (struct smu_context*)(handle);
1575         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1576
1577         if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
1578                 return -EINVAL;
1579
1580         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1581                 /* enter umd pstate, save current level, disable gfx cg*/
1582                 if (*level & profile_mode_mask) {
1583                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1584                         smu_dpm_ctx->enable_umd_pstate = true;
1585                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1586                                                                AMD_IP_BLOCK_TYPE_GFX,
1587                                                                AMD_CG_STATE_UNGATE);
1588                         amdgpu_device_ip_set_powergating_state(smu->adev,
1589                                                                AMD_IP_BLOCK_TYPE_GFX,
1590                                                                AMD_PG_STATE_UNGATE);
1591                 }
1592         } else {
1593                 /* exit umd pstate, restore level, enable gfx cg*/
1594                 if (!(*level & profile_mode_mask)) {
1595                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1596                                 *level = smu_dpm_ctx->saved_dpm_level;
1597                         smu_dpm_ctx->enable_umd_pstate = false;
1598                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1599                                                                AMD_IP_BLOCK_TYPE_GFX,
1600                                                                AMD_CG_STATE_GATE);
1601                         amdgpu_device_ip_set_powergating_state(smu->adev,
1602                                                                AMD_IP_BLOCK_TYPE_GFX,
1603                                                                AMD_PG_STATE_GATE);
1604                 }
1605         }
1606
1607         return 0;
1608 }
1609
1610 static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1611 {
1612         int ret = 0;
1613         uint32_t sclk_mask, mclk_mask, soc_mask;
1614
1615         switch (level) {
1616         case AMD_DPM_FORCED_LEVEL_HIGH:
1617                 ret = smu_force_dpm_limit_value(smu, true);
1618                 break;
1619         case AMD_DPM_FORCED_LEVEL_LOW:
1620                 ret = smu_force_dpm_limit_value(smu, false);
1621                 break;
1622         case AMD_DPM_FORCED_LEVEL_AUTO:
1623         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1624                 ret = smu_unforce_dpm_levels(smu);
1625                 break;
1626         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1627         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1628         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1629                 ret = smu_get_profiling_clk_mask(smu, level,
1630                                                  &sclk_mask,
1631                                                  &mclk_mask,
1632                                                  &soc_mask);
1633                 if (ret)
1634                         return ret;
1635                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1636                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1637                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1638                 break;
1639         case AMD_DPM_FORCED_LEVEL_MANUAL:
1640         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1641         default:
1642                 break;
1643         }
1644         return ret;
1645 }
1646
1647 int smu_adjust_power_state_dynamic(struct smu_context *smu,
1648                                    enum amd_dpm_forced_level level,
1649                                    bool skip_display_settings)
1650 {
1651         int ret = 0;
1652         int index = 0;
1653         long workload;
1654         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1655
1656         if (!smu->pm_enabled)
1657                 return -EINVAL;
1658
1659         if (!skip_display_settings) {
1660                 ret = smu_display_config_changed(smu);
1661                 if (ret) {
1662                         pr_err("Failed to change display config!");
1663                         return ret;
1664                 }
1665         }
1666
1667         ret = smu_apply_clocks_adjust_rules(smu);
1668         if (ret) {
1669                 pr_err("Failed to apply clocks adjust rules!");
1670                 return ret;
1671         }
1672
1673         if (!skip_display_settings) {
1674                 ret = smu_notify_smc_display_config(smu);
1675                 if (ret) {
1676                         pr_err("Failed to notify smc display config!");
1677                         return ret;
1678                 }
1679         }
1680
1681         if (smu_dpm_ctx->dpm_level != level) {
1682                 ret = smu_asic_set_performance_level(smu, level);
1683                 if (ret) {
1684                         ret = smu_default_set_performance_level(smu, level);
1685                         if (ret) {
1686                                 pr_err("Failed to set performance level!");
1687                                 return ret;
1688                         }
1689                 }
1690
1691                 /* update the saved copy */
1692                 smu_dpm_ctx->dpm_level = level;
1693         }
1694
1695         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1696                 index = fls(smu->workload_mask);
1697                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1698                 workload = smu->workload_setting[index];
1699
1700                 if (smu->power_profile_mode != workload)
1701                         smu_set_power_profile_mode(smu, &workload, 0, false);
1702         }
1703
1704         return ret;
1705 }
1706
1707 int smu_handle_task(struct smu_context *smu,
1708                     enum amd_dpm_forced_level level,
1709                     enum amd_pp_task task_id,
1710                     bool lock_needed)
1711 {
1712         int ret = 0;
1713
1714         if (lock_needed)
1715                 mutex_lock(&smu->mutex);
1716
1717         switch (task_id) {
1718         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1719                 ret = smu_pre_display_config_changed(smu);
1720                 if (ret)
1721                         goto out;
1722                 ret = smu_set_cpu_power_state(smu);
1723                 if (ret)
1724                         goto out;
1725                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1726                 break;
1727         case AMD_PP_TASK_COMPLETE_INIT:
1728         case AMD_PP_TASK_READJUST_POWER_STATE:
1729                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1730                 break;
1731         default:
1732                 break;
1733         }
1734
1735 out:
1736         if (lock_needed)
1737                 mutex_unlock(&smu->mutex);
1738
1739         return ret;
1740 }
1741
1742 int smu_switch_power_profile(struct smu_context *smu,
1743                              enum PP_SMC_POWER_PROFILE type,
1744                              bool en)
1745 {
1746         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1747         long workload;
1748         uint32_t index;
1749
1750         if (!smu->pm_enabled)
1751                 return -EINVAL;
1752
1753         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1754                 return -EINVAL;
1755
1756         mutex_lock(&smu->mutex);
1757
1758         if (!en) {
1759                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1760                 index = fls(smu->workload_mask);
1761                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1762                 workload = smu->workload_setting[index];
1763         } else {
1764                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1765                 index = fls(smu->workload_mask);
1766                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1767                 workload = smu->workload_setting[index];
1768         }
1769
1770         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1771                 smu_set_power_profile_mode(smu, &workload, 0, false);
1772
1773         mutex_unlock(&smu->mutex);
1774
1775         return 0;
1776 }
1777
1778 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1779 {
1780         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1781         enum amd_dpm_forced_level level;
1782
1783         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1784                 return -EINVAL;
1785
1786         mutex_lock(&(smu->mutex));
1787         level = smu_dpm_ctx->dpm_level;
1788         mutex_unlock(&(smu->mutex));
1789
1790         return level;
1791 }
1792
1793 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1794 {
1795         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1796         int ret = 0;
1797
1798         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1799                 return -EINVAL;
1800
1801         mutex_lock(&smu->mutex);
1802
1803         ret = smu_enable_umd_pstate(smu, &level);
1804         if (ret) {
1805                 mutex_unlock(&smu->mutex);
1806                 return ret;
1807         }
1808
1809         ret = smu_handle_task(smu, level,
1810                               AMD_PP_TASK_READJUST_POWER_STATE,
1811                               false);
1812
1813         mutex_unlock(&smu->mutex);
1814
1815         return ret;
1816 }
1817
1818 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1819 {
1820         int ret = 0;
1821
1822         mutex_lock(&smu->mutex);
1823         ret = smu_init_display_count(smu, count);
1824         mutex_unlock(&smu->mutex);
1825
1826         return ret;
1827 }
1828
1829 int smu_force_clk_levels(struct smu_context *smu,
1830                          enum smu_clk_type clk_type,
1831                          uint32_t mask,
1832                          bool lock_needed)
1833 {
1834         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1835         int ret = 0;
1836
1837         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1838                 pr_debug("force clock level is for dpm manual mode only.\n");
1839                 return -EINVAL;
1840         }
1841
1842         if (lock_needed)
1843                 mutex_lock(&smu->mutex);
1844
1845         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1846                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1847
1848         if (lock_needed)
1849                 mutex_unlock(&smu->mutex);
1850
1851         return ret;
1852 }
1853
1854 int smu_set_mp1_state(struct smu_context *smu,
1855                       enum pp_mp1_state mp1_state)
1856 {
1857         uint16_t msg;
1858         int ret;
1859
1860         /*
1861          * The SMC is not fully ready. That may be
1862          * expected as the IP may be masked.
1863          * So, just return without error.
1864          */
1865         if (!smu->pm_enabled)
1866                 return 0;
1867
1868         mutex_lock(&smu->mutex);
1869
1870         switch (mp1_state) {
1871         case PP_MP1_STATE_SHUTDOWN:
1872                 msg = SMU_MSG_PrepareMp1ForShutdown;
1873                 break;
1874         case PP_MP1_STATE_UNLOAD:
1875                 msg = SMU_MSG_PrepareMp1ForUnload;
1876                 break;
1877         case PP_MP1_STATE_RESET:
1878                 msg = SMU_MSG_PrepareMp1ForReset;
1879                 break;
1880         case PP_MP1_STATE_NONE:
1881         default:
1882                 mutex_unlock(&smu->mutex);
1883                 return 0;
1884         }
1885
1886         /* some asics may not support those messages */
1887         if (smu_msg_get_index(smu, msg) < 0) {
1888                 mutex_unlock(&smu->mutex);
1889                 return 0;
1890         }
1891
1892         ret = smu_send_smc_msg(smu, msg);
1893         if (ret)
1894                 pr_err("[PrepareMp1] Failed!\n");
1895
1896         mutex_unlock(&smu->mutex);
1897
1898         return ret;
1899 }
1900
1901 int smu_set_df_cstate(struct smu_context *smu,
1902                       enum pp_df_cstate state)
1903 {
1904         int ret = 0;
1905
1906         /*
1907          * The SMC is not fully ready. That may be
1908          * expected as the IP may be masked.
1909          * So, just return without error.
1910          */
1911         if (!smu->pm_enabled)
1912                 return 0;
1913
1914         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1915                 return 0;
1916
1917         mutex_lock(&smu->mutex);
1918
1919         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1920         if (ret)
1921                 pr_err("[SetDfCstate] failed!\n");
1922
1923         mutex_unlock(&smu->mutex);
1924
1925         return ret;
1926 }
1927
1928 int smu_write_watermarks_table(struct smu_context *smu)
1929 {
1930         int ret = 0;
1931         struct smu_table_context *smu_table = &smu->smu_table;
1932         struct smu_table *table = NULL;
1933
1934         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
1935
1936         if (!table->cpu_addr)
1937                 return -EINVAL;
1938
1939         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
1940                                 true);
1941
1942         return ret;
1943 }
1944
1945 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1946                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1947 {
1948         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1949         void *table = watermarks->cpu_addr;
1950
1951         mutex_lock(&smu->mutex);
1952
1953         if (!smu->disable_watermark &&
1954                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1955                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1956                 smu_set_watermarks_table(smu, table, clock_ranges);
1957                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1958                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1959         }
1960
1961         mutex_unlock(&smu->mutex);
1962
1963         return 0;
1964 }
1965
1966 const struct amd_ip_funcs smu_ip_funcs = {
1967         .name = "smu",
1968         .early_init = smu_early_init,
1969         .late_init = smu_late_init,
1970         .sw_init = smu_sw_init,
1971         .sw_fini = smu_sw_fini,
1972         .hw_init = smu_hw_init,
1973         .hw_fini = smu_hw_fini,
1974         .suspend = smu_suspend,
1975         .resume = smu_resume,
1976         .is_idle = NULL,
1977         .check_soft_reset = NULL,
1978         .wait_for_idle = NULL,
1979         .soft_reset = NULL,
1980         .set_clockgating_state = smu_set_clockgating_state,
1981         .set_powergating_state = smu_set_powergating_state,
1982         .enable_umd_pstate = smu_enable_umd_pstate,
1983 };
1984
1985 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1986 {
1987         .type = AMD_IP_BLOCK_TYPE_SMC,
1988         .major = 11,
1989         .minor = 0,
1990         .rev = 0,
1991         .funcs = &smu_ip_funcs,
1992 };
1993
1994 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1995 {
1996         .type = AMD_IP_BLOCK_TYPE_SMC,
1997         .major = 12,
1998         .minor = 0,
1999         .rev = 0,
2000         .funcs = &smu_ip_funcs,
2001 };
2002
2003 int smu_load_microcode(struct smu_context *smu)
2004 {
2005         int ret = 0;
2006
2007         mutex_lock(&smu->mutex);
2008
2009         if (smu->ppt_funcs->load_microcode)
2010                 ret = smu->ppt_funcs->load_microcode(smu);
2011
2012         mutex_unlock(&smu->mutex);
2013
2014         return ret;
2015 }
2016
2017 int smu_check_fw_status(struct smu_context *smu)
2018 {
2019         int ret = 0;
2020
2021         mutex_lock(&smu->mutex);
2022
2023         if (smu->ppt_funcs->check_fw_status)
2024                 ret = smu->ppt_funcs->check_fw_status(smu);
2025
2026         mutex_unlock(&smu->mutex);
2027
2028         return ret;
2029 }
2030
2031 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2032 {
2033         int ret = 0;
2034
2035         mutex_lock(&smu->mutex);
2036
2037         if (smu->ppt_funcs->set_gfx_cgpg)
2038                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2039
2040         mutex_unlock(&smu->mutex);
2041
2042         return ret;
2043 }
2044
2045 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
2046 {
2047         int ret = 0;
2048
2049         mutex_lock(&smu->mutex);
2050
2051         if (smu->ppt_funcs->set_fan_speed_rpm)
2052                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2053
2054         mutex_unlock(&smu->mutex);
2055
2056         return ret;
2057 }
2058
2059 int smu_get_power_limit(struct smu_context *smu,
2060                         uint32_t *limit,
2061                         bool def,
2062                         bool lock_needed)
2063 {
2064         int ret = 0;
2065
2066         if (lock_needed)
2067                 mutex_lock(&smu->mutex);
2068
2069         if (smu->ppt_funcs->get_power_limit)
2070                 ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
2071
2072         if (lock_needed)
2073                 mutex_unlock(&smu->mutex);
2074
2075         return ret;
2076 }
2077
2078 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
2079 {
2080         int ret = 0;
2081
2082         mutex_lock(&smu->mutex);
2083
2084         if (smu->ppt_funcs->set_power_limit)
2085                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2086
2087         mutex_unlock(&smu->mutex);
2088
2089         return ret;
2090 }
2091
2092 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2093 {
2094         int ret = 0;
2095
2096         mutex_lock(&smu->mutex);
2097
2098         if (smu->ppt_funcs->print_clk_levels)
2099                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2100
2101         mutex_unlock(&smu->mutex);
2102
2103         return ret;
2104 }
2105
2106 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
2107 {
2108         int ret = 0;
2109
2110         mutex_lock(&smu->mutex);
2111
2112         if (smu->ppt_funcs->get_od_percentage)
2113                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2114
2115         mutex_unlock(&smu->mutex);
2116
2117         return ret;
2118 }
2119
2120 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2121 {
2122         int ret = 0;
2123
2124         mutex_lock(&smu->mutex);
2125
2126         if (smu->ppt_funcs->set_od_percentage)
2127                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2128
2129         mutex_unlock(&smu->mutex);
2130
2131         return ret;
2132 }
2133
2134 int smu_od_edit_dpm_table(struct smu_context *smu,
2135                           enum PP_OD_DPM_TABLE_COMMAND type,
2136                           long *input, uint32_t size)
2137 {
2138         int ret = 0;
2139
2140         mutex_lock(&smu->mutex);
2141
2142         if (smu->ppt_funcs->od_edit_dpm_table)
2143                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2144
2145         mutex_unlock(&smu->mutex);
2146
2147         return ret;
2148 }
2149
2150 int smu_read_sensor(struct smu_context *smu,
2151                     enum amd_pp_sensors sensor,
2152                     void *data, uint32_t *size)
2153 {
2154         int ret = 0;
2155
2156         mutex_lock(&smu->mutex);
2157
2158         if (smu->ppt_funcs->read_sensor)
2159                 ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
2160
2161         mutex_unlock(&smu->mutex);
2162
2163         return ret;
2164 }
2165
2166 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2167 {
2168         int ret = 0;
2169
2170         mutex_lock(&smu->mutex);
2171
2172         if (smu->ppt_funcs->get_power_profile_mode)
2173                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2174
2175         mutex_unlock(&smu->mutex);
2176
2177         return ret;
2178 }
2179
2180 int smu_set_power_profile_mode(struct smu_context *smu,
2181                                long *param,
2182                                uint32_t param_size,
2183                                bool lock_needed)
2184 {
2185         int ret = 0;
2186
2187         if (lock_needed)
2188                 mutex_lock(&smu->mutex);
2189
2190         if (smu->ppt_funcs->set_power_profile_mode)
2191                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2192
2193         if (lock_needed)
2194                 mutex_unlock(&smu->mutex);
2195
2196         return ret;
2197 }
2198
2199
2200 int smu_get_fan_control_mode(struct smu_context *smu)
2201 {
2202         int ret = 0;
2203
2204         mutex_lock(&smu->mutex);
2205
2206         if (smu->ppt_funcs->get_fan_control_mode)
2207                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2208
2209         mutex_unlock(&smu->mutex);
2210
2211         return ret;
2212 }
2213
2214 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2215 {
2216         int ret = 0;
2217
2218         mutex_lock(&smu->mutex);
2219
2220         if (smu->ppt_funcs->set_fan_control_mode)
2221                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2222
2223         mutex_unlock(&smu->mutex);
2224
2225         return ret;
2226 }
2227
2228 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2229 {
2230         int ret = 0;
2231
2232         mutex_lock(&smu->mutex);
2233
2234         if (smu->ppt_funcs->get_fan_speed_percent)
2235                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2236
2237         mutex_unlock(&smu->mutex);
2238
2239         return ret;
2240 }
2241
2242 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2243 {
2244         int ret = 0;
2245
2246         mutex_lock(&smu->mutex);
2247
2248         if (smu->ppt_funcs->set_fan_speed_percent)
2249                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2250
2251         mutex_unlock(&smu->mutex);
2252
2253         return ret;
2254 }
2255
2256 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2257 {
2258         int ret = 0;
2259
2260         mutex_lock(&smu->mutex);
2261
2262         if (smu->ppt_funcs->get_fan_speed_rpm)
2263                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2264
2265         mutex_unlock(&smu->mutex);
2266
2267         return ret;
2268 }
2269
2270 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2271 {
2272         int ret = 0;
2273
2274         mutex_lock(&smu->mutex);
2275
2276         if (smu->ppt_funcs->set_deep_sleep_dcefclk)
2277                 ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
2278
2279         mutex_unlock(&smu->mutex);
2280
2281         return ret;
2282 }
2283
2284 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2285 {
2286         int ret = 0;
2287
2288         mutex_lock(&smu->mutex);
2289
2290         if (smu->ppt_funcs->set_active_display_count)
2291                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2292
2293         mutex_unlock(&smu->mutex);
2294
2295         return ret;
2296 }
2297
2298 int smu_get_clock_by_type(struct smu_context *smu,
2299                           enum amd_pp_clock_type type,
2300                           struct amd_pp_clocks *clocks)
2301 {
2302         int ret = 0;
2303
2304         mutex_lock(&smu->mutex);
2305
2306         if (smu->ppt_funcs->get_clock_by_type)
2307                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2308
2309         mutex_unlock(&smu->mutex);
2310
2311         return ret;
2312 }
2313
2314 int smu_get_max_high_clocks(struct smu_context *smu,
2315                             struct amd_pp_simple_clock_info *clocks)
2316 {
2317         int ret = 0;
2318
2319         mutex_lock(&smu->mutex);
2320
2321         if (smu->ppt_funcs->get_max_high_clocks)
2322                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2323
2324         mutex_unlock(&smu->mutex);
2325
2326         return ret;
2327 }
2328
2329 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2330                                        enum smu_clk_type clk_type,
2331                                        struct pp_clock_levels_with_latency *clocks)
2332 {
2333         int ret = 0;
2334
2335         mutex_lock(&smu->mutex);
2336
2337         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2338                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2339
2340         mutex_unlock(&smu->mutex);
2341
2342         return ret;
2343 }
2344
2345 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2346                                        enum amd_pp_clock_type type,
2347                                        struct pp_clock_levels_with_voltage *clocks)
2348 {
2349         int ret = 0;
2350
2351         mutex_lock(&smu->mutex);
2352
2353         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2354                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2355
2356         mutex_unlock(&smu->mutex);
2357
2358         return ret;
2359 }
2360
2361
2362 int smu_display_clock_voltage_request(struct smu_context *smu,
2363                                       struct pp_display_clock_request *clock_req)
2364 {
2365         int ret = 0;
2366
2367         mutex_lock(&smu->mutex);
2368
2369         if (smu->ppt_funcs->display_clock_voltage_request)
2370                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2371
2372         mutex_unlock(&smu->mutex);
2373
2374         return ret;
2375 }
2376
2377
2378 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2379 {
2380         int ret = -EINVAL;
2381
2382         mutex_lock(&smu->mutex);
2383
2384         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2385                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2386
2387         mutex_unlock(&smu->mutex);
2388
2389         return ret;
2390 }
2391
2392 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2393 {
2394         int ret = 0;
2395
2396         mutex_lock(&smu->mutex);
2397
2398         if (smu->ppt_funcs->notify_smu_enable_pwe)
2399                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2400
2401         mutex_unlock(&smu->mutex);
2402
2403         return ret;
2404 }
2405
2406 int smu_set_xgmi_pstate(struct smu_context *smu,
2407                         uint32_t pstate)
2408 {
2409         int ret = 0;
2410
2411         mutex_lock(&smu->mutex);
2412
2413         if (smu->ppt_funcs->set_xgmi_pstate)
2414                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2415
2416         mutex_unlock(&smu->mutex);
2417
2418         return ret;
2419 }
2420
2421 int smu_set_azalia_d3_pme(struct smu_context *smu)
2422 {
2423         int ret = 0;
2424
2425         mutex_lock(&smu->mutex);
2426
2427         if (smu->ppt_funcs->set_azalia_d3_pme)
2428                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2429
2430         mutex_unlock(&smu->mutex);
2431
2432         return ret;
2433 }
2434
2435 bool smu_baco_is_support(struct smu_context *smu)
2436 {
2437         bool ret = false;
2438
2439         mutex_lock(&smu->mutex);
2440
2441         if (smu->ppt_funcs->baco_is_support)
2442                 ret = smu->ppt_funcs->baco_is_support(smu);
2443
2444         mutex_unlock(&smu->mutex);
2445
2446         return ret;
2447 }
2448
2449 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2450 {
2451         if (smu->ppt_funcs->baco_get_state)
2452                 return -EINVAL;
2453
2454         mutex_lock(&smu->mutex);
2455         *state = smu->ppt_funcs->baco_get_state(smu);
2456         mutex_unlock(&smu->mutex);
2457
2458         return 0;
2459 }
2460
2461 int smu_baco_enter(struct smu_context *smu)
2462 {
2463         int ret = 0;
2464
2465         mutex_lock(&smu->mutex);
2466
2467         if (smu->ppt_funcs->baco_enter)
2468                 ret = smu->ppt_funcs->baco_enter(smu);
2469
2470         mutex_unlock(&smu->mutex);
2471
2472         return ret;
2473 }
2474
2475 int smu_baco_exit(struct smu_context *smu)
2476 {
2477         int ret = 0;
2478
2479         mutex_lock(&smu->mutex);
2480
2481         if (smu->ppt_funcs->baco_exit)
2482                 ret = smu->ppt_funcs->baco_exit(smu);
2483
2484         mutex_unlock(&smu->mutex);
2485
2486         return ret;
2487 }
2488
2489 int smu_mode2_reset(struct smu_context *smu)
2490 {
2491         int ret = 0;
2492
2493         mutex_lock(&smu->mutex);
2494
2495         if (smu->ppt_funcs->mode2_reset)
2496                 ret = smu->ppt_funcs->mode2_reset(smu);
2497
2498         mutex_unlock(&smu->mutex);
2499
2500         return ret;
2501 }
2502
2503 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2504                                          struct pp_smu_nv_clock_table *max_clocks)
2505 {
2506         int ret = 0;
2507
2508         mutex_lock(&smu->mutex);
2509
2510         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2511                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2512
2513         mutex_unlock(&smu->mutex);
2514
2515         return ret;
2516 }
2517
2518 int smu_get_uclk_dpm_states(struct smu_context *smu,
2519                             unsigned int *clock_values_in_khz,
2520                             unsigned int *num_states)
2521 {
2522         int ret = 0;
2523
2524         mutex_lock(&smu->mutex);
2525
2526         if (smu->ppt_funcs->get_uclk_dpm_states)
2527                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2528
2529         mutex_unlock(&smu->mutex);
2530
2531         return ret;
2532 }
2533
2534 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2535 {
2536         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2537
2538         mutex_lock(&smu->mutex);
2539
2540         if (smu->ppt_funcs->get_current_power_state)
2541                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2542
2543         mutex_unlock(&smu->mutex);
2544
2545         return pm_state;
2546 }
2547
2548 int smu_get_dpm_clock_table(struct smu_context *smu,
2549                             struct dpm_clocks *clock_table)
2550 {
2551         int ret = 0;
2552
2553         mutex_lock(&smu->mutex);
2554
2555         if (smu->ppt_funcs->get_dpm_clock_table)
2556                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2557
2558         mutex_unlock(&smu->mutex);
2559
2560         return ret;
2561 }
2562
2563 uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
2564 {
2565         uint32_t ret = 0;
2566
2567         if (smu->ppt_funcs->get_pptable_power_limit)
2568                 ret = smu->ppt_funcs->get_pptable_power_limit(smu);
2569
2570         return ret;
2571 }
2572
2573 int smu_send_smc_msg(struct smu_context *smu,
2574                      enum smu_message_type msg)
2575 {
2576         int ret;
2577
2578         ret = smu_send_smc_msg_with_param(smu, msg, 0);
2579         return ret;
2580 }