drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39
  40 #define CTF_OFFSET_EDGE                 5
  41 #define CTF_OFFSET_HOTSPOT              5
  42 #define CTF_OFFSET_HBM                  5
  43
  44 #define MSG_MAP(msg, index) \
  45         [SMU_MSG_##msg] = {1, (index)}
  46 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  47         [smu_feature] = {1, (arcturus_feature)}
  48
  49 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  50 #define SMU_FEATURES_LOW_SHIFT       0
  51 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  52 #define SMU_FEATURES_HIGH_SHIFT      32
  53
  54 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  55         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  56         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  57         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  58         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  59         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  60         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  61         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  62         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  63         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  64         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  65         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  66         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  67         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  68         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  69         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  70         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  71         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  72         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  73         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  74         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  75         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  76         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  77         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  78         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  79         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  80         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
  81         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
  82         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
  83         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
  84         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
  85         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
  86         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
  87         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
  88         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
  89         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
  90         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
  91         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
  92         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
  93         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
  94         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
  95         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
  96         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
  97         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
  98         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
  99         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 100         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 101         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 102         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 103         MSG_MAP(RunGfxDcBtc,                         PPSMC_MSG_RunGfxDcBtc),
 104         MSG_MAP(RunSocDcBtc,                         PPSMC_MSG_RunSocDcBtc),
 105         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 106         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 107         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 108         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 109         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 110         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 111         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 112 };
 113
 114 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 115         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 116         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 117         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 118         CLK_MAP(FCLK, PPCLK_FCLK),
 119         CLK_MAP(UCLK, PPCLK_UCLK),
 120         CLK_MAP(MCLK, PPCLK_UCLK),
 121         CLK_MAP(DCLK, PPCLK_DCLK),
 122         CLK_MAP(VCLK, PPCLK_VCLK),
 123 };
 124
 125 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 126         FEA_MAP(DPM_PREFETCHER),
 127         FEA_MAP(DPM_GFXCLK),
 128         FEA_MAP(DPM_UCLK),
 129         FEA_MAP(DPM_SOCCLK),
 130         FEA_MAP(DPM_FCLK),
 131         FEA_MAP(DPM_MP0CLK),
 132         FEA_MAP(DS_GFXCLK),
 133         FEA_MAP(DS_SOCCLK),
 134         FEA_MAP(DS_LCLK),
 135         FEA_MAP(DS_FCLK),
 136         FEA_MAP(DS_UCLK),
 137         FEA_MAP(GFX_ULV),
 138         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 139         FEA_MAP(RSMU_SMN_CG),
 140         FEA_MAP(PPT),
 141         FEA_MAP(TDC),
 142         FEA_MAP(APCC_PLUS),
 143         FEA_MAP(VR0HOT),
 144         FEA_MAP(VR1HOT),
 145         FEA_MAP(FW_CTF),
 146         FEA_MAP(FAN_CONTROL),
 147         FEA_MAP(THERMAL),
 148         FEA_MAP(OUT_OF_BAND_MONITOR),
 149         FEA_MAP(TEMP_DEPENDENT_VMIN),
 150 };
 151
 152 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 153         TAB_MAP(PPTABLE),
 154         TAB_MAP(AVFS),
 155         TAB_MAP(AVFS_PSM_DEBUG),
 156         TAB_MAP(AVFS_FUSE_OVERRIDE),
 157         TAB_MAP(PMSTATUSLOG),
 158         TAB_MAP(SMU_METRICS),
 159         TAB_MAP(DRIVER_SMU_CONFIG),
 160         TAB_MAP(OVERDRIVE),
 161 };
 162
 163 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 164         PWR_MAP(AC),
 165         PWR_MAP(DC),
 166 };
 167
 168 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 169         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 170         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 171         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 172         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 173         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 174 };
 175
 176 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 177 {
 178         struct smu_11_0_cmn2aisc_mapping mapping;
 179
 180         if (index >= SMU_MSG_MAX_COUNT)
 181                 return -EINVAL;
 182
 183         mapping = arcturus_message_map[index];
 184         if (!(mapping.valid_mapping))
 185                 return -EINVAL;
 186
 187         return mapping.map_to;
 188 }
 189
 190 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 191 {
 192         struct smu_11_0_cmn2aisc_mapping mapping;
 193
 194         if (index >= SMU_CLK_COUNT)
 195                 return -EINVAL;
 196
 197         mapping = arcturus_clk_map[index];
 198         if (!(mapping.valid_mapping)) {
 199                 pr_warn("Unsupported SMU clk: %d\n", index);
 200                 return -EINVAL;
 201         }
 202
 203         return mapping.map_to;
 204 }
 205
 206 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 207 {
 208         struct smu_11_0_cmn2aisc_mapping mapping;
 209
 210         if (index >= SMU_FEATURE_COUNT)
 211                 return -EINVAL;
 212
 213         mapping = arcturus_feature_mask_map[index];
 214         if (!(mapping.valid_mapping)) {
 215                 pr_warn("Unsupported SMU feature: %d\n", index);
 216                 return -EINVAL;
 217         }
 218
 219         return mapping.map_to;
 220 }
 221
 222 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 223 {
 224         struct smu_11_0_cmn2aisc_mapping mapping;
 225
 226         if (index >= SMU_TABLE_COUNT)
 227                 return -EINVAL;
 228
 229         mapping = arcturus_table_map[index];
 230         if (!(mapping.valid_mapping)) {
 231                 pr_warn("Unsupported SMU table: %d\n", index);
 232                 return -EINVAL;
 233         }
 234
 235         return mapping.map_to;
 236 }
 237
 238 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 239 {
 240         struct smu_11_0_cmn2aisc_mapping mapping;
 241
 242         if (index >= SMU_POWER_SOURCE_COUNT)
 243                 return -EINVAL;
 244
 245         mapping = arcturus_pwr_src_map[index];
 246         if (!(mapping.valid_mapping)) {
 247                 pr_warn("Unsupported SMU power source: %d\n", index);
 248                 return -EINVAL;
 249         }
 250
 251         return mapping.map_to;
 252 }
 253
 254
 255 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 256 {
 257         struct smu_11_0_cmn2aisc_mapping mapping;
 258
 259         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 260                 return -EINVAL;
 261
 262         mapping = arcturus_workload_map[profile];
 263         if (!(mapping.valid_mapping)) {
 264                 pr_warn("Unsupported SMU power source: %d\n", profile);
 265                 return -EINVAL;
 266         }
 267
 268         return mapping.map_to;
 269 }
 270
 271 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 272 {
 273         struct smu_table_context *smu_table = &smu->smu_table;
 274
 275         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 276                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 277
 278         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 279                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 280
 281         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 282                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 283
 284         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 285         if (!smu_table->metrics_table)
 286                 return -ENOMEM;
 287         smu_table->metrics_time = 0;
 288
 289         return 0;
 290 }
 291
 292 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 293 {
 294         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 295
 296         if (smu_dpm->dpm_context)
 297                 return -EINVAL;
 298
 299         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 300                                        GFP_KERNEL);
 301         if (!smu_dpm->dpm_context)
 302                 return -ENOMEM;
 303
 304         if (smu_dpm->golden_dpm_context)
 305                 return -EINVAL;
 306
 307         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 308                                               GFP_KERNEL);
 309         if (!smu_dpm->golden_dpm_context)
 310                 return -ENOMEM;
 311
 312         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 313
 314         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 315                                        GFP_KERNEL);
 316         if (!smu_dpm->dpm_current_power_state)
 317                 return -ENOMEM;
 318
 319         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 320                                        GFP_KERNEL);
 321         if (!smu_dpm->dpm_request_power_state)
 322                 return -ENOMEM;
 323
 324         return 0;
 325 }
 326
 327 #define FEATURE_MASK(feature) (1ULL << feature)
 328 static int
 329 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 330                                   uint32_t *feature_mask, uint32_t num)
 331 {
 332         if (num > 2)
 333                 return -EINVAL;
 334
 335         memset(feature_mask, 0, sizeof(uint32_t) * num);
 336
 337         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
 338
 339         return 0;
 340 }
 341
 342 static int
 343 arcturus_set_single_dpm_table(struct smu_context *smu,
 344                             struct arcturus_single_dpm_table *single_dpm_table,
 345                             PPCLK_e clk_id)
 346 {
 347         int ret = 0;
 348         uint32_t i, num_of_levels = 0, clk;
 349
 350         ret = smu_send_smc_msg_with_param(smu,
 351                         SMU_MSG_GetDpmFreqByIndex,
 352                         (clk_id << 16 | 0xFF));
 353         if (ret) {
 354                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 355                 return ret;
 356         }
 357
 358         smu_read_smc_arg(smu, &num_of_levels);
 359         if (!num_of_levels) {
 360                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 361                 return -EINVAL;
 362         }
 363
 364         single_dpm_table->count = num_of_levels;
 365         for (i = 0; i < num_of_levels; i++) {
 366                 ret = smu_send_smc_msg_with_param(smu,
 367                                 SMU_MSG_GetDpmFreqByIndex,
 368                                 (clk_id << 16 | i));
 369                 if (ret) {
 370                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 371                         return ret;
 372                 }
 373                 smu_read_smc_arg(smu, &clk);
 374                 if (!clk) {
 375                         pr_err("[%s] clk value is invalid!\n", __func__);
 376                         return -EINVAL;
 377                 }
 378                 single_dpm_table->dpm_levels[i].value = clk;
 379                 single_dpm_table->dpm_levels[i].enabled = true;
 380         }
 381         return 0;
 382 }
 383
 384 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 385 {
 386         dpm_state->soft_min_level = 0x0;
 387         dpm_state->soft_max_level = 0xffff;
 388         dpm_state->hard_min_level = 0x0;
 389         dpm_state->hard_max_level = 0xffff;
 390 }
 391
 392 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 393 {
 394         int ret;
 395
 396         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 397         struct arcturus_dpm_table *dpm_table = NULL;
 398         struct arcturus_single_dpm_table *single_dpm_table;
 399
 400         dpm_table = smu_dpm->dpm_context;
 401
 402         /* socclk */
 403         single_dpm_table = &(dpm_table->soc_table);
 404         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 405                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 406                                                   PPCLK_SOCCLK);
 407                 if (ret) {
 408                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 409                         return ret;
 410                 }
 411         } else {
 412                 single_dpm_table->count = 1;
 413                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 414         }
 415         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 416
 417         /* gfxclk */
 418         single_dpm_table = &(dpm_table->gfx_table);
 419         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 420                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 421                                                   PPCLK_GFXCLK);
 422                 if (ret) {
 423                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 424                         return ret;
 425                 }
 426         } else {
 427                 single_dpm_table->count = 1;
 428                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 429         }
 430         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 431
 432         /* memclk */
 433         single_dpm_table = &(dpm_table->mem_table);
 434         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 435                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 436                                                   PPCLK_UCLK);
 437                 if (ret) {
 438                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 439                         return ret;
 440                 }
 441         } else {
 442                 single_dpm_table->count = 1;
 443                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 444         }
 445         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 446
 447         /* fclk */
 448         single_dpm_table = &(dpm_table->fclk_table);
 449         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 450                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 451                                                   PPCLK_FCLK);
 452                 if (ret) {
 453                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 454                         return ret;
 455                 }
 456         } else {
 457                 single_dpm_table->count = 0;
 458         }
 459         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 460
 461         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 462                sizeof(struct arcturus_dpm_table));
 463
 464         return 0;
 465 }
 466
 467 static int arcturus_check_powerplay_table(struct smu_context *smu)
 468 {
 469         return 0;
 470 }
 471
 472 static int arcturus_store_powerplay_table(struct smu_context *smu)
 473 {
 474         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 475         struct smu_table_context *table_context = &smu->smu_table;
 476         int ret = 0;
 477
 478         if (!table_context->power_play_table)
 479                 return -EINVAL;
 480
 481         powerplay_table = table_context->power_play_table;
 482
 483         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 484                sizeof(PPTable_t));
 485
 486         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 487
 488         return ret;
 489 }
 490
 491 static int arcturus_append_powerplay_table(struct smu_context *smu)
 492 {
 493         struct smu_table_context *table_context = &smu->smu_table;
 494         PPTable_t *smc_pptable = table_context->driver_pptable;
 495         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 496         int index, ret;
 497
 498         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 499                                            smc_dpm_info);
 500
 501         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 502                                       (uint8_t **)&smc_dpm_table);
 503         if (ret)
 504                 return ret;
 505
 506         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 507                         smc_dpm_table->table_header.format_revision,
 508                         smc_dpm_table->table_header.content_revision);
 509
 510         if ((smc_dpm_table->table_header.format_revision == 4) &&
 511             (smc_dpm_table->table_header.content_revision == 6))
 512                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 513                        &smc_dpm_table->maxvoltagestepgfx,
 514                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 515
 516         return 0;
 517 }
 518
 519 static int arcturus_run_btc_afll(struct smu_context *smu)
 520 {
 521         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 522 }
 523
 524 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 525 {
 526         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 527         struct arcturus_dpm_table *dpm_table = NULL;
 528         struct arcturus_single_dpm_table *gfx_table = NULL;
 529         struct arcturus_single_dpm_table *mem_table = NULL;
 530
 531         dpm_table = smu_dpm->dpm_context;
 532         gfx_table = &(dpm_table->gfx_table);
 533         mem_table = &(dpm_table->mem_table);
 534
 535         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 536         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 537
 538         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 539             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 540                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 541                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 542         }
 543
 544         smu->pstate_sclk = smu->pstate_sclk * 100;
 545         smu->pstate_mclk = smu->pstate_mclk * 100;
 546
 547         return 0;
 548 }
 549
 550 static int arcturus_get_clk_table(struct smu_context *smu,
 551                         struct pp_clock_levels_with_latency *clocks,
 552                         struct arcturus_single_dpm_table *dpm_table)
 553 {
 554         int i, count;
 555
 556         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 557         clocks->num_levels = count;
 558
 559         for (i = 0; i < count; i++) {
 560                 clocks->data[i].clocks_in_khz =
 561                         dpm_table->dpm_levels[i].value * 1000;
 562                 clocks->data[i].latency_in_us = 0;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int arcturus_print_clk_levels(struct smu_context *smu,
 569                         enum smu_clk_type type, char *buf)
 570 {
 571         int i, now, size = 0;
 572         int ret = 0;
 573         struct pp_clock_levels_with_latency clocks;
 574         struct arcturus_single_dpm_table *single_dpm_table;
 575         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 576         struct arcturus_dpm_table *dpm_table = NULL;
 577
 578         dpm_table = smu_dpm->dpm_context;
 579
 580         switch (type) {
 581         case SMU_SCLK:
 582                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 583                 if (ret) {
 584                         pr_err("Attempt to get current gfx clk Failed!");
 585                         return ret;
 586                 }
 587
 588                 single_dpm_table = &(dpm_table->gfx_table);
 589                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 590                 if (ret) {
 591                         pr_err("Attempt to get gfx clk levels Failed!");
 592                         return ret;
 593                 }
 594
 595                 for (i = 0; i < clocks.num_levels; i++)
 596                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 597                                         clocks.data[i].clocks_in_khz / 1000,
 598                                         (clocks.data[i].clocks_in_khz == now * 10)
 599                                         ? "*" : "");
 600                 break;
 601
 602         case SMU_MCLK:
 603                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 604                 if (ret) {
 605                         pr_err("Attempt to get current mclk Failed!");
 606                         return ret;
 607                 }
 608
 609                 single_dpm_table = &(dpm_table->mem_table);
 610                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 611                 if (ret) {
 612                         pr_err("Attempt to get memory clk levels Failed!");
 613                         return ret;
 614                 }
 615
 616                 for (i = 0; i < clocks.num_levels; i++)
 617                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 618                                 i, clocks.data[i].clocks_in_khz / 1000,
 619                                 (clocks.data[i].clocks_in_khz == now * 10)
 620                                 ? "*" : "");
 621                 break;
 622
 623         case SMU_SOCCLK:
 624                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 625                 if (ret) {
 626                         pr_err("Attempt to get current socclk Failed!");
 627                         return ret;
 628                 }
 629
 630                 single_dpm_table = &(dpm_table->soc_table);
 631                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 632                 if (ret) {
 633                         pr_err("Attempt to get socclk levels Failed!");
 634                         return ret;
 635                 }
 636
 637                 for (i = 0; i < clocks.num_levels; i++)
 638                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 639                                 i, clocks.data[i].clocks_in_khz / 1000,
 640                                 (clocks.data[i].clocks_in_khz == now * 10)
 641                                 ? "*" : "");
 642                 break;
 643
 644         case SMU_FCLK:
 645                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 646                 if (ret) {
 647                         pr_err("Attempt to get current fclk Failed!");
 648                         return ret;
 649                 }
 650
 651                 single_dpm_table = &(dpm_table->fclk_table);
 652                 for (i = 0; i < single_dpm_table->count; i++)
 653                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 654                                 i, single_dpm_table->dpm_levels[i].value,
 655                                 (single_dpm_table->dpm_levels[i].value == now / 100)
 656                                 ? "*" : "");
 657                 break;
 658
 659         default:
 660                 break;
 661         }
 662
 663         return size;
 664 }
 665
 666 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 667                                    uint32_t feature_mask)
 668 {
 669         struct arcturus_dpm_table *dpm_table;
 670         struct arcturus_single_dpm_table *single_dpm_table;
 671         uint32_t freq;
 672         int ret = 0;
 673
 674         dpm_table = smu->smu_dpm.dpm_context;
 675         if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
 676             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 677                 single_dpm_table = &(dpm_table->gfx_table);
 678                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 679                         single_dpm_table->dpm_state.soft_min_level;
 680                 ret = smu_send_smc_msg_with_param(smu,
 681                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 682                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 683                 if (ret) {
 684                         pr_err("Failed to set soft %s gfxclk !\n",
 685                                                 max ? "max" : "min");
 686                         return ret;
 687                 }
 688         }
 689
 690         return ret;
 691 }
 692
 693 static int arcturus_force_clk_levels(struct smu_context *smu,
 694                         enum smu_clk_type type, uint32_t mask)
 695 {
 696         struct arcturus_dpm_table *dpm_table;
 697         struct arcturus_single_dpm_table *single_dpm_table;
 698         uint32_t soft_min_level, soft_max_level;
 699         int ret = 0;
 700
 701         mutex_lock(&(smu->mutex));
 702
 703         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 704         soft_max_level = mask ? (fls(mask) - 1) : 0;
 705
 706         dpm_table = smu->smu_dpm.dpm_context;
 707
 708         switch (type) {
 709         case SMU_SCLK:
 710                 single_dpm_table = &(dpm_table->gfx_table);
 711
 712                 if (soft_max_level >= single_dpm_table->count) {
 713                         pr_err("Clock level specified %d is over max allowed %d\n",
 714                                         soft_max_level, single_dpm_table->count - 1);
 715                         ret = -EINVAL;
 716                         break;
 717                 }
 718
 719                 single_dpm_table->dpm_state.soft_min_level =
 720                         single_dpm_table->dpm_levels[soft_min_level].value;
 721                 single_dpm_table->dpm_state.soft_max_level =
 722                         single_dpm_table->dpm_levels[soft_max_level].value;
 723
 724                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 725                 if (ret) {
 726                         pr_err("Failed to upload boot level to lowest!\n");
 727                         break;
 728                 }
 729
 730                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 731                 if (ret)
 732                         pr_err("Failed to upload dpm max level to highest!\n");
 733
 734                 break;
 735
 736         case SMU_MCLK:
 737                 single_dpm_table = &(dpm_table->mem_table);
 738
 739                 if (soft_max_level >= single_dpm_table->count) {
 740                         pr_err("Clock level specified %d is over max allowed %d\n",
 741                                         soft_max_level, single_dpm_table->count - 1);
 742                         ret = -EINVAL;
 743                         break;
 744                 }
 745
 746                 single_dpm_table->dpm_state.soft_min_level =
 747                         single_dpm_table->dpm_levels[soft_min_level].value;
 748                 single_dpm_table->dpm_state.soft_max_level =
 749                         single_dpm_table->dpm_levels[soft_max_level].value;
 750
 751                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
 752                 if (ret) {
 753                         pr_err("Failed to upload boot level to lowest!\n");
 754                         break;
 755                 }
 756
 757                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
 758                 if (ret)
 759                         pr_err("Failed to upload dpm max level to highest!\n");
 760
 761                 break;
 762
 763         case SMU_SOCCLK:
 764                 single_dpm_table = &(dpm_table->soc_table);
 765
 766                 if (soft_max_level >= single_dpm_table->count) {
 767                         pr_err("Clock level specified %d is over max allowed %d\n",
 768                                         soft_max_level, single_dpm_table->count - 1);
 769                         ret = -EINVAL;
 770                         break;
 771                 }
 772
 773                 single_dpm_table->dpm_state.soft_min_level =
 774                         single_dpm_table->dpm_levels[soft_min_level].value;
 775                 single_dpm_table->dpm_state.soft_max_level =
 776                         single_dpm_table->dpm_levels[soft_max_level].value;
 777
 778                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
 779                 if (ret) {
 780                         pr_err("Failed to upload boot level to lowest!\n");
 781                         break;
 782                 }
 783
 784                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
 785                 if (ret)
 786                         pr_err("Failed to upload dpm max level to highest!\n");
 787
 788                 break;
 789
 790         case SMU_FCLK:
 791                 single_dpm_table = &(dpm_table->fclk_table);
 792
 793                 if (soft_max_level >= single_dpm_table->count) {
 794                         pr_err("Clock level specified %d is over max allowed %d\n",
 795                                         soft_max_level, single_dpm_table->count - 1);
 796                         ret = -EINVAL;
 797                         break;
 798                 }
 799
 800                 single_dpm_table->dpm_state.soft_min_level =
 801                         single_dpm_table->dpm_levels[soft_min_level].value;
 802                 single_dpm_table->dpm_state.soft_max_level =
 803                         single_dpm_table->dpm_levels[soft_max_level].value;
 804
 805                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
 806                 if (ret) {
 807                         pr_err("Failed to upload boot level to lowest!\n");
 808                         break;
 809                 }
 810
 811                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
 812                 if (ret)
 813                         pr_err("Failed to upload dpm max level to highest!\n");
 814
 815                 break;
 816
 817         default:
 818                 break;
 819         }
 820
 821         mutex_unlock(&(smu->mutex));
 822         return ret;
 823 }
 824
 825 static const struct smu_temperature_range arcturus_thermal_policy[] =
 826 {
 827         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
 828         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
 829 };
 830
 831 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 832                                                 struct smu_temperature_range *range)
 833 {
 834
 835         PPTable_t *pptable = smu->smu_table.driver_pptable;
 836
 837         if (!range)
 838                 return -EINVAL;
 839
 840         memcpy(range, &arcturus_thermal_policy[0], sizeof(struct smu_temperature_range));
 841
 842         range->max = pptable->TedgeLimit *
 843                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 844         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 845                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 846         range->hotspot_crit_max = pptable->ThotspotLimit *
 847                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 848         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 849                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 850         range->mem_crit_max = pptable->TmemLimit *
 851                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 852         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 853                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 854
 855
 856         return 0;
 857 }
 858
 859 static int arcturus_get_metrics_table(struct smu_context *smu,
 860                                       SmuMetrics_t *metrics_table)
 861 {
 862         struct smu_table_context *smu_table= &smu->smu_table;
 863         int ret = 0;
 864
 865         if (!smu_table->metrics_time ||
 866              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 867                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 868                                 (void *)smu_table->metrics_table, false);
 869                 if (ret) {
 870                         pr_info("Failed to export SMU metrics table!\n");
 871                         return ret;
 872                 }
 873                 smu_table->metrics_time = jiffies;
 874         }
 875
 876         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 877
 878         return ret;
 879 }
 880
 881 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 882                                                  enum amd_pp_sensors sensor,
 883                                                  uint32_t *value)
 884 {
 885         SmuMetrics_t metrics;
 886         int ret = 0;
 887
 888         if (!value)
 889                 return -EINVAL;
 890
 891         ret = arcturus_get_metrics_table(smu, &metrics);
 892         if (ret)
 893                 return ret;
 894
 895         switch (sensor) {
 896         case AMDGPU_PP_SENSOR_GPU_LOAD:
 897                 *value = metrics.AverageGfxActivity;
 898                 break;
 899         case AMDGPU_PP_SENSOR_MEM_LOAD:
 900                 *value = metrics.AverageUclkActivity;
 901                 break;
 902         default:
 903                 pr_err("Invalid sensor for retrieving clock activity\n");
 904                 return -EINVAL;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 911 {
 912         SmuMetrics_t metrics;
 913         int ret = 0;
 914
 915         if (!value)
 916                 return -EINVAL;
 917
 918         ret = arcturus_get_metrics_table(smu, &metrics);
 919         if (ret)
 920                 return ret;
 921
 922         *value = metrics.AverageSocketPower << 8;
 923
 924         return 0;
 925 }
 926
 927 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 928                                             enum amd_pp_sensors sensor,
 929                                             uint32_t *value)
 930 {
 931         SmuMetrics_t metrics;
 932         int ret = 0;
 933
 934         if (!value)
 935                 return -EINVAL;
 936
 937         ret = arcturus_get_metrics_table(smu, &metrics);
 938         if (ret)
 939                 return ret;
 940
 941         switch (sensor) {
 942         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 943                 *value = metrics.TemperatureHotspot *
 944                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 945                 break;
 946         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 947                 *value = metrics.TemperatureEdge *
 948                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 949                 break;
 950         case AMDGPU_PP_SENSOR_MEM_TEMP:
 951                 *value = metrics.TemperatureHBM *
 952                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 953                 break;
 954         default:
 955                 pr_err("Invalid sensor for retrieving temp\n");
 956                 return -EINVAL;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int arcturus_read_sensor(struct smu_context *smu,
 963                                 enum amd_pp_sensors sensor,
 964                                 void *data, uint32_t *size)
 965 {
 966         struct smu_table_context *table_context = &smu->smu_table;
 967         PPTable_t *pptable = table_context->driver_pptable;
 968         int ret = 0;
 969
 970         switch (sensor) {
 971         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 972                 *(uint32_t *)data = pptable->FanMaximumRpm;
 973                 *size = 4;
 974                 break;
 975         case AMDGPU_PP_SENSOR_MEM_LOAD:
 976         case AMDGPU_PP_SENSOR_GPU_LOAD:
 977                 ret = arcturus_get_current_activity_percent(smu,
 978                                                             sensor,
 979                                                 (uint32_t *)data);
 980                 *size = 4;
 981                 break;
 982         case AMDGPU_PP_SENSOR_GPU_POWER:
 983                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
 984                 *size = 4;
 985                 break;
 986         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 987         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 988         case AMDGPU_PP_SENSOR_MEM_TEMP:
 989                 ret = arcturus_thermal_get_temperature(smu, sensor,
 990                                                 (uint32_t *)data);
 991                 *size = 4;
 992                 break;
 993         default:
 994                 return -EINVAL;
 995         }
 996
 997         return ret;
 998 }
 999
1000 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1001                                       uint32_t *speed)
1002 {
1003         SmuMetrics_t metrics;
1004         int ret = 0;
1005
1006         if (!speed)
1007                 return -EINVAL;
1008
1009         ret = arcturus_get_metrics_table(smu, &metrics);
1010         if (ret)
1011                 return ret;
1012
1013         *speed = metrics.CurrFanSpeed;
1014
1015         return ret;
1016 }
1017
1018 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1019                                           uint32_t *speed)
1020 {
1021         PPTable_t *pptable = smu->smu_table.driver_pptable;
1022         uint32_t percent, current_rpm;
1023         int ret = 0;
1024
1025         if (!speed)
1026                 return -EINVAL;
1027
1028         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1029         if (ret)
1030                 return ret;
1031
1032         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1033         *speed = percent > 100 ? 100 : percent;
1034
1035         return ret;
1036 }
1037
1038 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1039                                        enum smu_clk_type clk_type,
1040                                        uint32_t *value)
1041 {
1042         static SmuMetrics_t metrics;
1043         int ret = 0, clk_id = 0;
1044
1045         if (!value)
1046                 return -EINVAL;
1047
1048         clk_id = smu_clk_get_index(smu, clk_type);
1049         if (clk_id < 0)
1050                 return -EINVAL;
1051
1052         ret = arcturus_get_metrics_table(smu, &metrics);
1053         if (ret)
1054                 return ret;
1055
1056         switch (clk_id) {
1057         case PPCLK_GFXCLK:
1058                 /*
1059                  * CurrClock[clk_id] can provide accurate
1060                  *   output only when the dpm feature is enabled.
1061                  * We can use Average_* for dpm disabled case.
1062                  *   But this is available for gfxclk/uclk/socclk.
1063                  */
1064                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1065                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1066                 else
1067                         *value = metrics.AverageGfxclkFrequency;
1068                 break;
1069         case PPCLK_UCLK:
1070                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1071                         *value = metrics.CurrClock[PPCLK_UCLK];
1072                 else
1073                         *value = metrics.AverageUclkFrequency;
1074                 break;
1075         case PPCLK_SOCCLK:
1076                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1077                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1078                 else
1079                         *value = metrics.AverageSocclkFrequency;
1080                 break;
1081         default:
1082                 *value = metrics.CurrClock[clk_id];
1083                 break;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static void arcturus_dump_pptable(struct smu_context *smu)
1090 {
1091         struct smu_table_context *table_context = &smu->smu_table;
1092         PPTable_t *pptable = table_context->driver_pptable;
1093         int i;
1094
1095         pr_info("Dumped PPTable:\n");
1096
1097         pr_info("Version = 0x%08x\n", pptable->Version);
1098
1099         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1100         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1101
1102         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1103                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1104                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1105         }
1106
1107         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1108         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1109         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1110         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1111
1112         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1113         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1114         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1115         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1116         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1117         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1118         pr_info("FitLimit = %d\n", pptable->FitLimit);
1119
1120         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1121         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1122
1123         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1124
1125         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1126         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1127
1128         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1129         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1130         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1131         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1132
1133         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1134         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1135         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1136         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1137
1138         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1139         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1140
1141         pr_info("[PPCLK_GFXCLK]\n"
1142                         "  .VoltageMode          = 0x%02x\n"
1143                         "  .SnapToDiscrete       = 0x%02x\n"
1144                         "  .NumDiscreteLevels    = 0x%02x\n"
1145                         "  .padding              = 0x%02x\n"
1146                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1147                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1148                         "  .SsFmin               = 0x%04x\n"
1149                         "  .Padding_16           = 0x%04x\n",
1150                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1151                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1152                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1153                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1154                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1155                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1156                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1157                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1158                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1159                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1160                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1161
1162         pr_info("[PPCLK_VCLK]\n"
1163                         "  .VoltageMode          = 0x%02x\n"
1164                         "  .SnapToDiscrete       = 0x%02x\n"
1165                         "  .NumDiscreteLevels    = 0x%02x\n"
1166                         "  .padding              = 0x%02x\n"
1167                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1168                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1169                         "  .SsFmin               = 0x%04x\n"
1170                         "  .Padding_16           = 0x%04x\n",
1171                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1172                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1173                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1174                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1175                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1176                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1177                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1178                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1179                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1180                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1181                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1182
1183         pr_info("[PPCLK_DCLK]\n"
1184                         "  .VoltageMode          = 0x%02x\n"
1185                         "  .SnapToDiscrete       = 0x%02x\n"
1186                         "  .NumDiscreteLevels    = 0x%02x\n"
1187                         "  .padding              = 0x%02x\n"
1188                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1189                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1190                         "  .SsFmin               = 0x%04x\n"
1191                         "  .Padding_16           = 0x%04x\n",
1192                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1193                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1194                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1195                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1196                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1197                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1198                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1199                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1200                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1201                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1202                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1203
1204         pr_info("[PPCLK_SOCCLK]\n"
1205                         "  .VoltageMode          = 0x%02x\n"
1206                         "  .SnapToDiscrete       = 0x%02x\n"
1207                         "  .NumDiscreteLevels    = 0x%02x\n"
1208                         "  .padding              = 0x%02x\n"
1209                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1210                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1211                         "  .SsFmin               = 0x%04x\n"
1212                         "  .Padding_16           = 0x%04x\n",
1213                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1214                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1215                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1216                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1217                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1218                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1219                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1220                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1221                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1222                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1223                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1224
1225         pr_info("[PPCLK_UCLK]\n"
1226                         "  .VoltageMode          = 0x%02x\n"
1227                         "  .SnapToDiscrete       = 0x%02x\n"
1228                         "  .NumDiscreteLevels    = 0x%02x\n"
1229                         "  .padding              = 0x%02x\n"
1230                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1231                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1232                         "  .SsFmin               = 0x%04x\n"
1233                         "  .Padding_16           = 0x%04x\n",
1234                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1235                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1236                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1237                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1238                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1239                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1240                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1241                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1242                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1243                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1244                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1245
1246         pr_info("[PPCLK_FCLK]\n"
1247                         "  .VoltageMode          = 0x%02x\n"
1248                         "  .SnapToDiscrete       = 0x%02x\n"
1249                         "  .NumDiscreteLevels    = 0x%02x\n"
1250                         "  .padding              = 0x%02x\n"
1251                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1252                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1253                         "  .SsFmin               = 0x%04x\n"
1254                         "  .Padding_16           = 0x%04x\n",
1255                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1256                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1257                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1258                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1259                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1260                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1261                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1262                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1263                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1264                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1265                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1266
1267
1268         pr_info("FreqTableGfx\n");
1269         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1270                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1271
1272         pr_info("FreqTableVclk\n");
1273         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1274                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1275
1276         pr_info("FreqTableDclk\n");
1277         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1278                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1279
1280         pr_info("FreqTableSocclk\n");
1281         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1282                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1283
1284         pr_info("FreqTableUclk\n");
1285         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1286                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1287
1288         pr_info("FreqTableFclk\n");
1289         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1290                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1291
1292         pr_info("Mp0clkFreq\n");
1293         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1294                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1295
1296         pr_info("Mp0DpmVoltage\n");
1297         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1298                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1299
1300         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1301         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1302         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1303         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1304         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1305         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1306         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1307         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1308         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1309
1310         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1311         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1312         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1313         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1314
1315         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1316         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1317
1318         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1319         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1320         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1321         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1322         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1323         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1324
1325         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1326         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1327         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1328         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1329         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1330         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1331         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1332         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1333         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1334
1335         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1336         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1337         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1338         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1339
1340         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1341         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1342         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1343         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1344
1345         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1346                         pptable->dBtcGbGfxPll.a,
1347                         pptable->dBtcGbGfxPll.b,
1348                         pptable->dBtcGbGfxPll.c);
1349         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1350                         pptable->dBtcGbGfxAfll.a,
1351                         pptable->dBtcGbGfxAfll.b,
1352                         pptable->dBtcGbGfxAfll.c);
1353         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1354                         pptable->dBtcGbSoc.a,
1355                         pptable->dBtcGbSoc.b,
1356                         pptable->dBtcGbSoc.c);
1357
1358         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1359                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1360                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1361         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1362                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1363                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1364
1365         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1366                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1367                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1368                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1369         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1370                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1371                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1372                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1373
1374         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1375         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1376
1377         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1378         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1379         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1380         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1381
1382         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1383         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1384         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1385         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1386
1387         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1388         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1389
1390         pr_info("XgmiDpmPstates\n");
1391         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1392                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1393         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1394         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1395
1396         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1397         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1398         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1399         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1400         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1401         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1402         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1403         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1404
1405         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1406         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1407                         pptable->ReservedEquation0.a,
1408                         pptable->ReservedEquation0.b,
1409                         pptable->ReservedEquation0.c);
1410         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1411                         pptable->ReservedEquation1.a,
1412                         pptable->ReservedEquation1.b,
1413                         pptable->ReservedEquation1.c);
1414         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1415                         pptable->ReservedEquation2.a,
1416                         pptable->ReservedEquation2.b,
1417                         pptable->ReservedEquation2.c);
1418         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1419                         pptable->ReservedEquation3.a,
1420                         pptable->ReservedEquation3.b,
1421                         pptable->ReservedEquation3.c);
1422
1423         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1424         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1425
1426         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1427         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1428         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1429
1430         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1431         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1432
1433         pr_info("Board Parameters:\n");
1434         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1435         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1436
1437         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1438         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1439         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1440         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1441
1442         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1443         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1444
1445         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1446         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1447         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1448
1449         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1450         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1451         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1452
1453         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1454         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1455         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1456
1457         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1458         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1459         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1460
1461         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1462         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1463         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1464         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1465
1466         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1467         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1468         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1469
1470         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1471         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1472         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1473
1474         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1475         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1476         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1477
1478         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1479         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1480         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1481
1482         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1483                 pr_info("I2cControllers[%d]:\n", i);
1484                 pr_info("                   .Enabled = %d\n",
1485                                 pptable->I2cControllers[i].Enabled);
1486                 pr_info("                   .SlaveAddress = 0x%x\n",
1487                                 pptable->I2cControllers[i].SlaveAddress);
1488                 pr_info("                   .ControllerPort = %d\n",
1489                                 pptable->I2cControllers[i].ControllerPort);
1490                 pr_info("                   .ControllerName = %d\n",
1491                                 pptable->I2cControllers[i].ControllerName);
1492                 pr_info("                   .ThermalThrottler = %d\n",
1493                                 pptable->I2cControllers[i].ThermalThrotter);
1494                 pr_info("                   .I2cProtocol = %d\n",
1495                                 pptable->I2cControllers[i].I2cProtocol);
1496                 pr_info("                   .Speed = %d\n",
1497                                 pptable->I2cControllers[i].Speed);
1498         }
1499
1500         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1501         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1502
1503         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1504
1505         pr_info("XgmiLinkSpeed\n");
1506         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1507                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1508         pr_info("XgmiLinkWidth\n");
1509         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1510                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1511         pr_info("XgmiFclkFreq\n");
1512         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1513                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1514         pr_info("XgmiSocVoltage\n");
1515         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1516                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1517
1518 }
1519
1520 static const struct pptable_funcs arcturus_ppt_funcs = {
1521         /* translate smu index into arcturus specific index */
1522         .get_smu_msg_index = arcturus_get_smu_msg_index,
1523         .get_smu_clk_index = arcturus_get_smu_clk_index,
1524         .get_smu_feature_index = arcturus_get_smu_feature_index,
1525         .get_smu_table_index = arcturus_get_smu_table_index,
1526         .get_smu_power_index= arcturus_get_pwr_src_index,
1527         .get_workload_type = arcturus_get_workload_type,
1528         /* internal structurs allocations */
1529         .tables_init = arcturus_tables_init,
1530         .alloc_dpm_context = arcturus_allocate_dpm_context,
1531         /* pptable related */
1532         .check_powerplay_table = arcturus_check_powerplay_table,
1533         .store_powerplay_table = arcturus_store_powerplay_table,
1534         .append_powerplay_table = arcturus_append_powerplay_table,
1535         /* init dpm */
1536         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1537         /* btc */
1538         .run_afll_btc = arcturus_run_btc_afll,
1539         /* dpm/clk tables */
1540         .set_default_dpm_table = arcturus_set_default_dpm_table,
1541         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1542         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1543         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1544         .print_clk_levels = arcturus_print_clk_levels,
1545         .force_clk_levels = arcturus_force_clk_levels,
1546         .read_sensor = arcturus_read_sensor,
1547         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1548         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1549         /* debug (internal used) */
1550         .dump_pptable = arcturus_dump_pptable,
1551 };
1552
1553 void arcturus_set_ppt_funcs(struct smu_context *smu)
1554 {
1555         struct smu_table_context *smu_table = &smu->smu_table;
1556
1557         smu->ppt_funcs = &arcturus_ppt_funcs;
1558         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1559         smu_table->table_count = TABLE_COUNT;
1560 }