2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if_arcturus.h"
32 #include "soc15_common.h"
34 #include "power_state.h"
35 #include "arcturus_ppt.h"
36 #include "smu_v11_0_pptable.h"
37 #include "arcturus_ppsmc.h"
38 #include "nbio/nbio_7_4_sh_mask.h"
40 #define CTF_OFFSET_EDGE 5
41 #define CTF_OFFSET_HOTSPOT 5
42 #define CTF_OFFSET_HBM 5
44 #define MSG_MAP(msg, index) \
45 [SMU_MSG_##msg] = {1, (index)}
47 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
48 #define SMU_FEATURES_LOW_SHIFT 0
49 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
50 #define SMU_FEATURES_HIGH_SHIFT 32
52 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
53 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
54 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
55 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
56 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
57 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
58 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
59 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
60 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
61 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
62 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
63 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
64 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
65 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
68 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
69 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
72 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
73 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
74 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
75 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
76 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
77 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
78 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
79 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
80 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
81 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
82 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
83 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
84 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
85 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
86 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
87 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType),
88 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm),
89 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
91 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
92 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0),
93 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0),
94 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1),
95 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1),
96 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
97 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
98 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
99 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
100 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc),
101 MSG_MAP(RunGfxDcBtc, PPSMC_MSG_RunGfxDcBtc),
102 MSG_MAP(RunSocDcBtc, PPSMC_MSG_RunSocDcBtc),
103 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
104 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
105 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
106 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
107 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
108 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
109 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
112 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
113 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
114 CLK_MAP(SCLK, PPCLK_GFXCLK),
115 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
116 CLK_MAP(FCLK, PPCLK_FCLK),
117 CLK_MAP(UCLK, PPCLK_UCLK),
118 CLK_MAP(MCLK, PPCLK_UCLK),
119 CLK_MAP(DCLK, PPCLK_DCLK),
120 CLK_MAP(VCLK, PPCLK_VCLK),
123 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
124 FEA_MAP(DPM_PREFETCHER),
134 FEA_MAP(RSMU_SMN_CG),
141 FEA_MAP(FAN_CONTROL),
143 FEA_MAP(OUT_OF_BAND_MONITOR),
144 FEA_MAP(TEMP_DEPENDENT_VMIN),
147 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
150 TAB_MAP(AVFS_PSM_DEBUG),
151 TAB_MAP(AVFS_FUSE_OVERRIDE),
152 TAB_MAP(PMSTATUSLOG),
153 TAB_MAP(SMU_METRICS),
154 TAB_MAP(DRIVER_SMU_CONFIG),
158 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
163 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
164 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
165 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
166 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
167 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
168 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
171 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
173 struct smu_11_0_cmn2aisc_mapping mapping;
175 if (index >= SMU_MSG_MAX_COUNT)
178 mapping = arcturus_message_map[index];
179 if (!(mapping.valid_mapping)) {
180 pr_warn("Unsupported SMU message: %d\n", index);
184 return mapping.map_to;
187 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
189 struct smu_11_0_cmn2aisc_mapping mapping;
191 if (index >= SMU_CLK_COUNT)
194 mapping = arcturus_clk_map[index];
195 if (!(mapping.valid_mapping)) {
196 pr_warn("Unsupported SMU clk: %d\n", index);
200 return mapping.map_to;
203 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
205 struct smu_11_0_cmn2aisc_mapping mapping;
207 if (index >= SMU_FEATURE_COUNT)
210 mapping = arcturus_feature_mask_map[index];
211 if (!(mapping.valid_mapping)) {
212 pr_warn("Unsupported SMU feature: %d\n", index);
216 return mapping.map_to;
219 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
221 struct smu_11_0_cmn2aisc_mapping mapping;
223 if (index >= SMU_TABLE_COUNT)
226 mapping = arcturus_table_map[index];
227 if (!(mapping.valid_mapping)) {
228 pr_warn("Unsupported SMU table: %d\n", index);
232 return mapping.map_to;
235 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
237 struct smu_11_0_cmn2aisc_mapping mapping;
239 if (index >= SMU_POWER_SOURCE_COUNT)
242 mapping = arcturus_pwr_src_map[index];
243 if (!(mapping.valid_mapping)) {
244 pr_warn("Unsupported SMU power source: %d\n", index);
248 return mapping.map_to;
252 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
254 struct smu_11_0_cmn2aisc_mapping mapping;
256 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
259 mapping = arcturus_workload_map[profile];
260 if (!(mapping.valid_mapping)) {
261 pr_warn("Unsupported SMU power source: %d\n", profile);
265 return mapping.map_to;
268 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
270 struct smu_table_context *smu_table = &smu->smu_table;
272 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
273 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
275 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
276 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
278 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
279 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
281 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
282 if (!smu_table->metrics_table)
284 smu_table->metrics_time = 0;
289 static int arcturus_allocate_dpm_context(struct smu_context *smu)
291 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
293 if (smu_dpm->dpm_context)
296 smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
298 if (!smu_dpm->dpm_context)
301 if (smu_dpm->golden_dpm_context)
304 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
306 if (!smu_dpm->golden_dpm_context)
309 smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
311 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
313 if (!smu_dpm->dpm_current_power_state)
316 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
318 if (!smu_dpm->dpm_request_power_state)
324 #define FEATURE_MASK(feature) (1ULL << feature)
326 arcturus_get_allowed_feature_mask(struct smu_context *smu,
327 uint32_t *feature_mask, uint32_t num)
332 memset(feature_mask, 0, sizeof(uint32_t) * num);
334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
340 arcturus_set_single_dpm_table(struct smu_context *smu,
341 struct arcturus_single_dpm_table *single_dpm_table,
345 uint32_t i, num_of_levels = 0, clk;
347 ret = smu_send_smc_msg_with_param(smu,
348 SMU_MSG_GetDpmFreqByIndex,
349 (clk_id << 16 | 0xFF));
351 pr_err("[%s] failed to get dpm levels!\n", __func__);
355 smu_read_smc_arg(smu, &num_of_levels);
356 if (!num_of_levels) {
357 pr_err("[%s] number of clk levels is invalid!\n", __func__);
361 single_dpm_table->count = num_of_levels;
362 for (i = 0; i < num_of_levels; i++) {
363 ret = smu_send_smc_msg_with_param(smu,
364 SMU_MSG_GetDpmFreqByIndex,
367 pr_err("[%s] failed to get dpm freq by index!\n", __func__);
370 smu_read_smc_arg(smu, &clk);
372 pr_err("[%s] clk value is invalid!\n", __func__);
375 single_dpm_table->dpm_levels[i].value = clk;
376 single_dpm_table->dpm_levels[i].enabled = true;
381 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
383 dpm_state->soft_min_level = 0x0;
384 dpm_state->soft_max_level = 0xffff;
385 dpm_state->hard_min_level = 0x0;
386 dpm_state->hard_max_level = 0xffff;
389 static int arcturus_set_default_dpm_table(struct smu_context *smu)
393 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
394 struct arcturus_dpm_table *dpm_table = NULL;
395 struct arcturus_single_dpm_table *single_dpm_table;
397 dpm_table = smu_dpm->dpm_context;
400 single_dpm_table = &(dpm_table->soc_table);
401 if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
402 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
405 pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
409 single_dpm_table->count = 1;
410 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
412 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
415 single_dpm_table = &(dpm_table->gfx_table);
416 if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
417 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
420 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
424 single_dpm_table->count = 1;
425 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
427 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
430 single_dpm_table = &(dpm_table->mem_table);
431 if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
432 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
435 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
439 single_dpm_table->count = 1;
440 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
442 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
445 single_dpm_table = &(dpm_table->fclk_table);
446 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
447 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
450 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
454 single_dpm_table->count = 0;
456 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
458 memcpy(smu_dpm->golden_dpm_context, dpm_table,
459 sizeof(struct arcturus_dpm_table));
464 static int arcturus_check_powerplay_table(struct smu_context *smu)
469 static int arcturus_store_powerplay_table(struct smu_context *smu)
471 struct smu_11_0_powerplay_table *powerplay_table = NULL;
472 struct smu_table_context *table_context = &smu->smu_table;
475 if (!table_context->power_play_table)
478 powerplay_table = table_context->power_play_table;
480 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
483 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
488 static int arcturus_append_powerplay_table(struct smu_context *smu)
490 struct smu_table_context *table_context = &smu->smu_table;
491 PPTable_t *smc_pptable = table_context->driver_pptable;
492 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
495 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
498 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
499 (uint8_t **)&smc_dpm_table);
503 pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
504 smc_dpm_table->table_header.format_revision,
505 smc_dpm_table->table_header.content_revision);
507 if ((smc_dpm_table->table_header.format_revision == 4) &&
508 (smc_dpm_table->table_header.content_revision == 6))
509 memcpy(&smc_pptable->MaxVoltageStepGfx,
510 &smc_dpm_table->maxvoltagestepgfx,
511 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
516 static int arcturus_run_btc_afll(struct smu_context *smu)
518 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
521 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
523 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
524 struct arcturus_dpm_table *dpm_table = NULL;
525 struct arcturus_single_dpm_table *gfx_table = NULL;
526 struct arcturus_single_dpm_table *mem_table = NULL;
528 dpm_table = smu_dpm->dpm_context;
529 gfx_table = &(dpm_table->gfx_table);
530 mem_table = &(dpm_table->mem_table);
532 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
533 smu->pstate_mclk = mem_table->dpm_levels[0].value;
535 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
536 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
537 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
538 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
541 smu->pstate_sclk = smu->pstate_sclk * 100;
542 smu->pstate_mclk = smu->pstate_mclk * 100;
547 static int arcturus_get_clk_table(struct smu_context *smu,
548 struct pp_clock_levels_with_latency *clocks,
549 struct arcturus_single_dpm_table *dpm_table)
553 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
554 clocks->num_levels = count;
556 for (i = 0; i < count; i++) {
557 clocks->data[i].clocks_in_khz =
558 dpm_table->dpm_levels[i].value * 1000;
559 clocks->data[i].latency_in_us = 0;
565 static int arcturus_print_clk_levels(struct smu_context *smu,
566 enum smu_clk_type type, char *buf)
568 int i, now, size = 0;
570 struct pp_clock_levels_with_latency clocks;
571 struct arcturus_single_dpm_table *single_dpm_table;
572 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
573 struct arcturus_dpm_table *dpm_table = NULL;
575 dpm_table = smu_dpm->dpm_context;
579 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
581 pr_err("Attempt to get current gfx clk Failed!");
585 single_dpm_table = &(dpm_table->gfx_table);
586 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
588 pr_err("Attempt to get gfx clk levels Failed!");
592 for (i = 0; i < clocks.num_levels; i++)
593 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
594 clocks.data[i].clocks_in_khz / 1000,
595 (clocks.data[i].clocks_in_khz == now * 10)
600 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
602 pr_err("Attempt to get current mclk Failed!");
606 single_dpm_table = &(dpm_table->mem_table);
607 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
609 pr_err("Attempt to get memory clk levels Failed!");
613 for (i = 0; i < clocks.num_levels; i++)
614 size += sprintf(buf + size, "%d: %uMhz %s\n",
615 i, clocks.data[i].clocks_in_khz / 1000,
616 (clocks.data[i].clocks_in_khz == now * 10)
621 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
623 pr_err("Attempt to get current socclk Failed!");
627 single_dpm_table = &(dpm_table->soc_table);
628 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
630 pr_err("Attempt to get socclk levels Failed!");
634 for (i = 0; i < clocks.num_levels; i++)
635 size += sprintf(buf + size, "%d: %uMhz %s\n",
636 i, clocks.data[i].clocks_in_khz / 1000,
637 (clocks.data[i].clocks_in_khz == now * 10)
642 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
644 pr_err("Attempt to get current fclk Failed!");
648 single_dpm_table = &(dpm_table->fclk_table);
649 for (i = 0; i < single_dpm_table->count; i++)
650 size += sprintf(buf + size, "%d: %uMhz %s\n",
651 i, single_dpm_table->dpm_levels[i].value,
652 (single_dpm_table->dpm_levels[i].value == now / 100)
663 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
664 uint32_t feature_mask)
666 struct arcturus_dpm_table *dpm_table;
667 struct arcturus_single_dpm_table *single_dpm_table;
671 dpm_table = smu->smu_dpm.dpm_context;
672 if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
673 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
674 single_dpm_table = &(dpm_table->gfx_table);
675 freq = max ? single_dpm_table->dpm_state.soft_max_level :
676 single_dpm_table->dpm_state.soft_min_level;
677 ret = smu_send_smc_msg_with_param(smu,
678 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
679 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
681 pr_err("Failed to set soft %s gfxclk !\n",
682 max ? "max" : "min");
690 static int arcturus_force_clk_levels(struct smu_context *smu,
691 enum smu_clk_type type, uint32_t mask)
693 struct arcturus_dpm_table *dpm_table;
694 struct arcturus_single_dpm_table *single_dpm_table;
695 uint32_t soft_min_level, soft_max_level;
698 mutex_lock(&(smu->mutex));
700 soft_min_level = mask ? (ffs(mask) - 1) : 0;
701 soft_max_level = mask ? (fls(mask) - 1) : 0;
703 dpm_table = smu->smu_dpm.dpm_context;
707 single_dpm_table = &(dpm_table->gfx_table);
709 if (soft_max_level >= single_dpm_table->count) {
710 pr_err("Clock level specified %d is over max allowed %d\n",
711 soft_max_level, single_dpm_table->count - 1);
716 single_dpm_table->dpm_state.soft_min_level =
717 single_dpm_table->dpm_levels[soft_min_level].value;
718 single_dpm_table->dpm_state.soft_max_level =
719 single_dpm_table->dpm_levels[soft_max_level].value;
721 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
723 pr_err("Failed to upload boot level to lowest!\n");
727 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
729 pr_err("Failed to upload dpm max level to highest!\n");
734 single_dpm_table = &(dpm_table->mem_table);
736 if (soft_max_level >= single_dpm_table->count) {
737 pr_err("Clock level specified %d is over max allowed %d\n",
738 soft_max_level, single_dpm_table->count - 1);
743 single_dpm_table->dpm_state.soft_min_level =
744 single_dpm_table->dpm_levels[soft_min_level].value;
745 single_dpm_table->dpm_state.soft_max_level =
746 single_dpm_table->dpm_levels[soft_max_level].value;
748 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
750 pr_err("Failed to upload boot level to lowest!\n");
754 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
756 pr_err("Failed to upload dpm max level to highest!\n");
761 single_dpm_table = &(dpm_table->soc_table);
763 if (soft_max_level >= single_dpm_table->count) {
764 pr_err("Clock level specified %d is over max allowed %d\n",
765 soft_max_level, single_dpm_table->count - 1);
770 single_dpm_table->dpm_state.soft_min_level =
771 single_dpm_table->dpm_levels[soft_min_level].value;
772 single_dpm_table->dpm_state.soft_max_level =
773 single_dpm_table->dpm_levels[soft_max_level].value;
775 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
777 pr_err("Failed to upload boot level to lowest!\n");
781 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
783 pr_err("Failed to upload dpm max level to highest!\n");
788 single_dpm_table = &(dpm_table->fclk_table);
790 if (soft_max_level >= single_dpm_table->count) {
791 pr_err("Clock level specified %d is over max allowed %d\n",
792 soft_max_level, single_dpm_table->count - 1);
797 single_dpm_table->dpm_state.soft_min_level =
798 single_dpm_table->dpm_levels[soft_min_level].value;
799 single_dpm_table->dpm_state.soft_max_level =
800 single_dpm_table->dpm_levels[soft_max_level].value;
802 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
804 pr_err("Failed to upload boot level to lowest!\n");
808 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
810 pr_err("Failed to upload dpm max level to highest!\n");
818 mutex_unlock(&(smu->mutex));
822 static const struct smu_temperature_range arcturus_thermal_policy[] =
824 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
825 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
828 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
829 struct smu_temperature_range *range)
832 PPTable_t *pptable = smu->smu_table.driver_pptable;
837 memcpy(range, &arcturus_thermal_policy[0], sizeof(struct smu_temperature_range));
839 range->max = pptable->TedgeLimit *
840 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
841 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
842 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
843 range->hotspot_crit_max = pptable->ThotspotLimit *
844 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
845 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
846 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
847 range->mem_crit_max = pptable->TmemLimit *
848 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
849 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
850 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
856 static int arcturus_get_metrics_table(struct smu_context *smu,
857 SmuMetrics_t *metrics_table)
859 struct smu_table_context *smu_table= &smu->smu_table;
862 if (!smu_table->metrics_time ||
863 time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
864 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
865 (void *)smu_table->metrics_table, false);
867 pr_info("Failed to export SMU metrics table!\n");
870 smu_table->metrics_time = jiffies;
873 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
878 static int arcturus_get_current_activity_percent(struct smu_context *smu,
879 enum amd_pp_sensors sensor,
882 SmuMetrics_t metrics;
888 ret = arcturus_get_metrics_table(smu, &metrics);
893 case AMDGPU_PP_SENSOR_GPU_LOAD:
894 *value = metrics.AverageGfxActivity;
896 case AMDGPU_PP_SENSOR_MEM_LOAD:
897 *value = metrics.AverageUclkActivity;
900 pr_err("Invalid sensor for retrieving clock activity\n");
907 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
909 SmuMetrics_t metrics;
915 ret = arcturus_get_metrics_table(smu, &metrics);
919 *value = metrics.AverageSocketPower << 8;
924 static int arcturus_thermal_get_temperature(struct smu_context *smu,
925 enum amd_pp_sensors sensor,
928 SmuMetrics_t metrics;
934 ret = arcturus_get_metrics_table(smu, &metrics);
939 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
940 *value = metrics.TemperatureHotspot *
941 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
943 case AMDGPU_PP_SENSOR_EDGE_TEMP:
944 *value = metrics.TemperatureEdge *
945 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
947 case AMDGPU_PP_SENSOR_MEM_TEMP:
948 *value = metrics.TemperatureHBM *
949 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
952 pr_err("Invalid sensor for retrieving temp\n");
959 static int arcturus_read_sensor(struct smu_context *smu,
960 enum amd_pp_sensors sensor,
961 void *data, uint32_t *size)
963 struct smu_table_context *table_context = &smu->smu_table;
964 PPTable_t *pptable = table_context->driver_pptable;
968 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
969 *(uint32_t *)data = pptable->FanMaximumRpm;
972 case AMDGPU_PP_SENSOR_MEM_LOAD:
973 case AMDGPU_PP_SENSOR_GPU_LOAD:
974 ret = arcturus_get_current_activity_percent(smu,
979 case AMDGPU_PP_SENSOR_GPU_POWER:
980 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
983 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
984 case AMDGPU_PP_SENSOR_EDGE_TEMP:
985 case AMDGPU_PP_SENSOR_MEM_TEMP:
986 ret = arcturus_thermal_get_temperature(smu, sensor,
997 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1000 SmuMetrics_t metrics;
1006 ret = arcturus_get_metrics_table(smu, &metrics);
1010 *speed = metrics.CurrFanSpeed;
1015 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1018 PPTable_t *pptable = smu->smu_table.driver_pptable;
1019 uint32_t percent, current_rpm;
1025 ret = arcturus_get_fan_speed_rpm(smu, ¤t_rpm);
1029 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1030 *speed = percent > 100 ? 100 : percent;
1035 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1036 enum smu_clk_type clk_type,
1039 static SmuMetrics_t metrics;
1040 int ret = 0, clk_id = 0;
1045 clk_id = smu_clk_get_index(smu, clk_type);
1049 ret = arcturus_get_metrics_table(smu, &metrics);
1053 *value = metrics.CurrClock[clk_id];
1058 static void arcturus_dump_pptable(struct smu_context *smu)
1060 struct smu_table_context *table_context = &smu->smu_table;
1061 PPTable_t *pptable = table_context->driver_pptable;
1064 pr_info("Dumped PPTable:\n");
1066 pr_info("Version = 0x%08x\n", pptable->Version);
1068 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1069 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1071 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1072 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1073 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1076 pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1077 pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1078 pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1079 pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1081 pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1082 pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1083 pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1084 pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1085 pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1086 pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1087 pr_info("FitLimit = %d\n", pptable->FitLimit);
1089 pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1090 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1092 pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1094 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1095 pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1097 pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1098 pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1099 pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1100 pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1102 pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1103 pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1104 pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1105 pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1107 pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1108 pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1110 pr_info("[PPCLK_GFXCLK]\n"
1111 " .VoltageMode = 0x%02x\n"
1112 " .SnapToDiscrete = 0x%02x\n"
1113 " .NumDiscreteLevels = 0x%02x\n"
1114 " .padding = 0x%02x\n"
1115 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1116 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1117 " .SsFmin = 0x%04x\n"
1118 " .Padding_16 = 0x%04x\n",
1119 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1120 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1121 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1122 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1123 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1124 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1125 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1126 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1127 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1128 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1129 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1131 pr_info("[PPCLK_VCLK]\n"
1132 " .VoltageMode = 0x%02x\n"
1133 " .SnapToDiscrete = 0x%02x\n"
1134 " .NumDiscreteLevels = 0x%02x\n"
1135 " .padding = 0x%02x\n"
1136 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1137 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1138 " .SsFmin = 0x%04x\n"
1139 " .Padding_16 = 0x%04x\n",
1140 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1141 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1142 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1143 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1144 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1145 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1146 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1147 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1148 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1149 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1150 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1152 pr_info("[PPCLK_DCLK]\n"
1153 " .VoltageMode = 0x%02x\n"
1154 " .SnapToDiscrete = 0x%02x\n"
1155 " .NumDiscreteLevels = 0x%02x\n"
1156 " .padding = 0x%02x\n"
1157 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1158 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1159 " .SsFmin = 0x%04x\n"
1160 " .Padding_16 = 0x%04x\n",
1161 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1162 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1163 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1164 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1165 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1166 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1167 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1168 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1169 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1170 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1171 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1173 pr_info("[PPCLK_SOCCLK]\n"
1174 " .VoltageMode = 0x%02x\n"
1175 " .SnapToDiscrete = 0x%02x\n"
1176 " .NumDiscreteLevels = 0x%02x\n"
1177 " .padding = 0x%02x\n"
1178 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1179 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1180 " .SsFmin = 0x%04x\n"
1181 " .Padding_16 = 0x%04x\n",
1182 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1183 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1184 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1185 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1186 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1187 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1188 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1189 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1190 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1191 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1192 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1194 pr_info("[PPCLK_UCLK]\n"
1195 " .VoltageMode = 0x%02x\n"
1196 " .SnapToDiscrete = 0x%02x\n"
1197 " .NumDiscreteLevels = 0x%02x\n"
1198 " .padding = 0x%02x\n"
1199 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1200 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1201 " .SsFmin = 0x%04x\n"
1202 " .Padding_16 = 0x%04x\n",
1203 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1204 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1205 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1206 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1207 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1208 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1209 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1210 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1211 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1212 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1213 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1215 pr_info("[PPCLK_FCLK]\n"
1216 " .VoltageMode = 0x%02x\n"
1217 " .SnapToDiscrete = 0x%02x\n"
1218 " .NumDiscreteLevels = 0x%02x\n"
1219 " .padding = 0x%02x\n"
1220 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1221 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1222 " .SsFmin = 0x%04x\n"
1223 " .Padding_16 = 0x%04x\n",
1224 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1225 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1226 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1227 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1228 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1229 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1230 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1231 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1232 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1233 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1234 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1237 pr_info("FreqTableGfx\n");
1238 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1239 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1241 pr_info("FreqTableVclk\n");
1242 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1243 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1245 pr_info("FreqTableDclk\n");
1246 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1247 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1249 pr_info("FreqTableSocclk\n");
1250 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1251 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1253 pr_info("FreqTableUclk\n");
1254 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1255 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1257 pr_info("FreqTableFclk\n");
1258 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1259 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1261 pr_info("Mp0clkFreq\n");
1262 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1263 pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1265 pr_info("Mp0DpmVoltage\n");
1266 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1267 pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1269 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1270 pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1271 pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1272 pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1273 pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1274 pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1275 pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1276 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1277 pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1279 pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1280 pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1281 pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1282 pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1284 pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1285 pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1287 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1288 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1289 pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1290 pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1291 pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1292 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1294 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1295 pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1296 pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1297 pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1298 pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1299 pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1300 pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1301 pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1302 pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1304 pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1305 pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1306 pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1307 pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1309 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1310 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1311 pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1312 pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1314 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1315 pptable->dBtcGbGfxPll.a,
1316 pptable->dBtcGbGfxPll.b,
1317 pptable->dBtcGbGfxPll.c);
1318 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1319 pptable->dBtcGbGfxAfll.a,
1320 pptable->dBtcGbGfxAfll.b,
1321 pptable->dBtcGbGfxAfll.c);
1322 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1323 pptable->dBtcGbSoc.a,
1324 pptable->dBtcGbSoc.b,
1325 pptable->dBtcGbSoc.c);
1327 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1328 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1329 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1330 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1331 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1332 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1334 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1335 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1336 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1337 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1338 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1339 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1340 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1341 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1343 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1344 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1346 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1347 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1348 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1349 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1351 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1352 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1353 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1354 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1356 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1357 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1359 pr_info("XgmiDpmPstates\n");
1360 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1361 pr_info(" .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1362 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1363 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1365 pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1366 pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1367 pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1368 pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1369 pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1370 pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1371 pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1372 pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1374 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1375 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1376 pptable->ReservedEquation0.a,
1377 pptable->ReservedEquation0.b,
1378 pptable->ReservedEquation0.c);
1379 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1380 pptable->ReservedEquation1.a,
1381 pptable->ReservedEquation1.b,
1382 pptable->ReservedEquation1.c);
1383 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1384 pptable->ReservedEquation2.a,
1385 pptable->ReservedEquation2.b,
1386 pptable->ReservedEquation2.c);
1387 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1388 pptable->ReservedEquation3.a,
1389 pptable->ReservedEquation3.b,
1390 pptable->ReservedEquation3.c);
1392 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1393 pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1395 pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1396 pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1397 pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1399 pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1400 pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1402 pr_info("Board Parameters:\n");
1403 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1404 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1406 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1407 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1408 pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1409 pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1411 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1412 pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1414 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1415 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1416 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1418 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1419 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1420 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1422 pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1423 pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1424 pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1426 pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1427 pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1428 pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1430 pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1431 pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1432 pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1433 pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1435 pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1436 pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1437 pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1439 pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1440 pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1441 pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1443 pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1444 pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1445 pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1447 pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1448 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1449 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1451 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1452 pr_info("I2cControllers[%d]:\n", i);
1453 pr_info(" .Enabled = %d\n",
1454 pptable->I2cControllers[i].Enabled);
1455 pr_info(" .SlaveAddress = 0x%x\n",
1456 pptable->I2cControllers[i].SlaveAddress);
1457 pr_info(" .ControllerPort = %d\n",
1458 pptable->I2cControllers[i].ControllerPort);
1459 pr_info(" .ControllerName = %d\n",
1460 pptable->I2cControllers[i].ControllerName);
1461 pr_info(" .ThermalThrottler = %d\n",
1462 pptable->I2cControllers[i].ThermalThrotter);
1463 pr_info(" .I2cProtocol = %d\n",
1464 pptable->I2cControllers[i].I2cProtocol);
1465 pr_info(" .Speed = %d\n",
1466 pptable->I2cControllers[i].Speed);
1469 pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1470 pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1472 pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1474 pr_info("XgmiLinkSpeed\n");
1475 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1476 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1477 pr_info("XgmiLinkWidth\n");
1478 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1479 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1480 pr_info("XgmiFclkFreq\n");
1481 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1482 pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1483 pr_info("XgmiSocVoltage\n");
1484 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1485 pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1489 static const struct pptable_funcs arcturus_ppt_funcs = {
1490 /* translate smu index into arcturus specific index */
1491 .get_smu_msg_index = arcturus_get_smu_msg_index,
1492 .get_smu_clk_index = arcturus_get_smu_clk_index,
1493 .get_smu_feature_index = arcturus_get_smu_feature_index,
1494 .get_smu_table_index = arcturus_get_smu_table_index,
1495 .get_smu_power_index= arcturus_get_pwr_src_index,
1496 .get_workload_type = arcturus_get_workload_type,
1497 /* internal structurs allocations */
1498 .tables_init = arcturus_tables_init,
1499 .alloc_dpm_context = arcturus_allocate_dpm_context,
1500 /* pptable related */
1501 .check_powerplay_table = arcturus_check_powerplay_table,
1502 .store_powerplay_table = arcturus_store_powerplay_table,
1503 .append_powerplay_table = arcturus_append_powerplay_table,
1505 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1507 .run_afll_btc = arcturus_run_btc_afll,
1508 /* dpm/clk tables */
1509 .set_default_dpm_table = arcturus_set_default_dpm_table,
1510 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1511 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1512 .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1513 .print_clk_levels = arcturus_print_clk_levels,
1514 .force_clk_levels = arcturus_force_clk_levels,
1515 .read_sensor = arcturus_read_sensor,
1516 .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1517 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1518 /* debug (internal used) */
1519 .dump_pptable = arcturus_dump_pptable,
1522 void arcturus_set_ppt_funcs(struct smu_context *smu)
1524 struct smu_table_context *smu_table = &smu->smu_table;
1526 smu->ppt_funcs = &arcturus_ppt_funcs;
1527 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1528 smu_table->table_count = TABLE_COUNT;