2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "smu_v11_0.h"
32 #include "smu11_driver_if_arcturus.h"
33 #include "soc15_common.h"
35 #include "power_state.h"
36 #include "arcturus_ppt.h"
37 #include "smu_v11_0_pptable.h"
38 #include "arcturus_ppsmc.h"
39 #include "nbio/nbio_7_4_sh_mask.h"
41 #define CTF_OFFSET_EDGE 5
42 #define CTF_OFFSET_HOTSPOT 5
43 #define CTF_OFFSET_HBM 5
45 #define MSG_MAP(msg, index) \
46 [SMU_MSG_##msg] = {1, (index)}
47 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
48 [smu_feature] = {1, (arcturus_feature)}
50 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
51 #define SMU_FEATURES_LOW_SHIFT 0
52 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
53 #define SMU_FEATURES_HIGH_SHIFT 32
55 #define SMC_DPM_FEATURE ( \
56 FEATURE_DPM_PREFETCHER_MASK | \
57 FEATURE_DPM_GFXCLK_MASK | \
58 FEATURE_DPM_UCLK_MASK | \
59 FEATURE_DPM_SOCCLK_MASK | \
60 FEATURE_DPM_MP0CLK_MASK | \
61 FEATURE_DPM_FCLK_MASK | \
62 FEATURE_DPM_XGMI_MASK)
64 /* possible frequency drift (1Mhz) */
67 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
68 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
69 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
70 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
71 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
72 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
73 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
74 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
75 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
76 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
77 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
78 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
79 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
80 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
81 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
82 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
83 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
84 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
85 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
86 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
87 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
88 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
89 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
90 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
91 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
92 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
93 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
94 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
95 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
96 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
97 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
98 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
99 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
100 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
101 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
102 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType),
103 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm),
104 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive),
105 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
106 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
107 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0),
108 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0),
109 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1),
110 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1),
111 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
112 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
113 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
114 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
115 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc),
116 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc),
117 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
118 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
119 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
120 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
121 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
122 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
123 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
126 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
127 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
128 CLK_MAP(SCLK, PPCLK_GFXCLK),
129 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
130 CLK_MAP(FCLK, PPCLK_FCLK),
131 CLK_MAP(UCLK, PPCLK_UCLK),
132 CLK_MAP(MCLK, PPCLK_UCLK),
133 CLK_MAP(DCLK, PPCLK_DCLK),
134 CLK_MAP(VCLK, PPCLK_VCLK),
137 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
138 FEA_MAP(DPM_PREFETCHER),
144 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
151 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
152 FEA_MAP(RSMU_SMN_CG),
160 FEA_MAP(FAN_CONTROL),
162 FEA_MAP(OUT_OF_BAND_MONITOR),
163 FEA_MAP(TEMP_DEPENDENT_VMIN),
166 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
169 TAB_MAP(AVFS_PSM_DEBUG),
170 TAB_MAP(AVFS_FUSE_OVERRIDE),
171 TAB_MAP(PMSTATUSLOG),
172 TAB_MAP(SMU_METRICS),
173 TAB_MAP(DRIVER_SMU_CONFIG),
177 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
182 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
184 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
190 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
192 struct smu_11_0_cmn2aisc_mapping mapping;
194 if (index >= SMU_MSG_MAX_COUNT)
197 mapping = arcturus_message_map[index];
198 if (!(mapping.valid_mapping))
201 return mapping.map_to;
204 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
206 struct smu_11_0_cmn2aisc_mapping mapping;
208 if (index >= SMU_CLK_COUNT)
211 mapping = arcturus_clk_map[index];
212 if (!(mapping.valid_mapping)) {
213 pr_warn("Unsupported SMU clk: %d\n", index);
217 return mapping.map_to;
220 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
222 struct smu_11_0_cmn2aisc_mapping mapping;
224 if (index >= SMU_FEATURE_COUNT)
227 mapping = arcturus_feature_mask_map[index];
228 if (!(mapping.valid_mapping)) {
232 return mapping.map_to;
235 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
237 struct smu_11_0_cmn2aisc_mapping mapping;
239 if (index >= SMU_TABLE_COUNT)
242 mapping = arcturus_table_map[index];
243 if (!(mapping.valid_mapping)) {
244 pr_warn("Unsupported SMU table: %d\n", index);
248 return mapping.map_to;
251 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
253 struct smu_11_0_cmn2aisc_mapping mapping;
255 if (index >= SMU_POWER_SOURCE_COUNT)
258 mapping = arcturus_pwr_src_map[index];
259 if (!(mapping.valid_mapping)) {
260 pr_warn("Unsupported SMU power source: %d\n", index);
264 return mapping.map_to;
268 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
270 struct smu_11_0_cmn2aisc_mapping mapping;
272 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
275 mapping = arcturus_workload_map[profile];
276 if (!(mapping.valid_mapping)) {
277 pr_warn("Unsupported SMU power source: %d\n", profile);
281 return mapping.map_to;
284 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
286 struct smu_table_context *smu_table = &smu->smu_table;
288 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
289 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
291 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
292 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
294 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
295 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
297 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
298 if (!smu_table->metrics_table)
300 smu_table->metrics_time = 0;
305 static int arcturus_allocate_dpm_context(struct smu_context *smu)
307 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
309 if (smu_dpm->dpm_context)
312 smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
314 if (!smu_dpm->dpm_context)
317 if (smu_dpm->golden_dpm_context)
320 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
322 if (!smu_dpm->golden_dpm_context)
325 smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
327 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
329 if (!smu_dpm->dpm_current_power_state)
332 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
334 if (!smu_dpm->dpm_request_power_state)
341 arcturus_get_allowed_feature_mask(struct smu_context *smu,
342 uint32_t *feature_mask, uint32_t num)
347 /* pptable will handle the features to enable */
348 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
354 arcturus_set_single_dpm_table(struct smu_context *smu,
355 struct arcturus_single_dpm_table *single_dpm_table,
359 uint32_t i, num_of_levels = 0, clk;
361 ret = smu_send_smc_msg_with_param(smu,
362 SMU_MSG_GetDpmFreqByIndex,
363 (clk_id << 16 | 0xFF));
365 pr_err("[%s] failed to get dpm levels!\n", __func__);
369 smu_read_smc_arg(smu, &num_of_levels);
370 if (!num_of_levels) {
371 pr_err("[%s] number of clk levels is invalid!\n", __func__);
375 single_dpm_table->count = num_of_levels;
376 for (i = 0; i < num_of_levels; i++) {
377 ret = smu_send_smc_msg_with_param(smu,
378 SMU_MSG_GetDpmFreqByIndex,
381 pr_err("[%s] failed to get dpm freq by index!\n", __func__);
384 smu_read_smc_arg(smu, &clk);
386 pr_err("[%s] clk value is invalid!\n", __func__);
389 single_dpm_table->dpm_levels[i].value = clk;
390 single_dpm_table->dpm_levels[i].enabled = true;
395 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
397 dpm_state->soft_min_level = 0x0;
398 dpm_state->soft_max_level = 0xffff;
399 dpm_state->hard_min_level = 0x0;
400 dpm_state->hard_max_level = 0xffff;
403 static int arcturus_set_default_dpm_table(struct smu_context *smu)
407 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
408 struct arcturus_dpm_table *dpm_table = NULL;
409 struct arcturus_single_dpm_table *single_dpm_table;
411 dpm_table = smu_dpm->dpm_context;
414 single_dpm_table = &(dpm_table->soc_table);
415 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
416 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
419 pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
423 single_dpm_table->count = 1;
424 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
426 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
429 single_dpm_table = &(dpm_table->gfx_table);
430 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
431 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
434 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
438 single_dpm_table->count = 1;
439 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
441 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
444 single_dpm_table = &(dpm_table->mem_table);
445 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
446 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
449 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
453 single_dpm_table->count = 1;
454 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
456 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
459 single_dpm_table = &(dpm_table->fclk_table);
460 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
461 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
464 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
468 single_dpm_table->count = 1;
469 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
471 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
473 memcpy(smu_dpm->golden_dpm_context, dpm_table,
474 sizeof(struct arcturus_dpm_table));
479 static int arcturus_check_powerplay_table(struct smu_context *smu)
484 static int arcturus_store_powerplay_table(struct smu_context *smu)
486 struct smu_11_0_powerplay_table *powerplay_table = NULL;
487 struct smu_table_context *table_context = &smu->smu_table;
490 if (!table_context->power_play_table)
493 powerplay_table = table_context->power_play_table;
495 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
498 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
503 static int arcturus_append_powerplay_table(struct smu_context *smu)
505 struct smu_table_context *table_context = &smu->smu_table;
506 PPTable_t *smc_pptable = table_context->driver_pptable;
507 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
510 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
513 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
514 (uint8_t **)&smc_dpm_table);
518 pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
519 smc_dpm_table->table_header.format_revision,
520 smc_dpm_table->table_header.content_revision);
522 if ((smc_dpm_table->table_header.format_revision == 4) &&
523 (smc_dpm_table->table_header.content_revision == 6))
524 memcpy(&smc_pptable->MaxVoltageStepGfx,
525 &smc_dpm_table->maxvoltagestepgfx,
526 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
531 static int arcturus_run_btc(struct smu_context *smu)
535 ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
537 pr_err("RunAfllBtc failed!\n");
541 return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
544 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
546 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
547 struct arcturus_dpm_table *dpm_table = NULL;
548 struct arcturus_single_dpm_table *gfx_table = NULL;
549 struct arcturus_single_dpm_table *mem_table = NULL;
551 dpm_table = smu_dpm->dpm_context;
552 gfx_table = &(dpm_table->gfx_table);
553 mem_table = &(dpm_table->mem_table);
555 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
556 smu->pstate_mclk = mem_table->dpm_levels[0].value;
558 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
559 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
560 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
561 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
564 smu->pstate_sclk = smu->pstate_sclk * 100;
565 smu->pstate_mclk = smu->pstate_mclk * 100;
570 static int arcturus_get_clk_table(struct smu_context *smu,
571 struct pp_clock_levels_with_latency *clocks,
572 struct arcturus_single_dpm_table *dpm_table)
576 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
577 clocks->num_levels = count;
579 for (i = 0; i < count; i++) {
580 clocks->data[i].clocks_in_khz =
581 dpm_table->dpm_levels[i].value * 1000;
582 clocks->data[i].latency_in_us = 0;
588 static int arcturus_freqs_in_same_level(int32_t frequency1,
591 return (abs(frequency1 - frequency2) <= EPSILON);
594 static int arcturus_print_clk_levels(struct smu_context *smu,
595 enum smu_clk_type type, char *buf)
597 int i, now, size = 0;
599 struct pp_clock_levels_with_latency clocks;
600 struct arcturus_single_dpm_table *single_dpm_table;
601 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
602 struct arcturus_dpm_table *dpm_table = NULL;
604 dpm_table = smu_dpm->dpm_context;
608 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
610 pr_err("Attempt to get current gfx clk Failed!");
614 single_dpm_table = &(dpm_table->gfx_table);
615 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
617 pr_err("Attempt to get gfx clk levels Failed!");
621 for (i = 0; i < clocks.num_levels; i++)
622 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
623 clocks.data[i].clocks_in_khz / 1000,
624 arcturus_freqs_in_same_level(
625 clocks.data[i].clocks_in_khz / 1000,
626 now / 100) ? "*" : "");
630 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
632 pr_err("Attempt to get current mclk Failed!");
636 single_dpm_table = &(dpm_table->mem_table);
637 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
639 pr_err("Attempt to get memory clk levels Failed!");
643 for (i = 0; i < clocks.num_levels; i++)
644 size += sprintf(buf + size, "%d: %uMhz %s\n",
645 i, clocks.data[i].clocks_in_khz / 1000,
646 arcturus_freqs_in_same_level(
647 clocks.data[i].clocks_in_khz / 1000,
648 now / 100) ? "*" : "");
652 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
654 pr_err("Attempt to get current socclk Failed!");
658 single_dpm_table = &(dpm_table->soc_table);
659 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
661 pr_err("Attempt to get socclk levels Failed!");
665 for (i = 0; i < clocks.num_levels; i++)
666 size += sprintf(buf + size, "%d: %uMhz %s\n",
667 i, clocks.data[i].clocks_in_khz / 1000,
668 arcturus_freqs_in_same_level(
669 clocks.data[i].clocks_in_khz / 1000,
670 now / 100) ? "*" : "");
674 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
676 pr_err("Attempt to get current fclk Failed!");
680 single_dpm_table = &(dpm_table->fclk_table);
681 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
683 pr_err("Attempt to get fclk levels Failed!");
687 for (i = 0; i < single_dpm_table->count; i++)
688 size += sprintf(buf + size, "%d: %uMhz %s\n",
689 i, single_dpm_table->dpm_levels[i].value,
690 arcturus_freqs_in_same_level(
691 clocks.data[i].clocks_in_khz / 1000,
692 now / 100) ? "*" : "");
702 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
703 uint32_t feature_mask)
705 struct arcturus_single_dpm_table *single_dpm_table;
706 struct arcturus_dpm_table *dpm_table =
707 smu->smu_dpm.dpm_context;
711 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
712 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
713 single_dpm_table = &(dpm_table->gfx_table);
714 freq = max ? single_dpm_table->dpm_state.soft_max_level :
715 single_dpm_table->dpm_state.soft_min_level;
716 ret = smu_send_smc_msg_with_param(smu,
717 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
718 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
720 pr_err("Failed to set soft %s gfxclk !\n",
721 max ? "max" : "min");
726 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
727 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
728 single_dpm_table = &(dpm_table->mem_table);
729 freq = max ? single_dpm_table->dpm_state.soft_max_level :
730 single_dpm_table->dpm_state.soft_min_level;
731 ret = smu_send_smc_msg_with_param(smu,
732 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
733 (PPCLK_UCLK << 16) | (freq & 0xffff));
735 pr_err("Failed to set soft %s memclk !\n",
736 max ? "max" : "min");
741 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
742 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
743 single_dpm_table = &(dpm_table->soc_table);
744 freq = max ? single_dpm_table->dpm_state.soft_max_level :
745 single_dpm_table->dpm_state.soft_min_level;
746 ret = smu_send_smc_msg_with_param(smu,
747 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
748 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
750 pr_err("Failed to set soft %s socclk !\n",
751 max ? "max" : "min");
759 static int arcturus_force_clk_levels(struct smu_context *smu,
760 enum smu_clk_type type, uint32_t mask)
762 struct arcturus_dpm_table *dpm_table;
763 struct arcturus_single_dpm_table *single_dpm_table;
764 uint32_t soft_min_level, soft_max_level;
767 soft_min_level = mask ? (ffs(mask) - 1) : 0;
768 soft_max_level = mask ? (fls(mask) - 1) : 0;
770 dpm_table = smu->smu_dpm.dpm_context;
774 single_dpm_table = &(dpm_table->gfx_table);
776 if (soft_max_level >= single_dpm_table->count) {
777 pr_err("Clock level specified %d is over max allowed %d\n",
778 soft_max_level, single_dpm_table->count - 1);
783 single_dpm_table->dpm_state.soft_min_level =
784 single_dpm_table->dpm_levels[soft_min_level].value;
785 single_dpm_table->dpm_state.soft_max_level =
786 single_dpm_table->dpm_levels[soft_max_level].value;
788 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
790 pr_err("Failed to upload boot level to lowest!\n");
794 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
796 pr_err("Failed to upload dpm max level to highest!\n");
801 single_dpm_table = &(dpm_table->mem_table);
803 if (soft_max_level >= single_dpm_table->count) {
804 pr_err("Clock level specified %d is over max allowed %d\n",
805 soft_max_level, single_dpm_table->count - 1);
810 single_dpm_table->dpm_state.soft_min_level =
811 single_dpm_table->dpm_levels[soft_min_level].value;
812 single_dpm_table->dpm_state.soft_max_level =
813 single_dpm_table->dpm_levels[soft_max_level].value;
815 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
817 pr_err("Failed to upload boot level to lowest!\n");
821 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
823 pr_err("Failed to upload dpm max level to highest!\n");
828 single_dpm_table = &(dpm_table->soc_table);
830 if (soft_max_level >= single_dpm_table->count) {
831 pr_err("Clock level specified %d is over max allowed %d\n",
832 soft_max_level, single_dpm_table->count - 1);
837 single_dpm_table->dpm_state.soft_min_level =
838 single_dpm_table->dpm_levels[soft_min_level].value;
839 single_dpm_table->dpm_state.soft_max_level =
840 single_dpm_table->dpm_levels[soft_max_level].value;
842 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
844 pr_err("Failed to upload boot level to lowest!\n");
848 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
850 pr_err("Failed to upload dpm max level to highest!\n");
855 single_dpm_table = &(dpm_table->fclk_table);
857 if (soft_max_level >= single_dpm_table->count) {
858 pr_err("Clock level specified %d is over max allowed %d\n",
859 soft_max_level, single_dpm_table->count - 1);
864 single_dpm_table->dpm_state.soft_min_level =
865 single_dpm_table->dpm_levels[soft_min_level].value;
866 single_dpm_table->dpm_state.soft_max_level =
867 single_dpm_table->dpm_levels[soft_max_level].value;
869 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
871 pr_err("Failed to upload boot level to lowest!\n");
875 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
877 pr_err("Failed to upload dpm max level to highest!\n");
888 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
889 struct smu_temperature_range *range)
891 PPTable_t *pptable = smu->smu_table.driver_pptable;
896 range->max = pptable->TedgeLimit *
897 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
898 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
899 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
900 range->hotspot_crit_max = pptable->ThotspotLimit *
901 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
902 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
903 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
904 range->mem_crit_max = pptable->TmemLimit *
905 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
906 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
907 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
912 static int arcturus_get_metrics_table(struct smu_context *smu,
913 SmuMetrics_t *metrics_table)
915 struct smu_table_context *smu_table= &smu->smu_table;
918 if (!smu_table->metrics_time ||
919 time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
920 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
921 (void *)smu_table->metrics_table, false);
923 pr_info("Failed to export SMU metrics table!\n");
926 smu_table->metrics_time = jiffies;
929 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
934 static int arcturus_get_current_activity_percent(struct smu_context *smu,
935 enum amd_pp_sensors sensor,
938 SmuMetrics_t metrics;
944 ret = arcturus_get_metrics_table(smu, &metrics);
949 case AMDGPU_PP_SENSOR_GPU_LOAD:
950 *value = metrics.AverageGfxActivity;
952 case AMDGPU_PP_SENSOR_MEM_LOAD:
953 *value = metrics.AverageUclkActivity;
956 pr_err("Invalid sensor for retrieving clock activity\n");
963 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
965 SmuMetrics_t metrics;
971 ret = arcturus_get_metrics_table(smu, &metrics);
975 *value = metrics.AverageSocketPower << 8;
980 static int arcturus_thermal_get_temperature(struct smu_context *smu,
981 enum amd_pp_sensors sensor,
984 SmuMetrics_t metrics;
990 ret = arcturus_get_metrics_table(smu, &metrics);
995 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
996 *value = metrics.TemperatureHotspot *
997 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
999 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1000 *value = metrics.TemperatureEdge *
1001 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1003 case AMDGPU_PP_SENSOR_MEM_TEMP:
1004 *value = metrics.TemperatureHBM *
1005 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1008 pr_err("Invalid sensor for retrieving temp\n");
1015 static int arcturus_read_sensor(struct smu_context *smu,
1016 enum amd_pp_sensors sensor,
1017 void *data, uint32_t *size)
1019 struct smu_table_context *table_context = &smu->smu_table;
1020 PPTable_t *pptable = table_context->driver_pptable;
1026 mutex_lock(&smu->sensor_lock);
1028 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1029 *(uint32_t *)data = pptable->FanMaximumRpm;
1032 case AMDGPU_PP_SENSOR_MEM_LOAD:
1033 case AMDGPU_PP_SENSOR_GPU_LOAD:
1034 ret = arcturus_get_current_activity_percent(smu,
1039 case AMDGPU_PP_SENSOR_GPU_POWER:
1040 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1043 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1044 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1045 case AMDGPU_PP_SENSOR_MEM_TEMP:
1046 ret = arcturus_thermal_get_temperature(smu, sensor,
1051 ret = smu_smc_read_sensor(smu, sensor, data, size);
1053 mutex_unlock(&smu->sensor_lock);
1058 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1061 SmuMetrics_t metrics;
1067 ret = arcturus_get_metrics_table(smu, &metrics);
1071 *speed = metrics.CurrFanSpeed;
1076 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1079 PPTable_t *pptable = smu->smu_table.driver_pptable;
1080 uint32_t percent, current_rpm;
1086 ret = arcturus_get_fan_speed_rpm(smu, ¤t_rpm);
1090 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1091 *speed = percent > 100 ? 100 : percent;
1096 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1097 enum smu_clk_type clk_type,
1100 static SmuMetrics_t metrics;
1101 int ret = 0, clk_id = 0;
1106 clk_id = smu_clk_get_index(smu, clk_type);
1110 ret = arcturus_get_metrics_table(smu, &metrics);
1117 * CurrClock[clk_id] can provide accurate
1118 * output only when the dpm feature is enabled.
1119 * We can use Average_* for dpm disabled case.
1120 * But this is available for gfxclk/uclk/socclk.
1122 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1123 *value = metrics.CurrClock[PPCLK_GFXCLK];
1125 *value = metrics.AverageGfxclkFrequency;
1128 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1129 *value = metrics.CurrClock[PPCLK_UCLK];
1131 *value = metrics.AverageUclkFrequency;
1134 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1135 *value = metrics.CurrClock[PPCLK_SOCCLK];
1137 *value = metrics.AverageSocclkFrequency;
1140 *value = metrics.CurrClock[clk_id];
1147 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1151 for (i = 0; i < table->count; i++) {
1152 if (table->dpm_levels[i].enabled)
1155 if (i >= table->count) {
1157 table->dpm_levels[i].enabled = true;
1163 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1167 if (table->count <= 0) {
1168 pr_err("[%s] DPM Table has no entry!", __func__);
1171 if (table->count > MAX_DPM_NUMBER) {
1172 pr_err("[%s] DPM Table has too many entries!", __func__);
1173 return MAX_DPM_NUMBER - 1;
1176 for (i = table->count - 1; i >= 0; i--) {
1177 if (table->dpm_levels[i].enabled)
1182 table->dpm_levels[i].enabled = true;
1190 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1192 struct arcturus_dpm_table *dpm_table =
1193 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1194 uint32_t soft_level;
1199 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1201 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1203 dpm_table->gfx_table.dpm_state.soft_min_level =
1204 dpm_table->gfx_table.dpm_state.soft_max_level =
1205 dpm_table->gfx_table.dpm_levels[soft_level].value;
1209 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1211 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1213 dpm_table->mem_table.dpm_state.soft_min_level =
1214 dpm_table->mem_table.dpm_state.soft_max_level =
1215 dpm_table->mem_table.dpm_levels[soft_level].value;
1219 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1221 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1223 dpm_table->soc_table.dpm_state.soft_min_level =
1224 dpm_table->soc_table.dpm_state.soft_max_level =
1225 dpm_table->soc_table.dpm_levels[soft_level].value;
1227 ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1229 pr_err("Failed to upload boot level to %s!\n",
1230 highest ? "highest" : "lowest");
1234 ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1236 pr_err("Failed to upload dpm max level to %s!\n!",
1237 highest ? "highest" : "lowest");
1244 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1246 struct arcturus_dpm_table *dpm_table =
1247 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1248 uint32_t soft_min_level, soft_max_level;
1252 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1253 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1254 dpm_table->gfx_table.dpm_state.soft_min_level =
1255 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1256 dpm_table->gfx_table.dpm_state.soft_max_level =
1257 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1260 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1261 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1262 dpm_table->mem_table.dpm_state.soft_min_level =
1263 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1264 dpm_table->mem_table.dpm_state.soft_max_level =
1265 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1268 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1269 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1270 dpm_table->soc_table.dpm_state.soft_min_level =
1271 dpm_table->soc_table.dpm_levels[soft_min_level].value;
1272 dpm_table->soc_table.dpm_state.soft_max_level =
1273 dpm_table->soc_table.dpm_levels[soft_max_level].value;
1275 ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1277 pr_err("Failed to upload DPM Bootup Levels!");
1281 ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1283 pr_err("Failed to upload DPM Max Levels!");
1291 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1292 enum amd_dpm_forced_level level,
1293 uint32_t *sclk_mask,
1294 uint32_t *mclk_mask,
1297 struct arcturus_dpm_table *dpm_table =
1298 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1299 struct arcturus_single_dpm_table *gfx_dpm_table;
1300 struct arcturus_single_dpm_table *mem_dpm_table;
1301 struct arcturus_single_dpm_table *soc_dpm_table;
1303 if (!smu->smu_dpm.dpm_context)
1306 gfx_dpm_table = &dpm_table->gfx_table;
1307 mem_dpm_table = &dpm_table->mem_table;
1308 soc_dpm_table = &dpm_table->soc_table;
1314 if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1315 mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1316 soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1317 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1318 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1319 *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1322 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1324 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1326 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1327 *sclk_mask = gfx_dpm_table->count - 1;
1328 *mclk_mask = mem_dpm_table->count - 1;
1329 *soc_mask = soc_dpm_table->count - 1;
1335 static int arcturus_get_power_limit(struct smu_context *smu,
1339 PPTable_t *pptable = smu->smu_table.driver_pptable;
1340 uint32_t asic_default_power_limit = 0;
1344 if (!smu->default_power_limit ||
1345 !smu->power_limit) {
1346 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1347 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1351 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1354 pr_err("[%s] get PPT limit failed!", __func__);
1357 smu_read_smc_arg(smu, &asic_default_power_limit);
1359 /* the last hope to figure out the ppt limit */
1361 pr_err("Cannot get PPT limit due to pptable missing!");
1364 asic_default_power_limit =
1365 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1368 if (smu->od_enabled) {
1369 asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1370 asic_default_power_limit /= 100;
1373 smu->default_power_limit = asic_default_power_limit;
1374 smu->power_limit = asic_default_power_limit;
1378 *limit = smu->default_power_limit;
1380 *limit = smu->power_limit;
1385 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1388 static const char *profile_name[] = {
1396 uint32_t i, size = 0;
1397 int16_t workload_type = 0;
1399 if (!smu->pm_enabled || !buf)
1402 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1404 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1405 * Not all profile modes are supported on arcturus.
1407 workload_type = smu_workload_get_type(smu, i);
1408 if (workload_type < 0)
1411 size += sprintf(buf + size, "%2d %14s%s\n",
1412 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1418 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1422 int workload_type = 0;
1423 uint32_t profile_mode = input[size];
1426 if (!smu->pm_enabled)
1429 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1430 pr_err("Invalid power profile mode %d\n", profile_mode);
1435 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1436 * Not all profile modes are supported on arcturus.
1438 workload_type = smu_workload_get_type(smu, profile_mode);
1439 if (workload_type < 0) {
1440 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1444 ret = smu_send_smc_msg_with_param(smu,
1445 SMU_MSG_SetWorkloadMask,
1446 1 << workload_type);
1448 pr_err("Fail to set workload type %d\n", workload_type);
1452 smu->power_profile_mode = profile_mode;
1457 static void arcturus_dump_pptable(struct smu_context *smu)
1459 struct smu_table_context *table_context = &smu->smu_table;
1460 PPTable_t *pptable = table_context->driver_pptable;
1463 pr_info("Dumped PPTable:\n");
1465 pr_info("Version = 0x%08x\n", pptable->Version);
1467 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1468 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1470 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1471 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1472 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1475 pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1476 pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1477 pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1478 pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1480 pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1481 pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1482 pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1483 pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1484 pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1485 pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1486 pr_info("FitLimit = %d\n", pptable->FitLimit);
1488 pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1489 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1491 pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1493 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1494 pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1496 pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1497 pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1498 pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1499 pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1501 pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1502 pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1503 pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1504 pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1506 pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1507 pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1509 pr_info("[PPCLK_GFXCLK]\n"
1510 " .VoltageMode = 0x%02x\n"
1511 " .SnapToDiscrete = 0x%02x\n"
1512 " .NumDiscreteLevels = 0x%02x\n"
1513 " .padding = 0x%02x\n"
1514 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1515 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1516 " .SsFmin = 0x%04x\n"
1517 " .Padding_16 = 0x%04x\n",
1518 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1519 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1520 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1521 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1522 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1523 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1524 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1525 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1526 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1527 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1528 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1530 pr_info("[PPCLK_VCLK]\n"
1531 " .VoltageMode = 0x%02x\n"
1532 " .SnapToDiscrete = 0x%02x\n"
1533 " .NumDiscreteLevels = 0x%02x\n"
1534 " .padding = 0x%02x\n"
1535 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1536 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1537 " .SsFmin = 0x%04x\n"
1538 " .Padding_16 = 0x%04x\n",
1539 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1540 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1541 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1542 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1543 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1544 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1545 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1546 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1547 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1548 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1549 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1551 pr_info("[PPCLK_DCLK]\n"
1552 " .VoltageMode = 0x%02x\n"
1553 " .SnapToDiscrete = 0x%02x\n"
1554 " .NumDiscreteLevels = 0x%02x\n"
1555 " .padding = 0x%02x\n"
1556 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1557 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1558 " .SsFmin = 0x%04x\n"
1559 " .Padding_16 = 0x%04x\n",
1560 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1561 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1562 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1563 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1564 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1565 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1566 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1567 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1568 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1569 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1570 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1572 pr_info("[PPCLK_SOCCLK]\n"
1573 " .VoltageMode = 0x%02x\n"
1574 " .SnapToDiscrete = 0x%02x\n"
1575 " .NumDiscreteLevels = 0x%02x\n"
1576 " .padding = 0x%02x\n"
1577 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1578 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1579 " .SsFmin = 0x%04x\n"
1580 " .Padding_16 = 0x%04x\n",
1581 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1582 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1583 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1584 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1585 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1586 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1587 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1588 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1589 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1590 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1591 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1593 pr_info("[PPCLK_UCLK]\n"
1594 " .VoltageMode = 0x%02x\n"
1595 " .SnapToDiscrete = 0x%02x\n"
1596 " .NumDiscreteLevels = 0x%02x\n"
1597 " .padding = 0x%02x\n"
1598 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1599 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1600 " .SsFmin = 0x%04x\n"
1601 " .Padding_16 = 0x%04x\n",
1602 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1603 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1604 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1605 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1606 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1607 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1608 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1609 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1610 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1611 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1612 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1614 pr_info("[PPCLK_FCLK]\n"
1615 " .VoltageMode = 0x%02x\n"
1616 " .SnapToDiscrete = 0x%02x\n"
1617 " .NumDiscreteLevels = 0x%02x\n"
1618 " .padding = 0x%02x\n"
1619 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1620 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1621 " .SsFmin = 0x%04x\n"
1622 " .Padding_16 = 0x%04x\n",
1623 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1624 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1625 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1626 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1627 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1628 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1629 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1630 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1631 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1632 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1633 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1636 pr_info("FreqTableGfx\n");
1637 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1638 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1640 pr_info("FreqTableVclk\n");
1641 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1642 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1644 pr_info("FreqTableDclk\n");
1645 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1646 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1648 pr_info("FreqTableSocclk\n");
1649 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1650 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1652 pr_info("FreqTableUclk\n");
1653 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1654 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1656 pr_info("FreqTableFclk\n");
1657 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1658 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1660 pr_info("Mp0clkFreq\n");
1661 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1662 pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1664 pr_info("Mp0DpmVoltage\n");
1665 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1666 pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1668 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1669 pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1670 pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1671 pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1672 pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1673 pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1674 pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1675 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1676 pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1678 pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1679 pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1680 pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1681 pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1683 pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1684 pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1686 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1687 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1688 pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1689 pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1690 pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1691 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1693 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1694 pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1695 pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1696 pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1697 pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1698 pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1699 pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1700 pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1701 pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1703 pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1704 pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1705 pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1706 pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1708 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1709 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1710 pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1711 pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1713 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1714 pptable->dBtcGbGfxPll.a,
1715 pptable->dBtcGbGfxPll.b,
1716 pptable->dBtcGbGfxPll.c);
1717 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1718 pptable->dBtcGbGfxAfll.a,
1719 pptable->dBtcGbGfxAfll.b,
1720 pptable->dBtcGbGfxAfll.c);
1721 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1722 pptable->dBtcGbSoc.a,
1723 pptable->dBtcGbSoc.b,
1724 pptable->dBtcGbSoc.c);
1726 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1727 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1728 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1729 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1730 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1731 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1733 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1734 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1735 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1736 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1737 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1738 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1739 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1740 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1742 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1743 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1745 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1746 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1747 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1748 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1750 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1751 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1752 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1753 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1755 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1756 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1758 pr_info("XgmiDpmPstates\n");
1759 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1760 pr_info(" .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1761 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1762 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1764 pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1765 pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1766 pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1767 pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1768 pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1769 pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1770 pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1771 pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1773 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1774 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1775 pptable->ReservedEquation0.a,
1776 pptable->ReservedEquation0.b,
1777 pptable->ReservedEquation0.c);
1778 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1779 pptable->ReservedEquation1.a,
1780 pptable->ReservedEquation1.b,
1781 pptable->ReservedEquation1.c);
1782 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1783 pptable->ReservedEquation2.a,
1784 pptable->ReservedEquation2.b,
1785 pptable->ReservedEquation2.c);
1786 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1787 pptable->ReservedEquation3.a,
1788 pptable->ReservedEquation3.b,
1789 pptable->ReservedEquation3.c);
1791 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1792 pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1794 pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1795 pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1796 pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1798 pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1799 pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1801 pr_info("Board Parameters:\n");
1802 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1803 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1805 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1806 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1807 pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1808 pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1810 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1811 pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1813 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1814 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1815 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1817 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1818 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1819 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1821 pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1822 pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1823 pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1825 pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1826 pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1827 pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1829 pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1830 pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1831 pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1832 pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1834 pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1835 pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1836 pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1838 pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1839 pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1840 pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1842 pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1843 pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1844 pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1846 pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1847 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1848 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1850 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1851 pr_info("I2cControllers[%d]:\n", i);
1852 pr_info(" .Enabled = %d\n",
1853 pptable->I2cControllers[i].Enabled);
1854 pr_info(" .SlaveAddress = 0x%x\n",
1855 pptable->I2cControllers[i].SlaveAddress);
1856 pr_info(" .ControllerPort = %d\n",
1857 pptable->I2cControllers[i].ControllerPort);
1858 pr_info(" .ControllerName = %d\n",
1859 pptable->I2cControllers[i].ControllerName);
1860 pr_info(" .ThermalThrottler = %d\n",
1861 pptable->I2cControllers[i].ThermalThrotter);
1862 pr_info(" .I2cProtocol = %d\n",
1863 pptable->I2cControllers[i].I2cProtocol);
1864 pr_info(" .Speed = %d\n",
1865 pptable->I2cControllers[i].Speed);
1868 pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1869 pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1871 pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1873 pr_info("XgmiLinkSpeed\n");
1874 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1875 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1876 pr_info("XgmiLinkWidth\n");
1877 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1878 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1879 pr_info("XgmiFclkFreq\n");
1880 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1881 pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1882 pr_info("XgmiSocVoltage\n");
1883 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1884 pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1888 static bool arcturus_is_dpm_running(struct smu_context *smu)
1891 uint32_t feature_mask[2];
1892 unsigned long feature_enabled;
1893 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1894 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1895 ((uint64_t)feature_mask[1] << 32));
1896 return !!(feature_enabled & SMC_DPM_FEATURE);
1899 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1901 struct smu_power_context *smu_power = &smu->smu_power;
1902 struct smu_power_gate *power_gate = &smu_power->power_gate;
1906 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1907 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1909 pr_err("[EnableVCNDPM] failed!\n");
1913 power_gate->vcn_gated = false;
1915 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1916 ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1918 pr_err("[DisableVCNDPM] failed!\n");
1922 power_gate->vcn_gated = true;
1928 static const struct pptable_funcs arcturus_ppt_funcs = {
1929 /* translate smu index into arcturus specific index */
1930 .get_smu_msg_index = arcturus_get_smu_msg_index,
1931 .get_smu_clk_index = arcturus_get_smu_clk_index,
1932 .get_smu_feature_index = arcturus_get_smu_feature_index,
1933 .get_smu_table_index = arcturus_get_smu_table_index,
1934 .get_smu_power_index= arcturus_get_pwr_src_index,
1935 .get_workload_type = arcturus_get_workload_type,
1936 /* internal structurs allocations */
1937 .tables_init = arcturus_tables_init,
1938 .alloc_dpm_context = arcturus_allocate_dpm_context,
1939 /* pptable related */
1940 .check_powerplay_table = arcturus_check_powerplay_table,
1941 .store_powerplay_table = arcturus_store_powerplay_table,
1942 .append_powerplay_table = arcturus_append_powerplay_table,
1944 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1946 .run_btc = arcturus_run_btc,
1947 /* dpm/clk tables */
1948 .set_default_dpm_table = arcturus_set_default_dpm_table,
1949 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1950 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1951 .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1952 .print_clk_levels = arcturus_print_clk_levels,
1953 .force_clk_levels = arcturus_force_clk_levels,
1954 .read_sensor = arcturus_read_sensor,
1955 .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1956 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1957 .force_dpm_limit_value = arcturus_force_dpm_limit_value,
1958 .unforce_dpm_levels = arcturus_unforce_dpm_levels,
1959 .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
1960 .get_power_profile_mode = arcturus_get_power_profile_mode,
1961 .set_power_profile_mode = arcturus_set_power_profile_mode,
1962 /* debug (internal used) */
1963 .dump_pptable = arcturus_dump_pptable,
1964 .get_power_limit = arcturus_get_power_limit,
1965 .is_dpm_running = arcturus_is_dpm_running,
1966 .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
1969 void arcturus_set_ppt_funcs(struct smu_context *smu)
1971 smu->ppt_funcs = &arcturus_ppt_funcs;