drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if_arcturus.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "power_state.h"
  36 #include "arcturus_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "arcturus_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = {1, (index)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 130 };
 131
 132 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 133         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 134         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 135         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 136         CLK_MAP(FCLK, PPCLK_FCLK),
 137         CLK_MAP(UCLK, PPCLK_UCLK),
 138         CLK_MAP(MCLK, PPCLK_UCLK),
 139         CLK_MAP(DCLK, PPCLK_DCLK),
 140         CLK_MAP(VCLK, PPCLK_VCLK),
 141 };
 142
 143 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(DPM_PREFETCHER),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_UCLK),
 147         FEA_MAP(DPM_SOCCLK),
 148         FEA_MAP(DPM_FCLK),
 149         FEA_MAP(DPM_MP0CLK),
 150         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 151         FEA_MAP(DS_GFXCLK),
 152         FEA_MAP(DS_SOCCLK),
 153         FEA_MAP(DS_LCLK),
 154         FEA_MAP(DS_FCLK),
 155         FEA_MAP(DS_UCLK),
 156         FEA_MAP(GFX_ULV),
 157         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 158         FEA_MAP(RSMU_SMN_CG),
 159         FEA_MAP(WAFL_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(APCC_PLUS),
 163         FEA_MAP(VR0HOT),
 164         FEA_MAP(VR1HOT),
 165         FEA_MAP(FW_CTF),
 166         FEA_MAP(FAN_CONTROL),
 167         FEA_MAP(THERMAL),
 168         FEA_MAP(OUT_OF_BAND_MONITOR),
 169         FEA_MAP(TEMP_DEPENDENT_VMIN),
 170 };
 171
 172 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 173         TAB_MAP(PPTABLE),
 174         TAB_MAP(AVFS),
 175         TAB_MAP(AVFS_PSM_DEBUG),
 176         TAB_MAP(AVFS_FUSE_OVERRIDE),
 177         TAB_MAP(PMSTATUSLOG),
 178         TAB_MAP(SMU_METRICS),
 179         TAB_MAP(DRIVER_SMU_CONFIG),
 180         TAB_MAP(OVERDRIVE),
 181         TAB_MAP(I2C_COMMANDS),
 182 };
 183
 184 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 185         PWR_MAP(AC),
 186         PWR_MAP(DC),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 191         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 195 };
 196
 197 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 198 {
 199         struct smu_11_0_cmn2aisc_mapping mapping;
 200
 201         if (index >= SMU_MSG_MAX_COUNT)
 202                 return -EINVAL;
 203
 204         mapping = arcturus_message_map[index];
 205         if (!(mapping.valid_mapping))
 206                 return -EINVAL;
 207
 208         return mapping.map_to;
 209 }
 210
 211 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 212 {
 213         struct smu_11_0_cmn2aisc_mapping mapping;
 214
 215         if (index >= SMU_CLK_COUNT)
 216                 return -EINVAL;
 217
 218         mapping = arcturus_clk_map[index];
 219         if (!(mapping.valid_mapping)) {
 220                 pr_warn("Unsupported SMU clk: %d\n", index);
 221                 return -EINVAL;
 222         }
 223
 224         return mapping.map_to;
 225 }
 226
 227 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 228 {
 229         struct smu_11_0_cmn2aisc_mapping mapping;
 230
 231         if (index >= SMU_FEATURE_COUNT)
 232                 return -EINVAL;
 233
 234         mapping = arcturus_feature_mask_map[index];
 235         if (!(mapping.valid_mapping)) {
 236                 return -EINVAL;
 237         }
 238
 239         return mapping.map_to;
 240 }
 241
 242 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 243 {
 244         struct smu_11_0_cmn2aisc_mapping mapping;
 245
 246         if (index >= SMU_TABLE_COUNT)
 247                 return -EINVAL;
 248
 249         mapping = arcturus_table_map[index];
 250         if (!(mapping.valid_mapping)) {
 251                 pr_warn("Unsupported SMU table: %d\n", index);
 252                 return -EINVAL;
 253         }
 254
 255         return mapping.map_to;
 256 }
 257
 258 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 259 {
 260         struct smu_11_0_cmn2aisc_mapping mapping;
 261
 262         if (index >= SMU_POWER_SOURCE_COUNT)
 263                 return -EINVAL;
 264
 265         mapping = arcturus_pwr_src_map[index];
 266         if (!(mapping.valid_mapping)) {
 267                 pr_warn("Unsupported SMU power source: %d\n", index);
 268                 return -EINVAL;
 269         }
 270
 271         return mapping.map_to;
 272 }
 273
 274
 275 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 280                 return -EINVAL;
 281
 282         mapping = arcturus_workload_map[profile];
 283         if (!(mapping.valid_mapping)) {
 284                 pr_warn("Unsupported SMU power source: %d\n", profile);
 285                 return -EINVAL;
 286         }
 287
 288         return mapping.map_to;
 289 }
 290
 291 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 292 {
 293         struct smu_table_context *smu_table = &smu->smu_table;
 294
 295         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 296                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 297
 298         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 299                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 300
 301         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 302                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 303
 304         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 305                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 306
 307         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 308         if (!smu_table->metrics_table)
 309                 return -ENOMEM;
 310         smu_table->metrics_time = 0;
 311
 312         return 0;
 313 }
 314
 315 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 316 {
 317         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 318
 319         if (smu_dpm->dpm_context)
 320                 return -EINVAL;
 321
 322         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 323                                        GFP_KERNEL);
 324         if (!smu_dpm->dpm_context)
 325                 return -ENOMEM;
 326
 327         if (smu_dpm->golden_dpm_context)
 328                 return -EINVAL;
 329
 330         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 331                                               GFP_KERNEL);
 332         if (!smu_dpm->golden_dpm_context)
 333                 return -ENOMEM;
 334
 335         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 336
 337         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 338                                        GFP_KERNEL);
 339         if (!smu_dpm->dpm_current_power_state)
 340                 return -ENOMEM;
 341
 342         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 343                                        GFP_KERNEL);
 344         if (!smu_dpm->dpm_request_power_state)
 345                 return -ENOMEM;
 346
 347         return 0;
 348 }
 349
 350 static int
 351 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 352                                   uint32_t *feature_mask, uint32_t num)
 353 {
 354         if (num > 2)
 355                 return -EINVAL;
 356
 357         /* pptable will handle the features to enable */
 358         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 359
 360         return 0;
 361 }
 362
 363 static int
 364 arcturus_set_single_dpm_table(struct smu_context *smu,
 365                             struct arcturus_single_dpm_table *single_dpm_table,
 366                             PPCLK_e clk_id)
 367 {
 368         int ret = 0;
 369         uint32_t i, num_of_levels = 0, clk;
 370
 371         ret = smu_send_smc_msg_with_param(smu,
 372                         SMU_MSG_GetDpmFreqByIndex,
 373                         (clk_id << 16 | 0xFF));
 374         if (ret) {
 375                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 376                 return ret;
 377         }
 378
 379         smu_read_smc_arg(smu, &num_of_levels);
 380         if (!num_of_levels) {
 381                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 382                 return -EINVAL;
 383         }
 384
 385         single_dpm_table->count = num_of_levels;
 386         for (i = 0; i < num_of_levels; i++) {
 387                 ret = smu_send_smc_msg_with_param(smu,
 388                                 SMU_MSG_GetDpmFreqByIndex,
 389                                 (clk_id << 16 | i));
 390                 if (ret) {
 391                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 392                         return ret;
 393                 }
 394                 smu_read_smc_arg(smu, &clk);
 395                 if (!clk) {
 396                         pr_err("[%s] clk value is invalid!\n", __func__);
 397                         return -EINVAL;
 398                 }
 399                 single_dpm_table->dpm_levels[i].value = clk;
 400                 single_dpm_table->dpm_levels[i].enabled = true;
 401         }
 402         return 0;
 403 }
 404
 405 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 406 {
 407         dpm_state->soft_min_level = 0x0;
 408         dpm_state->soft_max_level = 0xffff;
 409         dpm_state->hard_min_level = 0x0;
 410         dpm_state->hard_max_level = 0xffff;
 411 }
 412
 413 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 414 {
 415         int ret;
 416
 417         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 418         struct arcturus_dpm_table *dpm_table = NULL;
 419         struct arcturus_single_dpm_table *single_dpm_table;
 420
 421         dpm_table = smu_dpm->dpm_context;
 422
 423         /* socclk */
 424         single_dpm_table = &(dpm_table->soc_table);
 425         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 426                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 427                                                   PPCLK_SOCCLK);
 428                 if (ret) {
 429                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 430                         return ret;
 431                 }
 432         } else {
 433                 single_dpm_table->count = 1;
 434                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 435         }
 436         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 437
 438         /* gfxclk */
 439         single_dpm_table = &(dpm_table->gfx_table);
 440         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 441                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 442                                                   PPCLK_GFXCLK);
 443                 if (ret) {
 444                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 445                         return ret;
 446                 }
 447         } else {
 448                 single_dpm_table->count = 1;
 449                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 450         }
 451         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 452
 453         /* memclk */
 454         single_dpm_table = &(dpm_table->mem_table);
 455         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 456                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 457                                                   PPCLK_UCLK);
 458                 if (ret) {
 459                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 460                         return ret;
 461                 }
 462         } else {
 463                 single_dpm_table->count = 1;
 464                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 465         }
 466         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 467
 468         /* fclk */
 469         single_dpm_table = &(dpm_table->fclk_table);
 470         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 471                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 472                                                   PPCLK_FCLK);
 473                 if (ret) {
 474                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 475                         return ret;
 476                 }
 477         } else {
 478                 single_dpm_table->count = 1;
 479                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 480         }
 481         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 482
 483         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 484                sizeof(struct arcturus_dpm_table));
 485
 486         return 0;
 487 }
 488
 489 static int arcturus_check_powerplay_table(struct smu_context *smu)
 490 {
 491         return 0;
 492 }
 493
 494 static int arcturus_store_powerplay_table(struct smu_context *smu)
 495 {
 496         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 497         struct smu_table_context *table_context = &smu->smu_table;
 498         int ret = 0;
 499
 500         if (!table_context->power_play_table)
 501                 return -EINVAL;
 502
 503         powerplay_table = table_context->power_play_table;
 504
 505         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 506                sizeof(PPTable_t));
 507
 508         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 509
 510         return ret;
 511 }
 512
 513 static int arcturus_append_powerplay_table(struct smu_context *smu)
 514 {
 515         struct smu_table_context *table_context = &smu->smu_table;
 516         PPTable_t *smc_pptable = table_context->driver_pptable;
 517         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 518         int index, ret;
 519
 520         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 521                                            smc_dpm_info);
 522
 523         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 524                                       (uint8_t **)&smc_dpm_table);
 525         if (ret)
 526                 return ret;
 527
 528         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 529                         smc_dpm_table->table_header.format_revision,
 530                         smc_dpm_table->table_header.content_revision);
 531
 532         if ((smc_dpm_table->table_header.format_revision == 4) &&
 533             (smc_dpm_table->table_header.content_revision == 6))
 534                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 535                        &smc_dpm_table->maxvoltagestepgfx,
 536                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 537
 538         return 0;
 539 }
 540
 541 static int arcturus_run_btc(struct smu_context *smu)
 542 {
 543         int ret = 0;
 544
 545         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 546         if (ret) {
 547                 pr_err("RunAfllBtc failed!\n");
 548                 return ret;
 549         }
 550
 551         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
 552 }
 553
 554 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 555 {
 556         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 557         struct arcturus_dpm_table *dpm_table = NULL;
 558         struct arcturus_single_dpm_table *gfx_table = NULL;
 559         struct arcturus_single_dpm_table *mem_table = NULL;
 560
 561         dpm_table = smu_dpm->dpm_context;
 562         gfx_table = &(dpm_table->gfx_table);
 563         mem_table = &(dpm_table->mem_table);
 564
 565         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 566         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 567
 568         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 569             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 570                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 571                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 572         }
 573
 574         smu->pstate_sclk = smu->pstate_sclk * 100;
 575         smu->pstate_mclk = smu->pstate_mclk * 100;
 576
 577         return 0;
 578 }
 579
 580 static int arcturus_get_clk_table(struct smu_context *smu,
 581                         struct pp_clock_levels_with_latency *clocks,
 582                         struct arcturus_single_dpm_table *dpm_table)
 583 {
 584         int i, count;
 585
 586         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 587         clocks->num_levels = count;
 588
 589         for (i = 0; i < count; i++) {
 590                 clocks->data[i].clocks_in_khz =
 591                         dpm_table->dpm_levels[i].value * 1000;
 592                 clocks->data[i].latency_in_us = 0;
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int arcturus_freqs_in_same_level(int32_t frequency1,
 599                                         int32_t frequency2)
 600 {
 601         return (abs(frequency1 - frequency2) <= EPSILON);
 602 }
 603
 604 static int arcturus_print_clk_levels(struct smu_context *smu,
 605                         enum smu_clk_type type, char *buf)
 606 {
 607         int i, now, size = 0;
 608         int ret = 0;
 609         struct pp_clock_levels_with_latency clocks;
 610         struct arcturus_single_dpm_table *single_dpm_table;
 611         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 612         struct arcturus_dpm_table *dpm_table = NULL;
 613
 614         dpm_table = smu_dpm->dpm_context;
 615
 616         switch (type) {
 617         case SMU_SCLK:
 618                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 619                 if (ret) {
 620                         pr_err("Attempt to get current gfx clk Failed!");
 621                         return ret;
 622                 }
 623
 624                 single_dpm_table = &(dpm_table->gfx_table);
 625                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 626                 if (ret) {
 627                         pr_err("Attempt to get gfx clk levels Failed!");
 628                         return ret;
 629                 }
 630
 631                 /*
 632                  * For DPM disabled case, there will be only one clock level.
 633                  * And it's safe to assume that is always the current clock.
 634                  */
 635                 for (i = 0; i < clocks.num_levels; i++)
 636                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 637                                         clocks.data[i].clocks_in_khz / 1000,
 638                                         (clocks.num_levels == 1) ? "*" :
 639                                         (arcturus_freqs_in_same_level(
 640                                         clocks.data[i].clocks_in_khz / 1000,
 641                                         now / 100) ? "*" : ""));
 642                 break;
 643
 644         case SMU_MCLK:
 645                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 646                 if (ret) {
 647                         pr_err("Attempt to get current mclk Failed!");
 648                         return ret;
 649                 }
 650
 651                 single_dpm_table = &(dpm_table->mem_table);
 652                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 653                 if (ret) {
 654                         pr_err("Attempt to get memory clk levels Failed!");
 655                         return ret;
 656                 }
 657
 658                 for (i = 0; i < clocks.num_levels; i++)
 659                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 660                                 i, clocks.data[i].clocks_in_khz / 1000,
 661                                 (clocks.num_levels == 1) ? "*" :
 662                                 (arcturus_freqs_in_same_level(
 663                                 clocks.data[i].clocks_in_khz / 1000,
 664                                 now / 100) ? "*" : ""));
 665                 break;
 666
 667         case SMU_SOCCLK:
 668                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 669                 if (ret) {
 670                         pr_err("Attempt to get current socclk Failed!");
 671                         return ret;
 672                 }
 673
 674                 single_dpm_table = &(dpm_table->soc_table);
 675                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 676                 if (ret) {
 677                         pr_err("Attempt to get socclk levels Failed!");
 678                         return ret;
 679                 }
 680
 681                 for (i = 0; i < clocks.num_levels; i++)
 682                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 683                                 i, clocks.data[i].clocks_in_khz / 1000,
 684                                 (clocks.num_levels == 1) ? "*" :
 685                                 (arcturus_freqs_in_same_level(
 686                                 clocks.data[i].clocks_in_khz / 1000,
 687                                 now / 100) ? "*" : ""));
 688                 break;
 689
 690         case SMU_FCLK:
 691                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 692                 if (ret) {
 693                         pr_err("Attempt to get current fclk Failed!");
 694                         return ret;
 695                 }
 696
 697                 single_dpm_table = &(dpm_table->fclk_table);
 698                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 699                 if (ret) {
 700                         pr_err("Attempt to get fclk levels Failed!");
 701                         return ret;
 702                 }
 703
 704                 for (i = 0; i < single_dpm_table->count; i++)
 705                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 706                                 i, single_dpm_table->dpm_levels[i].value,
 707                                 (clocks.num_levels == 1) ? "*" :
 708                                 (arcturus_freqs_in_same_level(
 709                                 clocks.data[i].clocks_in_khz / 1000,
 710                                 now / 100) ? "*" : ""));
 711                 break;
 712
 713         default:
 714                 break;
 715         }
 716
 717         return size;
 718 }
 719
 720 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 721                                      uint32_t feature_mask)
 722 {
 723         struct arcturus_single_dpm_table *single_dpm_table;
 724         struct arcturus_dpm_table *dpm_table =
 725                         smu->smu_dpm.dpm_context;
 726         uint32_t freq;
 727         int ret = 0;
 728
 729         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 730             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 731                 single_dpm_table = &(dpm_table->gfx_table);
 732                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 733                         single_dpm_table->dpm_state.soft_min_level;
 734                 ret = smu_send_smc_msg_with_param(smu,
 735                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 736                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 737                 if (ret) {
 738                         pr_err("Failed to set soft %s gfxclk !\n",
 739                                                 max ? "max" : "min");
 740                         return ret;
 741                 }
 742         }
 743
 744         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 745             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 746                 single_dpm_table = &(dpm_table->mem_table);
 747                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 748                         single_dpm_table->dpm_state.soft_min_level;
 749                 ret = smu_send_smc_msg_with_param(smu,
 750                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 751                         (PPCLK_UCLK << 16) | (freq & 0xffff));
 752                 if (ret) {
 753                         pr_err("Failed to set soft %s memclk !\n",
 754                                                 max ? "max" : "min");
 755                         return ret;
 756                 }
 757         }
 758
 759         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 760             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 761                 single_dpm_table = &(dpm_table->soc_table);
 762                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 763                         single_dpm_table->dpm_state.soft_min_level;
 764                 ret = smu_send_smc_msg_with_param(smu,
 765                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 766                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
 767                 if (ret) {
 768                         pr_err("Failed to set soft %s socclk !\n",
 769                                                 max ? "max" : "min");
 770                         return ret;
 771                 }
 772         }
 773
 774         return ret;
 775 }
 776
 777 static int arcturus_force_clk_levels(struct smu_context *smu,
 778                         enum smu_clk_type type, uint32_t mask)
 779 {
 780         struct arcturus_dpm_table *dpm_table;
 781         struct arcturus_single_dpm_table *single_dpm_table;
 782         uint32_t soft_min_level, soft_max_level;
 783         int ret = 0;
 784
 785         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 786         soft_max_level = mask ? (fls(mask) - 1) : 0;
 787
 788         dpm_table = smu->smu_dpm.dpm_context;
 789
 790         switch (type) {
 791         case SMU_SCLK:
 792                 single_dpm_table = &(dpm_table->gfx_table);
 793
 794                 if (soft_max_level >= single_dpm_table->count) {
 795                         pr_err("Clock level specified %d is over max allowed %d\n",
 796                                         soft_max_level, single_dpm_table->count - 1);
 797                         ret = -EINVAL;
 798                         break;
 799                 }
 800
 801                 single_dpm_table->dpm_state.soft_min_level =
 802                         single_dpm_table->dpm_levels[soft_min_level].value;
 803                 single_dpm_table->dpm_state.soft_max_level =
 804                         single_dpm_table->dpm_levels[soft_max_level].value;
 805
 806                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 807                 if (ret) {
 808                         pr_err("Failed to upload boot level to lowest!\n");
 809                         break;
 810                 }
 811
 812                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 813                 if (ret)
 814                         pr_err("Failed to upload dpm max level to highest!\n");
 815
 816                 break;
 817
 818         case SMU_MCLK:
 819         case SMU_SOCCLK:
 820         case SMU_FCLK:
 821                 /*
 822                  * Should not arrive here since Arcturus does not
 823                  * support mclk/socclk/fclk softmin/softmax settings
 824                  */
 825                 ret = -EINVAL;
 826                 break;
 827
 828         default:
 829                 break;
 830         }
 831
 832         return ret;
 833 }
 834
 835 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 836                                                 struct smu_temperature_range *range)
 837 {
 838         PPTable_t *pptable = smu->smu_table.driver_pptable;
 839
 840         if (!range)
 841                 return -EINVAL;
 842
 843         range->max = pptable->TedgeLimit *
 844                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 845         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 846                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 847         range->hotspot_crit_max = pptable->ThotspotLimit *
 848                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 849         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 850                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 851         range->mem_crit_max = pptable->TmemLimit *
 852                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 853         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 854                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 855
 856         return 0;
 857 }
 858
 859 static int arcturus_get_metrics_table(struct smu_context *smu,
 860                                       SmuMetrics_t *metrics_table)
 861 {
 862         struct smu_table_context *smu_table= &smu->smu_table;
 863         int ret = 0;
 864
 865         if (!smu_table->metrics_time ||
 866              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 867                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 868                                 (void *)smu_table->metrics_table, false);
 869                 if (ret) {
 870                         pr_info("Failed to export SMU metrics table!\n");
 871                         return ret;
 872                 }
 873                 smu_table->metrics_time = jiffies;
 874         }
 875
 876         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 877
 878         return ret;
 879 }
 880
 881 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 882                                                  enum amd_pp_sensors sensor,
 883                                                  uint32_t *value)
 884 {
 885         SmuMetrics_t metrics;
 886         int ret = 0;
 887
 888         if (!value)
 889                 return -EINVAL;
 890
 891         ret = arcturus_get_metrics_table(smu, &metrics);
 892         if (ret)
 893                 return ret;
 894
 895         switch (sensor) {
 896         case AMDGPU_PP_SENSOR_GPU_LOAD:
 897                 *value = metrics.AverageGfxActivity;
 898                 break;
 899         case AMDGPU_PP_SENSOR_MEM_LOAD:
 900                 *value = metrics.AverageUclkActivity;
 901                 break;
 902         default:
 903                 pr_err("Invalid sensor for retrieving clock activity\n");
 904                 return -EINVAL;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 911 {
 912         SmuMetrics_t metrics;
 913         int ret = 0;
 914
 915         if (!value)
 916                 return -EINVAL;
 917
 918         ret = arcturus_get_metrics_table(smu, &metrics);
 919         if (ret)
 920                 return ret;
 921
 922         *value = metrics.AverageSocketPower << 8;
 923
 924         return 0;
 925 }
 926
 927 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 928                                             enum amd_pp_sensors sensor,
 929                                             uint32_t *value)
 930 {
 931         SmuMetrics_t metrics;
 932         int ret = 0;
 933
 934         if (!value)
 935                 return -EINVAL;
 936
 937         ret = arcturus_get_metrics_table(smu, &metrics);
 938         if (ret)
 939                 return ret;
 940
 941         switch (sensor) {
 942         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 943                 *value = metrics.TemperatureHotspot *
 944                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 945                 break;
 946         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 947                 *value = metrics.TemperatureEdge *
 948                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 949                 break;
 950         case AMDGPU_PP_SENSOR_MEM_TEMP:
 951                 *value = metrics.TemperatureHBM *
 952                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 953                 break;
 954         default:
 955                 pr_err("Invalid sensor for retrieving temp\n");
 956                 return -EINVAL;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int arcturus_read_sensor(struct smu_context *smu,
 963                                 enum amd_pp_sensors sensor,
 964                                 void *data, uint32_t *size)
 965 {
 966         struct smu_table_context *table_context = &smu->smu_table;
 967         PPTable_t *pptable = table_context->driver_pptable;
 968         int ret = 0;
 969
 970         if (!data || !size)
 971                 return -EINVAL;
 972
 973         mutex_lock(&smu->sensor_lock);
 974         switch (sensor) {
 975         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 976                 *(uint32_t *)data = pptable->FanMaximumRpm;
 977                 *size = 4;
 978                 break;
 979         case AMDGPU_PP_SENSOR_MEM_LOAD:
 980         case AMDGPU_PP_SENSOR_GPU_LOAD:
 981                 ret = arcturus_get_current_activity_percent(smu,
 982                                                             sensor,
 983                                                 (uint32_t *)data);
 984                 *size = 4;
 985                 break;
 986         case AMDGPU_PP_SENSOR_GPU_POWER:
 987                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
 988                 *size = 4;
 989                 break;
 990         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 991         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 992         case AMDGPU_PP_SENSOR_MEM_TEMP:
 993                 ret = arcturus_thermal_get_temperature(smu, sensor,
 994                                                 (uint32_t *)data);
 995                 *size = 4;
 996                 break;
 997         default:
 998                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
 999         }
1000         mutex_unlock(&smu->sensor_lock);
1001
1002         return ret;
1003 }
1004
1005 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1006                                       uint32_t *speed)
1007 {
1008         SmuMetrics_t metrics;
1009         int ret = 0;
1010
1011         if (!speed)
1012                 return -EINVAL;
1013
1014         ret = arcturus_get_metrics_table(smu, &metrics);
1015         if (ret)
1016                 return ret;
1017
1018         *speed = metrics.CurrFanSpeed;
1019
1020         return ret;
1021 }
1022
1023 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1024                                           uint32_t *speed)
1025 {
1026         PPTable_t *pptable = smu->smu_table.driver_pptable;
1027         uint32_t percent, current_rpm;
1028         int ret = 0;
1029
1030         if (!speed)
1031                 return -EINVAL;
1032
1033         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1034         if (ret)
1035                 return ret;
1036
1037         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1038         *speed = percent > 100 ? 100 : percent;
1039
1040         return ret;
1041 }
1042
1043 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1044                                        enum smu_clk_type clk_type,
1045                                        uint32_t *value)
1046 {
1047         static SmuMetrics_t metrics;
1048         int ret = 0, clk_id = 0;
1049
1050         if (!value)
1051                 return -EINVAL;
1052
1053         clk_id = smu_clk_get_index(smu, clk_type);
1054         if (clk_id < 0)
1055                 return -EINVAL;
1056
1057         ret = arcturus_get_metrics_table(smu, &metrics);
1058         if (ret)
1059                 return ret;
1060
1061         switch (clk_id) {
1062         case PPCLK_GFXCLK:
1063                 /*
1064                  * CurrClock[clk_id] can provide accurate
1065                  *   output only when the dpm feature is enabled.
1066                  * We can use Average_* for dpm disabled case.
1067                  *   But this is available for gfxclk/uclk/socclk.
1068                  */
1069                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1070                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1071                 else
1072                         *value = metrics.AverageGfxclkFrequency;
1073                 break;
1074         case PPCLK_UCLK:
1075                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1076                         *value = metrics.CurrClock[PPCLK_UCLK];
1077                 else
1078                         *value = metrics.AverageUclkFrequency;
1079                 break;
1080         case PPCLK_SOCCLK:
1081                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1082                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1083                 else
1084                         *value = metrics.AverageSocclkFrequency;
1085                 break;
1086         default:
1087                 *value = metrics.CurrClock[clk_id];
1088                 break;
1089         }
1090
1091         return ret;
1092 }
1093
1094 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1095 {
1096         uint32_t i;
1097
1098         for (i = 0; i < table->count; i++) {
1099                 if (table->dpm_levels[i].enabled)
1100                         break;
1101         }
1102         if (i >= table->count) {
1103                 i = 0;
1104                 table->dpm_levels[i].enabled = true;
1105         }
1106
1107         return i;
1108 }
1109
1110 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1111 {
1112         int i = 0;
1113
1114         if (table->count <= 0) {
1115                 pr_err("[%s] DPM Table has no entry!", __func__);
1116                 return 0;
1117         }
1118         if (table->count > MAX_DPM_NUMBER) {
1119                 pr_err("[%s] DPM Table has too many entries!", __func__);
1120                 return MAX_DPM_NUMBER - 1;
1121         }
1122
1123         for (i = table->count - 1; i >= 0; i--) {
1124                 if (table->dpm_levels[i].enabled)
1125                         break;
1126         }
1127         if (i < 0) {
1128                 i = 0;
1129                 table->dpm_levels[i].enabled = true;
1130         }
1131
1132         return i;
1133 }
1134
1135
1136
1137 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1138 {
1139         struct arcturus_dpm_table *dpm_table =
1140                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1141         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1142         uint32_t soft_level;
1143         int ret = 0;
1144
1145         /* gfxclk */
1146         if (highest)
1147                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1148         else
1149                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1150
1151         dpm_table->gfx_table.dpm_state.soft_min_level =
1152                 dpm_table->gfx_table.dpm_state.soft_max_level =
1153                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1154
1155         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1156         if (ret) {
1157                 pr_err("Failed to upload boot level to %s!\n",
1158                                 highest ? "highest" : "lowest");
1159                 return ret;
1160         }
1161
1162         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1163         if (ret) {
1164                 pr_err("Failed to upload dpm max level to %s!\n!",
1165                                 highest ? "highest" : "lowest");
1166                 return ret;
1167         }
1168
1169         if (hive)
1170                 /*
1171                  * Force XGMI Pstate to highest or lowest
1172                  * TODO: revise this when xgmi dpm is functional
1173                  */
1174                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1175
1176         return ret;
1177 }
1178
1179 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1180 {
1181         struct arcturus_dpm_table *dpm_table =
1182                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1183         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1184         uint32_t soft_min_level, soft_max_level;
1185         int ret = 0;
1186
1187         /* gfxclk */
1188         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1189         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1190         dpm_table->gfx_table.dpm_state.soft_min_level =
1191                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1192         dpm_table->gfx_table.dpm_state.soft_max_level =
1193                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1194
1195         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1196         if (ret) {
1197                 pr_err("Failed to upload DPM Bootup Levels!");
1198                 return ret;
1199         }
1200
1201         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1202         if (ret) {
1203                 pr_err("Failed to upload DPM Max Levels!");
1204                 return ret;
1205         }
1206
1207         if (hive)
1208                 /*
1209                  * Reset XGMI Pstate back to default
1210                  * TODO: revise this when xgmi dpm is functional
1211                  */
1212                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1213
1214         return ret;
1215 }
1216
1217 static int
1218 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1219                                 enum amd_dpm_forced_level level,
1220                                 uint32_t *sclk_mask,
1221                                 uint32_t *mclk_mask,
1222                                 uint32_t *soc_mask)
1223 {
1224         struct arcturus_dpm_table *dpm_table =
1225                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1226         struct arcturus_single_dpm_table *gfx_dpm_table;
1227         struct arcturus_single_dpm_table *mem_dpm_table;
1228         struct arcturus_single_dpm_table *soc_dpm_table;
1229
1230         if (!smu->smu_dpm.dpm_context)
1231                 return -EINVAL;
1232
1233         gfx_dpm_table = &dpm_table->gfx_table;
1234         mem_dpm_table = &dpm_table->mem_table;
1235         soc_dpm_table = &dpm_table->soc_table;
1236
1237         *sclk_mask = 0;
1238         *mclk_mask = 0;
1239         *soc_mask  = 0;
1240
1241         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1242             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1243             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1244                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1245                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1246                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1247         }
1248
1249         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1250                 *sclk_mask = 0;
1251         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1252                 *mclk_mask = 0;
1253         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1254                 *sclk_mask = gfx_dpm_table->count - 1;
1255                 *mclk_mask = mem_dpm_table->count - 1;
1256                 *soc_mask  = soc_dpm_table->count - 1;
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int arcturus_get_power_limit(struct smu_context *smu,
1263                                      uint32_t *limit,
1264                                      bool cap)
1265 {
1266         PPTable_t *pptable = smu->smu_table.driver_pptable;
1267         uint32_t asic_default_power_limit = 0;
1268         int ret = 0;
1269         int power_src;
1270
1271         if (!smu->power_limit) {
1272                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1273                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1274                         if (power_src < 0)
1275                                 return -EINVAL;
1276
1277                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1278                                 power_src << 16);
1279                         if (ret) {
1280                                 pr_err("[%s] get PPT limit failed!", __func__);
1281                                 return ret;
1282                         }
1283                         smu_read_smc_arg(smu, &asic_default_power_limit);
1284                 } else {
1285                         /* the last hope to figure out the ppt limit */
1286                         if (!pptable) {
1287                                 pr_err("Cannot get PPT limit due to pptable missing!");
1288                                 return -EINVAL;
1289                         }
1290                         asic_default_power_limit =
1291                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1292                 }
1293
1294                 smu->power_limit = asic_default_power_limit;
1295         }
1296
1297         if (cap)
1298                 *limit = smu_v11_0_get_max_power_limit(smu);
1299         else
1300                 *limit = smu->power_limit;
1301
1302         return 0;
1303 }
1304
1305 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1306                                            char *buf)
1307 {
1308         static const char *profile_name[] = {
1309                                         "BOOTUP_DEFAULT",
1310                                         "3D_FULL_SCREEN",
1311                                         "POWER_SAVING",
1312                                         "VIDEO",
1313                                         "VR",
1314                                         "COMPUTE",
1315                                         "CUSTOM"};
1316         uint32_t i, size = 0;
1317         int16_t workload_type = 0;
1318
1319         if (!smu->pm_enabled || !buf)
1320                 return -EINVAL;
1321
1322         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1323                 /*
1324                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1325                  * Not all profile modes are supported on arcturus.
1326                  */
1327                 workload_type = smu_workload_get_type(smu, i);
1328                 if (workload_type < 0)
1329                         continue;
1330
1331                 size += sprintf(buf + size, "%2d %14s%s\n",
1332                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1333         }
1334
1335         return size;
1336 }
1337
1338 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1339                                            long *input,
1340                                            uint32_t size)
1341 {
1342         int workload_type = 0;
1343         uint32_t profile_mode = input[size];
1344         int ret = 0;
1345
1346         if (!smu->pm_enabled)
1347                 return -EINVAL;
1348
1349         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1350                 pr_err("Invalid power profile mode %d\n", profile_mode);
1351                 return -EINVAL;
1352         }
1353
1354         /*
1355          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1356          * Not all profile modes are supported on arcturus.
1357          */
1358         workload_type = smu_workload_get_type(smu, profile_mode);
1359         if (workload_type < 0) {
1360                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1361                 return -EINVAL;
1362         }
1363
1364         ret = smu_send_smc_msg_with_param(smu,
1365                                           SMU_MSG_SetWorkloadMask,
1366                                           1 << workload_type);
1367         if (ret) {
1368                 pr_err("Fail to set workload type %d\n", workload_type);
1369                 return ret;
1370         }
1371
1372         smu->power_profile_mode = profile_mode;
1373
1374         return 0;
1375 }
1376
1377 static void arcturus_dump_pptable(struct smu_context *smu)
1378 {
1379         struct smu_table_context *table_context = &smu->smu_table;
1380         PPTable_t *pptable = table_context->driver_pptable;
1381         int i;
1382
1383         pr_info("Dumped PPTable:\n");
1384
1385         pr_info("Version = 0x%08x\n", pptable->Version);
1386
1387         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1388         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1389
1390         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1391                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1392                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1393         }
1394
1395         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1396         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1397         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1398         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1399
1400         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1401         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1402         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1403         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1404         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1405         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1406         pr_info("FitLimit = %d\n", pptable->FitLimit);
1407
1408         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1409         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1410
1411         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1412
1413         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1414         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1415
1416         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1417         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1418         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1419         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1420
1421         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1422         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1423         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1424         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1425
1426         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1427         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1428
1429         pr_info("[PPCLK_GFXCLK]\n"
1430                         "  .VoltageMode          = 0x%02x\n"
1431                         "  .SnapToDiscrete       = 0x%02x\n"
1432                         "  .NumDiscreteLevels    = 0x%02x\n"
1433                         "  .padding              = 0x%02x\n"
1434                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1435                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1436                         "  .SsFmin               = 0x%04x\n"
1437                         "  .Padding_16           = 0x%04x\n",
1438                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1439                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1440                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1441                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1442                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1443                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1444                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1445                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1446                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1447                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1448                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1449
1450         pr_info("[PPCLK_VCLK]\n"
1451                         "  .VoltageMode          = 0x%02x\n"
1452                         "  .SnapToDiscrete       = 0x%02x\n"
1453                         "  .NumDiscreteLevels    = 0x%02x\n"
1454                         "  .padding              = 0x%02x\n"
1455                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1456                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1457                         "  .SsFmin               = 0x%04x\n"
1458                         "  .Padding_16           = 0x%04x\n",
1459                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1460                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1461                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1462                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1463                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1464                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1465                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1466                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1467                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1468                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1469                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1470
1471         pr_info("[PPCLK_DCLK]\n"
1472                         "  .VoltageMode          = 0x%02x\n"
1473                         "  .SnapToDiscrete       = 0x%02x\n"
1474                         "  .NumDiscreteLevels    = 0x%02x\n"
1475                         "  .padding              = 0x%02x\n"
1476                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1477                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1478                         "  .SsFmin               = 0x%04x\n"
1479                         "  .Padding_16           = 0x%04x\n",
1480                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1481                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1482                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1483                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1484                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1485                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1486                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1487                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1488                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1489                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1490                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1491
1492         pr_info("[PPCLK_SOCCLK]\n"
1493                         "  .VoltageMode          = 0x%02x\n"
1494                         "  .SnapToDiscrete       = 0x%02x\n"
1495                         "  .NumDiscreteLevels    = 0x%02x\n"
1496                         "  .padding              = 0x%02x\n"
1497                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1498                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1499                         "  .SsFmin               = 0x%04x\n"
1500                         "  .Padding_16           = 0x%04x\n",
1501                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1502                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1503                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1504                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1505                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1506                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1507                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1508                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1509                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1510                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1511                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1512
1513         pr_info("[PPCLK_UCLK]\n"
1514                         "  .VoltageMode          = 0x%02x\n"
1515                         "  .SnapToDiscrete       = 0x%02x\n"
1516                         "  .NumDiscreteLevels    = 0x%02x\n"
1517                         "  .padding              = 0x%02x\n"
1518                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1519                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1520                         "  .SsFmin               = 0x%04x\n"
1521                         "  .Padding_16           = 0x%04x\n",
1522                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1523                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1524                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1525                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1526                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1527                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1528                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1529                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1530                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1531                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1532                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1533
1534         pr_info("[PPCLK_FCLK]\n"
1535                         "  .VoltageMode          = 0x%02x\n"
1536                         "  .SnapToDiscrete       = 0x%02x\n"
1537                         "  .NumDiscreteLevels    = 0x%02x\n"
1538                         "  .padding              = 0x%02x\n"
1539                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1540                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1541                         "  .SsFmin               = 0x%04x\n"
1542                         "  .Padding_16           = 0x%04x\n",
1543                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1544                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1545                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1546                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1547                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1548                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1549                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1550                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1551                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1552                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1553                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1554
1555
1556         pr_info("FreqTableGfx\n");
1557         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1558                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1559
1560         pr_info("FreqTableVclk\n");
1561         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1562                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1563
1564         pr_info("FreqTableDclk\n");
1565         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1566                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1567
1568         pr_info("FreqTableSocclk\n");
1569         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1570                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1571
1572         pr_info("FreqTableUclk\n");
1573         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1574                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1575
1576         pr_info("FreqTableFclk\n");
1577         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1578                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1579
1580         pr_info("Mp0clkFreq\n");
1581         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1582                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1583
1584         pr_info("Mp0DpmVoltage\n");
1585         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1586                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1587
1588         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1589         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1590         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1591         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1592         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1593         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1594         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1595         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1596         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1597
1598         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1599         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1600         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1601         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1602
1603         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1604         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1605
1606         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1607         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1608         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1609         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1610         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1611         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1612
1613         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1614         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1615         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1616         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1617         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1618         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1619         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1620         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1621         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1622
1623         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1624         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1625         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1626         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1627
1628         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1629         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1630         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1631         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1632
1633         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1634                         pptable->dBtcGbGfxPll.a,
1635                         pptable->dBtcGbGfxPll.b,
1636                         pptable->dBtcGbGfxPll.c);
1637         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1638                         pptable->dBtcGbGfxAfll.a,
1639                         pptable->dBtcGbGfxAfll.b,
1640                         pptable->dBtcGbGfxAfll.c);
1641         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1642                         pptable->dBtcGbSoc.a,
1643                         pptable->dBtcGbSoc.b,
1644                         pptable->dBtcGbSoc.c);
1645
1646         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1647                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1648                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1649         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1650                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1651                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1652
1653         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1654                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1655                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1656                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1657         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1658                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1659                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1660                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1661
1662         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1663         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1664
1665         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1666         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1667         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1668         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1669
1670         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1671         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1672         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1673         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1674
1675         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1676         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1677
1678         pr_info("XgmiDpmPstates\n");
1679         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1680                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1681         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1682         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1683
1684         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1685         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1686         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1687         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1688         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1689         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1690         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1691         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1692
1693         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1694         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1695                         pptable->ReservedEquation0.a,
1696                         pptable->ReservedEquation0.b,
1697                         pptable->ReservedEquation0.c);
1698         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1699                         pptable->ReservedEquation1.a,
1700                         pptable->ReservedEquation1.b,
1701                         pptable->ReservedEquation1.c);
1702         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1703                         pptable->ReservedEquation2.a,
1704                         pptable->ReservedEquation2.b,
1705                         pptable->ReservedEquation2.c);
1706         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1707                         pptable->ReservedEquation3.a,
1708                         pptable->ReservedEquation3.b,
1709                         pptable->ReservedEquation3.c);
1710
1711         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1712         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1713
1714         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1715         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1716         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1717
1718         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1719         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1720
1721         pr_info("Board Parameters:\n");
1722         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1723         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1724
1725         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1726         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1727         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1728         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1729
1730         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1731         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1732
1733         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1734         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1735         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1736
1737         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1738         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1739         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1740
1741         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1742         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1743         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1744
1745         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1746         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1747         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1748
1749         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1750         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1751         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1752         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1753
1754         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1755         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1756         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1757
1758         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1759         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1760         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1761
1762         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1763         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1764         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1765
1766         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1767         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1768         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1769
1770         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1771                 pr_info("I2cControllers[%d]:\n", i);
1772                 pr_info("                   .Enabled = %d\n",
1773                                 pptable->I2cControllers[i].Enabled);
1774                 pr_info("                   .SlaveAddress = 0x%x\n",
1775                                 pptable->I2cControllers[i].SlaveAddress);
1776                 pr_info("                   .ControllerPort = %d\n",
1777                                 pptable->I2cControllers[i].ControllerPort);
1778                 pr_info("                   .ControllerName = %d\n",
1779                                 pptable->I2cControllers[i].ControllerName);
1780                 pr_info("                   .ThermalThrottler = %d\n",
1781                                 pptable->I2cControllers[i].ThermalThrotter);
1782                 pr_info("                   .I2cProtocol = %d\n",
1783                                 pptable->I2cControllers[i].I2cProtocol);
1784                 pr_info("                   .Speed = %d\n",
1785                                 pptable->I2cControllers[i].Speed);
1786         }
1787
1788         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1789         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1790
1791         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1792
1793         pr_info("XgmiLinkSpeed\n");
1794         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1795                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1796         pr_info("XgmiLinkWidth\n");
1797         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1798                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1799         pr_info("XgmiFclkFreq\n");
1800         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1801                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1802         pr_info("XgmiSocVoltage\n");
1803         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1804                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1805
1806 }
1807
1808 static bool arcturus_is_dpm_running(struct smu_context *smu)
1809 {
1810         int ret = 0;
1811         uint32_t feature_mask[2];
1812         unsigned long feature_enabled;
1813         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1814         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1815                            ((uint64_t)feature_mask[1] << 32));
1816         return !!(feature_enabled & SMC_DPM_FEATURE);
1817 }
1818
1819 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1820 {
1821         struct smu_power_context *smu_power = &smu->smu_power;
1822         struct smu_power_gate *power_gate = &smu_power->power_gate;
1823         int ret = 0;
1824
1825         if (enable) {
1826                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1827                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1828                         if (ret) {
1829                                 pr_err("[EnableVCNDPM] failed!\n");
1830                                 return ret;
1831                         }
1832                 }
1833                 power_gate->vcn_gated = false;
1834         } else {
1835                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1836                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1837                         if (ret) {
1838                                 pr_err("[DisableVCNDPM] failed!\n");
1839                                 return ret;
1840                         }
1841                 }
1842                 power_gate->vcn_gated = true;
1843         }
1844
1845         return ret;
1846 }
1847
1848
1849 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
1850                                   uint8_t address, uint32_t numbytes,
1851                                   uint8_t *data)
1852 {
1853         int i;
1854
1855         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
1856
1857         req->I2CcontrollerPort = 0;
1858         req->I2CSpeed = 2;
1859         req->SlaveAddress = address;
1860         req->NumCmds = numbytes;
1861
1862         for (i = 0; i < numbytes; i++) {
1863                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1864
1865                 /* First 2 bytes are always write for lower 2b EEPROM address */
1866                 if (i < 2)
1867                         cmd->Cmd = 1;
1868                 else
1869                         cmd->Cmd = write;
1870
1871
1872                 /* Add RESTART for read  after address filled */
1873                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1874
1875                 /* Add STOP in the end */
1876                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1877
1878                 /* Fill with data regardless if read or write to simplify code */
1879                 cmd->RegisterAddr = data[i];
1880         }
1881 }
1882
1883 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
1884                                                uint8_t address,
1885                                                uint8_t *data,
1886                                                uint32_t numbytes)
1887 {
1888         uint32_t  i, ret = 0;
1889         SwI2cRequest_t req;
1890         struct amdgpu_device *adev = to_amdgpu_device(control);
1891         struct smu_table_context *smu_table = &adev->smu.smu_table;
1892         struct smu_table *table = &smu_table->tables[SMU_TABLE_I2C_COMMANDS];
1893
1894         memset(&req, 0, sizeof(req));
1895         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
1896
1897         mutex_lock(&adev->smu.mutex);
1898         /* Now read data starting with that address */
1899         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1900                                         true);
1901         mutex_unlock(&adev->smu.mutex);
1902
1903         if (!ret) {
1904                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1905
1906                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1907                 for (i = 0; i < numbytes; i++)
1908                         data[i] = res->SwI2cCmds[i].Data;
1909
1910                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
1911                                   (uint16_t)address, numbytes);
1912
1913                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1914                                8, 1, data, numbytes, false);
1915         } else
1916                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
1917
1918         return ret;
1919 }
1920
1921 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
1922                                                 uint8_t address,
1923                                                 uint8_t *data,
1924                                                 uint32_t numbytes)
1925 {
1926         uint32_t ret;
1927         SwI2cRequest_t req;
1928         struct amdgpu_device *adev = to_amdgpu_device(control);
1929
1930         memset(&req, 0, sizeof(req));
1931         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
1932
1933         mutex_lock(&adev->smu.mutex);
1934         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1935         mutex_unlock(&adev->smu.mutex);
1936
1937         if (!ret) {
1938                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1939                                          (uint16_t)address, numbytes);
1940
1941                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1942                                8, 1, data, numbytes, false);
1943                 /*
1944                  * According to EEPROM spec there is a MAX of 10 ms required for
1945                  * EEPROM to flush internal RX buffer after STOP was issued at the
1946                  * end of write transaction. During this time the EEPROM will not be
1947                  * responsive to any more commands - so wait a bit more.
1948                  */
1949                 msleep(10);
1950
1951         } else
1952                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
1953
1954         return ret;
1955 }
1956
1957 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
1958                               struct i2c_msg *msgs, int num)
1959 {
1960         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1961         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1962
1963         for (i = 0; i < num; i++) {
1964                 /*
1965                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1966                  * once and hence the data needs to be spliced into chunks and sent each
1967                  * chunk separately
1968                  */
1969                 data_size = msgs[i].len - 2;
1970                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1971                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1972                 data_ptr = msgs[i].buf + 2;
1973
1974                 for (j = 0; j < data_size / data_chunk_size; j++) {
1975                         /* Insert the EEPROM dest addess, bits 0-15 */
1976                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1977                         data_chunk[1] = (next_eeprom_addr & 0xff);
1978
1979                         if (msgs[i].flags & I2C_M_RD) {
1980                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
1981                                                                 (uint8_t)msgs[i].addr,
1982                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
1983
1984                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1985                         } else {
1986
1987                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1988
1989                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
1990                                                                  (uint8_t)msgs[i].addr,
1991                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
1992                         }
1993
1994                         if (ret) {
1995                                 num = -EIO;
1996                                 goto fail;
1997                         }
1998
1999                         next_eeprom_addr += data_chunk_size;
2000                         data_ptr += data_chunk_size;
2001                 }
2002
2003                 if (data_size % data_chunk_size) {
2004                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2005                         data_chunk[1] = (next_eeprom_addr & 0xff);
2006
2007                         if (msgs[i].flags & I2C_M_RD) {
2008                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2009                                                                 (uint8_t)msgs[i].addr,
2010                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2011
2012                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2013                         } else {
2014                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2015
2016                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2017                                                                  (uint8_t)msgs[i].addr,
2018                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2019                         }
2020
2021                         if (ret) {
2022                                 num = -EIO;
2023                                 goto fail;
2024                         }
2025                 }
2026         }
2027
2028 fail:
2029         return num;
2030 }
2031
2032 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2033 {
2034         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2035 }
2036
2037
2038 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2039         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2040         .functionality = arcturus_i2c_eeprom_i2c_func,
2041 };
2042
2043 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2044 {
2045         struct amdgpu_device *adev = to_amdgpu_device(control);
2046         int res;
2047
2048         control->owner = THIS_MODULE;
2049         control->class = I2C_CLASS_SPD;
2050         control->dev.parent = &adev->pdev->dev;
2051         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2052         snprintf(control->name, sizeof(control->name), "RAS EEPROM");
2053
2054         res = i2c_add_adapter(control);
2055         if (res)
2056                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2057
2058         return res;
2059 }
2060
2061 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2062 {
2063         i2c_del_adapter(control);
2064 }
2065
2066 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2067 {
2068         PPTable_t *pptable = smu->smu_table.driver_pptable;
2069
2070         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2071 }
2072
2073 static const struct pptable_funcs arcturus_ppt_funcs = {
2074         /* translate smu index into arcturus specific index */
2075         .get_smu_msg_index = arcturus_get_smu_msg_index,
2076         .get_smu_clk_index = arcturus_get_smu_clk_index,
2077         .get_smu_feature_index = arcturus_get_smu_feature_index,
2078         .get_smu_table_index = arcturus_get_smu_table_index,
2079         .get_smu_power_index= arcturus_get_pwr_src_index,
2080         .get_workload_type = arcturus_get_workload_type,
2081         /* internal structurs allocations */
2082         .tables_init = arcturus_tables_init,
2083         .alloc_dpm_context = arcturus_allocate_dpm_context,
2084         /* pptable related */
2085         .check_powerplay_table = arcturus_check_powerplay_table,
2086         .store_powerplay_table = arcturus_store_powerplay_table,
2087         .append_powerplay_table = arcturus_append_powerplay_table,
2088         /* init dpm */
2089         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2090         /* btc */
2091         .run_btc = arcturus_run_btc,
2092         /* dpm/clk tables */
2093         .set_default_dpm_table = arcturus_set_default_dpm_table,
2094         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2095         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2096         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2097         .print_clk_levels = arcturus_print_clk_levels,
2098         .force_clk_levels = arcturus_force_clk_levels,
2099         .read_sensor = arcturus_read_sensor,
2100         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2101         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2102         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2103         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2104         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2105         .get_power_profile_mode = arcturus_get_power_profile_mode,
2106         .set_power_profile_mode = arcturus_set_power_profile_mode,
2107         /* debug (internal used) */
2108         .dump_pptable = arcturus_dump_pptable,
2109         .get_power_limit = arcturus_get_power_limit,
2110         .is_dpm_running = arcturus_is_dpm_running,
2111         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2112         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2113         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2114         .init_microcode = smu_v11_0_init_microcode,
2115         .load_microcode = smu_v11_0_load_microcode,
2116         .init_smc_tables = smu_v11_0_init_smc_tables,
2117         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2118         .init_power = smu_v11_0_init_power,
2119         .fini_power = smu_v11_0_fini_power,
2120         .check_fw_status = smu_v11_0_check_fw_status,
2121         .setup_pptable = smu_v11_0_setup_pptable,
2122         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2123         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2124         .check_pptable = smu_v11_0_check_pptable,
2125         .parse_pptable = smu_v11_0_parse_pptable,
2126         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2127         .check_fw_version = smu_v11_0_check_fw_version,
2128         .write_pptable = smu_v11_0_write_pptable,
2129         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2130         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2131         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2132         .system_features_control = smu_v11_0_system_features_control,
2133         .send_smc_msg = smu_v11_0_send_msg,
2134         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2135         .read_smc_arg = smu_v11_0_read_arg,
2136         .init_display_count = smu_v11_0_init_display_count,
2137         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2138         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2139         .notify_display_change = smu_v11_0_notify_display_change,
2140         .set_power_limit = smu_v11_0_set_power_limit,
2141         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2142         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2143         .start_thermal_control = smu_v11_0_start_thermal_control,
2144         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2145         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2146         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2147         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2148         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2149         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2150         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2151         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2152         .gfx_off_control = smu_v11_0_gfx_off_control,
2153         .register_irq_handler = smu_v11_0_register_irq_handler,
2154         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2155         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2156         .baco_is_support= smu_v11_0_baco_is_support,
2157         .baco_get_state = smu_v11_0_baco_get_state,
2158         .baco_set_state = smu_v11_0_baco_set_state,
2159         .baco_reset = smu_v11_0_baco_reset,
2160         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2161         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2162         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2163         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2164 };
2165
2166 void arcturus_set_ppt_funcs(struct smu_context *smu)
2167 {
2168         smu->ppt_funcs = &arcturus_ppt_funcs;
2169 }