drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if_arcturus.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "power_state.h"
  36 #include "arcturus_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "arcturus_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = {1, (index)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 130 };
 131
 132 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 133         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 134         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 135         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 136         CLK_MAP(FCLK, PPCLK_FCLK),
 137         CLK_MAP(UCLK, PPCLK_UCLK),
 138         CLK_MAP(MCLK, PPCLK_UCLK),
 139         CLK_MAP(DCLK, PPCLK_DCLK),
 140         CLK_MAP(VCLK, PPCLK_VCLK),
 141 };
 142
 143 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(DPM_PREFETCHER),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_UCLK),
 147         FEA_MAP(DPM_SOCCLK),
 148         FEA_MAP(DPM_FCLK),
 149         FEA_MAP(DPM_MP0CLK),
 150         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 151         FEA_MAP(DS_GFXCLK),
 152         FEA_MAP(DS_SOCCLK),
 153         FEA_MAP(DS_LCLK),
 154         FEA_MAP(DS_FCLK),
 155         FEA_MAP(DS_UCLK),
 156         FEA_MAP(GFX_ULV),
 157         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 158         FEA_MAP(RSMU_SMN_CG),
 159         FEA_MAP(WAFL_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(APCC_PLUS),
 163         FEA_MAP(VR0HOT),
 164         FEA_MAP(VR1HOT),
 165         FEA_MAP(FW_CTF),
 166         FEA_MAP(FAN_CONTROL),
 167         FEA_MAP(THERMAL),
 168         FEA_MAP(OUT_OF_BAND_MONITOR),
 169         FEA_MAP(TEMP_DEPENDENT_VMIN),
 170 };
 171
 172 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 173         TAB_MAP(PPTABLE),
 174         TAB_MAP(AVFS),
 175         TAB_MAP(AVFS_PSM_DEBUG),
 176         TAB_MAP(AVFS_FUSE_OVERRIDE),
 177         TAB_MAP(PMSTATUSLOG),
 178         TAB_MAP(SMU_METRICS),
 179         TAB_MAP(DRIVER_SMU_CONFIG),
 180         TAB_MAP(OVERDRIVE),
 181         TAB_MAP(I2C_COMMANDS),
 182 };
 183
 184 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 185         PWR_MAP(AC),
 186         PWR_MAP(DC),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 191         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 195 };
 196
 197 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 198 {
 199         struct smu_11_0_cmn2aisc_mapping mapping;
 200
 201         if (index >= SMU_MSG_MAX_COUNT)
 202                 return -EINVAL;
 203
 204         mapping = arcturus_message_map[index];
 205         if (!(mapping.valid_mapping))
 206                 return -EINVAL;
 207
 208         return mapping.map_to;
 209 }
 210
 211 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 212 {
 213         struct smu_11_0_cmn2aisc_mapping mapping;
 214
 215         if (index >= SMU_CLK_COUNT)
 216                 return -EINVAL;
 217
 218         mapping = arcturus_clk_map[index];
 219         if (!(mapping.valid_mapping)) {
 220                 pr_warn("Unsupported SMU clk: %d\n", index);
 221                 return -EINVAL;
 222         }
 223
 224         return mapping.map_to;
 225 }
 226
 227 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 228 {
 229         struct smu_11_0_cmn2aisc_mapping mapping;
 230
 231         if (index >= SMU_FEATURE_COUNT)
 232                 return -EINVAL;
 233
 234         mapping = arcturus_feature_mask_map[index];
 235         if (!(mapping.valid_mapping)) {
 236                 return -EINVAL;
 237         }
 238
 239         return mapping.map_to;
 240 }
 241
 242 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 243 {
 244         struct smu_11_0_cmn2aisc_mapping mapping;
 245
 246         if (index >= SMU_TABLE_COUNT)
 247                 return -EINVAL;
 248
 249         mapping = arcturus_table_map[index];
 250         if (!(mapping.valid_mapping)) {
 251                 pr_warn("Unsupported SMU table: %d\n", index);
 252                 return -EINVAL;
 253         }
 254
 255         return mapping.map_to;
 256 }
 257
 258 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 259 {
 260         struct smu_11_0_cmn2aisc_mapping mapping;
 261
 262         if (index >= SMU_POWER_SOURCE_COUNT)
 263                 return -EINVAL;
 264
 265         mapping = arcturus_pwr_src_map[index];
 266         if (!(mapping.valid_mapping)) {
 267                 pr_warn("Unsupported SMU power source: %d\n", index);
 268                 return -EINVAL;
 269         }
 270
 271         return mapping.map_to;
 272 }
 273
 274
 275 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 280                 return -EINVAL;
 281
 282         mapping = arcturus_workload_map[profile];
 283         if (!(mapping.valid_mapping)) {
 284                 pr_warn("Unsupported SMU power source: %d\n", profile);
 285                 return -EINVAL;
 286         }
 287
 288         return mapping.map_to;
 289 }
 290
 291 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 292 {
 293         struct smu_table_context *smu_table = &smu->smu_table;
 294
 295         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 296                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 297
 298         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 299                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 300
 301         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 302                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 303
 304         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 305                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 306
 307         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 308         if (!smu_table->metrics_table)
 309                 return -ENOMEM;
 310         smu_table->metrics_time = 0;
 311
 312         return 0;
 313 }
 314
 315 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 316 {
 317         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 318
 319         if (smu_dpm->dpm_context)
 320                 return -EINVAL;
 321
 322         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 323                                        GFP_KERNEL);
 324         if (!smu_dpm->dpm_context)
 325                 return -ENOMEM;
 326
 327         if (smu_dpm->golden_dpm_context)
 328                 return -EINVAL;
 329
 330         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 331                                               GFP_KERNEL);
 332         if (!smu_dpm->golden_dpm_context)
 333                 return -ENOMEM;
 334
 335         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 336
 337         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 338                                        GFP_KERNEL);
 339         if (!smu_dpm->dpm_current_power_state)
 340                 return -ENOMEM;
 341
 342         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 343                                        GFP_KERNEL);
 344         if (!smu_dpm->dpm_request_power_state)
 345                 return -ENOMEM;
 346
 347         return 0;
 348 }
 349
 350 static int
 351 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 352                                   uint32_t *feature_mask, uint32_t num)
 353 {
 354         if (num > 2)
 355                 return -EINVAL;
 356
 357         /* pptable will handle the features to enable */
 358         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 359
 360         return 0;
 361 }
 362
 363 static int
 364 arcturus_set_single_dpm_table(struct smu_context *smu,
 365                             struct arcturus_single_dpm_table *single_dpm_table,
 366                             PPCLK_e clk_id)
 367 {
 368         int ret = 0;
 369         uint32_t i, num_of_levels = 0, clk;
 370
 371         ret = smu_send_smc_msg_with_param(smu,
 372                         SMU_MSG_GetDpmFreqByIndex,
 373                         (clk_id << 16 | 0xFF));
 374         if (ret) {
 375                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 376                 return ret;
 377         }
 378
 379         smu_read_smc_arg(smu, &num_of_levels);
 380         if (!num_of_levels) {
 381                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 382                 return -EINVAL;
 383         }
 384
 385         single_dpm_table->count = num_of_levels;
 386         for (i = 0; i < num_of_levels; i++) {
 387                 ret = smu_send_smc_msg_with_param(smu,
 388                                 SMU_MSG_GetDpmFreqByIndex,
 389                                 (clk_id << 16 | i));
 390                 if (ret) {
 391                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 392                         return ret;
 393                 }
 394                 smu_read_smc_arg(smu, &clk);
 395                 if (!clk) {
 396                         pr_err("[%s] clk value is invalid!\n", __func__);
 397                         return -EINVAL;
 398                 }
 399                 single_dpm_table->dpm_levels[i].value = clk;
 400                 single_dpm_table->dpm_levels[i].enabled = true;
 401         }
 402         return 0;
 403 }
 404
 405 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 406 {
 407         dpm_state->soft_min_level = 0x0;
 408         dpm_state->soft_max_level = 0xffff;
 409         dpm_state->hard_min_level = 0x0;
 410         dpm_state->hard_max_level = 0xffff;
 411 }
 412
 413 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 414 {
 415         int ret;
 416
 417         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 418         struct arcturus_dpm_table *dpm_table = NULL;
 419         struct arcturus_single_dpm_table *single_dpm_table;
 420
 421         dpm_table = smu_dpm->dpm_context;
 422
 423         /* socclk */
 424         single_dpm_table = &(dpm_table->soc_table);
 425         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 426                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 427                                                   PPCLK_SOCCLK);
 428                 if (ret) {
 429                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 430                         return ret;
 431                 }
 432         } else {
 433                 single_dpm_table->count = 1;
 434                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 435         }
 436         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 437
 438         /* gfxclk */
 439         single_dpm_table = &(dpm_table->gfx_table);
 440         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 441                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 442                                                   PPCLK_GFXCLK);
 443                 if (ret) {
 444                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 445                         return ret;
 446                 }
 447         } else {
 448                 single_dpm_table->count = 1;
 449                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 450         }
 451         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 452
 453         /* memclk */
 454         single_dpm_table = &(dpm_table->mem_table);
 455         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 456                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 457                                                   PPCLK_UCLK);
 458                 if (ret) {
 459                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 460                         return ret;
 461                 }
 462         } else {
 463                 single_dpm_table->count = 1;
 464                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 465         }
 466         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 467
 468         /* fclk */
 469         single_dpm_table = &(dpm_table->fclk_table);
 470         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 471                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 472                                                   PPCLK_FCLK);
 473                 if (ret) {
 474                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 475                         return ret;
 476                 }
 477         } else {
 478                 single_dpm_table->count = 1;
 479                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 480         }
 481         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 482
 483         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 484                sizeof(struct arcturus_dpm_table));
 485
 486         return 0;
 487 }
 488
 489 static int arcturus_check_powerplay_table(struct smu_context *smu)
 490 {
 491         return 0;
 492 }
 493
 494 static int arcturus_store_powerplay_table(struct smu_context *smu)
 495 {
 496         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 497         struct smu_table_context *table_context = &smu->smu_table;
 498         struct smu_baco_context *smu_baco = &smu->smu_baco;
 499         int ret = 0;
 500
 501         if (!table_context->power_play_table)
 502                 return -EINVAL;
 503
 504         powerplay_table = table_context->power_play_table;
 505
 506         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 507                sizeof(PPTable_t));
 508
 509         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 510
 511         mutex_lock(&smu_baco->mutex);
 512         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 513             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 514                 smu_baco->platform_support = true;
 515         mutex_unlock(&smu_baco->mutex);
 516
 517         return ret;
 518 }
 519
 520 static int arcturus_append_powerplay_table(struct smu_context *smu)
 521 {
 522         struct smu_table_context *table_context = &smu->smu_table;
 523         PPTable_t *smc_pptable = table_context->driver_pptable;
 524         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 525         int index, ret;
 526
 527         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 528                                            smc_dpm_info);
 529
 530         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 531                                       (uint8_t **)&smc_dpm_table);
 532         if (ret)
 533                 return ret;
 534
 535         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 536                         smc_dpm_table->table_header.format_revision,
 537                         smc_dpm_table->table_header.content_revision);
 538
 539         if ((smc_dpm_table->table_header.format_revision == 4) &&
 540             (smc_dpm_table->table_header.content_revision == 6))
 541                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 542                        &smc_dpm_table->maxvoltagestepgfx,
 543                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 544
 545         return 0;
 546 }
 547
 548 static int arcturus_run_btc(struct smu_context *smu)
 549 {
 550         int ret = 0;
 551
 552         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 553         if (ret) {
 554                 pr_err("RunAfllBtc failed!\n");
 555                 return ret;
 556         }
 557
 558         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
 559 }
 560
 561 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 562 {
 563         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 564         struct arcturus_dpm_table *dpm_table = NULL;
 565         struct arcturus_single_dpm_table *gfx_table = NULL;
 566         struct arcturus_single_dpm_table *mem_table = NULL;
 567
 568         dpm_table = smu_dpm->dpm_context;
 569         gfx_table = &(dpm_table->gfx_table);
 570         mem_table = &(dpm_table->mem_table);
 571
 572         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 573         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 574
 575         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 576             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 577                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 578                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 579         }
 580
 581         smu->pstate_sclk = smu->pstate_sclk * 100;
 582         smu->pstate_mclk = smu->pstate_mclk * 100;
 583
 584         return 0;
 585 }
 586
 587 static int arcturus_get_clk_table(struct smu_context *smu,
 588                         struct pp_clock_levels_with_latency *clocks,
 589                         struct arcturus_single_dpm_table *dpm_table)
 590 {
 591         int i, count;
 592
 593         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 594         clocks->num_levels = count;
 595
 596         for (i = 0; i < count; i++) {
 597                 clocks->data[i].clocks_in_khz =
 598                         dpm_table->dpm_levels[i].value * 1000;
 599                 clocks->data[i].latency_in_us = 0;
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int arcturus_freqs_in_same_level(int32_t frequency1,
 606                                         int32_t frequency2)
 607 {
 608         return (abs(frequency1 - frequency2) <= EPSILON);
 609 }
 610
 611 static int arcturus_print_clk_levels(struct smu_context *smu,
 612                         enum smu_clk_type type, char *buf)
 613 {
 614         int i, now, size = 0;
 615         int ret = 0;
 616         struct pp_clock_levels_with_latency clocks;
 617         struct arcturus_single_dpm_table *single_dpm_table;
 618         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 619         struct arcturus_dpm_table *dpm_table = NULL;
 620
 621         dpm_table = smu_dpm->dpm_context;
 622
 623         switch (type) {
 624         case SMU_SCLK:
 625                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 626                 if (ret) {
 627                         pr_err("Attempt to get current gfx clk Failed!");
 628                         return ret;
 629                 }
 630
 631                 single_dpm_table = &(dpm_table->gfx_table);
 632                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 633                 if (ret) {
 634                         pr_err("Attempt to get gfx clk levels Failed!");
 635                         return ret;
 636                 }
 637
 638                 /*
 639                  * For DPM disabled case, there will be only one clock level.
 640                  * And it's safe to assume that is always the current clock.
 641                  */
 642                 for (i = 0; i < clocks.num_levels; i++)
 643                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 644                                         clocks.data[i].clocks_in_khz / 1000,
 645                                         (clocks.num_levels == 1) ? "*" :
 646                                         (arcturus_freqs_in_same_level(
 647                                         clocks.data[i].clocks_in_khz / 1000,
 648                                         now / 100) ? "*" : ""));
 649                 break;
 650
 651         case SMU_MCLK:
 652                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 653                 if (ret) {
 654                         pr_err("Attempt to get current mclk Failed!");
 655                         return ret;
 656                 }
 657
 658                 single_dpm_table = &(dpm_table->mem_table);
 659                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 660                 if (ret) {
 661                         pr_err("Attempt to get memory clk levels Failed!");
 662                         return ret;
 663                 }
 664
 665                 for (i = 0; i < clocks.num_levels; i++)
 666                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 667                                 i, clocks.data[i].clocks_in_khz / 1000,
 668                                 (clocks.num_levels == 1) ? "*" :
 669                                 (arcturus_freqs_in_same_level(
 670                                 clocks.data[i].clocks_in_khz / 1000,
 671                                 now / 100) ? "*" : ""));
 672                 break;
 673
 674         case SMU_SOCCLK:
 675                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 676                 if (ret) {
 677                         pr_err("Attempt to get current socclk Failed!");
 678                         return ret;
 679                 }
 680
 681                 single_dpm_table = &(dpm_table->soc_table);
 682                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 683                 if (ret) {
 684                         pr_err("Attempt to get socclk levels Failed!");
 685                         return ret;
 686                 }
 687
 688                 for (i = 0; i < clocks.num_levels; i++)
 689                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 690                                 i, clocks.data[i].clocks_in_khz / 1000,
 691                                 (clocks.num_levels == 1) ? "*" :
 692                                 (arcturus_freqs_in_same_level(
 693                                 clocks.data[i].clocks_in_khz / 1000,
 694                                 now / 100) ? "*" : ""));
 695                 break;
 696
 697         case SMU_FCLK:
 698                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 699                 if (ret) {
 700                         pr_err("Attempt to get current fclk Failed!");
 701                         return ret;
 702                 }
 703
 704                 single_dpm_table = &(dpm_table->fclk_table);
 705                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 706                 if (ret) {
 707                         pr_err("Attempt to get fclk levels Failed!");
 708                         return ret;
 709                 }
 710
 711                 for (i = 0; i < single_dpm_table->count; i++)
 712                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 713                                 i, single_dpm_table->dpm_levels[i].value,
 714                                 (clocks.num_levels == 1) ? "*" :
 715                                 (arcturus_freqs_in_same_level(
 716                                 clocks.data[i].clocks_in_khz / 1000,
 717                                 now / 100) ? "*" : ""));
 718                 break;
 719
 720         default:
 721                 break;
 722         }
 723
 724         return size;
 725 }
 726
 727 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 728                                      uint32_t feature_mask)
 729 {
 730         struct arcturus_single_dpm_table *single_dpm_table;
 731         struct arcturus_dpm_table *dpm_table =
 732                         smu->smu_dpm.dpm_context;
 733         uint32_t freq;
 734         int ret = 0;
 735
 736         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 737             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 738                 single_dpm_table = &(dpm_table->gfx_table);
 739                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 740                         single_dpm_table->dpm_state.soft_min_level;
 741                 ret = smu_send_smc_msg_with_param(smu,
 742                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 743                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 744                 if (ret) {
 745                         pr_err("Failed to set soft %s gfxclk !\n",
 746                                                 max ? "max" : "min");
 747                         return ret;
 748                 }
 749         }
 750
 751         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 752             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 753                 single_dpm_table = &(dpm_table->mem_table);
 754                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 755                         single_dpm_table->dpm_state.soft_min_level;
 756                 ret = smu_send_smc_msg_with_param(smu,
 757                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 758                         (PPCLK_UCLK << 16) | (freq & 0xffff));
 759                 if (ret) {
 760                         pr_err("Failed to set soft %s memclk !\n",
 761                                                 max ? "max" : "min");
 762                         return ret;
 763                 }
 764         }
 765
 766         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 767             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 768                 single_dpm_table = &(dpm_table->soc_table);
 769                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 770                         single_dpm_table->dpm_state.soft_min_level;
 771                 ret = smu_send_smc_msg_with_param(smu,
 772                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 773                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
 774                 if (ret) {
 775                         pr_err("Failed to set soft %s socclk !\n",
 776                                                 max ? "max" : "min");
 777                         return ret;
 778                 }
 779         }
 780
 781         return ret;
 782 }
 783
 784 static int arcturus_force_clk_levels(struct smu_context *smu,
 785                         enum smu_clk_type type, uint32_t mask)
 786 {
 787         struct arcturus_dpm_table *dpm_table;
 788         struct arcturus_single_dpm_table *single_dpm_table;
 789         uint32_t soft_min_level, soft_max_level;
 790         int ret = 0;
 791
 792         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 793         soft_max_level = mask ? (fls(mask) - 1) : 0;
 794
 795         dpm_table = smu->smu_dpm.dpm_context;
 796
 797         switch (type) {
 798         case SMU_SCLK:
 799                 single_dpm_table = &(dpm_table->gfx_table);
 800
 801                 if (soft_max_level >= single_dpm_table->count) {
 802                         pr_err("Clock level specified %d is over max allowed %d\n",
 803                                         soft_max_level, single_dpm_table->count - 1);
 804                         ret = -EINVAL;
 805                         break;
 806                 }
 807
 808                 single_dpm_table->dpm_state.soft_min_level =
 809                         single_dpm_table->dpm_levels[soft_min_level].value;
 810                 single_dpm_table->dpm_state.soft_max_level =
 811                         single_dpm_table->dpm_levels[soft_max_level].value;
 812
 813                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 814                 if (ret) {
 815                         pr_err("Failed to upload boot level to lowest!\n");
 816                         break;
 817                 }
 818
 819                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 820                 if (ret)
 821                         pr_err("Failed to upload dpm max level to highest!\n");
 822
 823                 break;
 824
 825         case SMU_MCLK:
 826         case SMU_SOCCLK:
 827         case SMU_FCLK:
 828                 /*
 829                  * Should not arrive here since Arcturus does not
 830                  * support mclk/socclk/fclk softmin/softmax settings
 831                  */
 832                 ret = -EINVAL;
 833                 break;
 834
 835         default:
 836                 break;
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 843                                                 struct smu_temperature_range *range)
 844 {
 845         PPTable_t *pptable = smu->smu_table.driver_pptable;
 846
 847         if (!range)
 848                 return -EINVAL;
 849
 850         range->max = pptable->TedgeLimit *
 851                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 852         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 853                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 854         range->hotspot_crit_max = pptable->ThotspotLimit *
 855                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 856         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 857                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 858         range->mem_crit_max = pptable->TmemLimit *
 859                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 860         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 861                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 862
 863         return 0;
 864 }
 865
 866 static int arcturus_get_metrics_table(struct smu_context *smu,
 867                                       SmuMetrics_t *metrics_table)
 868 {
 869         struct smu_table_context *smu_table= &smu->smu_table;
 870         int ret = 0;
 871
 872         if (!smu_table->metrics_time ||
 873              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 874                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 875                                 (void *)smu_table->metrics_table, false);
 876                 if (ret) {
 877                         pr_info("Failed to export SMU metrics table!\n");
 878                         return ret;
 879                 }
 880                 smu_table->metrics_time = jiffies;
 881         }
 882
 883         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 884
 885         return ret;
 886 }
 887
 888 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 889                                                  enum amd_pp_sensors sensor,
 890                                                  uint32_t *value)
 891 {
 892         SmuMetrics_t metrics;
 893         int ret = 0;
 894
 895         if (!value)
 896                 return -EINVAL;
 897
 898         ret = arcturus_get_metrics_table(smu, &metrics);
 899         if (ret)
 900                 return ret;
 901
 902         switch (sensor) {
 903         case AMDGPU_PP_SENSOR_GPU_LOAD:
 904                 *value = metrics.AverageGfxActivity;
 905                 break;
 906         case AMDGPU_PP_SENSOR_MEM_LOAD:
 907                 *value = metrics.AverageUclkActivity;
 908                 break;
 909         default:
 910                 pr_err("Invalid sensor for retrieving clock activity\n");
 911                 return -EINVAL;
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 918 {
 919         SmuMetrics_t metrics;
 920         int ret = 0;
 921
 922         if (!value)
 923                 return -EINVAL;
 924
 925         ret = arcturus_get_metrics_table(smu, &metrics);
 926         if (ret)
 927                 return ret;
 928
 929         *value = metrics.AverageSocketPower << 8;
 930
 931         return 0;
 932 }
 933
 934 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 935                                             enum amd_pp_sensors sensor,
 936                                             uint32_t *value)
 937 {
 938         SmuMetrics_t metrics;
 939         int ret = 0;
 940
 941         if (!value)
 942                 return -EINVAL;
 943
 944         ret = arcturus_get_metrics_table(smu, &metrics);
 945         if (ret)
 946                 return ret;
 947
 948         switch (sensor) {
 949         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 950                 *value = metrics.TemperatureHotspot *
 951                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 952                 break;
 953         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 954                 *value = metrics.TemperatureEdge *
 955                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 956                 break;
 957         case AMDGPU_PP_SENSOR_MEM_TEMP:
 958                 *value = metrics.TemperatureHBM *
 959                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 960                 break;
 961         default:
 962                 pr_err("Invalid sensor for retrieving temp\n");
 963                 return -EINVAL;
 964         }
 965
 966         return 0;
 967 }
 968
 969 static int arcturus_read_sensor(struct smu_context *smu,
 970                                 enum amd_pp_sensors sensor,
 971                                 void *data, uint32_t *size)
 972 {
 973         struct smu_table_context *table_context = &smu->smu_table;
 974         PPTable_t *pptable = table_context->driver_pptable;
 975         int ret = 0;
 976
 977         if (!data || !size)
 978                 return -EINVAL;
 979
 980         mutex_lock(&smu->sensor_lock);
 981         switch (sensor) {
 982         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 983                 *(uint32_t *)data = pptable->FanMaximumRpm;
 984                 *size = 4;
 985                 break;
 986         case AMDGPU_PP_SENSOR_MEM_LOAD:
 987         case AMDGPU_PP_SENSOR_GPU_LOAD:
 988                 ret = arcturus_get_current_activity_percent(smu,
 989                                                             sensor,
 990                                                 (uint32_t *)data);
 991                 *size = 4;
 992                 break;
 993         case AMDGPU_PP_SENSOR_GPU_POWER:
 994                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
 995                 *size = 4;
 996                 break;
 997         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 998         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 999         case AMDGPU_PP_SENSOR_MEM_TEMP:
1000                 ret = arcturus_thermal_get_temperature(smu, sensor,
1001                                                 (uint32_t *)data);
1002                 *size = 4;
1003                 break;
1004         default:
1005                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1006         }
1007         mutex_unlock(&smu->sensor_lock);
1008
1009         return ret;
1010 }
1011
1012 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1013                                       uint32_t *speed)
1014 {
1015         SmuMetrics_t metrics;
1016         int ret = 0;
1017
1018         if (!speed)
1019                 return -EINVAL;
1020
1021         ret = arcturus_get_metrics_table(smu, &metrics);
1022         if (ret)
1023                 return ret;
1024
1025         *speed = metrics.CurrFanSpeed;
1026
1027         return ret;
1028 }
1029
1030 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1031                                           uint32_t *speed)
1032 {
1033         PPTable_t *pptable = smu->smu_table.driver_pptable;
1034         uint32_t percent, current_rpm;
1035         int ret = 0;
1036
1037         if (!speed)
1038                 return -EINVAL;
1039
1040         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1041         if (ret)
1042                 return ret;
1043
1044         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1045         *speed = percent > 100 ? 100 : percent;
1046
1047         return ret;
1048 }
1049
1050 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1051                                        enum smu_clk_type clk_type,
1052                                        uint32_t *value)
1053 {
1054         static SmuMetrics_t metrics;
1055         int ret = 0, clk_id = 0;
1056
1057         if (!value)
1058                 return -EINVAL;
1059
1060         clk_id = smu_clk_get_index(smu, clk_type);
1061         if (clk_id < 0)
1062                 return -EINVAL;
1063
1064         ret = arcturus_get_metrics_table(smu, &metrics);
1065         if (ret)
1066                 return ret;
1067
1068         switch (clk_id) {
1069         case PPCLK_GFXCLK:
1070                 /*
1071                  * CurrClock[clk_id] can provide accurate
1072                  *   output only when the dpm feature is enabled.
1073                  * We can use Average_* for dpm disabled case.
1074                  *   But this is available for gfxclk/uclk/socclk.
1075                  */
1076                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1077                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1078                 else
1079                         *value = metrics.AverageGfxclkFrequency;
1080                 break;
1081         case PPCLK_UCLK:
1082                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1083                         *value = metrics.CurrClock[PPCLK_UCLK];
1084                 else
1085                         *value = metrics.AverageUclkFrequency;
1086                 break;
1087         case PPCLK_SOCCLK:
1088                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1089                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1090                 else
1091                         *value = metrics.AverageSocclkFrequency;
1092                 break;
1093         default:
1094                 *value = metrics.CurrClock[clk_id];
1095                 break;
1096         }
1097
1098         return ret;
1099 }
1100
1101 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1102 {
1103         uint32_t i;
1104
1105         for (i = 0; i < table->count; i++) {
1106                 if (table->dpm_levels[i].enabled)
1107                         break;
1108         }
1109         if (i >= table->count) {
1110                 i = 0;
1111                 table->dpm_levels[i].enabled = true;
1112         }
1113
1114         return i;
1115 }
1116
1117 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1118 {
1119         int i = 0;
1120
1121         if (table->count <= 0) {
1122                 pr_err("[%s] DPM Table has no entry!", __func__);
1123                 return 0;
1124         }
1125         if (table->count > MAX_DPM_NUMBER) {
1126                 pr_err("[%s] DPM Table has too many entries!", __func__);
1127                 return MAX_DPM_NUMBER - 1;
1128         }
1129
1130         for (i = table->count - 1; i >= 0; i--) {
1131                 if (table->dpm_levels[i].enabled)
1132                         break;
1133         }
1134         if (i < 0) {
1135                 i = 0;
1136                 table->dpm_levels[i].enabled = true;
1137         }
1138
1139         return i;
1140 }
1141
1142
1143
1144 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1145 {
1146         struct arcturus_dpm_table *dpm_table =
1147                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1148         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1149         uint32_t soft_level;
1150         int ret = 0;
1151
1152         /* gfxclk */
1153         if (highest)
1154                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1155         else
1156                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1157
1158         dpm_table->gfx_table.dpm_state.soft_min_level =
1159                 dpm_table->gfx_table.dpm_state.soft_max_level =
1160                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1161
1162         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1163         if (ret) {
1164                 pr_err("Failed to upload boot level to %s!\n",
1165                                 highest ? "highest" : "lowest");
1166                 return ret;
1167         }
1168
1169         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1170         if (ret) {
1171                 pr_err("Failed to upload dpm max level to %s!\n!",
1172                                 highest ? "highest" : "lowest");
1173                 return ret;
1174         }
1175
1176         if (hive)
1177                 /*
1178                  * Force XGMI Pstate to highest or lowest
1179                  * TODO: revise this when xgmi dpm is functional
1180                  */
1181                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1182
1183         return ret;
1184 }
1185
1186 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1187 {
1188         struct arcturus_dpm_table *dpm_table =
1189                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1190         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1191         uint32_t soft_min_level, soft_max_level;
1192         int ret = 0;
1193
1194         /* gfxclk */
1195         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1196         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1197         dpm_table->gfx_table.dpm_state.soft_min_level =
1198                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1199         dpm_table->gfx_table.dpm_state.soft_max_level =
1200                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1201
1202         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1203         if (ret) {
1204                 pr_err("Failed to upload DPM Bootup Levels!");
1205                 return ret;
1206         }
1207
1208         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1209         if (ret) {
1210                 pr_err("Failed to upload DPM Max Levels!");
1211                 return ret;
1212         }
1213
1214         if (hive)
1215                 /*
1216                  * Reset XGMI Pstate back to default
1217                  * TODO: revise this when xgmi dpm is functional
1218                  */
1219                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1220
1221         return ret;
1222 }
1223
1224 static int
1225 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1226                                 enum amd_dpm_forced_level level,
1227                                 uint32_t *sclk_mask,
1228                                 uint32_t *mclk_mask,
1229                                 uint32_t *soc_mask)
1230 {
1231         struct arcturus_dpm_table *dpm_table =
1232                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1233         struct arcturus_single_dpm_table *gfx_dpm_table;
1234         struct arcturus_single_dpm_table *mem_dpm_table;
1235         struct arcturus_single_dpm_table *soc_dpm_table;
1236
1237         if (!smu->smu_dpm.dpm_context)
1238                 return -EINVAL;
1239
1240         gfx_dpm_table = &dpm_table->gfx_table;
1241         mem_dpm_table = &dpm_table->mem_table;
1242         soc_dpm_table = &dpm_table->soc_table;
1243
1244         *sclk_mask = 0;
1245         *mclk_mask = 0;
1246         *soc_mask  = 0;
1247
1248         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1249             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1250             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1251                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1252                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1253                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1254         }
1255
1256         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1257                 *sclk_mask = 0;
1258         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1259                 *mclk_mask = 0;
1260         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1261                 *sclk_mask = gfx_dpm_table->count - 1;
1262                 *mclk_mask = mem_dpm_table->count - 1;
1263                 *soc_mask  = soc_dpm_table->count - 1;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int arcturus_get_power_limit(struct smu_context *smu,
1270                                      uint32_t *limit,
1271                                      bool cap)
1272 {
1273         PPTable_t *pptable = smu->smu_table.driver_pptable;
1274         uint32_t asic_default_power_limit = 0;
1275         int ret = 0;
1276         int power_src;
1277
1278         if (!smu->power_limit) {
1279                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1280                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1281                         if (power_src < 0)
1282                                 return -EINVAL;
1283
1284                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1285                                 power_src << 16);
1286                         if (ret) {
1287                                 pr_err("[%s] get PPT limit failed!", __func__);
1288                                 return ret;
1289                         }
1290                         smu_read_smc_arg(smu, &asic_default_power_limit);
1291                 } else {
1292                         /* the last hope to figure out the ppt limit */
1293                         if (!pptable) {
1294                                 pr_err("Cannot get PPT limit due to pptable missing!");
1295                                 return -EINVAL;
1296                         }
1297                         asic_default_power_limit =
1298                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1299                 }
1300
1301                 smu->power_limit = asic_default_power_limit;
1302         }
1303
1304         if (cap)
1305                 *limit = smu_v11_0_get_max_power_limit(smu);
1306         else
1307                 *limit = smu->power_limit;
1308
1309         return 0;
1310 }
1311
1312 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1313                                            char *buf)
1314 {
1315         static const char *profile_name[] = {
1316                                         "BOOTUP_DEFAULT",
1317                                         "3D_FULL_SCREEN",
1318                                         "POWER_SAVING",
1319                                         "VIDEO",
1320                                         "VR",
1321                                         "COMPUTE",
1322                                         "CUSTOM"};
1323         static const char *title[] = {
1324                         "PROFILE_INDEX(NAME)"};
1325         uint32_t i, size = 0;
1326         int16_t workload_type = 0;
1327
1328         if (!smu->pm_enabled || !buf)
1329                 return -EINVAL;
1330
1331         size += sprintf(buf + size, "%16s\n",
1332                         title[0]);
1333
1334         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1335                 /*
1336                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1337                  * Not all profile modes are supported on arcturus.
1338                  */
1339                 workload_type = smu_workload_get_type(smu, i);
1340                 if (workload_type < 0)
1341                         continue;
1342
1343                 size += sprintf(buf + size, "%2d %14s%s\n",
1344                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1345         }
1346
1347         return size;
1348 }
1349
1350 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1351                                            long *input,
1352                                            uint32_t size)
1353 {
1354         int workload_type = 0;
1355         uint32_t profile_mode = input[size];
1356         int ret = 0;
1357
1358         if (!smu->pm_enabled)
1359                 return -EINVAL;
1360
1361         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1362                 pr_err("Invalid power profile mode %d\n", profile_mode);
1363                 return -EINVAL;
1364         }
1365
1366         /*
1367          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1368          * Not all profile modes are supported on arcturus.
1369          */
1370         workload_type = smu_workload_get_type(smu, profile_mode);
1371         if (workload_type < 0) {
1372                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1373                 return -EINVAL;
1374         }
1375
1376         ret = smu_send_smc_msg_with_param(smu,
1377                                           SMU_MSG_SetWorkloadMask,
1378                                           1 << workload_type);
1379         if (ret) {
1380                 pr_err("Fail to set workload type %d\n", workload_type);
1381                 return ret;
1382         }
1383
1384         smu->power_profile_mode = profile_mode;
1385
1386         return 0;
1387 }
1388
1389 static void arcturus_dump_pptable(struct smu_context *smu)
1390 {
1391         struct smu_table_context *table_context = &smu->smu_table;
1392         PPTable_t *pptable = table_context->driver_pptable;
1393         int i;
1394
1395         pr_info("Dumped PPTable:\n");
1396
1397         pr_info("Version = 0x%08x\n", pptable->Version);
1398
1399         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1400         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1401
1402         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1403                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1404                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1405         }
1406
1407         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1408         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1409         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1410         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1411
1412         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1413         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1414         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1415         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1416         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1417         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1418         pr_info("FitLimit = %d\n", pptable->FitLimit);
1419
1420         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1421         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1422
1423         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1424
1425         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1426         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1427
1428         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1429         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1430         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1431         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1432
1433         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1434         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1435         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1436         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1437
1438         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1439         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1440
1441         pr_info("[PPCLK_GFXCLK]\n"
1442                         "  .VoltageMode          = 0x%02x\n"
1443                         "  .SnapToDiscrete       = 0x%02x\n"
1444                         "  .NumDiscreteLevels    = 0x%02x\n"
1445                         "  .padding              = 0x%02x\n"
1446                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1447                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1448                         "  .SsFmin               = 0x%04x\n"
1449                         "  .Padding_16           = 0x%04x\n",
1450                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1451                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1452                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1453                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1454                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1455                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1456                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1457                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1458                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1459                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1460                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1461
1462         pr_info("[PPCLK_VCLK]\n"
1463                         "  .VoltageMode          = 0x%02x\n"
1464                         "  .SnapToDiscrete       = 0x%02x\n"
1465                         "  .NumDiscreteLevels    = 0x%02x\n"
1466                         "  .padding              = 0x%02x\n"
1467                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1468                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1469                         "  .SsFmin               = 0x%04x\n"
1470                         "  .Padding_16           = 0x%04x\n",
1471                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1472                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1473                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1474                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1475                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1476                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1477                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1478                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1479                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1480                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1481                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1482
1483         pr_info("[PPCLK_DCLK]\n"
1484                         "  .VoltageMode          = 0x%02x\n"
1485                         "  .SnapToDiscrete       = 0x%02x\n"
1486                         "  .NumDiscreteLevels    = 0x%02x\n"
1487                         "  .padding              = 0x%02x\n"
1488                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1489                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1490                         "  .SsFmin               = 0x%04x\n"
1491                         "  .Padding_16           = 0x%04x\n",
1492                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1493                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1494                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1495                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1496                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1497                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1498                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1499                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1500                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1501                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1502                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1503
1504         pr_info("[PPCLK_SOCCLK]\n"
1505                         "  .VoltageMode          = 0x%02x\n"
1506                         "  .SnapToDiscrete       = 0x%02x\n"
1507                         "  .NumDiscreteLevels    = 0x%02x\n"
1508                         "  .padding              = 0x%02x\n"
1509                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1510                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1511                         "  .SsFmin               = 0x%04x\n"
1512                         "  .Padding_16           = 0x%04x\n",
1513                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1514                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1515                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1516                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1517                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1518                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1519                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1520                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1521                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1522                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1523                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1524
1525         pr_info("[PPCLK_UCLK]\n"
1526                         "  .VoltageMode          = 0x%02x\n"
1527                         "  .SnapToDiscrete       = 0x%02x\n"
1528                         "  .NumDiscreteLevels    = 0x%02x\n"
1529                         "  .padding              = 0x%02x\n"
1530                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1531                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1532                         "  .SsFmin               = 0x%04x\n"
1533                         "  .Padding_16           = 0x%04x\n",
1534                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1535                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1536                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1537                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1538                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1539                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1540                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1541                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1542                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1543                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1544                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1545
1546         pr_info("[PPCLK_FCLK]\n"
1547                         "  .VoltageMode          = 0x%02x\n"
1548                         "  .SnapToDiscrete       = 0x%02x\n"
1549                         "  .NumDiscreteLevels    = 0x%02x\n"
1550                         "  .padding              = 0x%02x\n"
1551                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1552                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1553                         "  .SsFmin               = 0x%04x\n"
1554                         "  .Padding_16           = 0x%04x\n",
1555                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1556                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1557                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1558                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1559                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1560                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1561                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1562                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1563                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1564                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1565                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1566
1567
1568         pr_info("FreqTableGfx\n");
1569         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1570                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1571
1572         pr_info("FreqTableVclk\n");
1573         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1574                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1575
1576         pr_info("FreqTableDclk\n");
1577         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1578                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1579
1580         pr_info("FreqTableSocclk\n");
1581         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1582                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1583
1584         pr_info("FreqTableUclk\n");
1585         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1586                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1587
1588         pr_info("FreqTableFclk\n");
1589         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1590                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1591
1592         pr_info("Mp0clkFreq\n");
1593         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1594                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1595
1596         pr_info("Mp0DpmVoltage\n");
1597         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1598                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1599
1600         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1601         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1602         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1603         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1604         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1605         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1606         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1607         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1608         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1609
1610         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1611         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1612         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1613         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1614
1615         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1616         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1617
1618         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1619         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1620         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1621         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1622         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1623         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1624
1625         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1626         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1627         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1628         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1629         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1630         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1631         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1632         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1633         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1634
1635         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1636         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1637         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1638         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1639
1640         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1641         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1642         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1643         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1644
1645         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1646                         pptable->dBtcGbGfxPll.a,
1647                         pptable->dBtcGbGfxPll.b,
1648                         pptable->dBtcGbGfxPll.c);
1649         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1650                         pptable->dBtcGbGfxAfll.a,
1651                         pptable->dBtcGbGfxAfll.b,
1652                         pptable->dBtcGbGfxAfll.c);
1653         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1654                         pptable->dBtcGbSoc.a,
1655                         pptable->dBtcGbSoc.b,
1656                         pptable->dBtcGbSoc.c);
1657
1658         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1659                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1660                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1661         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1662                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1663                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1664
1665         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1666                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1667                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1668                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1669         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1670                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1671                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1672                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1673
1674         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1675         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1676
1677         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1678         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1679         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1680         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1681
1682         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1683         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1684         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1685         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1686
1687         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1688         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1689
1690         pr_info("XgmiDpmPstates\n");
1691         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1692                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1693         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1694         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1695
1696         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1697         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1698         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1699         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1700         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1701         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1702         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1703         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1704
1705         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1706         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1707                         pptable->ReservedEquation0.a,
1708                         pptable->ReservedEquation0.b,
1709                         pptable->ReservedEquation0.c);
1710         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1711                         pptable->ReservedEquation1.a,
1712                         pptable->ReservedEquation1.b,
1713                         pptable->ReservedEquation1.c);
1714         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1715                         pptable->ReservedEquation2.a,
1716                         pptable->ReservedEquation2.b,
1717                         pptable->ReservedEquation2.c);
1718         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1719                         pptable->ReservedEquation3.a,
1720                         pptable->ReservedEquation3.b,
1721                         pptable->ReservedEquation3.c);
1722
1723         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1724         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1725
1726         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1727         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1728         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1729
1730         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1731         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1732
1733         pr_info("Board Parameters:\n");
1734         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1735         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1736
1737         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1738         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1739         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1740         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1741
1742         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1743         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1744
1745         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1746         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1747         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1748
1749         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1750         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1751         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1752
1753         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1754         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1755         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1756
1757         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1758         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1759         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1760
1761         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1762         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1763         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1764         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1765
1766         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1767         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1768         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1769
1770         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1771         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1772         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1773
1774         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1775         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1776         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1777
1778         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1779         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1780         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1781
1782         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1783                 pr_info("I2cControllers[%d]:\n", i);
1784                 pr_info("                   .Enabled = %d\n",
1785                                 pptable->I2cControllers[i].Enabled);
1786                 pr_info("                   .SlaveAddress = 0x%x\n",
1787                                 pptable->I2cControllers[i].SlaveAddress);
1788                 pr_info("                   .ControllerPort = %d\n",
1789                                 pptable->I2cControllers[i].ControllerPort);
1790                 pr_info("                   .ControllerName = %d\n",
1791                                 pptable->I2cControllers[i].ControllerName);
1792                 pr_info("                   .ThermalThrottler = %d\n",
1793                                 pptable->I2cControllers[i].ThermalThrotter);
1794                 pr_info("                   .I2cProtocol = %d\n",
1795                                 pptable->I2cControllers[i].I2cProtocol);
1796                 pr_info("                   .Speed = %d\n",
1797                                 pptable->I2cControllers[i].Speed);
1798         }
1799
1800         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1801         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1802
1803         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1804
1805         pr_info("XgmiLinkSpeed\n");
1806         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1807                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1808         pr_info("XgmiLinkWidth\n");
1809         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1810                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1811         pr_info("XgmiFclkFreq\n");
1812         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1813                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1814         pr_info("XgmiSocVoltage\n");
1815         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1816                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1817
1818 }
1819
1820 static bool arcturus_is_dpm_running(struct smu_context *smu)
1821 {
1822         int ret = 0;
1823         uint32_t feature_mask[2];
1824         unsigned long feature_enabled;
1825         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1826         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1827                            ((uint64_t)feature_mask[1] << 32));
1828         return !!(feature_enabled & SMC_DPM_FEATURE);
1829 }
1830
1831 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1832 {
1833         struct smu_power_context *smu_power = &smu->smu_power;
1834         struct smu_power_gate *power_gate = &smu_power->power_gate;
1835         int ret = 0;
1836
1837         if (enable) {
1838                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1839                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1840                         if (ret) {
1841                                 pr_err("[EnableVCNDPM] failed!\n");
1842                                 return ret;
1843                         }
1844                 }
1845                 power_gate->vcn_gated = false;
1846         } else {
1847                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1848                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1849                         if (ret) {
1850                                 pr_err("[DisableVCNDPM] failed!\n");
1851                                 return ret;
1852                         }
1853                 }
1854                 power_gate->vcn_gated = true;
1855         }
1856
1857         return ret;
1858 }
1859
1860
1861 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
1862                                   uint8_t address, uint32_t numbytes,
1863                                   uint8_t *data)
1864 {
1865         int i;
1866
1867         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
1868
1869         req->I2CcontrollerPort = 0;
1870         req->I2CSpeed = 2;
1871         req->SlaveAddress = address;
1872         req->NumCmds = numbytes;
1873
1874         for (i = 0; i < numbytes; i++) {
1875                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1876
1877                 /* First 2 bytes are always write for lower 2b EEPROM address */
1878                 if (i < 2)
1879                         cmd->Cmd = 1;
1880                 else
1881                         cmd->Cmd = write;
1882
1883
1884                 /* Add RESTART for read  after address filled */
1885                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1886
1887                 /* Add STOP in the end */
1888                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1889
1890                 /* Fill with data regardless if read or write to simplify code */
1891                 cmd->RegisterAddr = data[i];
1892         }
1893 }
1894
1895 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
1896                                                uint8_t address,
1897                                                uint8_t *data,
1898                                                uint32_t numbytes)
1899 {
1900         uint32_t  i, ret = 0;
1901         SwI2cRequest_t req;
1902         struct amdgpu_device *adev = to_amdgpu_device(control);
1903         struct smu_table_context *smu_table = &adev->smu.smu_table;
1904         struct smu_table *table = &smu_table->tables[SMU_TABLE_I2C_COMMANDS];
1905
1906         memset(&req, 0, sizeof(req));
1907         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
1908
1909         mutex_lock(&adev->smu.mutex);
1910         /* Now read data starting with that address */
1911         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1912                                         true);
1913         mutex_unlock(&adev->smu.mutex);
1914
1915         if (!ret) {
1916                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1917
1918                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1919                 for (i = 0; i < numbytes; i++)
1920                         data[i] = res->SwI2cCmds[i].Data;
1921
1922                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
1923                                   (uint16_t)address, numbytes);
1924
1925                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1926                                8, 1, data, numbytes, false);
1927         } else
1928                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
1929
1930         return ret;
1931 }
1932
1933 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
1934                                                 uint8_t address,
1935                                                 uint8_t *data,
1936                                                 uint32_t numbytes)
1937 {
1938         uint32_t ret;
1939         SwI2cRequest_t req;
1940         struct amdgpu_device *adev = to_amdgpu_device(control);
1941
1942         memset(&req, 0, sizeof(req));
1943         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
1944
1945         mutex_lock(&adev->smu.mutex);
1946         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1947         mutex_unlock(&adev->smu.mutex);
1948
1949         if (!ret) {
1950                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1951                                          (uint16_t)address, numbytes);
1952
1953                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1954                                8, 1, data, numbytes, false);
1955                 /*
1956                  * According to EEPROM spec there is a MAX of 10 ms required for
1957                  * EEPROM to flush internal RX buffer after STOP was issued at the
1958                  * end of write transaction. During this time the EEPROM will not be
1959                  * responsive to any more commands - so wait a bit more.
1960                  */
1961                 msleep(10);
1962
1963         } else
1964                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
1965
1966         return ret;
1967 }
1968
1969 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
1970                               struct i2c_msg *msgs, int num)
1971 {
1972         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1973         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1974
1975         for (i = 0; i < num; i++) {
1976                 /*
1977                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1978                  * once and hence the data needs to be spliced into chunks and sent each
1979                  * chunk separately
1980                  */
1981                 data_size = msgs[i].len - 2;
1982                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1983                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1984                 data_ptr = msgs[i].buf + 2;
1985
1986                 for (j = 0; j < data_size / data_chunk_size; j++) {
1987                         /* Insert the EEPROM dest addess, bits 0-15 */
1988                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1989                         data_chunk[1] = (next_eeprom_addr & 0xff);
1990
1991                         if (msgs[i].flags & I2C_M_RD) {
1992                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
1993                                                                 (uint8_t)msgs[i].addr,
1994                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
1995
1996                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1997                         } else {
1998
1999                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2000
2001                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2002                                                                  (uint8_t)msgs[i].addr,
2003                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2004                         }
2005
2006                         if (ret) {
2007                                 num = -EIO;
2008                                 goto fail;
2009                         }
2010
2011                         next_eeprom_addr += data_chunk_size;
2012                         data_ptr += data_chunk_size;
2013                 }
2014
2015                 if (data_size % data_chunk_size) {
2016                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2017                         data_chunk[1] = (next_eeprom_addr & 0xff);
2018
2019                         if (msgs[i].flags & I2C_M_RD) {
2020                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2021                                                                 (uint8_t)msgs[i].addr,
2022                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2023
2024                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2025                         } else {
2026                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2027
2028                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2029                                                                  (uint8_t)msgs[i].addr,
2030                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2031                         }
2032
2033                         if (ret) {
2034                                 num = -EIO;
2035                                 goto fail;
2036                         }
2037                 }
2038         }
2039
2040 fail:
2041         return num;
2042 }
2043
2044 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2045 {
2046         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2047 }
2048
2049
2050 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2051         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2052         .functionality = arcturus_i2c_eeprom_i2c_func,
2053 };
2054
2055 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2056 {
2057         struct amdgpu_device *adev = to_amdgpu_device(control);
2058         int res;
2059
2060         control->owner = THIS_MODULE;
2061         control->class = I2C_CLASS_SPD;
2062         control->dev.parent = &adev->pdev->dev;
2063         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2064         snprintf(control->name, sizeof(control->name), "RAS EEPROM");
2065
2066         res = i2c_add_adapter(control);
2067         if (res)
2068                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2069
2070         return res;
2071 }
2072
2073 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2074 {
2075         i2c_del_adapter(control);
2076 }
2077
2078 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2079 {
2080         PPTable_t *pptable = smu->smu_table.driver_pptable;
2081
2082         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2083 }
2084
2085 static const struct pptable_funcs arcturus_ppt_funcs = {
2086         /* translate smu index into arcturus specific index */
2087         .get_smu_msg_index = arcturus_get_smu_msg_index,
2088         .get_smu_clk_index = arcturus_get_smu_clk_index,
2089         .get_smu_feature_index = arcturus_get_smu_feature_index,
2090         .get_smu_table_index = arcturus_get_smu_table_index,
2091         .get_smu_power_index= arcturus_get_pwr_src_index,
2092         .get_workload_type = arcturus_get_workload_type,
2093         /* internal structurs allocations */
2094         .tables_init = arcturus_tables_init,
2095         .alloc_dpm_context = arcturus_allocate_dpm_context,
2096         /* pptable related */
2097         .check_powerplay_table = arcturus_check_powerplay_table,
2098         .store_powerplay_table = arcturus_store_powerplay_table,
2099         .append_powerplay_table = arcturus_append_powerplay_table,
2100         /* init dpm */
2101         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2102         /* btc */
2103         .run_btc = arcturus_run_btc,
2104         /* dpm/clk tables */
2105         .set_default_dpm_table = arcturus_set_default_dpm_table,
2106         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2107         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2108         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2109         .print_clk_levels = arcturus_print_clk_levels,
2110         .force_clk_levels = arcturus_force_clk_levels,
2111         .read_sensor = arcturus_read_sensor,
2112         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2113         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2114         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2115         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2116         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2117         .get_power_profile_mode = arcturus_get_power_profile_mode,
2118         .set_power_profile_mode = arcturus_set_power_profile_mode,
2119         /* debug (internal used) */
2120         .dump_pptable = arcturus_dump_pptable,
2121         .get_power_limit = arcturus_get_power_limit,
2122         .is_dpm_running = arcturus_is_dpm_running,
2123         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2124         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2125         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2126         .init_microcode = smu_v11_0_init_microcode,
2127         .load_microcode = smu_v11_0_load_microcode,
2128         .init_smc_tables = smu_v11_0_init_smc_tables,
2129         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2130         .init_power = smu_v11_0_init_power,
2131         .fini_power = smu_v11_0_fini_power,
2132         .check_fw_status = smu_v11_0_check_fw_status,
2133         .setup_pptable = smu_v11_0_setup_pptable,
2134         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2135         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2136         .check_pptable = smu_v11_0_check_pptable,
2137         .parse_pptable = smu_v11_0_parse_pptable,
2138         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2139         .check_fw_version = smu_v11_0_check_fw_version,
2140         .write_pptable = smu_v11_0_write_pptable,
2141         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2142         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2143         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2144         .system_features_control = smu_v11_0_system_features_control,
2145         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2146         .read_smc_arg = smu_v11_0_read_arg,
2147         .init_display_count = smu_v11_0_init_display_count,
2148         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2149         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2150         .notify_display_change = smu_v11_0_notify_display_change,
2151         .set_power_limit = smu_v11_0_set_power_limit,
2152         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2153         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2154         .start_thermal_control = smu_v11_0_start_thermal_control,
2155         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2156         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2157         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2158         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2159         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2160         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2161         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2162         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2163         .gfx_off_control = smu_v11_0_gfx_off_control,
2164         .register_irq_handler = smu_v11_0_register_irq_handler,
2165         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2166         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2167         .baco_is_support= smu_v11_0_baco_is_support,
2168         .baco_get_state = smu_v11_0_baco_get_state,
2169         .baco_set_state = smu_v11_0_baco_set_state,
2170         .baco_enter = smu_v11_0_baco_enter,
2171         .baco_exit = smu_v11_0_baco_exit,
2172         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2173         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2174         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2175         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2176 };
2177
2178 void arcturus_set_ppt_funcs(struct smu_context *smu)
2179 {
2180         smu->ppt_funcs = &arcturus_ppt_funcs;
2181 }