drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if_arcturus.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "power_state.h"
  36 #include "arcturus_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "arcturus_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = {1, (index)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 130 };
 131
 132 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 133         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 134         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 135         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 136         CLK_MAP(FCLK, PPCLK_FCLK),
 137         CLK_MAP(UCLK, PPCLK_UCLK),
 138         CLK_MAP(MCLK, PPCLK_UCLK),
 139         CLK_MAP(DCLK, PPCLK_DCLK),
 140         CLK_MAP(VCLK, PPCLK_VCLK),
 141 };
 142
 143 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(DPM_PREFETCHER),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_UCLK),
 147         FEA_MAP(DPM_SOCCLK),
 148         FEA_MAP(DPM_FCLK),
 149         FEA_MAP(DPM_MP0CLK),
 150         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 151         FEA_MAP(DS_GFXCLK),
 152         FEA_MAP(DS_SOCCLK),
 153         FEA_MAP(DS_LCLK),
 154         FEA_MAP(DS_FCLK),
 155         FEA_MAP(DS_UCLK),
 156         FEA_MAP(GFX_ULV),
 157         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 158         FEA_MAP(RSMU_SMN_CG),
 159         FEA_MAP(WAFL_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(APCC_PLUS),
 163         FEA_MAP(VR0HOT),
 164         FEA_MAP(VR1HOT),
 165         FEA_MAP(FW_CTF),
 166         FEA_MAP(FAN_CONTROL),
 167         FEA_MAP(THERMAL),
 168         FEA_MAP(OUT_OF_BAND_MONITOR),
 169         FEA_MAP(TEMP_DEPENDENT_VMIN),
 170 };
 171
 172 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 173         TAB_MAP(PPTABLE),
 174         TAB_MAP(AVFS),
 175         TAB_MAP(AVFS_PSM_DEBUG),
 176         TAB_MAP(AVFS_FUSE_OVERRIDE),
 177         TAB_MAP(PMSTATUSLOG),
 178         TAB_MAP(SMU_METRICS),
 179         TAB_MAP(DRIVER_SMU_CONFIG),
 180         TAB_MAP(OVERDRIVE),
 181         TAB_MAP(I2C_COMMANDS),
 182 };
 183
 184 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 185         PWR_MAP(AC),
 186         PWR_MAP(DC),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 191         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 195 };
 196
 197 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 198 {
 199         struct smu_11_0_cmn2aisc_mapping mapping;
 200
 201         if (index >= SMU_MSG_MAX_COUNT)
 202                 return -EINVAL;
 203
 204         mapping = arcturus_message_map[index];
 205         if (!(mapping.valid_mapping))
 206                 return -EINVAL;
 207
 208         return mapping.map_to;
 209 }
 210
 211 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 212 {
 213         struct smu_11_0_cmn2aisc_mapping mapping;
 214
 215         if (index >= SMU_CLK_COUNT)
 216                 return -EINVAL;
 217
 218         mapping = arcturus_clk_map[index];
 219         if (!(mapping.valid_mapping)) {
 220                 pr_warn("Unsupported SMU clk: %d\n", index);
 221                 return -EINVAL;
 222         }
 223
 224         return mapping.map_to;
 225 }
 226
 227 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 228 {
 229         struct smu_11_0_cmn2aisc_mapping mapping;
 230
 231         if (index >= SMU_FEATURE_COUNT)
 232                 return -EINVAL;
 233
 234         mapping = arcturus_feature_mask_map[index];
 235         if (!(mapping.valid_mapping)) {
 236                 return -EINVAL;
 237         }
 238
 239         return mapping.map_to;
 240 }
 241
 242 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 243 {
 244         struct smu_11_0_cmn2aisc_mapping mapping;
 245
 246         if (index >= SMU_TABLE_COUNT)
 247                 return -EINVAL;
 248
 249         mapping = arcturus_table_map[index];
 250         if (!(mapping.valid_mapping)) {
 251                 pr_warn("Unsupported SMU table: %d\n", index);
 252                 return -EINVAL;
 253         }
 254
 255         return mapping.map_to;
 256 }
 257
 258 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 259 {
 260         struct smu_11_0_cmn2aisc_mapping mapping;
 261
 262         if (index >= SMU_POWER_SOURCE_COUNT)
 263                 return -EINVAL;
 264
 265         mapping = arcturus_pwr_src_map[index];
 266         if (!(mapping.valid_mapping)) {
 267                 pr_warn("Unsupported SMU power source: %d\n", index);
 268                 return -EINVAL;
 269         }
 270
 271         return mapping.map_to;
 272 }
 273
 274
 275 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 280                 return -EINVAL;
 281
 282         mapping = arcturus_workload_map[profile];
 283         if (!(mapping.valid_mapping))
 284                 return -EINVAL;
 285
 286         return mapping.map_to;
 287 }
 288
 289 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 290 {
 291         struct smu_table_context *smu_table = &smu->smu_table;
 292
 293         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 294                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 295
 296         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 297                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 298
 299         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 300                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 301
 302         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 303                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 304
 305         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 306         if (!smu_table->metrics_table)
 307                 return -ENOMEM;
 308         smu_table->metrics_time = 0;
 309
 310         return 0;
 311 }
 312
 313 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 314 {
 315         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 316
 317         if (smu_dpm->dpm_context)
 318                 return -EINVAL;
 319
 320         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 321                                        GFP_KERNEL);
 322         if (!smu_dpm->dpm_context)
 323                 return -ENOMEM;
 324
 325         if (smu_dpm->golden_dpm_context)
 326                 return -EINVAL;
 327
 328         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 329                                               GFP_KERNEL);
 330         if (!smu_dpm->golden_dpm_context)
 331                 return -ENOMEM;
 332
 333         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 334
 335         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 336                                        GFP_KERNEL);
 337         if (!smu_dpm->dpm_current_power_state)
 338                 return -ENOMEM;
 339
 340         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 341                                        GFP_KERNEL);
 342         if (!smu_dpm->dpm_request_power_state)
 343                 return -ENOMEM;
 344
 345         return 0;
 346 }
 347
 348 static int
 349 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 350                                   uint32_t *feature_mask, uint32_t num)
 351 {
 352         if (num > 2)
 353                 return -EINVAL;
 354
 355         /* pptable will handle the features to enable */
 356         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 357
 358         return 0;
 359 }
 360
 361 static int
 362 arcturus_set_single_dpm_table(struct smu_context *smu,
 363                             struct arcturus_single_dpm_table *single_dpm_table,
 364                             PPCLK_e clk_id)
 365 {
 366         int ret = 0;
 367         uint32_t i, num_of_levels = 0, clk;
 368
 369         ret = smu_send_smc_msg_with_param(smu,
 370                         SMU_MSG_GetDpmFreqByIndex,
 371                         (clk_id << 16 | 0xFF));
 372         if (ret) {
 373                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 374                 return ret;
 375         }
 376
 377         smu_read_smc_arg(smu, &num_of_levels);
 378         if (!num_of_levels) {
 379                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 380                 return -EINVAL;
 381         }
 382
 383         single_dpm_table->count = num_of_levels;
 384         for (i = 0; i < num_of_levels; i++) {
 385                 ret = smu_send_smc_msg_with_param(smu,
 386                                 SMU_MSG_GetDpmFreqByIndex,
 387                                 (clk_id << 16 | i));
 388                 if (ret) {
 389                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 390                         return ret;
 391                 }
 392                 smu_read_smc_arg(smu, &clk);
 393                 if (!clk) {
 394                         pr_err("[%s] clk value is invalid!\n", __func__);
 395                         return -EINVAL;
 396                 }
 397                 single_dpm_table->dpm_levels[i].value = clk;
 398                 single_dpm_table->dpm_levels[i].enabled = true;
 399         }
 400         return 0;
 401 }
 402
 403 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 404 {
 405         dpm_state->soft_min_level = 0x0;
 406         dpm_state->soft_max_level = 0xffff;
 407         dpm_state->hard_min_level = 0x0;
 408         dpm_state->hard_max_level = 0xffff;
 409 }
 410
 411 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 412 {
 413         int ret;
 414
 415         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 416         struct arcturus_dpm_table *dpm_table = NULL;
 417         struct arcturus_single_dpm_table *single_dpm_table;
 418
 419         dpm_table = smu_dpm->dpm_context;
 420
 421         /* socclk */
 422         single_dpm_table = &(dpm_table->soc_table);
 423         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 424                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 425                                                   PPCLK_SOCCLK);
 426                 if (ret) {
 427                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 428                         return ret;
 429                 }
 430         } else {
 431                 single_dpm_table->count = 1;
 432                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 433         }
 434         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 435
 436         /* gfxclk */
 437         single_dpm_table = &(dpm_table->gfx_table);
 438         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 439                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 440                                                   PPCLK_GFXCLK);
 441                 if (ret) {
 442                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 443                         return ret;
 444                 }
 445         } else {
 446                 single_dpm_table->count = 1;
 447                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 448         }
 449         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 450
 451         /* memclk */
 452         single_dpm_table = &(dpm_table->mem_table);
 453         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 454                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 455                                                   PPCLK_UCLK);
 456                 if (ret) {
 457                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 458                         return ret;
 459                 }
 460         } else {
 461                 single_dpm_table->count = 1;
 462                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 463         }
 464         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 465
 466         /* fclk */
 467         single_dpm_table = &(dpm_table->fclk_table);
 468         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 469                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 470                                                   PPCLK_FCLK);
 471                 if (ret) {
 472                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 473                         return ret;
 474                 }
 475         } else {
 476                 single_dpm_table->count = 1;
 477                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 478         }
 479         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 480
 481         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 482                sizeof(struct arcturus_dpm_table));
 483
 484         return 0;
 485 }
 486
 487 static int arcturus_check_powerplay_table(struct smu_context *smu)
 488 {
 489         return 0;
 490 }
 491
 492 static int arcturus_store_powerplay_table(struct smu_context *smu)
 493 {
 494         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 495         struct smu_table_context *table_context = &smu->smu_table;
 496         struct smu_baco_context *smu_baco = &smu->smu_baco;
 497         int ret = 0;
 498
 499         if (!table_context->power_play_table)
 500                 return -EINVAL;
 501
 502         powerplay_table = table_context->power_play_table;
 503
 504         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 505                sizeof(PPTable_t));
 506
 507         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 508
 509         mutex_lock(&smu_baco->mutex);
 510         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 511             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 512                 smu_baco->platform_support = true;
 513         mutex_unlock(&smu_baco->mutex);
 514
 515         return ret;
 516 }
 517
 518 static int arcturus_append_powerplay_table(struct smu_context *smu)
 519 {
 520         struct smu_table_context *table_context = &smu->smu_table;
 521         PPTable_t *smc_pptable = table_context->driver_pptable;
 522         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 523         int index, ret;
 524
 525         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 526                                            smc_dpm_info);
 527
 528         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 529                                       (uint8_t **)&smc_dpm_table);
 530         if (ret)
 531                 return ret;
 532
 533         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 534                         smc_dpm_table->table_header.format_revision,
 535                         smc_dpm_table->table_header.content_revision);
 536
 537         if ((smc_dpm_table->table_header.format_revision == 4) &&
 538             (smc_dpm_table->table_header.content_revision == 6))
 539                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 540                        &smc_dpm_table->maxvoltagestepgfx,
 541                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 542
 543         return 0;
 544 }
 545
 546 static int arcturus_run_btc(struct smu_context *smu)
 547 {
 548         int ret = 0;
 549
 550         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 551         if (ret) {
 552                 pr_err("RunAfllBtc failed!\n");
 553                 return ret;
 554         }
 555
 556         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
 557 }
 558
 559 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 560 {
 561         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 562         struct arcturus_dpm_table *dpm_table = NULL;
 563         struct arcturus_single_dpm_table *gfx_table = NULL;
 564         struct arcturus_single_dpm_table *mem_table = NULL;
 565
 566         dpm_table = smu_dpm->dpm_context;
 567         gfx_table = &(dpm_table->gfx_table);
 568         mem_table = &(dpm_table->mem_table);
 569
 570         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 571         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 572
 573         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 574             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 575                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 576                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 577         }
 578
 579         smu->pstate_sclk = smu->pstate_sclk * 100;
 580         smu->pstate_mclk = smu->pstate_mclk * 100;
 581
 582         return 0;
 583 }
 584
 585 static int arcturus_get_clk_table(struct smu_context *smu,
 586                         struct pp_clock_levels_with_latency *clocks,
 587                         struct arcturus_single_dpm_table *dpm_table)
 588 {
 589         int i, count;
 590
 591         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 592         clocks->num_levels = count;
 593
 594         for (i = 0; i < count; i++) {
 595                 clocks->data[i].clocks_in_khz =
 596                         dpm_table->dpm_levels[i].value * 1000;
 597                 clocks->data[i].latency_in_us = 0;
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int arcturus_freqs_in_same_level(int32_t frequency1,
 604                                         int32_t frequency2)
 605 {
 606         return (abs(frequency1 - frequency2) <= EPSILON);
 607 }
 608
 609 static int arcturus_print_clk_levels(struct smu_context *smu,
 610                         enum smu_clk_type type, char *buf)
 611 {
 612         int i, now, size = 0;
 613         int ret = 0;
 614         struct pp_clock_levels_with_latency clocks;
 615         struct arcturus_single_dpm_table *single_dpm_table;
 616         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 617         struct arcturus_dpm_table *dpm_table = NULL;
 618
 619         dpm_table = smu_dpm->dpm_context;
 620
 621         switch (type) {
 622         case SMU_SCLK:
 623                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 624                 if (ret) {
 625                         pr_err("Attempt to get current gfx clk Failed!");
 626                         return ret;
 627                 }
 628
 629                 single_dpm_table = &(dpm_table->gfx_table);
 630                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 631                 if (ret) {
 632                         pr_err("Attempt to get gfx clk levels Failed!");
 633                         return ret;
 634                 }
 635
 636                 /*
 637                  * For DPM disabled case, there will be only one clock level.
 638                  * And it's safe to assume that is always the current clock.
 639                  */
 640                 for (i = 0; i < clocks.num_levels; i++)
 641                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 642                                         clocks.data[i].clocks_in_khz / 1000,
 643                                         (clocks.num_levels == 1) ? "*" :
 644                                         (arcturus_freqs_in_same_level(
 645                                         clocks.data[i].clocks_in_khz / 1000,
 646                                         now / 100) ? "*" : ""));
 647                 break;
 648
 649         case SMU_MCLK:
 650                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 651                 if (ret) {
 652                         pr_err("Attempt to get current mclk Failed!");
 653                         return ret;
 654                 }
 655
 656                 single_dpm_table = &(dpm_table->mem_table);
 657                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 658                 if (ret) {
 659                         pr_err("Attempt to get memory clk levels Failed!");
 660                         return ret;
 661                 }
 662
 663                 for (i = 0; i < clocks.num_levels; i++)
 664                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 665                                 i, clocks.data[i].clocks_in_khz / 1000,
 666                                 (clocks.num_levels == 1) ? "*" :
 667                                 (arcturus_freqs_in_same_level(
 668                                 clocks.data[i].clocks_in_khz / 1000,
 669                                 now / 100) ? "*" : ""));
 670                 break;
 671
 672         case SMU_SOCCLK:
 673                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 674                 if (ret) {
 675                         pr_err("Attempt to get current socclk Failed!");
 676                         return ret;
 677                 }
 678
 679                 single_dpm_table = &(dpm_table->soc_table);
 680                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 681                 if (ret) {
 682                         pr_err("Attempt to get socclk levels Failed!");
 683                         return ret;
 684                 }
 685
 686                 for (i = 0; i < clocks.num_levels; i++)
 687                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 688                                 i, clocks.data[i].clocks_in_khz / 1000,
 689                                 (clocks.num_levels == 1) ? "*" :
 690                                 (arcturus_freqs_in_same_level(
 691                                 clocks.data[i].clocks_in_khz / 1000,
 692                                 now / 100) ? "*" : ""));
 693                 break;
 694
 695         case SMU_FCLK:
 696                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 697                 if (ret) {
 698                         pr_err("Attempt to get current fclk Failed!");
 699                         return ret;
 700                 }
 701
 702                 single_dpm_table = &(dpm_table->fclk_table);
 703                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 704                 if (ret) {
 705                         pr_err("Attempt to get fclk levels Failed!");
 706                         return ret;
 707                 }
 708
 709                 for (i = 0; i < single_dpm_table->count; i++)
 710                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 711                                 i, single_dpm_table->dpm_levels[i].value,
 712                                 (clocks.num_levels == 1) ? "*" :
 713                                 (arcturus_freqs_in_same_level(
 714                                 clocks.data[i].clocks_in_khz / 1000,
 715                                 now / 100) ? "*" : ""));
 716                 break;
 717
 718         default:
 719                 break;
 720         }
 721
 722         return size;
 723 }
 724
 725 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 726                                      uint32_t feature_mask)
 727 {
 728         struct arcturus_single_dpm_table *single_dpm_table;
 729         struct arcturus_dpm_table *dpm_table =
 730                         smu->smu_dpm.dpm_context;
 731         uint32_t freq;
 732         int ret = 0;
 733
 734         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 735             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 736                 single_dpm_table = &(dpm_table->gfx_table);
 737                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 738                         single_dpm_table->dpm_state.soft_min_level;
 739                 ret = smu_send_smc_msg_with_param(smu,
 740                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 741                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
 742                 if (ret) {
 743                         pr_err("Failed to set soft %s gfxclk !\n",
 744                                                 max ? "max" : "min");
 745                         return ret;
 746                 }
 747         }
 748
 749         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 750             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 751                 single_dpm_table = &(dpm_table->mem_table);
 752                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 753                         single_dpm_table->dpm_state.soft_min_level;
 754                 ret = smu_send_smc_msg_with_param(smu,
 755                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 756                         (PPCLK_UCLK << 16) | (freq & 0xffff));
 757                 if (ret) {
 758                         pr_err("Failed to set soft %s memclk !\n",
 759                                                 max ? "max" : "min");
 760                         return ret;
 761                 }
 762         }
 763
 764         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 765             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 766                 single_dpm_table = &(dpm_table->soc_table);
 767                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 768                         single_dpm_table->dpm_state.soft_min_level;
 769                 ret = smu_send_smc_msg_with_param(smu,
 770                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 771                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
 772                 if (ret) {
 773                         pr_err("Failed to set soft %s socclk !\n",
 774                                                 max ? "max" : "min");
 775                         return ret;
 776                 }
 777         }
 778
 779         return ret;
 780 }
 781
 782 static int arcturus_force_clk_levels(struct smu_context *smu,
 783                         enum smu_clk_type type, uint32_t mask)
 784 {
 785         struct arcturus_dpm_table *dpm_table;
 786         struct arcturus_single_dpm_table *single_dpm_table;
 787         uint32_t soft_min_level, soft_max_level;
 788         int ret = 0;
 789
 790         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 791         soft_max_level = mask ? (fls(mask) - 1) : 0;
 792
 793         dpm_table = smu->smu_dpm.dpm_context;
 794
 795         switch (type) {
 796         case SMU_SCLK:
 797                 single_dpm_table = &(dpm_table->gfx_table);
 798
 799                 if (soft_max_level >= single_dpm_table->count) {
 800                         pr_err("Clock level specified %d is over max allowed %d\n",
 801                                         soft_max_level, single_dpm_table->count - 1);
 802                         ret = -EINVAL;
 803                         break;
 804                 }
 805
 806                 single_dpm_table->dpm_state.soft_min_level =
 807                         single_dpm_table->dpm_levels[soft_min_level].value;
 808                 single_dpm_table->dpm_state.soft_max_level =
 809                         single_dpm_table->dpm_levels[soft_max_level].value;
 810
 811                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 812                 if (ret) {
 813                         pr_err("Failed to upload boot level to lowest!\n");
 814                         break;
 815                 }
 816
 817                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 818                 if (ret)
 819                         pr_err("Failed to upload dpm max level to highest!\n");
 820
 821                 break;
 822
 823         case SMU_MCLK:
 824         case SMU_SOCCLK:
 825         case SMU_FCLK:
 826                 /*
 827                  * Should not arrive here since Arcturus does not
 828                  * support mclk/socclk/fclk softmin/softmax settings
 829                  */
 830                 ret = -EINVAL;
 831                 break;
 832
 833         default:
 834                 break;
 835         }
 836
 837         return ret;
 838 }
 839
 840 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 841                                                 struct smu_temperature_range *range)
 842 {
 843         PPTable_t *pptable = smu->smu_table.driver_pptable;
 844
 845         if (!range)
 846                 return -EINVAL;
 847
 848         range->max = pptable->TedgeLimit *
 849                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 850         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 851                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 852         range->hotspot_crit_max = pptable->ThotspotLimit *
 853                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 854         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 855                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 856         range->mem_crit_max = pptable->TmemLimit *
 857                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 858         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 859                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 860
 861         return 0;
 862 }
 863
 864 static int arcturus_get_metrics_table(struct smu_context *smu,
 865                                       SmuMetrics_t *metrics_table)
 866 {
 867         struct smu_table_context *smu_table= &smu->smu_table;
 868         int ret = 0;
 869
 870         if (!smu_table->metrics_time ||
 871              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 872                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 873                                 (void *)smu_table->metrics_table, false);
 874                 if (ret) {
 875                         pr_info("Failed to export SMU metrics table!\n");
 876                         return ret;
 877                 }
 878                 smu_table->metrics_time = jiffies;
 879         }
 880
 881         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 882
 883         return ret;
 884 }
 885
 886 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 887                                                  enum amd_pp_sensors sensor,
 888                                                  uint32_t *value)
 889 {
 890         SmuMetrics_t metrics;
 891         int ret = 0;
 892
 893         if (!value)
 894                 return -EINVAL;
 895
 896         ret = arcturus_get_metrics_table(smu, &metrics);
 897         if (ret)
 898                 return ret;
 899
 900         switch (sensor) {
 901         case AMDGPU_PP_SENSOR_GPU_LOAD:
 902                 *value = metrics.AverageGfxActivity;
 903                 break;
 904         case AMDGPU_PP_SENSOR_MEM_LOAD:
 905                 *value = metrics.AverageUclkActivity;
 906                 break;
 907         default:
 908                 pr_err("Invalid sensor for retrieving clock activity\n");
 909                 return -EINVAL;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 916 {
 917         SmuMetrics_t metrics;
 918         int ret = 0;
 919
 920         if (!value)
 921                 return -EINVAL;
 922
 923         ret = arcturus_get_metrics_table(smu, &metrics);
 924         if (ret)
 925                 return ret;
 926
 927         *value = metrics.AverageSocketPower << 8;
 928
 929         return 0;
 930 }
 931
 932 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 933                                             enum amd_pp_sensors sensor,
 934                                             uint32_t *value)
 935 {
 936         SmuMetrics_t metrics;
 937         int ret = 0;
 938
 939         if (!value)
 940                 return -EINVAL;
 941
 942         ret = arcturus_get_metrics_table(smu, &metrics);
 943         if (ret)
 944                 return ret;
 945
 946         switch (sensor) {
 947         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 948                 *value = metrics.TemperatureHotspot *
 949                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 950                 break;
 951         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 952                 *value = metrics.TemperatureEdge *
 953                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 954                 break;
 955         case AMDGPU_PP_SENSOR_MEM_TEMP:
 956                 *value = metrics.TemperatureHBM *
 957                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 958                 break;
 959         default:
 960                 pr_err("Invalid sensor for retrieving temp\n");
 961                 return -EINVAL;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int arcturus_read_sensor(struct smu_context *smu,
 968                                 enum amd_pp_sensors sensor,
 969                                 void *data, uint32_t *size)
 970 {
 971         struct smu_table_context *table_context = &smu->smu_table;
 972         PPTable_t *pptable = table_context->driver_pptable;
 973         int ret = 0;
 974
 975         if (!data || !size)
 976                 return -EINVAL;
 977
 978         mutex_lock(&smu->sensor_lock);
 979         switch (sensor) {
 980         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 981                 *(uint32_t *)data = pptable->FanMaximumRpm;
 982                 *size = 4;
 983                 break;
 984         case AMDGPU_PP_SENSOR_MEM_LOAD:
 985         case AMDGPU_PP_SENSOR_GPU_LOAD:
 986                 ret = arcturus_get_current_activity_percent(smu,
 987                                                             sensor,
 988                                                 (uint32_t *)data);
 989                 *size = 4;
 990                 break;
 991         case AMDGPU_PP_SENSOR_GPU_POWER:
 992                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
 993                 *size = 4;
 994                 break;
 995         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 996         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 997         case AMDGPU_PP_SENSOR_MEM_TEMP:
 998                 ret = arcturus_thermal_get_temperature(smu, sensor,
 999                                                 (uint32_t *)data);
1000                 *size = 4;
1001                 break;
1002         default:
1003                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1004         }
1005         mutex_unlock(&smu->sensor_lock);
1006
1007         return ret;
1008 }
1009
1010 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1011                                       uint32_t *speed)
1012 {
1013         SmuMetrics_t metrics;
1014         int ret = 0;
1015
1016         if (!speed)
1017                 return -EINVAL;
1018
1019         ret = arcturus_get_metrics_table(smu, &metrics);
1020         if (ret)
1021                 return ret;
1022
1023         *speed = metrics.CurrFanSpeed;
1024
1025         return ret;
1026 }
1027
1028 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1029                                           uint32_t *speed)
1030 {
1031         PPTable_t *pptable = smu->smu_table.driver_pptable;
1032         uint32_t percent, current_rpm;
1033         int ret = 0;
1034
1035         if (!speed)
1036                 return -EINVAL;
1037
1038         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1039         if (ret)
1040                 return ret;
1041
1042         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1043         *speed = percent > 100 ? 100 : percent;
1044
1045         return ret;
1046 }
1047
1048 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1049                                        enum smu_clk_type clk_type,
1050                                        uint32_t *value)
1051 {
1052         static SmuMetrics_t metrics;
1053         int ret = 0, clk_id = 0;
1054
1055         if (!value)
1056                 return -EINVAL;
1057
1058         clk_id = smu_clk_get_index(smu, clk_type);
1059         if (clk_id < 0)
1060                 return -EINVAL;
1061
1062         ret = arcturus_get_metrics_table(smu, &metrics);
1063         if (ret)
1064                 return ret;
1065
1066         switch (clk_id) {
1067         case PPCLK_GFXCLK:
1068                 /*
1069                  * CurrClock[clk_id] can provide accurate
1070                  *   output only when the dpm feature is enabled.
1071                  * We can use Average_* for dpm disabled case.
1072                  *   But this is available for gfxclk/uclk/socclk.
1073                  */
1074                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1075                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1076                 else
1077                         *value = metrics.AverageGfxclkFrequency;
1078                 break;
1079         case PPCLK_UCLK:
1080                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1081                         *value = metrics.CurrClock[PPCLK_UCLK];
1082                 else
1083                         *value = metrics.AverageUclkFrequency;
1084                 break;
1085         case PPCLK_SOCCLK:
1086                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1087                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1088                 else
1089                         *value = metrics.AverageSocclkFrequency;
1090                 break;
1091         default:
1092                 *value = metrics.CurrClock[clk_id];
1093                 break;
1094         }
1095
1096         return ret;
1097 }
1098
1099 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1100 {
1101         uint32_t i;
1102
1103         for (i = 0; i < table->count; i++) {
1104                 if (table->dpm_levels[i].enabled)
1105                         break;
1106         }
1107         if (i >= table->count) {
1108                 i = 0;
1109                 table->dpm_levels[i].enabled = true;
1110         }
1111
1112         return i;
1113 }
1114
1115 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1116 {
1117         int i = 0;
1118
1119         if (table->count <= 0) {
1120                 pr_err("[%s] DPM Table has no entry!", __func__);
1121                 return 0;
1122         }
1123         if (table->count > MAX_DPM_NUMBER) {
1124                 pr_err("[%s] DPM Table has too many entries!", __func__);
1125                 return MAX_DPM_NUMBER - 1;
1126         }
1127
1128         for (i = table->count - 1; i >= 0; i--) {
1129                 if (table->dpm_levels[i].enabled)
1130                         break;
1131         }
1132         if (i < 0) {
1133                 i = 0;
1134                 table->dpm_levels[i].enabled = true;
1135         }
1136
1137         return i;
1138 }
1139
1140
1141
1142 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1143 {
1144         struct arcturus_dpm_table *dpm_table =
1145                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1146         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1147         uint32_t soft_level;
1148         int ret = 0;
1149
1150         /* gfxclk */
1151         if (highest)
1152                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1153         else
1154                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1155
1156         dpm_table->gfx_table.dpm_state.soft_min_level =
1157                 dpm_table->gfx_table.dpm_state.soft_max_level =
1158                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1159
1160         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1161         if (ret) {
1162                 pr_err("Failed to upload boot level to %s!\n",
1163                                 highest ? "highest" : "lowest");
1164                 return ret;
1165         }
1166
1167         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1168         if (ret) {
1169                 pr_err("Failed to upload dpm max level to %s!\n!",
1170                                 highest ? "highest" : "lowest");
1171                 return ret;
1172         }
1173
1174         if (hive)
1175                 /*
1176                  * Force XGMI Pstate to highest or lowest
1177                  * TODO: revise this when xgmi dpm is functional
1178                  */
1179                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1180
1181         return ret;
1182 }
1183
1184 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1185 {
1186         struct arcturus_dpm_table *dpm_table =
1187                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1188         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1189         uint32_t soft_min_level, soft_max_level;
1190         int ret = 0;
1191
1192         /* gfxclk */
1193         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1194         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1195         dpm_table->gfx_table.dpm_state.soft_min_level =
1196                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1197         dpm_table->gfx_table.dpm_state.soft_max_level =
1198                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1199
1200         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1201         if (ret) {
1202                 pr_err("Failed to upload DPM Bootup Levels!");
1203                 return ret;
1204         }
1205
1206         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1207         if (ret) {
1208                 pr_err("Failed to upload DPM Max Levels!");
1209                 return ret;
1210         }
1211
1212         if (hive)
1213                 /*
1214                  * Reset XGMI Pstate back to default
1215                  * TODO: revise this when xgmi dpm is functional
1216                  */
1217                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1218
1219         return ret;
1220 }
1221
1222 static int
1223 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1224                                 enum amd_dpm_forced_level level,
1225                                 uint32_t *sclk_mask,
1226                                 uint32_t *mclk_mask,
1227                                 uint32_t *soc_mask)
1228 {
1229         struct arcturus_dpm_table *dpm_table =
1230                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1231         struct arcturus_single_dpm_table *gfx_dpm_table;
1232         struct arcturus_single_dpm_table *mem_dpm_table;
1233         struct arcturus_single_dpm_table *soc_dpm_table;
1234
1235         if (!smu->smu_dpm.dpm_context)
1236                 return -EINVAL;
1237
1238         gfx_dpm_table = &dpm_table->gfx_table;
1239         mem_dpm_table = &dpm_table->mem_table;
1240         soc_dpm_table = &dpm_table->soc_table;
1241
1242         *sclk_mask = 0;
1243         *mclk_mask = 0;
1244         *soc_mask  = 0;
1245
1246         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1247             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1248             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1249                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1250                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1251                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1252         }
1253
1254         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1255                 *sclk_mask = 0;
1256         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1257                 *mclk_mask = 0;
1258         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1259                 *sclk_mask = gfx_dpm_table->count - 1;
1260                 *mclk_mask = mem_dpm_table->count - 1;
1261                 *soc_mask  = soc_dpm_table->count - 1;
1262         }
1263
1264         return 0;
1265 }
1266
1267 static int arcturus_get_power_limit(struct smu_context *smu,
1268                                      uint32_t *limit,
1269                                      bool cap)
1270 {
1271         PPTable_t *pptable = smu->smu_table.driver_pptable;
1272         uint32_t asic_default_power_limit = 0;
1273         int ret = 0;
1274         int power_src;
1275
1276         if (!smu->power_limit) {
1277                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1278                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1279                         if (power_src < 0)
1280                                 return -EINVAL;
1281
1282                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1283                                 power_src << 16);
1284                         if (ret) {
1285                                 pr_err("[%s] get PPT limit failed!", __func__);
1286                                 return ret;
1287                         }
1288                         smu_read_smc_arg(smu, &asic_default_power_limit);
1289                 } else {
1290                         /* the last hope to figure out the ppt limit */
1291                         if (!pptable) {
1292                                 pr_err("Cannot get PPT limit due to pptable missing!");
1293                                 return -EINVAL;
1294                         }
1295                         asic_default_power_limit =
1296                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1297                 }
1298
1299                 smu->power_limit = asic_default_power_limit;
1300         }
1301
1302         if (cap)
1303                 *limit = smu_v11_0_get_max_power_limit(smu);
1304         else
1305                 *limit = smu->power_limit;
1306
1307         return 0;
1308 }
1309
1310 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1311                                            char *buf)
1312 {
1313         static const char *profile_name[] = {
1314                                         "BOOTUP_DEFAULT",
1315                                         "3D_FULL_SCREEN",
1316                                         "POWER_SAVING",
1317                                         "VIDEO",
1318                                         "VR",
1319                                         "COMPUTE",
1320                                         "CUSTOM"};
1321         static const char *title[] = {
1322                         "PROFILE_INDEX(NAME)"};
1323         uint32_t i, size = 0;
1324         int16_t workload_type = 0;
1325
1326         if (!smu->pm_enabled || !buf)
1327                 return -EINVAL;
1328
1329         size += sprintf(buf + size, "%16s\n",
1330                         title[0]);
1331
1332         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1333                 /*
1334                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1335                  * Not all profile modes are supported on arcturus.
1336                  */
1337                 workload_type = smu_workload_get_type(smu, i);
1338                 if (workload_type < 0)
1339                         continue;
1340
1341                 size += sprintf(buf + size, "%2d %14s%s\n",
1342                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1343         }
1344
1345         return size;
1346 }
1347
1348 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1349                                            long *input,
1350                                            uint32_t size)
1351 {
1352         int workload_type = 0;
1353         uint32_t profile_mode = input[size];
1354         int ret = 0;
1355
1356         if (!smu->pm_enabled)
1357                 return -EINVAL;
1358
1359         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1360                 pr_err("Invalid power profile mode %d\n", profile_mode);
1361                 return -EINVAL;
1362         }
1363
1364         /*
1365          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1366          * Not all profile modes are supported on arcturus.
1367          */
1368         workload_type = smu_workload_get_type(smu, profile_mode);
1369         if (workload_type < 0) {
1370                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1371                 return -EINVAL;
1372         }
1373
1374         ret = smu_send_smc_msg_with_param(smu,
1375                                           SMU_MSG_SetWorkloadMask,
1376                                           1 << workload_type);
1377         if (ret) {
1378                 pr_err("Fail to set workload type %d\n", workload_type);
1379                 return ret;
1380         }
1381
1382         smu->power_profile_mode = profile_mode;
1383
1384         return 0;
1385 }
1386
1387 static void arcturus_dump_pptable(struct smu_context *smu)
1388 {
1389         struct smu_table_context *table_context = &smu->smu_table;
1390         PPTable_t *pptable = table_context->driver_pptable;
1391         int i;
1392
1393         pr_info("Dumped PPTable:\n");
1394
1395         pr_info("Version = 0x%08x\n", pptable->Version);
1396
1397         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1398         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1399
1400         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1401                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1402                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1403         }
1404
1405         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1406         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1407         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1408         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1409
1410         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1411         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1412         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1413         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1414         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1415         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1416         pr_info("FitLimit = %d\n", pptable->FitLimit);
1417
1418         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1419         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1420
1421         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1422
1423         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1424         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1425
1426         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1427         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1428         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1429         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1430
1431         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1432         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1433         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1434         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1435
1436         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1437         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1438
1439         pr_info("[PPCLK_GFXCLK]\n"
1440                         "  .VoltageMode          = 0x%02x\n"
1441                         "  .SnapToDiscrete       = 0x%02x\n"
1442                         "  .NumDiscreteLevels    = 0x%02x\n"
1443                         "  .padding              = 0x%02x\n"
1444                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1445                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1446                         "  .SsFmin               = 0x%04x\n"
1447                         "  .Padding_16           = 0x%04x\n",
1448                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1449                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1450                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1451                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1452                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1453                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1454                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1455                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1456                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1457                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1458                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1459
1460         pr_info("[PPCLK_VCLK]\n"
1461                         "  .VoltageMode          = 0x%02x\n"
1462                         "  .SnapToDiscrete       = 0x%02x\n"
1463                         "  .NumDiscreteLevels    = 0x%02x\n"
1464                         "  .padding              = 0x%02x\n"
1465                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1466                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1467                         "  .SsFmin               = 0x%04x\n"
1468                         "  .Padding_16           = 0x%04x\n",
1469                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1470                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1471                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1472                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1473                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1474                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1475                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1476                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1477                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1478                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1479                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1480
1481         pr_info("[PPCLK_DCLK]\n"
1482                         "  .VoltageMode          = 0x%02x\n"
1483                         "  .SnapToDiscrete       = 0x%02x\n"
1484                         "  .NumDiscreteLevels    = 0x%02x\n"
1485                         "  .padding              = 0x%02x\n"
1486                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1487                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1488                         "  .SsFmin               = 0x%04x\n"
1489                         "  .Padding_16           = 0x%04x\n",
1490                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1491                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1492                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1493                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1494                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1495                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1496                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1497                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1498                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1499                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1500                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1501
1502         pr_info("[PPCLK_SOCCLK]\n"
1503                         "  .VoltageMode          = 0x%02x\n"
1504                         "  .SnapToDiscrete       = 0x%02x\n"
1505                         "  .NumDiscreteLevels    = 0x%02x\n"
1506                         "  .padding              = 0x%02x\n"
1507                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1508                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1509                         "  .SsFmin               = 0x%04x\n"
1510                         "  .Padding_16           = 0x%04x\n",
1511                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1512                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1513                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1514                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1515                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1516                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1517                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1518                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1519                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1520                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1521                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1522
1523         pr_info("[PPCLK_UCLK]\n"
1524                         "  .VoltageMode          = 0x%02x\n"
1525                         "  .SnapToDiscrete       = 0x%02x\n"
1526                         "  .NumDiscreteLevels    = 0x%02x\n"
1527                         "  .padding              = 0x%02x\n"
1528                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1529                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1530                         "  .SsFmin               = 0x%04x\n"
1531                         "  .Padding_16           = 0x%04x\n",
1532                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1533                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1534                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1535                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1536                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1537                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1538                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1539                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1540                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1541                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1542                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1543
1544         pr_info("[PPCLK_FCLK]\n"
1545                         "  .VoltageMode          = 0x%02x\n"
1546                         "  .SnapToDiscrete       = 0x%02x\n"
1547                         "  .NumDiscreteLevels    = 0x%02x\n"
1548                         "  .padding              = 0x%02x\n"
1549                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1550                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1551                         "  .SsFmin               = 0x%04x\n"
1552                         "  .Padding_16           = 0x%04x\n",
1553                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1554                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1555                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1556                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1557                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1558                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1559                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1560                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1561                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1562                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1563                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1564
1565
1566         pr_info("FreqTableGfx\n");
1567         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1568                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1569
1570         pr_info("FreqTableVclk\n");
1571         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1572                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1573
1574         pr_info("FreqTableDclk\n");
1575         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1576                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1577
1578         pr_info("FreqTableSocclk\n");
1579         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1580                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1581
1582         pr_info("FreqTableUclk\n");
1583         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1584                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1585
1586         pr_info("FreqTableFclk\n");
1587         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1588                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1589
1590         pr_info("Mp0clkFreq\n");
1591         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1592                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1593
1594         pr_info("Mp0DpmVoltage\n");
1595         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1596                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1597
1598         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1599         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1600         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1601         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1602         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1603         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1604         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1605         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1606         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1607
1608         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1609         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1610         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1611         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1612
1613         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1614         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1615
1616         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1617         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1618         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1619         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1620         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1621         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1622
1623         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1624         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1625         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1626         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1627         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1628         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1629         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1630         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1631         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1632
1633         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1634         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1635         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1636         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1637
1638         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1639         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1640         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1641         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1642
1643         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1644                         pptable->dBtcGbGfxPll.a,
1645                         pptable->dBtcGbGfxPll.b,
1646                         pptable->dBtcGbGfxPll.c);
1647         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1648                         pptable->dBtcGbGfxAfll.a,
1649                         pptable->dBtcGbGfxAfll.b,
1650                         pptable->dBtcGbGfxAfll.c);
1651         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1652                         pptable->dBtcGbSoc.a,
1653                         pptable->dBtcGbSoc.b,
1654                         pptable->dBtcGbSoc.c);
1655
1656         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1657                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1658                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1659         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1660                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1661                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1662
1663         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1664                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1665                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1666                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1667         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1668                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1669                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1670                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1671
1672         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1673         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1674
1675         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1676         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1677         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1678         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1679
1680         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1681         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1682         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1683         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1684
1685         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1686         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1687
1688         pr_info("XgmiDpmPstates\n");
1689         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1690                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1691         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1692         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1693
1694         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1695         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1696         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1697         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1698         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1699         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1700         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1701         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1702
1703         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1704         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1705                         pptable->ReservedEquation0.a,
1706                         pptable->ReservedEquation0.b,
1707                         pptable->ReservedEquation0.c);
1708         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1709                         pptable->ReservedEquation1.a,
1710                         pptable->ReservedEquation1.b,
1711                         pptable->ReservedEquation1.c);
1712         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1713                         pptable->ReservedEquation2.a,
1714                         pptable->ReservedEquation2.b,
1715                         pptable->ReservedEquation2.c);
1716         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1717                         pptable->ReservedEquation3.a,
1718                         pptable->ReservedEquation3.b,
1719                         pptable->ReservedEquation3.c);
1720
1721         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1722         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1723
1724         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1725         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1726         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1727
1728         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1729         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1730
1731         pr_info("Board Parameters:\n");
1732         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1733         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1734
1735         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1736         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1737         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1738         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1739
1740         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1741         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1742
1743         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1744         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1745         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1746
1747         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1748         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1749         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1750
1751         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1752         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1753         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1754
1755         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1756         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1757         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1758
1759         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1760         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1761         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1762         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1763
1764         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1765         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1766         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1767
1768         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1769         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1770         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1771
1772         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1773         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1774         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1775
1776         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1777         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1778         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1779
1780         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1781                 pr_info("I2cControllers[%d]:\n", i);
1782                 pr_info("                   .Enabled = %d\n",
1783                                 pptable->I2cControllers[i].Enabled);
1784                 pr_info("                   .SlaveAddress = 0x%x\n",
1785                                 pptable->I2cControllers[i].SlaveAddress);
1786                 pr_info("                   .ControllerPort = %d\n",
1787                                 pptable->I2cControllers[i].ControllerPort);
1788                 pr_info("                   .ControllerName = %d\n",
1789                                 pptable->I2cControllers[i].ControllerName);
1790                 pr_info("                   .ThermalThrottler = %d\n",
1791                                 pptable->I2cControllers[i].ThermalThrotter);
1792                 pr_info("                   .I2cProtocol = %d\n",
1793                                 pptable->I2cControllers[i].I2cProtocol);
1794                 pr_info("                   .Speed = %d\n",
1795                                 pptable->I2cControllers[i].Speed);
1796         }
1797
1798         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1799         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1800
1801         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1802
1803         pr_info("XgmiLinkSpeed\n");
1804         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1805                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1806         pr_info("XgmiLinkWidth\n");
1807         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1808                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1809         pr_info("XgmiFclkFreq\n");
1810         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1811                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1812         pr_info("XgmiSocVoltage\n");
1813         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1814                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1815
1816 }
1817
1818 static bool arcturus_is_dpm_running(struct smu_context *smu)
1819 {
1820         int ret = 0;
1821         uint32_t feature_mask[2];
1822         unsigned long feature_enabled;
1823         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1824         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1825                            ((uint64_t)feature_mask[1] << 32));
1826         return !!(feature_enabled & SMC_DPM_FEATURE);
1827 }
1828
1829 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1830 {
1831         struct smu_power_context *smu_power = &smu->smu_power;
1832         struct smu_power_gate *power_gate = &smu_power->power_gate;
1833         int ret = 0;
1834
1835         if (enable) {
1836                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1837                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1838                         if (ret) {
1839                                 pr_err("[EnableVCNDPM] failed!\n");
1840                                 return ret;
1841                         }
1842                 }
1843                 power_gate->vcn_gated = false;
1844         } else {
1845                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1846                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1847                         if (ret) {
1848                                 pr_err("[DisableVCNDPM] failed!\n");
1849                                 return ret;
1850                         }
1851                 }
1852                 power_gate->vcn_gated = true;
1853         }
1854
1855         return ret;
1856 }
1857
1858
1859 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
1860                                   uint8_t address, uint32_t numbytes,
1861                                   uint8_t *data)
1862 {
1863         int i;
1864
1865         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
1866
1867         req->I2CcontrollerPort = 0;
1868         req->I2CSpeed = 2;
1869         req->SlaveAddress = address;
1870         req->NumCmds = numbytes;
1871
1872         for (i = 0; i < numbytes; i++) {
1873                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1874
1875                 /* First 2 bytes are always write for lower 2b EEPROM address */
1876                 if (i < 2)
1877                         cmd->Cmd = 1;
1878                 else
1879                         cmd->Cmd = write;
1880
1881
1882                 /* Add RESTART for read  after address filled */
1883                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1884
1885                 /* Add STOP in the end */
1886                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1887
1888                 /* Fill with data regardless if read or write to simplify code */
1889                 cmd->RegisterAddr = data[i];
1890         }
1891 }
1892
1893 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
1894                                                uint8_t address,
1895                                                uint8_t *data,
1896                                                uint32_t numbytes)
1897 {
1898         uint32_t  i, ret = 0;
1899         SwI2cRequest_t req;
1900         struct amdgpu_device *adev = to_amdgpu_device(control);
1901         struct smu_table_context *smu_table = &adev->smu.smu_table;
1902         struct smu_table *table = &smu_table->tables[SMU_TABLE_I2C_COMMANDS];
1903
1904         memset(&req, 0, sizeof(req));
1905         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
1906
1907         mutex_lock(&adev->smu.mutex);
1908         /* Now read data starting with that address */
1909         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1910                                         true);
1911         mutex_unlock(&adev->smu.mutex);
1912
1913         if (!ret) {
1914                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1915
1916                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1917                 for (i = 0; i < numbytes; i++)
1918                         data[i] = res->SwI2cCmds[i].Data;
1919
1920                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
1921                                   (uint16_t)address, numbytes);
1922
1923                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1924                                8, 1, data, numbytes, false);
1925         } else
1926                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
1927
1928         return ret;
1929 }
1930
1931 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
1932                                                 uint8_t address,
1933                                                 uint8_t *data,
1934                                                 uint32_t numbytes)
1935 {
1936         uint32_t ret;
1937         SwI2cRequest_t req;
1938         struct amdgpu_device *adev = to_amdgpu_device(control);
1939
1940         memset(&req, 0, sizeof(req));
1941         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
1942
1943         mutex_lock(&adev->smu.mutex);
1944         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1945         mutex_unlock(&adev->smu.mutex);
1946
1947         if (!ret) {
1948                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1949                                          (uint16_t)address, numbytes);
1950
1951                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1952                                8, 1, data, numbytes, false);
1953                 /*
1954                  * According to EEPROM spec there is a MAX of 10 ms required for
1955                  * EEPROM to flush internal RX buffer after STOP was issued at the
1956                  * end of write transaction. During this time the EEPROM will not be
1957                  * responsive to any more commands - so wait a bit more.
1958                  */
1959                 msleep(10);
1960
1961         } else
1962                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
1963
1964         return ret;
1965 }
1966
1967 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
1968                               struct i2c_msg *msgs, int num)
1969 {
1970         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1971         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1972
1973         for (i = 0; i < num; i++) {
1974                 /*
1975                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1976                  * once and hence the data needs to be spliced into chunks and sent each
1977                  * chunk separately
1978                  */
1979                 data_size = msgs[i].len - 2;
1980                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1981                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1982                 data_ptr = msgs[i].buf + 2;
1983
1984                 for (j = 0; j < data_size / data_chunk_size; j++) {
1985                         /* Insert the EEPROM dest addess, bits 0-15 */
1986                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1987                         data_chunk[1] = (next_eeprom_addr & 0xff);
1988
1989                         if (msgs[i].flags & I2C_M_RD) {
1990                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
1991                                                                 (uint8_t)msgs[i].addr,
1992                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
1993
1994                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1995                         } else {
1996
1997                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1998
1999                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2000                                                                  (uint8_t)msgs[i].addr,
2001                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2002                         }
2003
2004                         if (ret) {
2005                                 num = -EIO;
2006                                 goto fail;
2007                         }
2008
2009                         next_eeprom_addr += data_chunk_size;
2010                         data_ptr += data_chunk_size;
2011                 }
2012
2013                 if (data_size % data_chunk_size) {
2014                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2015                         data_chunk[1] = (next_eeprom_addr & 0xff);
2016
2017                         if (msgs[i].flags & I2C_M_RD) {
2018                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2019                                                                 (uint8_t)msgs[i].addr,
2020                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2021
2022                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2023                         } else {
2024                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2025
2026                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2027                                                                  (uint8_t)msgs[i].addr,
2028                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2029                         }
2030
2031                         if (ret) {
2032                                 num = -EIO;
2033                                 goto fail;
2034                         }
2035                 }
2036         }
2037
2038 fail:
2039         return num;
2040 }
2041
2042 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2043 {
2044         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2045 }
2046
2047
2048 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2049         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2050         .functionality = arcturus_i2c_eeprom_i2c_func,
2051 };
2052
2053 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2054 {
2055         struct amdgpu_device *adev = to_amdgpu_device(control);
2056         int res;
2057
2058         control->owner = THIS_MODULE;
2059         control->class = I2C_CLASS_SPD;
2060         control->dev.parent = &adev->pdev->dev;
2061         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2062         snprintf(control->name, sizeof(control->name), "RAS EEPROM");
2063
2064         res = i2c_add_adapter(control);
2065         if (res)
2066                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2067
2068         return res;
2069 }
2070
2071 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2072 {
2073         i2c_del_adapter(control);
2074 }
2075
2076 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2077 {
2078         PPTable_t *pptable = smu->smu_table.driver_pptable;
2079
2080         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2081 }
2082
2083 static const struct pptable_funcs arcturus_ppt_funcs = {
2084         /* translate smu index into arcturus specific index */
2085         .get_smu_msg_index = arcturus_get_smu_msg_index,
2086         .get_smu_clk_index = arcturus_get_smu_clk_index,
2087         .get_smu_feature_index = arcturus_get_smu_feature_index,
2088         .get_smu_table_index = arcturus_get_smu_table_index,
2089         .get_smu_power_index= arcturus_get_pwr_src_index,
2090         .get_workload_type = arcturus_get_workload_type,
2091         /* internal structurs allocations */
2092         .tables_init = arcturus_tables_init,
2093         .alloc_dpm_context = arcturus_allocate_dpm_context,
2094         /* pptable related */
2095         .check_powerplay_table = arcturus_check_powerplay_table,
2096         .store_powerplay_table = arcturus_store_powerplay_table,
2097         .append_powerplay_table = arcturus_append_powerplay_table,
2098         /* init dpm */
2099         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2100         /* btc */
2101         .run_btc = arcturus_run_btc,
2102         /* dpm/clk tables */
2103         .set_default_dpm_table = arcturus_set_default_dpm_table,
2104         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2105         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2106         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2107         .print_clk_levels = arcturus_print_clk_levels,
2108         .force_clk_levels = arcturus_force_clk_levels,
2109         .read_sensor = arcturus_read_sensor,
2110         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2111         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2112         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2113         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2114         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2115         .get_power_profile_mode = arcturus_get_power_profile_mode,
2116         .set_power_profile_mode = arcturus_set_power_profile_mode,
2117         /* debug (internal used) */
2118         .dump_pptable = arcturus_dump_pptable,
2119         .get_power_limit = arcturus_get_power_limit,
2120         .is_dpm_running = arcturus_is_dpm_running,
2121         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2122         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2123         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2124         .init_microcode = smu_v11_0_init_microcode,
2125         .load_microcode = smu_v11_0_load_microcode,
2126         .init_smc_tables = smu_v11_0_init_smc_tables,
2127         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2128         .init_power = smu_v11_0_init_power,
2129         .fini_power = smu_v11_0_fini_power,
2130         .check_fw_status = smu_v11_0_check_fw_status,
2131         .setup_pptable = smu_v11_0_setup_pptable,
2132         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2133         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2134         .check_pptable = smu_v11_0_check_pptable,
2135         .parse_pptable = smu_v11_0_parse_pptable,
2136         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2137         .check_fw_version = smu_v11_0_check_fw_version,
2138         .write_pptable = smu_v11_0_write_pptable,
2139         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2140         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2141         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2142         .system_features_control = smu_v11_0_system_features_control,
2143         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2144         .read_smc_arg = smu_v11_0_read_arg,
2145         .init_display_count = smu_v11_0_init_display_count,
2146         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2147         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2148         .notify_display_change = smu_v11_0_notify_display_change,
2149         .set_power_limit = smu_v11_0_set_power_limit,
2150         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2151         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2152         .start_thermal_control = smu_v11_0_start_thermal_control,
2153         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2154         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2155         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2156         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2157         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2158         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2159         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2160         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2161         .gfx_off_control = smu_v11_0_gfx_off_control,
2162         .register_irq_handler = smu_v11_0_register_irq_handler,
2163         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2164         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2165         .baco_is_support= smu_v11_0_baco_is_support,
2166         .baco_get_state = smu_v11_0_baco_get_state,
2167         .baco_set_state = smu_v11_0_baco_set_state,
2168         .baco_enter = smu_v11_0_baco_enter,
2169         .baco_exit = smu_v11_0_baco_exit,
2170         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2171         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2172         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2173         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2174 };
2175
2176 void arcturus_set_ppt_funcs(struct smu_context *smu)
2177 {
2178         smu->ppt_funcs = &arcturus_ppt_funcs;
2179 }