2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include "linux/delay.h"
29 #include "fiji_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomctrl.h"
34 #include "cgs_common.h"
35 #include "fiji_dyn_defaults.h"
36 #include "fiji_powertune.h"
38 #include "smu/smu_7_1_3_d.h"
39 #include "smu/smu_7_1_3_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46 #include "pppcielanes.h"
47 #include "fiji_hwmgr.h"
48 #include "tonga_processpptables.h"
49 #include "tonga_pptable.h"
52 #include "amd_pcie_helpers.h"
53 #include "cgs_linux.h"
54 #include "ppinterrupt.h"
56 #include "fiji_clockpowergating.h"
57 #include "fiji_thermal.h"
59 #define VOLTAGE_SCALE 4
60 #define SMC_RAM_END 0x40000
61 #define VDDC_VDDCI_DELTA 300
63 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
64 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
65 #define MC_SEQ_MISC0_GDDR5_VALUE 5
67 #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
68 #define MC_CG_ARB_FREQ_F1 0x0b
69 #define MC_CG_ARB_FREQ_F2 0x0c
70 #define MC_CG_ARB_FREQ_F3 0x0d
73 #define SMC_CG_IND_START 0xc0030000
74 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
76 #define VOLTAGE_SCALE 4
77 #define VOLTAGE_VID_OFFSET_SCALE1 625
78 #define VOLTAGE_VID_OFFSET_SCALE2 100
80 #define VDDC_VDDCI_DELTA 300
82 #define ixSWRST_COMMAND_1 0x1400103
83 #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
85 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
87 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
88 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
89 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
90 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
91 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
96 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
98 static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
99 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
101 /* [FF, SS] type, [] 4 voltage ranges, and
102 * [Floor Freq, Boundary Freq, VID min , VID max]
104 static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
106 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
109 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
111 static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
116 struct fiji_power_state *cast_phw_fiji_power_state(
117 struct pp_hw_power_state *hw_ps)
119 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
120 "Invalid Powerstate Type!",
123 return (struct fiji_power_state *)hw_ps;
126 const struct fiji_power_state *cast_const_phw_fiji_power_state(
127 const struct pp_hw_power_state *hw_ps)
129 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
130 "Invalid Powerstate Type!",
133 return (const struct fiji_power_state *)hw_ps;
136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
138 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
139 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
145 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
146 struct fiji_ulv_parm *ulv = &data->ulv;
148 ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
149 data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
150 data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
151 data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
152 data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
153 data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
154 data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
155 data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
156 data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
158 data->static_screen_threshold_unit =
159 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
160 data->static_screen_threshold =
161 PPFIJI_STATICSCREENTHRESHOLD_DFLT;
163 /* Unset ABM cap as it moved to DAL.
164 * Add PHM_PlatformCaps_NonABMSupportInPPLib
165 * for re-direct ABM related request to DAL
167 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
168 PHM_PlatformCaps_ABM);
169 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 PHM_PlatformCaps_NonABMSupportInPPLib);
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_DynamicACTiming);
175 fiji_initialize_power_tune_defaults(hwmgr);
177 data->mclk_stutter_mode_threshold = 60000;
178 data->pcie_gen_performance.max = PP_PCIEGen1;
179 data->pcie_gen_performance.min = PP_PCIEGen3;
180 data->pcie_gen_power_saving.max = PP_PCIEGen1;
181 data->pcie_gen_power_saving.min = PP_PCIEGen3;
182 data->pcie_lane_performance.max = 0;
183 data->pcie_lane_performance.min = 16;
184 data->pcie_lane_power_saving.max = 0;
185 data->pcie_lane_power_saving.min = 16;
187 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
188 PHM_PlatformCaps_DynamicUVDState);
191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
192 phm_ppt_v1_voltage_lookup_table *lookup_table,
193 uint16_t virtual_voltage_id, int32_t *sclk)
197 struct phm_ppt_v1_information *table_info =
198 (struct phm_ppt_v1_information *)(hwmgr->pptable);
200 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
202 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
203 for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
204 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
205 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
209 PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
210 "Can't find requested voltage id in vdd_dep_on_sclk table!",
214 *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
220 * Get Leakage VDDC based on leakage ID.
222 * @param hwmgr the address of the powerplay hardware manager.
225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
227 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
230 uint16_t evv_default = 1150;
233 struct phm_ppt_v1_information *table_info =
234 (struct phm_ppt_v1_information *)hwmgr->pptable;
235 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
236 table_info->vdd_dep_on_sclk;
239 for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
240 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
241 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
242 table_info->vddc_lookup_table, vv_id, &sclk)) {
243 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_ClockStretcher)) {
245 for (j = 1; j < sclk_table->count; j++) {
246 if (sclk_table->entries[j].clk == sclk &&
247 sclk_table->entries[j].cks_enable == 0) {
254 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_EnableDriverEVV))
256 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
257 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
262 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
263 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
265 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
266 PP_ASSERT_WITH_CODE((vddc < 2000),
267 "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
270 /* 1.15V is the default safe value for Fiji */
273 /* the voltage should not be zero nor equal to leakage ID */
274 if (vddc != 0 && vddc != vv_id) {
275 data->vddc_leakage.actual_voltage
276 [data->vddc_leakage.count] = vddc;
277 data->vddc_leakage.leakage_id
278 [data->vddc_leakage.count] = vv_id;
279 data->vddc_leakage.count++;
287 * Change virtual leakage voltage to actual value.
289 * @param hwmgr the address of the powerplay hardware manager.
290 * @param pointer to changing voltage
291 * @param pointer to leakage table
293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
294 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
298 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
299 for (index = 0; index < leakage_table->count; index++) {
300 /* if this voltage matches a leakage voltage ID */
301 /* patch with actual leakage voltage */
302 if (leakage_table->leakage_id[index] == *voltage) {
303 *voltage = leakage_table->actual_voltage[index];
308 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
309 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
313 * Patch voltage lookup table by EVV leakages.
315 * @param hwmgr the address of the powerplay hardware manager.
316 * @param pointer to voltage lookup table
317 * @param pointer to leakage table
320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
321 phm_ppt_v1_voltage_lookup_table *lookup_table,
322 struct fiji_leakage_voltage *leakage_table)
326 for (i = 0; i < lookup_table->count; i++)
327 fiji_patch_with_vdd_leakage(hwmgr,
328 &lookup_table->entries[i].us_vdd, leakage_table);
333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
334 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
337 struct phm_ppt_v1_information *table_info =
338 (struct phm_ppt_v1_information *)(hwmgr->pptable);
339 fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
340 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
341 table_info->max_clock_voltage_on_dc.vddc;
345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
346 struct pp_hwmgr *hwmgr)
350 struct phm_ppt_v1_information *table_info =
351 (struct phm_ppt_v1_information *)(hwmgr->pptable);
353 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
354 table_info->vdd_dep_on_sclk;
355 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
356 table_info->vdd_dep_on_mclk;
357 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
358 table_info->mm_dep_table;
360 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
361 voltageId = sclk_table->entries[entryId].vddInd;
362 sclk_table->entries[entryId].vddc =
363 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
366 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
367 voltageId = mclk_table->entries[entryId].vddInd;
368 mclk_table->entries[entryId].vddc =
369 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
372 for (entryId = 0; entryId < mm_table->count; ++entryId) {
373 voltageId = mm_table->entries[entryId].vddcInd;
374 mm_table->entries[entryId].vddc =
375 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
384 /* Need to determine if we need calculated voltage. */
388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
390 /* Need to determine if we need calculated voltage from mm table. */
394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
395 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
397 uint32_t table_size, i, j;
398 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
399 table_size = lookup_table->count;
401 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
402 "Lookup table is empty", return -EINVAL);
404 /* Sorting voltages */
405 for (i = 0; i < table_size - 1; i++) {
406 for (j = i + 1; j > 0; j--) {
407 if (lookup_table->entries[j].us_vdd <
408 lookup_table->entries[j - 1].us_vdd) {
409 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
410 lookup_table->entries[j - 1] = lookup_table->entries[j];
411 lookup_table->entries[j] = tmp_voltage_lookup_record;
419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
423 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
424 struct phm_ppt_v1_information *table_info =
425 (struct phm_ppt_v1_information *)(hwmgr->pptable);
427 tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
428 table_info->vddc_lookup_table, &(data->vddc_leakage));
432 tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
433 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
437 tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
441 tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
445 tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
449 tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
458 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
459 struct phm_ppt_v1_information *table_info =
460 (struct phm_ppt_v1_information *)(hwmgr->pptable);
462 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
463 table_info->vdd_dep_on_sclk;
464 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
465 table_info->vdd_dep_on_mclk;
467 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
468 "VDD dependency on SCLK table is missing. \
469 This table is mandatory", return -EINVAL);
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
471 "VDD dependency on SCLK table has to have is missing. \
472 This table is mandatory", return -EINVAL);
474 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
475 "VDD dependency on MCLK table is missing. \
476 This table is mandatory", return -EINVAL);
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
478 "VDD dependency on MCLK table has to have is missing. \
479 This table is mandatory", return -EINVAL);
481 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
482 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->
483 entries[allowed_sclk_vdd_table->count - 1].vddc;
485 table_info->max_clock_voltage_on_ac.sclk =
486 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
487 table_info->max_clock_voltage_on_ac.mclk =
488 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
489 table_info->max_clock_voltage_on_ac.vddc =
490 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
491 table_info->max_clock_voltage_on_ac.vddci =
492 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
494 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
495 table_info->max_clock_voltage_on_ac.sclk;
496 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
497 table_info->max_clock_voltage_on_ac.mclk;
498 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
499 table_info->max_clock_voltage_on_ac.vddc;
500 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
501 table_info->max_clock_voltage_on_ac.vddci;
506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
508 uint32_t speedCntl = 0;
510 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
511 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
512 ixPCIE_LC_SPEED_CNTL);
513 return((uint16_t)PHM_GET_FIELD(speedCntl,
514 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
521 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
522 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
523 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
525 PP_ASSERT_WITH_CODE((7 >= link_width),
526 "Invalid PCIe lane width!", return 0);
528 return decode_pcie_lane_width(link_width);
531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
533 * @param hwmgr Pointer to the hardware manager.
534 * @param pPowerState The address of the PowerState instance being created.
537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
538 struct pp_hw_power_state *hw_ps)
540 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
541 struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
542 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
545 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
547 /* First retrieve the Boot clocks and VDDC from the firmware info table.
548 * We assume here that fw_info is unchanged if this call fails.
550 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
551 hwmgr->device, index,
552 &size, &frev, &crev);
554 /* During a test, there is no firmware info table. */
557 /* Patch the state. */
558 data->vbios_boot_state.sclk_bootup_value =
559 le32_to_cpu(fw_info->ulDefaultEngineClock);
560 data->vbios_boot_state.mclk_bootup_value =
561 le32_to_cpu(fw_info->ulDefaultMemoryClock);
562 data->vbios_boot_state.mvdd_bootup_value =
563 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
564 data->vbios_boot_state.vddc_bootup_value =
565 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
566 data->vbios_boot_state.vddci_bootup_value =
567 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
568 data->vbios_boot_state.pcie_gen_bootup_value =
569 fiji_get_current_pcie_speed(hwmgr);
570 data->vbios_boot_state.pcie_lane_bootup_value =
571 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
573 /* set boot power state */
574 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
575 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
576 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
577 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
582 static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
584 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
586 if (data->soft_pp_table) {
587 kfree(data->soft_pp_table);
588 data->soft_pp_table = NULL;
591 return phm_hwmgr_backend_fini(hwmgr);
594 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
596 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
598 struct phm_ppt_v1_information *table_info =
599 (struct phm_ppt_v1_information *)(hwmgr->pptable);
603 data->dll_default_on = false;
604 data->sram_end = SMC_RAM_END;
606 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
607 data->activity_target[i] = FIJI_AT_DFLT;
609 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
611 data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
612 data->mclk_dpm0_activity_target = 0xa;
614 data->sclk_dpm_key_disabled = 0;
615 data->mclk_dpm_key_disabled = 0;
616 data->pcie_dpm_key_disabled = 0;
618 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
619 PHM_PlatformCaps_UnTabledHardwareInterface);
620 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
621 PHM_PlatformCaps_TablelessHardwareInterface);
623 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
624 PHM_PlatformCaps_SclkDeepSleep);
626 data->gpio_debug = 0;
628 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
629 PHM_PlatformCaps_DynamicPatchPowerState);
631 /* need to set voltage control types before EVV patching */
632 data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
633 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
634 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
636 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
637 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
638 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
640 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
641 PHM_PlatformCaps_EnableMVDDControl))
642 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
643 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
644 data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
646 if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
647 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
648 PHM_PlatformCaps_EnableMVDDControl);
650 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
651 PHM_PlatformCaps_ControlVDDCI)) {
652 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
653 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
654 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
655 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
656 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
657 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
660 if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
661 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
662 PHM_PlatformCaps_ControlVDDCI);
664 if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
665 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
666 PHM_PlatformCaps_ClockStretcher);
668 fiji_init_dpm_defaults(hwmgr);
670 /* Get leakage voltage based on leakage ID. */
671 fiji_get_evv_voltages(hwmgr);
673 /* Patch our voltage dependency table with actual leakage voltage
674 * We need to perform leakage translation before it's used by other functions
676 fiji_complete_dependency_tables(hwmgr);
678 /* Parse pptable data read from VBIOS */
679 fiji_set_private_data_based_on_pptable(hwmgr);
682 data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
684 /* Initalize Dynamic State Adjustment Rule Settings */
685 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
688 data->uvd_enabled = false;
689 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
690 PHM_PlatformCaps_EnableSMU7ThermalManagement);
691 data->vddc_phase_shed_control = false;
694 stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
695 PHM_PlatformCaps_StayInBootState);
698 struct cgs_system_info sys_info = {0};
700 data->is_tlu_enabled = 0;
701 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
702 FIJI_MAX_HARDWARE_POWERLEVELS;
703 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
704 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
706 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
707 PHM_PlatformCaps_FanSpeedInTableIsRPM);
709 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
710 hwmgr->thermal_controller.
711 advanceFanControlParameters.ucFanControlMode) {
712 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
713 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
714 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
715 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
716 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
717 table_info->cac_dtp_table->usOperatingTempMinLimit;
718 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
719 table_info->cac_dtp_table->usOperatingTempMaxLimit;
720 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
721 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
722 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
723 table_info->cac_dtp_table->usOperatingTempStep;
724 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
725 table_info->cac_dtp_table->usTargetOperatingTemp;
727 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
728 PHM_PlatformCaps_ODFuzzyFanControlSupport);
731 sys_info.size = sizeof(struct cgs_system_info);
732 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
733 result = cgs_query_system_info(hwmgr->device, &sys_info);
735 data->pcie_gen_cap = 0x30007;
737 data->pcie_gen_cap = (uint32_t)sys_info.value;
738 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
739 data->pcie_spc_cap = 20;
740 sys_info.size = sizeof(struct cgs_system_info);
741 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
742 result = cgs_query_system_info(hwmgr->device, &sys_info);
744 data->pcie_lane_cap = 0x2f0000;
746 data->pcie_lane_cap = (uint32_t)sys_info.value;
748 /* Ignore return value in here, we are cleaning up a mess. */
749 fiji_hwmgr_backend_fini(hwmgr);
756 * Read clock related registers.
758 * @param hwmgr the address of the powerplay hardware manager.
761 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
763 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
765 data->clock_registers.vCG_SPLL_FUNC_CNTL =
766 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
767 ixCG_SPLL_FUNC_CNTL);
768 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
769 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
770 ixCG_SPLL_FUNC_CNTL_2);
771 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
772 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
773 ixCG_SPLL_FUNC_CNTL_3);
774 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
775 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
776 ixCG_SPLL_FUNC_CNTL_4);
777 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
778 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
779 ixCG_SPLL_SPREAD_SPECTRUM);
780 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
781 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
782 ixCG_SPLL_SPREAD_SPECTRUM_2);
788 * Find out if memory is GDDR5.
790 * @param hwmgr the address of the powerplay hardware manager.
793 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
795 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
798 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
800 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
801 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
802 MC_SEQ_MISC0_GDDR5_SHIFT));
808 * Enables Dynamic Power Management by SMC
810 * @param hwmgr the address of the powerplay hardware manager.
813 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
815 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
816 GENERAL_PWRMGT, STATIC_PM_EN, 1);
822 * Initialize PowerGating States for different engines
824 * @param hwmgr the address of the powerplay hardware manager.
827 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
829 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
831 data->uvd_power_gated = false;
832 data->vce_power_gated = false;
833 data->samu_power_gated = false;
834 data->acp_power_gated = false;
835 data->pg_acp_init = true;
840 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
842 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
843 data->low_sclk_interrupt_threshold = 0;
848 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
850 int tmp_result, result = 0;
852 tmp_result = fiji_read_clock_registers(hwmgr);
853 PP_ASSERT_WITH_CODE((0 == tmp_result),
854 "Failed to read clock registers!", result = tmp_result);
856 tmp_result = fiji_get_memory_type(hwmgr);
857 PP_ASSERT_WITH_CODE((0 == tmp_result),
858 "Failed to get memory type!", result = tmp_result);
860 tmp_result = fiji_enable_acpi_power_management(hwmgr);
861 PP_ASSERT_WITH_CODE((0 == tmp_result),
862 "Failed to enable ACPI power management!", result = tmp_result);
864 tmp_result = fiji_init_power_gate_state(hwmgr);
865 PP_ASSERT_WITH_CODE((0 == tmp_result),
866 "Failed to init power gate state!", result = tmp_result);
868 tmp_result = tonga_get_mc_microcode_version(hwmgr);
869 PP_ASSERT_WITH_CODE((0 == tmp_result),
870 "Failed to get MC microcode version!", result = tmp_result);
872 tmp_result = fiji_init_sclk_threshold(hwmgr);
873 PP_ASSERT_WITH_CODE((0 == tmp_result),
874 "Failed to init sclk threshold!", result = tmp_result);
880 * Checks if we want to support voltage control
882 * @param hwmgr the address of the powerplay hardware manager.
884 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
886 const struct fiji_hwmgr *data =
887 (const struct fiji_hwmgr *)(hwmgr->backend);
889 return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
893 * Enable voltage control
895 * @param hwmgr the address of the powerplay hardware manager.
898 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
900 /* enable voltage control */
901 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
902 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
908 * Remove repeated voltage values and create table with unique values.
910 * @param hwmgr the address of the powerplay hardware manager.
911 * @param vol_table the pointer to changing voltage table
912 * @return 0 in success
915 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
916 struct pp_atomctrl_voltage_table *vol_table)
921 struct pp_atomctrl_voltage_table *table;
923 PP_ASSERT_WITH_CODE((NULL != vol_table),
924 "Voltage Table empty.", return -EINVAL);
925 table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
931 table->mask_low = vol_table->mask_low;
932 table->phase_delay = vol_table->phase_delay;
934 for (i = 0; i < vol_table->count; i++) {
935 vvalue = vol_table->entries[i].value;
938 for (j = 0; j < table->count; j++) {
939 if (vvalue == table->entries[j].value) {
946 table->entries[table->count].value = vvalue;
947 table->entries[table->count].smio_low =
948 vol_table->entries[i].smio_low;
953 memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
959 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
960 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
964 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
965 struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
967 PP_ASSERT_WITH_CODE((0 != dep_table->count),
968 "Voltage Dependency Table empty.", return -EINVAL);
970 vol_table->mask_low = 0;
971 vol_table->phase_delay = 0;
972 vol_table->count = dep_table->count;
974 for (i = 0; i < dep_table->count; i++) {
975 vol_table->entries[i].value = dep_table->entries[i].mvdd;
976 vol_table->entries[i].smio_low = 0;
979 result = fiji_trim_voltage_table(hwmgr, vol_table);
980 PP_ASSERT_WITH_CODE((0 == result),
981 "Failed to trim MVDD table.", return result);
986 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
987 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
991 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
992 struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
994 PP_ASSERT_WITH_CODE((0 != dep_table->count),
995 "Voltage Dependency Table empty.", return -EINVAL);
997 vol_table->mask_low = 0;
998 vol_table->phase_delay = 0;
999 vol_table->count = dep_table->count;
1001 for (i = 0; i < dep_table->count; i++) {
1002 vol_table->entries[i].value = dep_table->entries[i].vddci;
1003 vol_table->entries[i].smio_low = 0;
1006 result = fiji_trim_voltage_table(hwmgr, vol_table);
1007 PP_ASSERT_WITH_CODE((0 == result),
1008 "Failed to trim VDDCI table.", return result);
1013 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1014 phm_ppt_v1_voltage_lookup_table *lookup_table)
1017 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1018 struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
1020 PP_ASSERT_WITH_CODE((0 != lookup_table->count),
1021 "Voltage Lookup Table empty.", return -EINVAL);
1023 vol_table->mask_low = 0;
1024 vol_table->phase_delay = 0;
1026 vol_table->count = lookup_table->count;
1028 for (i = 0; i < vol_table->count; i++) {
1029 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
1030 vol_table->entries[i].smio_low = 0;
1036 /* ---- Voltage Tables ----
1037 * If the voltage table would be bigger than
1038 * what will fit into the state table on
1039 * the SMC keep only the higher entries.
1041 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1042 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1044 unsigned int i, diff;
1046 if (vol_table->count <= max_vol_steps)
1049 diff = vol_table->count - max_vol_steps;
1051 for (i = 0; i < max_vol_steps; i++)
1052 vol_table->entries[i] = vol_table->entries[i + diff];
1054 vol_table->count = max_vol_steps;
1060 * Create Voltage Tables.
1062 * @param hwmgr the address of the powerplay hardware manager.
1065 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1067 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1068 struct phm_ppt_v1_information *table_info =
1069 (struct phm_ppt_v1_information *)hwmgr->pptable;
1072 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1073 result = atomctrl_get_voltage_table_v3(hwmgr,
1074 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
1075 &(data->mvdd_voltage_table));
1076 PP_ASSERT_WITH_CODE((0 == result),
1077 "Failed to retrieve MVDD table.",
1079 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1080 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1081 table_info->vdd_dep_on_mclk);
1082 PP_ASSERT_WITH_CODE((0 == result),
1083 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1087 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1088 result = atomctrl_get_voltage_table_v3(hwmgr,
1089 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1090 &(data->vddci_voltage_table));
1091 PP_ASSERT_WITH_CODE((0 == result),
1092 "Failed to retrieve VDDCI table.",
1094 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1095 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1096 table_info->vdd_dep_on_mclk);
1097 PP_ASSERT_WITH_CODE((0 == result),
1098 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1102 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1103 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1104 table_info->vddc_lookup_table);
1105 PP_ASSERT_WITH_CODE((0 == result),
1106 "Failed to retrieve SVI2 VDDC table from lookup table.",
1110 PP_ASSERT_WITH_CODE(
1111 (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1112 "Too many voltage values for VDDC. Trimming to fit state table.",
1113 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1114 SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1116 PP_ASSERT_WITH_CODE(
1117 (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1118 "Too many voltage values for VDDCI. Trimming to fit state table.",
1119 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1120 SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1122 PP_ASSERT_WITH_CODE(
1123 (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1124 "Too many voltage values for MVDD. Trimming to fit state table.",
1125 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1126 SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1131 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1133 /* Program additional LP registers
1134 * that are no longer programmed by VBIOS
1136 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1137 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1138 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1139 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1140 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1141 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1142 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1143 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1144 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1145 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1146 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1147 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1148 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1149 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1155 * Programs static screed detection parameters
1157 * @param hwmgr the address of the powerplay hardware manager.
1160 static int fiji_program_static_screen_threshold_parameters(
1161 struct pp_hwmgr *hwmgr)
1163 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1165 /* Set static screen threshold unit */
1166 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1167 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1168 data->static_screen_threshold_unit);
1169 /* Set static screen threshold */
1170 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1171 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1172 data->static_screen_threshold);
1178 * Setup display gap for glitch free memory clock switching.
1180 * @param hwmgr the address of the powerplay hardware manager.
1183 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1185 uint32_t displayGap =
1186 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1187 ixCG_DISPLAY_GAP_CNTL);
1189 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1190 DISP_GAP, DISPLAY_GAP_IGNORE);
1192 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1193 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1195 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1196 ixCG_DISPLAY_GAP_CNTL, displayGap);
1202 * Programs activity state transition voting clients
1204 * @param hwmgr the address of the powerplay hardware manager.
1207 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1209 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1211 /* Clear reset for voting clients before enabling DPM */
1212 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1213 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1214 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1215 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1217 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1218 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1219 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1220 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1221 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1222 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1223 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1224 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1225 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1226 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1227 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1228 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1229 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1230 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1231 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1232 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1238 * Get the location of various tables inside the FW image.
1240 * @param hwmgr the address of the powerplay hardware manager.
1243 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1245 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1246 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1251 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1252 SMU7_FIRMWARE_HEADER_LOCATION +
1253 offsetof(SMU73_Firmware_Header, DpmTable),
1254 &tmp, data->sram_end);
1257 data->dpm_table_start = tmp;
1259 error |= (0 != result);
1261 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1262 SMU7_FIRMWARE_HEADER_LOCATION +
1263 offsetof(SMU73_Firmware_Header, SoftRegisters),
1264 &tmp, data->sram_end);
1267 data->soft_regs_start = tmp;
1268 smu_data->soft_regs_start = tmp;
1271 error |= (0 != result);
1273 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1274 SMU7_FIRMWARE_HEADER_LOCATION +
1275 offsetof(SMU73_Firmware_Header, mcRegisterTable),
1276 &tmp, data->sram_end);
1279 data->mc_reg_table_start = tmp;
1281 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1282 SMU7_FIRMWARE_HEADER_LOCATION +
1283 offsetof(SMU73_Firmware_Header, FanTable),
1284 &tmp, data->sram_end);
1287 data->fan_table_start = tmp;
1289 error |= (0 != result);
1291 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1292 SMU7_FIRMWARE_HEADER_LOCATION +
1293 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1294 &tmp, data->sram_end);
1297 data->arb_table_start = tmp;
1299 error |= (0 != result);
1301 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1302 SMU7_FIRMWARE_HEADER_LOCATION +
1303 offsetof(SMU73_Firmware_Header, Version),
1304 &tmp, data->sram_end);
1307 hwmgr->microcode_version_info.SMC = tmp;
1309 error |= (0 != result);
1311 return error ? -1 : 0;
1314 /* Copy one arb setting to another and then switch the active set.
1315 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1317 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1318 uint32_t arb_src, uint32_t arb_dest)
1320 uint32_t mc_arb_dram_timing;
1321 uint32_t mc_arb_dram_timing2;
1322 uint32_t burst_time;
1323 uint32_t mc_cg_config;
1326 case MC_CG_ARB_FREQ_F0:
1327 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1328 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1329 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1331 case MC_CG_ARB_FREQ_F1:
1332 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1333 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1334 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1341 case MC_CG_ARB_FREQ_F0:
1342 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1343 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1344 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1346 case MC_CG_ARB_FREQ_F1:
1347 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1348 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1349 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1355 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1356 mc_cg_config |= 0x0000000F;
1357 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1358 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1364 * Initial switch from ARB F0->F1
1366 * @param hwmgr the address of the powerplay hardware manager.
1368 * This function is to be called from the SetPowerState table.
1370 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1372 return fiji_copy_and_switch_arb_sets(hwmgr,
1373 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1376 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1377 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1380 PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1381 "Fatal error, can not set up single DPM table entries "
1382 "to exceed max number!",);
1384 dpm_table->count = count;
1385 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1386 dpm_table->dpm_levels[i].enabled = false;
1391 static void fiji_setup_pcie_table_entry(
1392 struct fiji_single_dpm_table *dpm_table,
1393 uint32_t index, uint32_t pcie_gen,
1394 uint32_t pcie_lanes)
1396 dpm_table->dpm_levels[index].value = pcie_gen;
1397 dpm_table->dpm_levels[index].param1 = pcie_lanes;
1398 dpm_table->dpm_levels[index].enabled = 1;
1401 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1403 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1404 struct phm_ppt_v1_information *table_info =
1405 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1406 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1407 uint32_t i, max_entry;
1409 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1410 data->use_pcie_power_saving_levels), "No pcie performance levels!",
1413 if (data->use_pcie_performance_levels &&
1414 !data->use_pcie_power_saving_levels) {
1415 data->pcie_gen_power_saving = data->pcie_gen_performance;
1416 data->pcie_lane_power_saving = data->pcie_lane_performance;
1417 } else if (!data->use_pcie_performance_levels &&
1418 data->use_pcie_power_saving_levels) {
1419 data->pcie_gen_performance = data->pcie_gen_power_saving;
1420 data->pcie_lane_performance = data->pcie_lane_power_saving;
1423 fiji_reset_single_dpm_table(hwmgr,
1424 &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1426 if (pcie_table != NULL) {
1427 /* max_entry is used to make sure we reserve one PCIE level
1428 * for boot level (fix for A+A PSPP issue).
1429 * If PCIE table from PPTable have ULV entry + 8 entries,
1430 * then ignore the last entry.*/
1431 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1432 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1433 for (i = 1; i < max_entry; i++) {
1434 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1435 get_pcie_gen_support(data->pcie_gen_cap,
1436 pcie_table->entries[i].gen_speed),
1437 get_pcie_lane_support(data->pcie_lane_cap,
1438 pcie_table->entries[i].lane_width));
1440 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1442 /* Hardcode Pcie Table */
1443 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1444 get_pcie_gen_support(data->pcie_gen_cap,
1446 get_pcie_lane_support(data->pcie_lane_cap,
1448 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1449 get_pcie_gen_support(data->pcie_gen_cap,
1451 get_pcie_lane_support(data->pcie_lane_cap,
1453 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1454 get_pcie_gen_support(data->pcie_gen_cap,
1456 get_pcie_lane_support(data->pcie_lane_cap,
1458 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1459 get_pcie_gen_support(data->pcie_gen_cap,
1461 get_pcie_lane_support(data->pcie_lane_cap,
1463 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1464 get_pcie_gen_support(data->pcie_gen_cap,
1466 get_pcie_lane_support(data->pcie_lane_cap,
1468 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1469 get_pcie_gen_support(data->pcie_gen_cap,
1471 get_pcie_lane_support(data->pcie_lane_cap,
1474 data->dpm_table.pcie_speed_table.count = 6;
1476 /* Populate last level for boot PCIE level, but do not increment count. */
1477 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1478 data->dpm_table.pcie_speed_table.count,
1479 get_pcie_gen_support(data->pcie_gen_cap,
1481 get_pcie_lane_support(data->pcie_lane_cap,
1488 * This function is to initalize all DPM state tables
1489 * for SMU7 based on the dependency table.
1490 * Dynamic state patching function will then trim these
1491 * state tables to the allowed range based
1492 * on the power policy or external client requests,
1493 * such as UVD request, etc.
1495 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1497 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1498 struct phm_ppt_v1_information *table_info =
1499 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1502 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1503 table_info->vdd_dep_on_sclk;
1504 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1505 table_info->vdd_dep_on_mclk;
1507 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1508 "SCLK dependency table is missing. This table is mandatory",
1510 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1511 "SCLK dependency table has to have is missing. "
1512 "This table is mandatory",
1515 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1516 "MCLK dependency table is missing. This table is mandatory",
1518 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1519 "MCLK dependency table has to have is missing. "
1520 "This table is mandatory",
1523 /* clear the state table to reset everything to default */
1524 fiji_reset_single_dpm_table(hwmgr,
1525 &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1526 fiji_reset_single_dpm_table(hwmgr,
1527 &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1529 /* Initialize Sclk DPM table based on allow Sclk values */
1530 data->dpm_table.sclk_table.count = 0;
1531 for (i = 0; i < dep_sclk_table->count; i++) {
1532 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1533 [data->dpm_table.sclk_table.count - 1].value !=
1534 dep_sclk_table->entries[i].clk) {
1535 data->dpm_table.sclk_table.dpm_levels
1536 [data->dpm_table.sclk_table.count].value =
1537 dep_sclk_table->entries[i].clk;
1538 data->dpm_table.sclk_table.dpm_levels
1539 [data->dpm_table.sclk_table.count].enabled =
1540 (i == 0) ? true : false;
1541 data->dpm_table.sclk_table.count++;
1545 /* Initialize Mclk DPM table based on allow Mclk values */
1546 data->dpm_table.mclk_table.count = 0;
1547 for (i=0; i<dep_mclk_table->count; i++) {
1548 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1549 [data->dpm_table.mclk_table.count - 1].value !=
1550 dep_mclk_table->entries[i].clk) {
1551 data->dpm_table.mclk_table.dpm_levels
1552 [data->dpm_table.mclk_table.count].value =
1553 dep_mclk_table->entries[i].clk;
1554 data->dpm_table.mclk_table.dpm_levels
1555 [data->dpm_table.mclk_table.count].enabled =
1556 (i == 0) ? true : false;
1557 data->dpm_table.mclk_table.count++;
1561 /* setup PCIE gen speed levels */
1562 fiji_setup_default_pcie_table(hwmgr);
1564 /* save a copy of the default DPM table */
1565 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1566 sizeof(struct fiji_dpm_table));
1572 * @brief PhwFiji_GetVoltageOrder
1573 * Returns index of requested voltage record in lookup(table)
1574 * @param lookup_table - lookup list to search in
1575 * @param voltage - voltage to look for
1576 * @return 0 on success
1578 uint8_t fiji_get_voltage_index(
1579 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1581 uint8_t count = (uint8_t) (lookup_table->count);
1584 PP_ASSERT_WITH_CODE((NULL != lookup_table),
1585 "Lookup Table empty.", return 0);
1586 PP_ASSERT_WITH_CODE((0 != count),
1587 "Lookup Table empty.", return 0);
1589 for (i = 0; i < lookup_table->count; i++) {
1590 /* find first voltage equal or bigger than requested */
1591 if (lookup_table->entries[i].us_vdd >= voltage)
1594 /* voltage is bigger than max voltage in the table */
1599 * Preparation of vddc and vddgfx CAC tables for SMC.
1601 * @param hwmgr the address of the hardware manager
1602 * @param table the SMC DPM table structure to be populated
1605 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1606 struct SMU73_Discrete_DpmTable *table)
1611 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1612 struct phm_ppt_v1_information *table_info =
1613 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1614 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1615 table_info->vddc_lookup_table;
1616 /* tables is already swapped, so in order to use the value from it,
1617 * we need to swap it back.
1618 * We are populating vddc CAC data to BapmVddc table
1619 * in split and merged mode
1621 for( count = 0; count<lookup_table->count; count++) {
1622 index = fiji_get_voltage_index(lookup_table,
1623 data->vddc_voltage_table.entries[count].value);
1624 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1625 (lookup_table->entries[index].us_cac_low *
1626 VOLTAGE_SCALE)) / 25);
1627 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1628 (lookup_table->entries[index].us_cac_high *
1629 VOLTAGE_SCALE)) / 25);
1636 * Preparation of voltage tables for SMC.
1638 * @param hwmgr the address of the hardware manager
1639 * @param table the SMC DPM table structure to be populated
1643 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1644 struct SMU73_Discrete_DpmTable *table)
1648 result = fiji_populate_cac_table(hwmgr, table);
1649 PP_ASSERT_WITH_CODE(0 == result,
1650 "can not populate CAC voltage tables to SMC",
1656 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1657 struct SMU73_Discrete_Ulv *state)
1660 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1661 struct phm_ppt_v1_information *table_info =
1662 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1664 state->CcPwrDynRm = 0;
1665 state->CcPwrDynRm1 = 0;
1667 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1668 state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1669 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1671 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1674 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1675 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1676 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1681 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1682 struct SMU73_Discrete_DpmTable *table)
1684 return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1687 static int32_t fiji_get_dpm_level_enable_mask_value(
1688 struct fiji_single_dpm_table* dpm_table)
1693 for (i = dpm_table->count; i > 0; i--) {
1695 if (dpm_table->dpm_levels[i - 1].enabled)
1703 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1704 struct SMU73_Discrete_DpmTable *table)
1706 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1707 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1710 /* Index (dpm_table->pcie_speed_table.count)
1711 * is reserved for PCIE boot level. */
1712 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1713 table->LinkLevel[i].PcieGenSpeed =
1714 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1715 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1716 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1717 table->LinkLevel[i].EnabledForActivity = 1;
1718 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1719 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1720 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1723 data->smc_state_table.LinkLevelCount =
1724 (uint8_t)dpm_table->pcie_speed_table.count;
1725 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1726 fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1732 * Calculates the SCLK dividers using the provided engine clock
1734 * @param hwmgr the address of the hardware manager
1735 * @param clock the engine clock to use to populate the structure
1736 * @param sclk the SMC SCLK structure to be populated
1738 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1739 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1741 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1742 struct pp_atomctrl_clock_dividers_vi dividers;
1743 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1744 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1745 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1746 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1747 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1749 uint32_t ref_divider;
1753 /* get the engine clock dividers for this clock value */
1754 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs);
1756 PP_ASSERT_WITH_CODE(result == 0,
1757 "Error retrieving Engine Clock dividers from VBIOS.",
1760 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1761 ref_clock = atomctrl_get_reference_clock(hwmgr);
1762 ref_divider = 1 + dividers.uc_pll_ref_div;
1764 /* low 14 bits is fraction and high 12 bits is divider */
1765 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1767 /* SPLL_FUNC_CNTL setup */
1768 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1769 SPLL_REF_DIV, dividers.uc_pll_ref_div);
1770 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1771 SPLL_PDIV_A, dividers.uc_pll_post_div);
1773 /* SPLL_FUNC_CNTL_3 setup*/
1774 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1775 SPLL_FB_DIV, fbdiv);
1777 /* set to use fractional accumulation*/
1778 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1781 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1782 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1783 struct pp_atomctrl_internal_ss_info ssInfo;
1785 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1786 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1787 vco_freq, &ssInfo)) {
1789 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1790 * ss_info.speed_spectrum_rate -- in unit of khz
1792 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1794 uint32_t clk_s = ref_clock * 5 /
1795 (ref_divider * ssInfo.speed_spectrum_rate);
1796 /* clkv = 2 * D * fbdiv / NS */
1797 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1798 fbdiv / (clk_s * 10000);
1800 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1801 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1802 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1803 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1804 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1805 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1809 sclk->SclkFrequency = clock;
1810 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
1811 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
1812 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
1813 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
1814 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1819 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1822 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1823 struct pp_atomctrl_voltage_table *vddci_table =
1824 &(data->vddci_voltage_table);
1826 for (i = 0; i < vddci_table->count; i++) {
1827 if (vddci_table->entries[i].value >= vddci)
1828 return vddci_table->entries[i].value;
1831 PP_ASSERT_WITH_CODE(false,
1832 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1833 return vddci_table->entries[i].value);
1836 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1837 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1838 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1842 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1844 *voltage = *mvdd = 0;
1846 /* clock - voltage dependency table is empty table */
1847 if (dep_table->count == 0)
1850 for (i = 0; i < dep_table->count; i++) {
1851 /* find first sclk bigger than request */
1852 if (dep_table->entries[i].clk >= clock) {
1853 *voltage |= (dep_table->entries[i].vddc *
1854 VOLTAGE_SCALE) << VDDC_SHIFT;
1855 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1856 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1857 VOLTAGE_SCALE) << VDDCI_SHIFT;
1858 else if (dep_table->entries[i].vddci)
1859 *voltage |= (dep_table->entries[i].vddci *
1860 VOLTAGE_SCALE) << VDDCI_SHIFT;
1862 vddci = fiji_find_closest_vddci(hwmgr,
1863 (dep_table->entries[i].vddc -
1864 (uint16_t)data->vddc_vddci_delta));
1865 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1868 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1869 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1871 else if (dep_table->entries[i].mvdd)
1872 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1875 *voltage |= 1 << PHASES_SHIFT;
1880 /* sclk is bigger than max sclk in the dependence table */
1881 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1883 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1884 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1885 VOLTAGE_SCALE) << VDDCI_SHIFT;
1886 else if (dep_table->entries[i-1].vddci) {
1887 vddci = fiji_find_closest_vddci(hwmgr,
1888 (dep_table->entries[i].vddc -
1889 (uint16_t)data->vddc_vddci_delta));
1890 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1893 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1894 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1895 else if (dep_table->entries[i].mvdd)
1896 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1901 static uint8_t fiji_get_sleep_divider_id_from_clock(uint32_t clock,
1902 uint32_t clock_insr)
1906 uint32_t min = max(clock_insr, (uint32_t)FIJI_MINIMUM_ENGINE_CLOCK);
1908 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
1909 for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1912 if (temp >= min || i == 0)
1918 * Populates single SMC SCLK structure using the provided engine clock
1920 * @param hwmgr the address of the hardware manager
1921 * @param clock the engine clock to use to populate the structure
1922 * @param sclk the SMC SCLK structure to be populated
1925 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1926 uint32_t clock, uint16_t sclk_al_threshold,
1927 struct SMU73_Discrete_GraphicsLevel *level)
1930 /* PP_Clocks minClocks; */
1931 uint32_t threshold, mvdd;
1932 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1933 struct phm_ppt_v1_information *table_info =
1934 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1936 result = fiji_calculate_sclk_params(hwmgr, clock, level);
1938 /* populate graphics levels */
1939 result = fiji_get_dependency_volt_by_clk(hwmgr,
1940 table_info->vdd_dep_on_sclk, clock,
1941 &level->MinVoltage, &mvdd);
1942 PP_ASSERT_WITH_CODE((0 == result),
1943 "can not find VDDC voltage value for "
1944 "VDDC engine clock dependency table",
1947 level->SclkFrequency = clock;
1948 level->ActivityLevel = sclk_al_threshold;
1949 level->CcPwrDynRm = 0;
1950 level->CcPwrDynRm1 = 0;
1951 level->EnabledForActivity = 0;
1952 level->EnabledForThrottle = 1;
1954 level->DownHyst = 0;
1955 level->VoltageDownHyst = 0;
1956 level->PowerThrottle = 0;
1958 threshold = clock * data->fast_watermark_threshold / 100;
1961 data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
1963 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1964 level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(clock,
1965 hwmgr->display_config.min_core_set_clock_in_sr);
1968 /* Default to slow, highest DPM level will be
1969 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1971 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1973 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1974 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1975 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1976 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1977 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1978 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1979 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1980 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1981 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1986 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1988 * @param hwmgr the address of the hardware manager
1990 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1992 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1993 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1994 struct phm_ppt_v1_information *table_info =
1995 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1996 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1997 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1999 uint32_t array = data->dpm_table_start +
2000 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
2001 uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
2002 SMU73_MAX_LEVELS_GRAPHICS;
2003 struct SMU73_Discrete_GraphicsLevel *levels =
2004 data->smc_state_table.GraphicsLevel;
2005 uint32_t i, max_entry;
2006 uint8_t hightest_pcie_level_enabled = 0,
2007 lowest_pcie_level_enabled = 0,
2008 mid_pcie_level_enabled = 0,
2011 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2012 result = fiji_populate_single_graphic_level(hwmgr,
2013 dpm_table->sclk_table.dpm_levels[i].value,
2014 (uint16_t)data->activity_target[i],
2019 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2021 levels[i].DeepSleepDivId = 0;
2024 /* Only enable level 0 for now.*/
2025 levels[0].EnabledForActivity = 1;
2027 /* set highest level watermark to high */
2028 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
2029 PPSMC_DISPLAY_WATERMARK_HIGH;
2031 data->smc_state_table.GraphicsDpmLevelCount =
2032 (uint8_t)dpm_table->sclk_table.count;
2033 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2034 fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2036 if (pcie_table != NULL) {
2037 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
2038 "There must be 1 or more PCIE levels defined in PPTable.",
2040 max_entry = pcie_entry_cnt - 1;
2041 for (i = 0; i < dpm_table->sclk_table.count; i++)
2042 levels[i].pcieDpmLevel =
2043 (uint8_t) ((i < max_entry)? i : max_entry);
2045 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2046 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2047 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2048 hightest_pcie_level_enabled++;
2050 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2051 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2052 (1 << lowest_pcie_level_enabled)) == 0 ))
2053 lowest_pcie_level_enabled++;
2055 while ((count < hightest_pcie_level_enabled) &&
2056 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2057 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2060 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2061 hightest_pcie_level_enabled?
2062 (lowest_pcie_level_enabled + 1 + count) :
2063 hightest_pcie_level_enabled;
2065 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2066 for(i = 2; i < dpm_table->sclk_table.count; i++)
2067 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2069 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2070 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2072 /* set pcieDpmLevel to mid_pcie_level_enabled */
2073 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2075 /* level count will send to smc once at init smc table and never change */
2076 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2077 (uint32_t)array_size, data->sram_end);
2083 * MCLK Frequency Ratio
2084 * SEQ_CG_RESP Bit[31:24] - 0x0
2085 * Bit[27:24] \96 DDR3 Frequency ratio
2086 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2087 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2088 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2089 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2090 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2091 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2092 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2093 * 400 < 0x7 <= 450MHz, 800 < 0xF
2095 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2097 if (mem_clock <= 10000) return 0x0;
2098 if (mem_clock <= 15000) return 0x1;
2099 if (mem_clock <= 20000) return 0x2;
2100 if (mem_clock <= 25000) return 0x3;
2101 if (mem_clock <= 30000) return 0x4;
2102 if (mem_clock <= 35000) return 0x5;
2103 if (mem_clock <= 40000) return 0x6;
2104 if (mem_clock <= 45000) return 0x7;
2105 if (mem_clock <= 50000) return 0x8;
2106 if (mem_clock <= 55000) return 0x9;
2107 if (mem_clock <= 60000) return 0xa;
2108 if (mem_clock <= 65000) return 0xb;
2109 if (mem_clock <= 70000) return 0xc;
2110 if (mem_clock <= 75000) return 0xd;
2111 if (mem_clock <= 80000) return 0xe;
2112 /* mem_clock > 800MHz */
2117 * Populates the SMC MCLK structure using the provided memory clock
2119 * @param hwmgr the address of the hardware manager
2120 * @param clock the memory clock to use to populate the structure
2121 * @param sclk the SMC SCLK structure to be populated
2123 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2124 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2126 struct pp_atomctrl_memory_clock_param mem_param;
2129 result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2130 PP_ASSERT_WITH_CODE((0 == result),
2131 "Failed to get Memory PLL Dividers.",);
2133 /* Save the result data to outpupt memory level structure */
2134 mclk->MclkFrequency = clock;
2135 mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
2136 mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
2141 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2142 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2144 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2145 struct phm_ppt_v1_information *table_info =
2146 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2149 if (table_info->vdd_dep_on_mclk) {
2150 result = fiji_get_dependency_volt_by_clk(hwmgr,
2151 table_info->vdd_dep_on_mclk, clock,
2152 &mem_level->MinVoltage, &mem_level->MinMvdd);
2153 PP_ASSERT_WITH_CODE((0 == result),
2154 "can not find MinVddc voltage value from memory "
2155 "VDDC voltage dependency table", return result);
2158 mem_level->EnabledForThrottle = 1;
2159 mem_level->EnabledForActivity = 0;
2160 mem_level->UpHyst = 0;
2161 mem_level->DownHyst = 100;
2162 mem_level->VoltageDownHyst = 0;
2163 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2164 mem_level->StutterEnable = false;
2166 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2168 /* enable stutter mode if all the follow condition applied
2169 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2170 * &(data->DisplayTiming.numExistingDisplays));
2172 data->display_timing.num_existing_displays = 1;
2174 if ((data->mclk_stutter_mode_threshold) &&
2175 (clock <= data->mclk_stutter_mode_threshold) &&
2176 (!data->is_uvd_enabled) &&
2177 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2178 STUTTER_ENABLE) & 0x1))
2179 mem_level->StutterEnable = true;
2181 result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2183 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2184 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2185 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2186 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2192 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2194 * @param hwmgr the address of the hardware manager
2196 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2198 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2199 struct fiji_dpm_table *dpm_table = &data->dpm_table;
2201 /* populate MCLK dpm table to SMU7 */
2202 uint32_t array = data->dpm_table_start +
2203 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2204 uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2205 SMU73_MAX_LEVELS_MEMORY;
2206 struct SMU73_Discrete_MemoryLevel *levels =
2207 data->smc_state_table.MemoryLevel;
2210 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2211 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2212 "can not populate memory level as memory clock is zero",
2214 result = fiji_populate_single_memory_level(hwmgr,
2215 dpm_table->mclk_table.dpm_levels[i].value,
2221 /* Only enable level 0 for now. */
2222 levels[0].EnabledForActivity = 1;
2224 /* in order to prevent MC activity from stutter mode to push DPM up.
2225 * the UVD change complements this by putting the MCLK in
2226 * a higher state by default such that we are not effected by
2227 * up threshold or and MCLK DPM latency.
2229 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2230 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2232 data->smc_state_table.MemoryDpmLevelCount =
2233 (uint8_t)dpm_table->mclk_table.count;
2234 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2235 fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2236 /* set highest level watermark to high */
2237 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2238 PPSMC_DISPLAY_WATERMARK_HIGH;
2240 /* level count will send to smc once at init smc table and never change */
2241 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2242 (uint32_t)array_size, data->sram_end);
2248 * Populates the SMC MVDD structure using the provided memory clock.
2250 * @param hwmgr the address of the hardware manager
2251 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2252 * @param voltage the SMC VOLTAGE structure to be populated
2254 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2255 uint32_t mclk, SMIO_Pattern *smio_pat)
2257 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2258 struct phm_ppt_v1_information *table_info =
2259 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2262 if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2263 /* find mvdd value which clock is more than request */
2264 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2265 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2266 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2270 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2271 "MVDD Voltage is outside the supported range.",
2279 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2280 SMU73_Discrete_DpmTable *table)
2283 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2284 struct phm_ppt_v1_information *table_info =
2285 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2286 struct pp_atomctrl_clock_dividers_vi dividers;
2287 SMIO_Pattern vol_level;
2290 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2291 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2293 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2295 if (!data->sclk_dpm_key_disabled) {
2296 /* Get MinVoltage and Frequency from DPM0,
2297 * already converted to SMC_UL */
2298 table->ACPILevel.SclkFrequency =
2299 data->dpm_table.sclk_table.dpm_levels[0].value;
2300 result = fiji_get_dependency_volt_by_clk(hwmgr,
2301 table_info->vdd_dep_on_sclk,
2302 table->ACPILevel.SclkFrequency,
2303 &table->ACPILevel.MinVoltage, &mvdd);
2304 PP_ASSERT_WITH_CODE((0 == result),
2305 "Cannot find ACPI VDDC voltage value "
2306 "in Clock Dependency Table",);
2308 table->ACPILevel.SclkFrequency =
2309 data->vbios_boot_state.sclk_bootup_value;
2310 table->ACPILevel.MinVoltage =
2311 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2314 /* get the engine clock dividers for this clock value */
2315 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2316 table->ACPILevel.SclkFrequency, ÷rs);
2317 PP_ASSERT_WITH_CODE(result == 0,
2318 "Error retrieving Engine Clock dividers from VBIOS.",
2321 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2322 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2323 table->ACPILevel.DeepSleepDivId = 0;
2325 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2329 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2332 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2333 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2334 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2335 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2336 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2337 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2338 table->ACPILevel.CcPwrDynRm = 0;
2339 table->ACPILevel.CcPwrDynRm1 = 0;
2341 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2342 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2343 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2344 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2345 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2346 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2347 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2348 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2349 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2350 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2351 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2353 if (!data->mclk_dpm_key_disabled) {
2354 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2355 table->MemoryACPILevel.MclkFrequency =
2356 data->dpm_table.mclk_table.dpm_levels[0].value;
2357 result = fiji_get_dependency_volt_by_clk(hwmgr,
2358 table_info->vdd_dep_on_mclk,
2359 table->MemoryACPILevel.MclkFrequency,
2360 &table->MemoryACPILevel.MinVoltage, &mvdd);
2361 PP_ASSERT_WITH_CODE((0 == result),
2362 "Cannot find ACPI VDDCI voltage value "
2363 "in Clock Dependency Table",);
2365 table->MemoryACPILevel.MclkFrequency =
2366 data->vbios_boot_state.mclk_bootup_value;
2367 table->MemoryACPILevel.MinVoltage =
2368 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2372 if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2373 (data->mclk_dpm_key_disabled))
2374 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2376 if (!fiji_populate_mvdd_value(hwmgr,
2377 data->dpm_table.mclk_table.dpm_levels[0].value,
2379 us_mvdd = vol_level.Voltage;
2382 table->MemoryACPILevel.MinMvdd =
2383 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2385 table->MemoryACPILevel.EnabledForThrottle = 0;
2386 table->MemoryACPILevel.EnabledForActivity = 0;
2387 table->MemoryACPILevel.UpHyst = 0;
2388 table->MemoryACPILevel.DownHyst = 100;
2389 table->MemoryACPILevel.VoltageDownHyst = 0;
2390 table->MemoryACPILevel.ActivityLevel =
2391 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2393 table->MemoryACPILevel.StutterEnable = false;
2394 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2395 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2400 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2401 SMU73_Discrete_DpmTable *table)
2403 int result = -EINVAL;
2405 struct pp_atomctrl_clock_dividers_vi dividers;
2406 struct phm_ppt_v1_information *table_info =
2407 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2408 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2409 table_info->mm_dep_table;
2410 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2412 table->VceLevelCount = (uint8_t)(mm_table->count);
2413 table->VceBootLevel = 0;
2415 for(count = 0; count < table->VceLevelCount; count++) {
2416 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2417 table->VceLevel[count].MinVoltage = 0;
2418 table->VceLevel[count].MinVoltage |=
2419 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2420 table->VceLevel[count].MinVoltage |=
2421 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2422 VOLTAGE_SCALE) << VDDCI_SHIFT;
2423 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2425 /*retrieve divider value for VBIOS */
2426 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2427 table->VceLevel[count].Frequency, ÷rs);
2428 PP_ASSERT_WITH_CODE((0 == result),
2429 "can not find divide id for VCE engine clock",
2432 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2434 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2435 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2440 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2441 SMU73_Discrete_DpmTable *table)
2443 int result = -EINVAL;
2445 struct pp_atomctrl_clock_dividers_vi dividers;
2446 struct phm_ppt_v1_information *table_info =
2447 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2448 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2449 table_info->mm_dep_table;
2450 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2452 table->AcpLevelCount = (uint8_t)(mm_table->count);
2453 table->AcpBootLevel = 0;
2455 for (count = 0; count < table->AcpLevelCount; count++) {
2456 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2457 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2458 VOLTAGE_SCALE) << VDDC_SHIFT;
2459 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2460 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2461 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2463 /* retrieve divider value for VBIOS */
2464 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2465 table->AcpLevel[count].Frequency, ÷rs);
2466 PP_ASSERT_WITH_CODE((0 == result),
2467 "can not find divide id for engine clock", return result);
2469 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2471 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2472 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2477 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2478 SMU73_Discrete_DpmTable *table)
2480 int result = -EINVAL;
2482 struct pp_atomctrl_clock_dividers_vi dividers;
2483 struct phm_ppt_v1_information *table_info =
2484 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2485 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2486 table_info->mm_dep_table;
2487 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2489 table->SamuBootLevel = 0;
2490 table->SamuLevelCount = (uint8_t)(mm_table->count);
2492 for (count = 0; count < table->SamuLevelCount; count++) {
2493 /* not sure whether we need evclk or not */
2494 table->SamuLevel[count].MinVoltage = 0;
2495 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2496 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2497 VOLTAGE_SCALE) << VDDC_SHIFT;
2498 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2499 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2500 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2502 /* retrieve divider value for VBIOS */
2503 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2504 table->SamuLevel[count].Frequency, ÷rs);
2505 PP_ASSERT_WITH_CODE((0 == result),
2506 "can not find divide id for samu clock", return result);
2508 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2510 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2511 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2516 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2517 int32_t eng_clock, int32_t mem_clock,
2518 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2520 uint32_t dram_timing;
2521 uint32_t dram_timing2;
2523 ULONG state, trrds, trrdl;
2526 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2527 eng_clock, mem_clock);
2528 PP_ASSERT_WITH_CODE(result == 0,
2529 "Error calling VBIOS to set DRAM_TIMING.", return result);
2531 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2532 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2533 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2535 state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2536 trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2537 trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2539 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
2540 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2541 arb_regs->McArbBurstTime = (uint8_t)burstTime;
2542 arb_regs->TRRDS = (uint8_t)trrds;
2543 arb_regs->TRRDL = (uint8_t)trrdl;
2548 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2550 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2551 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2555 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2556 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2557 result = fiji_populate_memory_timing_parameters(hwmgr,
2558 data->dpm_table.sclk_table.dpm_levels[i].value,
2559 data->dpm_table.mclk_table.dpm_levels[j].value,
2560 &arb_regs.entries[i][j]);
2567 result = fiji_copy_bytes_to_smc(
2569 data->arb_table_start,
2570 (uint8_t *)&arb_regs,
2571 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2576 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2577 struct SMU73_Discrete_DpmTable *table)
2579 int result = -EINVAL;
2581 struct pp_atomctrl_clock_dividers_vi dividers;
2582 struct phm_ppt_v1_information *table_info =
2583 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2584 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2585 table_info->mm_dep_table;
2586 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2588 table->UvdLevelCount = (uint8_t)(mm_table->count);
2589 table->UvdBootLevel = 0;
2591 for (count = 0; count < table->UvdLevelCount; count++) {
2592 table->UvdLevel[count].MinVoltage = 0;
2593 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2594 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2595 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2596 VOLTAGE_SCALE) << VDDC_SHIFT;
2597 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2598 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2599 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2601 /* retrieve divider value for VBIOS */
2602 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2603 table->UvdLevel[count].VclkFrequency, ÷rs);
2604 PP_ASSERT_WITH_CODE((0 == result),
2605 "can not find divide id for Vclk clock", return result);
2607 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2609 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2610 table->UvdLevel[count].DclkFrequency, ÷rs);
2611 PP_ASSERT_WITH_CODE((0 == result),
2612 "can not find divide id for Dclk clock", return result);
2614 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2616 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2617 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2618 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2624 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2625 uint32_t value, uint32_t *boot_level)
2627 int result = -EINVAL;
2630 for (i = 0; i < table->count; i++) {
2631 if (value == table->dpm_levels[i].value) {
2639 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2640 struct SMU73_Discrete_DpmTable *table)
2643 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2645 table->GraphicsBootLevel = 0;
2646 table->MemoryBootLevel = 0;
2648 /* find boot level from dpm table */
2649 result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2650 data->vbios_boot_state.sclk_bootup_value,
2651 (uint32_t *)&(table->GraphicsBootLevel));
2653 result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2654 data->vbios_boot_state.mclk_bootup_value,
2655 (uint32_t *)&(table->MemoryBootLevel));
2657 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
2659 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2661 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
2664 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2665 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2666 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2671 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2673 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2674 struct phm_ppt_v1_information *table_info =
2675 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2676 uint8_t count, level;
2678 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2679 for (level = 0; level < count; level++) {
2680 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2681 data->vbios_boot_state.sclk_bootup_value) {
2682 data->smc_state_table.GraphicsBootLevel = level;
2687 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2688 for (level = 0; level < count; level++) {
2689 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2690 data->vbios_boot_state.mclk_bootup_value) {
2691 data->smc_state_table.MemoryBootLevel = level;
2699 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2701 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2702 volt_with_cks, value;
2703 uint16_t clock_freq_u16;
2704 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2705 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2707 struct phm_ppt_v1_information *table_info =
2708 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2709 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2710 table_info->vdd_dep_on_sclk;
2712 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2714 /* Read SMU_Eefuse to read and calculate RO and determine
2715 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2717 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2718 ixSMU_EFUSE_0 + (146 * 4));
2719 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2720 ixSMU_EFUSE_0 + (148 * 4));
2721 efuse &= 0xFF000000;
2722 efuse = efuse >> 24;
2726 ro = (2300 - 1350) * efuse / 255 + 1350;
2728 ro = (2500 - 1000) * efuse / 255 + 1000;
2735 /* Populate Stretch amount */
2736 data->smc_state_table.ClockStretcherAmount = stretch_amount;
2738 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2739 for (i = 0; i < sclk_table->count; i++) {
2740 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2741 sclk_table->entries[i].cks_enable << i;
2742 volt_without_cks = (uint32_t)((14041 *
2743 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2744 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2745 volt_with_cks = (uint32_t)((13946 *
2746 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2747 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2748 if (volt_without_cks >= volt_with_cks)
2749 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2750 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2751 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2754 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2755 STRETCH_ENABLE, 0x0);
2756 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2758 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2760 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2763 /* Populate CKS Lookup Table */
2764 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2765 stretch_amount2 = 0;
2766 else if (stretch_amount == 3 || stretch_amount == 4)
2767 stretch_amount2 = 1;
2769 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2770 PHM_PlatformCaps_ClockStretcher);
2771 PP_ASSERT_WITH_CODE(false,
2772 "Stretch Amount in PPTable not supported\n",
2776 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2778 value &= 0xFFC2FF87;
2779 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2780 fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2781 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2782 fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2783 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2784 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2785 SclkFrequency) / 100);
2786 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2788 fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2790 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2791 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2792 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2793 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2794 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2795 value |= (fiji_clock_stretch_amount_conversion
2796 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2797 [stretch_amount]) << 3;
2799 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2800 CKS_LOOKUPTableEntry[0].minFreq);
2801 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2802 CKS_LOOKUPTableEntry[0].maxFreq);
2803 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2804 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2805 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2806 (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2808 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2809 ixPWR_CKS_CNTL, value);
2811 /* Populate DDT Lookup Table */
2812 for (i = 0; i < 4; i++) {
2813 /* Assign the minimum and maximum VID stored
2814 * in the last row of Clock Stretcher Voltage Table.
2816 data->smc_state_table.ClockStretcherDataTable.
2817 ClockStretcherDataTableEntry[i].minVID =
2818 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2819 data->smc_state_table.ClockStretcherDataTable.
2820 ClockStretcherDataTableEntry[i].maxVID =
2821 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2822 /* Loop through each SCLK and check the frequency
2823 * to see if it lies within the frequency for clock stretcher.
2825 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2827 clock_freq = PP_SMC_TO_HOST_UL(
2828 data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2829 /* Check the allowed frequency against the sclk level[j].
2830 * Sclk's endianness has already been converted,
2831 * and it's in 10Khz unit,
2832 * as opposed to Data table, which is in Mhz unit.
2835 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2838 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2841 data->smc_state_table.ClockStretcherDataTable.
2842 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2844 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2845 ClockStretcherDataTable.
2846 ClockStretcherDataTableEntry[i].setting);
2849 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2850 value &= 0xFFFFFFFE;
2851 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2857 * Populates the SMC VRConfig field in DPM table.
2859 * @param hwmgr the address of the hardware manager
2860 * @param table the SMC DPM table structure to be populated
2863 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2864 struct SMU73_Discrete_DpmTable *table)
2866 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2869 config = VR_MERGED_WITH_VDDC;
2870 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2872 /* Set Vddc Voltage Controller */
2873 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2874 config = VR_SVI2_PLANE_1;
2875 table->VRConfig |= config;
2877 PP_ASSERT_WITH_CODE(false,
2878 "VDDC should be on SVI2 control in merged mode!",);
2880 /* Set Vddci Voltage Controller */
2881 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2882 config = VR_SVI2_PLANE_2; /* only in merged mode */
2883 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2884 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2885 config = VR_SMIO_PATTERN_1;
2886 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2888 config = VR_STATIC_VOLTAGE;
2889 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2891 /* Set Mvdd Voltage Controller */
2892 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2893 config = VR_SVI2_PLANE_2;
2894 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2895 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2896 config = VR_SMIO_PATTERN_2;
2897 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2899 config = VR_STATIC_VOLTAGE;
2900 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2907 * Initializes the SMC table and uploads it
2909 * @param hwmgr the address of the powerplay hardware manager.
2910 * @param pInput the pointer to input data (PowerState)
2913 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2916 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2917 struct phm_ppt_v1_information *table_info =
2918 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2919 struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2920 const struct fiji_ulv_parm *ulv = &(data->ulv);
2922 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2924 result = fiji_setup_default_dpm_tables(hwmgr);
2925 PP_ASSERT_WITH_CODE(0 == result,
2926 "Failed to setup default DPM tables!", return result);
2928 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2929 fiji_populate_smc_voltage_tables(hwmgr, table);
2931 table->SystemFlags = 0;
2933 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2934 PHM_PlatformCaps_AutomaticDCTransition))
2935 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2937 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2938 PHM_PlatformCaps_StepVddc))
2939 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2941 if (data->is_memory_gddr5)
2942 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2944 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2945 result = fiji_populate_ulv_state(hwmgr, table);
2946 PP_ASSERT_WITH_CODE(0 == result,
2947 "Failed to initialize ULV state!", return result);
2948 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2949 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2952 result = fiji_populate_smc_link_level(hwmgr, table);
2953 PP_ASSERT_WITH_CODE(0 == result,
2954 "Failed to initialize Link Level!", return result);
2956 result = fiji_populate_all_graphic_levels(hwmgr);
2957 PP_ASSERT_WITH_CODE(0 == result,
2958 "Failed to initialize Graphics Level!", return result);
2960 result = fiji_populate_all_memory_levels(hwmgr);
2961 PP_ASSERT_WITH_CODE(0 == result,
2962 "Failed to initialize Memory Level!", return result);
2964 result = fiji_populate_smc_acpi_level(hwmgr, table);
2965 PP_ASSERT_WITH_CODE(0 == result,
2966 "Failed to initialize ACPI Level!", return result);
2968 result = fiji_populate_smc_vce_level(hwmgr, table);
2969 PP_ASSERT_WITH_CODE(0 == result,
2970 "Failed to initialize VCE Level!", return result);
2972 result = fiji_populate_smc_acp_level(hwmgr, table);
2973 PP_ASSERT_WITH_CODE(0 == result,
2974 "Failed to initialize ACP Level!", return result);
2976 result = fiji_populate_smc_samu_level(hwmgr, table);
2977 PP_ASSERT_WITH_CODE(0 == result,
2978 "Failed to initialize SAMU Level!", return result);
2980 /* Since only the initial state is completely set up at this point
2981 * (the other states are just copies of the boot state) we only
2982 * need to populate the ARB settings for the initial state.
2984 result = fiji_program_memory_timing_parameters(hwmgr);
2985 PP_ASSERT_WITH_CODE(0 == result,
2986 "Failed to Write ARB settings for the initial state.", return result);
2988 result = fiji_populate_smc_uvd_level(hwmgr, table);
2989 PP_ASSERT_WITH_CODE(0 == result,
2990 "Failed to initialize UVD Level!", return result);
2992 result = fiji_populate_smc_boot_level(hwmgr, table);
2993 PP_ASSERT_WITH_CODE(0 == result,
2994 "Failed to initialize Boot Level!", return result);
2996 result = fiji_populate_smc_initailial_state(hwmgr);
2997 PP_ASSERT_WITH_CODE(0 == result,
2998 "Failed to initialize Boot State!", return result);
3000 result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
3001 PP_ASSERT_WITH_CODE(0 == result,
3002 "Failed to populate BAPM Parameters!", return result);
3004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3005 PHM_PlatformCaps_ClockStretcher)) {
3006 result = fiji_populate_clock_stretcher_data_table(hwmgr);
3007 PP_ASSERT_WITH_CODE(0 == result,
3008 "Failed to populate Clock Stretcher Data Table!",
3012 table->GraphicsVoltageChangeEnable = 1;
3013 table->GraphicsThermThrottleEnable = 1;
3014 table->GraphicsInterval = 1;
3015 table->VoltageInterval = 1;
3016 table->ThermalInterval = 1;
3017 table->TemperatureLimitHigh =
3018 table_info->cac_dtp_table->usTargetOperatingTemp *
3019 FIJI_Q88_FORMAT_CONVERSION_UNIT;
3020 table->TemperatureLimitLow =
3021 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3022 FIJI_Q88_FORMAT_CONVERSION_UNIT;
3023 table->MemoryVoltageChangeEnable = 1;
3024 table->MemoryInterval = 1;
3025 table->VoltageResponseTime = 0;
3026 table->PhaseResponseTime = 0;
3027 table->MemoryThermThrottleEnable = 1;
3028 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
3029 table->PCIeGenInterval = 1;
3030 table->VRConfig = 0;
3032 result = fiji_populate_vr_config(hwmgr, table);
3033 PP_ASSERT_WITH_CODE(0 == result,
3034 "Failed to populate VRConfig setting!", return result);
3036 table->ThermGpio = 17;
3037 table->SclkStepSize = 0x4000;
3039 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
3040 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
3041 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3042 PHM_PlatformCaps_RegulatorHot);
3044 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
3045 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3046 PHM_PlatformCaps_RegulatorHot);
3049 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3051 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
3052 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3053 PHM_PlatformCaps_AutomaticDCTransition);
3055 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3056 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3057 PHM_PlatformCaps_AutomaticDCTransition);
3060 /* Thermal Output GPIO */
3061 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3063 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3064 PHM_PlatformCaps_ThermalOutGPIO);
3066 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3068 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3069 * since VBIOS will program this register to set 'inactive state',
3070 * driver can then determine 'active state' from this and
3071 * program SMU with correct polarity
3073 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3074 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3075 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3077 /* if required, combine VRHot/PCC with thermal out GPIO */
3078 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3079 PHM_PlatformCaps_RegulatorHot) &&
3080 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3081 PHM_PlatformCaps_CombinePCCWithThermalSignal))
3082 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3084 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3085 PHM_PlatformCaps_ThermalOutGPIO);
3086 table->ThermOutGpio = 17;
3087 table->ThermOutPolarity = 1;
3088 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3091 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3092 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3094 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3095 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3096 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3097 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3098 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3099 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3100 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3101 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3102 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3104 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3105 result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3106 data->dpm_table_start +
3107 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3108 (uint8_t *)&(table->SystemFlags),
3109 sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3111 PP_ASSERT_WITH_CODE(0 == result,
3112 "Failed to upload dpm data to SMC memory!", return result);
3118 * Initialize the ARB DRAM timing table's index field.
3120 * @param hwmgr the address of the powerplay hardware manager.
3123 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3125 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3129 /* This is a read-modify-write on the first byte of the ARB table.
3130 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3131 * is the field 'current'.
3132 * This solution is ugly, but we never write the whole table only
3133 * individual fields in it.
3134 * In reality this field should not be in that structure
3135 * but in a soft register.
3137 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3138 data->arb_table_start, &tmp, data->sram_end);
3144 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3146 return fiji_write_smc_sram_dword(hwmgr->smumgr,
3147 data->arb_table_start, tmp, data->sram_end);
3150 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3152 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3153 PHM_PlatformCaps_RegulatorHot))
3154 return smum_send_msg_to_smc(hwmgr->smumgr,
3155 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3160 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3162 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3163 SCLK_PWRMGT_OFF, 0);
3167 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3169 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3170 struct fiji_ulv_parm *ulv = &(data->ulv);
3172 if (ulv->ulv_supported)
3173 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3178 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3180 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3181 PHM_PlatformCaps_SclkDeepSleep)) {
3182 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3183 PP_ASSERT_WITH_CODE(false,
3184 "Attempt to enable Master Deep Sleep switch failed!",
3187 if (smum_send_msg_to_smc(hwmgr->smumgr,
3188 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3189 PP_ASSERT_WITH_CODE(false,
3190 "Attempt to disable Master Deep Sleep switch failed!",
3198 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3200 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3201 uint32_t val, val0, val2;
3202 uint32_t i, cpl_cntl, cpl_threshold, mc_threshold;
3204 /* enable SCLK dpm */
3205 if(!data->sclk_dpm_key_disabled)
3206 PP_ASSERT_WITH_CODE(
3207 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3208 "Failed to enable SCLK DPM during DPM Start Function!",
3211 /* enable MCLK dpm */
3212 if(0 == data->mclk_dpm_key_disabled) {
3216 /* Read per MCD tile (0 - 7) */
3217 for (i = 0; i < 8; i++) {
3218 PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3219 val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3220 if (0xf0000000 != val) {
3221 /* count number of MCQ that has channel(s) enabled */
3223 /* only harvest 3 or full 4 supported */
3224 mc_threshold = val ? 3 : 4;
3227 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3228 "Number of MCQ is zero!", return -EINVAL;);
3230 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3231 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3232 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3233 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3234 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3235 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3236 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3238 ixLCAC_MC0_CNTL, mc_threshold);
3239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3240 ixLCAC_MC1_CNTL, mc_threshold);
3241 if (8 == cpl_threshold) {
3242 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3243 ixLCAC_MC2_CNTL, mc_threshold);
3244 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3245 ixLCAC_MC3_CNTL, mc_threshold);
3246 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3247 ixLCAC_MC4_CNTL, mc_threshold);
3248 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3249 ixLCAC_MC5_CNTL, mc_threshold);
3250 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3251 ixLCAC_MC6_CNTL, mc_threshold);
3252 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3253 ixLCAC_MC7_CNTL, mc_threshold);
3255 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3256 ixLCAC_CPL_CNTL, cpl_cntl);
3260 mc_threshold = mc_threshold |
3261 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3262 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3263 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3264 ixLCAC_MC0_CNTL, mc_threshold);
3265 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3266 ixLCAC_MC1_CNTL, mc_threshold);
3267 if (8 == cpl_threshold) {
3268 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3269 ixLCAC_MC2_CNTL, mc_threshold);
3270 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3271 ixLCAC_MC3_CNTL, mc_threshold);
3272 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3273 ixLCAC_MC4_CNTL, mc_threshold);
3274 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3275 ixLCAC_MC5_CNTL, mc_threshold);
3276 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3277 ixLCAC_MC6_CNTL, mc_threshold);
3278 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3279 ixLCAC_MC7_CNTL, mc_threshold);
3281 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3282 ixLCAC_CPL_CNTL, cpl_cntl);
3284 /* Program CAC_EN per MCD (0-7) Tile */
3285 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3286 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3287 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3288 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3289 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3290 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3291 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3292 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3293 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3294 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3296 for (i = 0; i < 8; i++) {
3297 /* Enable MCD i Tile read & write */
3298 val2 = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3300 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3301 /* Enbale CAC_ON MCD i Tile */
3302 val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3303 val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3304 cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3306 /* Set MC_CONFIG_MCD back to its default setting val0 */
3307 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3309 PP_ASSERT_WITH_CODE(
3310 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3311 PPSMC_MSG_MCLKDPM_Enable)),
3312 "Failed to enable MCLK DPM during DPM Start Function!",
3318 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3320 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3322 /*enable general power management */
3323 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3324 GLOBAL_PWRMGT_EN, 1);
3325 /* enable sclk deep sleep */
3326 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3328 /* prepare for PCIE DPM */
3329 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3330 data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3331 VoltageChangeTimeout), 0x1000);
3332 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3333 SWRST_COMMAND_1, RESETLC, 0x0);
3335 PP_ASSERT_WITH_CODE(
3336 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3337 PPSMC_MSG_Voltage_Cntl_Enable)),
3338 "Failed to enable voltage DPM during DPM Start Function!",
3341 if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3342 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3346 /* enable PCIE dpm */
3347 if(!data->pcie_dpm_key_disabled) {
3348 PP_ASSERT_WITH_CODE(
3349 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3350 PPSMC_MSG_PCIeDPM_Enable)),
3351 "Failed to enable pcie DPM during DPM Start Function!",
3358 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3362 enum DPM_EVENT_SRC src;
3366 printk(KERN_ERR "Unknown throttling event sources.");
3372 case (1 << PHM_AutoThrottleSource_Thermal):
3374 src = DPM_EVENT_SRC_DIGITAL;
3376 case (1 << PHM_AutoThrottleSource_External):
3378 src = DPM_EVENT_SRC_EXTERNAL;
3380 case (1 << PHM_AutoThrottleSource_External) |
3381 (1 << PHM_AutoThrottleSource_Thermal):
3383 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3386 /* Order matters - don't enable thermal protection for the wrong source. */
3388 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3389 DPM_EVENT_SRC, src);
3390 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3391 THERMAL_PROTECTION_DIS,
3392 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3393 PHM_PlatformCaps_ThermalController));
3395 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3396 THERMAL_PROTECTION_DIS, 1);
3399 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3400 PHM_AutoThrottleSource source)
3402 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3404 if (!(data->active_auto_throttle_sources & (1 << source))) {
3405 data->active_auto_throttle_sources |= 1 << source;
3406 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3411 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3413 return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3416 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3418 int tmp_result, result = 0;
3420 tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3421 PP_ASSERT_WITH_CODE(result == 0,
3422 "DPM is already running right now, no need to enable DPM!",
3425 if (fiji_voltage_control(hwmgr)) {
3426 tmp_result = fiji_enable_voltage_control(hwmgr);
3427 PP_ASSERT_WITH_CODE(tmp_result == 0,
3428 "Failed to enable voltage control!",
3429 result = tmp_result);
3432 if (fiji_voltage_control(hwmgr)) {
3433 tmp_result = fiji_construct_voltage_tables(hwmgr);
3434 PP_ASSERT_WITH_CODE((0 == tmp_result),
3435 "Failed to contruct voltage tables!",
3436 result = tmp_result);
3439 tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3440 PP_ASSERT_WITH_CODE((0 == tmp_result),
3441 "Failed to initialize MC reg table!", result = tmp_result);
3443 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3444 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3445 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3446 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3448 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3449 PHM_PlatformCaps_ThermalController))
3450 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3451 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3453 tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3454 PP_ASSERT_WITH_CODE((0 == tmp_result),
3455 "Failed to program static screen threshold parameters!",
3456 result = tmp_result);
3458 tmp_result = fiji_enable_display_gap(hwmgr);
3459 PP_ASSERT_WITH_CODE((0 == tmp_result),
3460 "Failed to enable display gap!", result = tmp_result);
3462 tmp_result = fiji_program_voting_clients(hwmgr);
3463 PP_ASSERT_WITH_CODE((0 == tmp_result),
3464 "Failed to program voting clients!", result = tmp_result);
3466 tmp_result = fiji_process_firmware_header(hwmgr);
3467 PP_ASSERT_WITH_CODE((0 == tmp_result),
3468 "Failed to process firmware header!", result = tmp_result);
3470 tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3471 PP_ASSERT_WITH_CODE((0 == tmp_result),
3472 "Failed to initialize switch from ArbF0 to F1!",
3473 result = tmp_result);
3475 tmp_result = fiji_init_smc_table(hwmgr);
3476 PP_ASSERT_WITH_CODE((0 == tmp_result),
3477 "Failed to initialize SMC table!", result = tmp_result);
3479 tmp_result = fiji_init_arb_table_index(hwmgr);
3480 PP_ASSERT_WITH_CODE((0 == tmp_result),
3481 "Failed to initialize ARB table index!", result = tmp_result);
3483 tmp_result = fiji_populate_pm_fuses(hwmgr);
3484 PP_ASSERT_WITH_CODE((0 == tmp_result),
3485 "Failed to populate PM fuses!", result = tmp_result);
3487 tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3488 PP_ASSERT_WITH_CODE((0 == tmp_result),
3489 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3491 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
3492 PP_ASSERT_WITH_CODE((0 == tmp_result),
3493 "Failed to notify no display!", result = tmp_result);
3495 tmp_result = fiji_enable_sclk_control(hwmgr);
3496 PP_ASSERT_WITH_CODE((0 == tmp_result),
3497 "Failed to enable SCLK control!", result = tmp_result);
3499 tmp_result = fiji_enable_ulv(hwmgr);
3500 PP_ASSERT_WITH_CODE((0 == tmp_result),
3501 "Failed to enable ULV!", result = tmp_result);
3503 tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3504 PP_ASSERT_WITH_CODE((0 == tmp_result),
3505 "Failed to enable deep sleep master switch!", result = tmp_result);
3507 tmp_result = fiji_start_dpm(hwmgr);
3508 PP_ASSERT_WITH_CODE((0 == tmp_result),
3509 "Failed to start DPM!", result = tmp_result);
3511 tmp_result = fiji_enable_smc_cac(hwmgr);
3512 PP_ASSERT_WITH_CODE((0 == tmp_result),
3513 "Failed to enable SMC CAC!", result = tmp_result);
3515 tmp_result = fiji_enable_power_containment(hwmgr);
3516 PP_ASSERT_WITH_CODE((0 == tmp_result),
3517 "Failed to enable power containment!", result = tmp_result);
3519 tmp_result = fiji_power_control_set_level(hwmgr);
3520 PP_ASSERT_WITH_CODE((0 == tmp_result),
3521 "Failed to power control set level!", result = tmp_result);
3523 tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3524 PP_ASSERT_WITH_CODE((0 == tmp_result),
3525 "Failed to enable thermal auto throttle!", result = tmp_result);
3530 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3532 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3533 uint32_t level, tmp;
3535 if (!data->sclk_dpm_key_disabled) {
3536 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3538 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3542 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3543 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3548 if (!data->mclk_dpm_key_disabled) {
3549 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3551 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3555 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3556 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3561 if (!data->pcie_dpm_key_disabled) {
3562 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3564 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3568 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3569 PPSMC_MSG_PCIeDPM_ForceLevel,
3576 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3578 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3580 phm_apply_dal_min_voltage_request(hwmgr);
3582 if (!data->sclk_dpm_key_disabled) {
3583 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3584 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3585 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3586 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3591 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3593 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3595 if (!fiji_is_dpm_running(hwmgr))
3598 if (!data->pcie_dpm_key_disabled) {
3599 smum_send_msg_to_smc(hwmgr->smumgr,
3600 PPSMC_MSG_PCIeDPM_UnForceLevel);
3603 return fiji_upload_dpmlevel_enable_mask(hwmgr);
3606 static uint32_t fiji_get_lowest_enabled_level(
3607 struct pp_hwmgr *hwmgr, uint32_t mask)
3611 while(0 == (mask & (1 << level)))
3617 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3619 struct fiji_hwmgr *data =
3620 (struct fiji_hwmgr *)(hwmgr->backend);
3623 if (!data->sclk_dpm_key_disabled)
3624 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3625 level = fiji_get_lowest_enabled_level(hwmgr,
3626 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3627 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3628 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3633 if (!data->mclk_dpm_key_disabled) {
3634 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3635 level = fiji_get_lowest_enabled_level(hwmgr,
3636 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3637 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3638 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3643 if (!data->pcie_dpm_key_disabled) {
3644 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3645 level = fiji_get_lowest_enabled_level(hwmgr,
3646 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3647 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3648 PPSMC_MSG_PCIeDPM_ForceLevel,
3656 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3657 enum amd_dpm_forced_level level)
3662 case AMD_DPM_FORCED_LEVEL_HIGH:
3663 ret = fiji_force_dpm_highest(hwmgr);
3667 case AMD_DPM_FORCED_LEVEL_LOW:
3668 ret = fiji_force_dpm_lowest(hwmgr);
3672 case AMD_DPM_FORCED_LEVEL_AUTO:
3673 ret = fiji_unforce_dpm_levels(hwmgr);
3681 hwmgr->dpm_level = level;
3686 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3688 return sizeof(struct fiji_power_state);
3691 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3692 void *state, struct pp_power_state *power_state,
3693 void *pp_table, uint32_t classification_flag)
3695 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3696 struct fiji_power_state *fiji_power_state =
3697 (struct fiji_power_state *)(&(power_state->hardware));
3698 struct fiji_performance_level *performance_level;
3699 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3700 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3701 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3702 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3703 (ATOM_Tonga_SCLK_Dependency_Table *)
3704 (((unsigned long)powerplay_table) +
3705 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3706 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3707 (ATOM_Tonga_MCLK_Dependency_Table *)
3708 (((unsigned long)powerplay_table) +
3709 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3711 /* The following fields are not initialized here: id orderedList allStatesList */
3712 power_state->classification.ui_label =
3713 (le16_to_cpu(state_entry->usClassification) &
3714 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3715 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3716 power_state->classification.flags = classification_flag;
3717 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3719 power_state->classification.temporary_state = false;
3720 power_state->classification.to_be_deleted = false;
3722 power_state->validation.disallowOnDC =
3723 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3724 ATOM_Tonga_DISALLOW_ON_DC));
3726 power_state->pcie.lanes = 0;
3728 power_state->display.disableFrameModulation = false;
3729 power_state->display.limitRefreshrate = false;
3730 power_state->display.enableVariBright =
3731 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3732 ATOM_Tonga_ENABLE_VARIBRIGHT));
3734 power_state->validation.supportedPowerLevels = 0;
3735 power_state->uvd_clocks.VCLK = 0;
3736 power_state->uvd_clocks.DCLK = 0;
3737 power_state->temperatures.min = 0;
3738 power_state->temperatures.max = 0;
3740 performance_level = &(fiji_power_state->performance_levels
3741 [fiji_power_state->performance_level_count++]);
3743 PP_ASSERT_WITH_CODE(
3744 (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3745 "Performance levels exceeds SMC limit!",
3748 PP_ASSERT_WITH_CODE(
3749 (fiji_power_state->performance_level_count <=
3750 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3751 "Performance levels exceeds Driver limit!",
3754 /* Performance levels are arranged from low to high. */
3755 performance_level->memory_clock = mclk_dep_table->entries
3756 [state_entry->ucMemoryClockIndexLow].ulMclk;
3757 performance_level->engine_clock = sclk_dep_table->entries
3758 [state_entry->ucEngineClockIndexLow].ulSclk;
3759 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3760 state_entry->ucPCIEGenLow);
3761 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3762 state_entry->ucPCIELaneHigh);
3764 performance_level = &(fiji_power_state->performance_levels
3765 [fiji_power_state->performance_level_count++]);
3766 performance_level->memory_clock = mclk_dep_table->entries
3767 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3768 performance_level->engine_clock = sclk_dep_table->entries
3769 [state_entry->ucEngineClockIndexHigh].ulSclk;
3770 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3771 state_entry->ucPCIEGenHigh);
3772 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3773 state_entry->ucPCIELaneHigh);
3778 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3779 unsigned long entry_index, struct pp_power_state *state)
3782 struct fiji_power_state *ps;
3783 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3784 struct phm_ppt_v1_information *table_info =
3785 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3786 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3787 table_info->vdd_dep_on_mclk;
3789 state->hardware.magic = PHM_VIslands_Magic;
3791 ps = (struct fiji_power_state *)(&state->hardware);
3793 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3794 fiji_get_pp_table_entry_callback_func);
3796 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3797 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3798 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3800 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3801 if (dep_mclk_table->entries[0].clk !=
3802 data->vbios_boot_state.mclk_bootup_value)
3803 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3804 "does not match VBIOS boot MCLK level");
3805 if (dep_mclk_table->entries[0].vddci !=
3806 data->vbios_boot_state.vddci_bootup_value)
3807 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3808 "does not match VBIOS boot VDDCI level");
3811 /* set DC compatible flag if this state supports DC */
3812 if (!state->validation.disallowOnDC)
3813 ps->dc_compatible = true;
3815 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3816 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3818 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3819 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3824 switch (state->classification.ui_label) {
3825 case PP_StateUILabel_Performance:
3826 data->use_pcie_performance_levels = true;
3828 for (i = 0; i < ps->performance_level_count; i++) {
3829 if (data->pcie_gen_performance.max <
3830 ps->performance_levels[i].pcie_gen)
3831 data->pcie_gen_performance.max =
3832 ps->performance_levels[i].pcie_gen;
3834 if (data->pcie_gen_performance.min >
3835 ps->performance_levels[i].pcie_gen)
3836 data->pcie_gen_performance.min =
3837 ps->performance_levels[i].pcie_gen;
3839 if (data->pcie_lane_performance.max <
3840 ps->performance_levels[i].pcie_lane)
3841 data->pcie_lane_performance.max =
3842 ps->performance_levels[i].pcie_lane;
3844 if (data->pcie_lane_performance.min >
3845 ps->performance_levels[i].pcie_lane)
3846 data->pcie_lane_performance.min =
3847 ps->performance_levels[i].pcie_lane;
3850 case PP_StateUILabel_Battery:
3851 data->use_pcie_power_saving_levels = true;
3853 for (i = 0; i < ps->performance_level_count; i++) {
3854 if (data->pcie_gen_power_saving.max <
3855 ps->performance_levels[i].pcie_gen)
3856 data->pcie_gen_power_saving.max =
3857 ps->performance_levels[i].pcie_gen;
3859 if (data->pcie_gen_power_saving.min >
3860 ps->performance_levels[i].pcie_gen)
3861 data->pcie_gen_power_saving.min =
3862 ps->performance_levels[i].pcie_gen;
3864 if (data->pcie_lane_power_saving.max <
3865 ps->performance_levels[i].pcie_lane)
3866 data->pcie_lane_power_saving.max =
3867 ps->performance_levels[i].pcie_lane;
3869 if (data->pcie_lane_power_saving.min >
3870 ps->performance_levels[i].pcie_lane)
3871 data->pcie_lane_power_saving.min =
3872 ps->performance_levels[i].pcie_lane;
3882 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3883 struct pp_power_state *request_ps,
3884 const struct pp_power_state *current_ps)
3886 struct fiji_power_state *fiji_ps =
3887 cast_phw_fiji_power_state(&request_ps->hardware);
3890 struct PP_Clocks minimum_clocks = {0};
3891 bool disable_mclk_switching;
3892 bool disable_mclk_switching_for_frame_lock;
3893 struct cgs_display_info info = {0};
3894 const struct phm_clock_and_voltage_limits *max_limits;
3896 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3897 struct phm_ppt_v1_information *table_info =
3898 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3900 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3902 data->battery_state = (PP_StateUILabel_Battery ==
3903 request_ps->classification.ui_label);
3905 PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3906 "VI should always have 2 performance levels",);
3908 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3909 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3910 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3912 /* Cap clock DPM tables at DC MAX if it is in DC. */
3913 if (PP_PowerSource_DC == hwmgr->power_source) {
3914 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3915 if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3916 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3917 if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3918 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3922 fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3923 fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3925 fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3927 cgs_get_active_displays_info(hwmgr->device, &info);
3929 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3931 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3933 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3934 PHM_PlatformCaps_StablePState)) {
3935 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3936 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3938 for (count = table_info->vdd_dep_on_sclk->count - 1;
3939 count >= 0; count--) {
3940 if (stable_pstate_sclk >=
3941 table_info->vdd_dep_on_sclk->entries[count].clk) {
3942 stable_pstate_sclk =
3943 table_info->vdd_dep_on_sclk->entries[count].clk;
3949 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3951 stable_pstate_mclk = max_limits->mclk;
3953 minimum_clocks.engineClock = stable_pstate_sclk;
3954 minimum_clocks.memoryClock = stable_pstate_mclk;
3957 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3958 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3960 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3961 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3963 fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3965 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3966 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3967 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3968 "Overdrive sclk exceeds limit",
3969 hwmgr->gfx_arbiter.sclk_over_drive =
3970 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3972 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3973 fiji_ps->performance_levels[1].engine_clock =
3974 hwmgr->gfx_arbiter.sclk_over_drive;
3977 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3978 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3979 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3980 "Overdrive mclk exceeds limit",
3981 hwmgr->gfx_arbiter.mclk_over_drive =
3982 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3984 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3985 fiji_ps->performance_levels[1].memory_clock =
3986 hwmgr->gfx_arbiter.mclk_over_drive;
3989 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3990 hwmgr->platform_descriptor.platformCaps,
3991 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3993 disable_mclk_switching = (1 < info.display_count) ||
3994 disable_mclk_switching_for_frame_lock;
3996 sclk = fiji_ps->performance_levels[0].engine_clock;
3997 mclk = fiji_ps->performance_levels[0].memory_clock;
3999 if (disable_mclk_switching)
4000 mclk = fiji_ps->performance_levels
4001 [fiji_ps->performance_level_count - 1].memory_clock;
4003 if (sclk < minimum_clocks.engineClock)
4004 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
4005 max_limits->sclk : minimum_clocks.engineClock;
4007 if (mclk < minimum_clocks.memoryClock)
4008 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
4009 max_limits->mclk : minimum_clocks.memoryClock;
4011 fiji_ps->performance_levels[0].engine_clock = sclk;
4012 fiji_ps->performance_levels[0].memory_clock = mclk;
4014 fiji_ps->performance_levels[1].engine_clock =
4015 (fiji_ps->performance_levels[1].engine_clock >=
4016 fiji_ps->performance_levels[0].engine_clock) ?
4017 fiji_ps->performance_levels[1].engine_clock :
4018 fiji_ps->performance_levels[0].engine_clock;
4020 if (disable_mclk_switching) {
4021 if (mclk < fiji_ps->performance_levels[1].memory_clock)
4022 mclk = fiji_ps->performance_levels[1].memory_clock;
4024 fiji_ps->performance_levels[0].memory_clock = mclk;
4025 fiji_ps->performance_levels[1].memory_clock = mclk;
4027 if (fiji_ps->performance_levels[1].memory_clock <
4028 fiji_ps->performance_levels[0].memory_clock)
4029 fiji_ps->performance_levels[1].memory_clock =
4030 fiji_ps->performance_levels[0].memory_clock;
4033 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4034 PHM_PlatformCaps_StablePState)) {
4035 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4036 fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4037 fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4038 fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4039 fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4046 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4048 const struct phm_set_power_state_input *states =
4049 (const struct phm_set_power_state_input *)input;
4050 const struct fiji_power_state *fiji_ps =
4051 cast_const_phw_fiji_power_state(states->pnew_state);
4052 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4053 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4054 uint32_t sclk = fiji_ps->performance_levels
4055 [fiji_ps->performance_level_count - 1].engine_clock;
4056 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4057 uint32_t mclk = fiji_ps->performance_levels
4058 [fiji_ps->performance_level_count - 1].memory_clock;
4060 struct cgs_display_info info = {0};
4062 data->need_update_smu7_dpm_table = 0;
4064 for (i = 0; i < sclk_table->count; i++) {
4065 if (sclk == sclk_table->dpm_levels[i].value)
4069 if (i >= sclk_table->count)
4070 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4072 if(data->display_timing.min_clock_in_sr !=
4073 hwmgr->display_config.min_core_set_clock_in_sr)
4074 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4077 for (i = 0; i < mclk_table->count; i++) {
4078 if (mclk == mclk_table->dpm_levels[i].value)
4082 if (i >= mclk_table->count)
4083 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4085 cgs_get_active_displays_info(hwmgr->device, &info);
4087 if (data->display_timing.num_existing_displays != info.display_count)
4088 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4093 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4094 const struct fiji_power_state *fiji_ps)
4097 uint32_t sclk, max_sclk = 0;
4098 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4099 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4101 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4102 sclk = fiji_ps->performance_levels[i].engine_clock;
4103 if (max_sclk < sclk)
4107 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4108 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4109 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4110 dpm_table->pcie_speed_table.dpm_levels
4111 [dpm_table->pcie_speed_table.count - 1].value :
4112 dpm_table->pcie_speed_table.dpm_levels[i].value);
4118 static int fiji_request_link_speed_change_before_state_change(
4119 struct pp_hwmgr *hwmgr, const void *input)
4121 const struct phm_set_power_state_input *states =
4122 (const struct phm_set_power_state_input *)input;
4123 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4124 const struct fiji_power_state *fiji_nps =
4125 cast_const_phw_fiji_power_state(states->pnew_state);
4126 const struct fiji_power_state *fiji_cps =
4127 cast_const_phw_fiji_power_state(states->pcurrent_state);
4129 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4130 uint16_t current_link_speed;
4132 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4133 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4135 current_link_speed = data->force_pcie_gen;
4137 data->force_pcie_gen = PP_PCIEGenInvalid;
4138 data->pspp_notify_required = false;
4139 if (target_link_speed > current_link_speed) {
4140 switch(target_link_speed) {
4142 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4144 data->force_pcie_gen = PP_PCIEGen2;
4145 if (current_link_speed == PP_PCIEGen2)
4148 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4151 data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4155 if (target_link_speed < current_link_speed)
4156 data->pspp_notify_required = true;
4162 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4164 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4166 if (0 == data->need_update_smu7_dpm_table)
4169 if ((0 == data->sclk_dpm_key_disabled) &&
4170 (data->need_update_smu7_dpm_table &
4171 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4172 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4173 "Trying to freeze SCLK DPM when DPM is disabled",);
4174 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4175 PPSMC_MSG_SCLKDPM_FreezeLevel),
4176 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4180 if ((0 == data->mclk_dpm_key_disabled) &&
4181 (data->need_update_smu7_dpm_table &
4182 DPMTABLE_OD_UPDATE_MCLK)) {
4183 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4184 "Trying to freeze MCLK DPM when DPM is disabled",);
4185 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4186 PPSMC_MSG_MCLKDPM_FreezeLevel),
4187 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4194 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4195 struct pp_hwmgr *hwmgr, const void *input)
4198 const struct phm_set_power_state_input *states =
4199 (const struct phm_set_power_state_input *)input;
4200 const struct fiji_power_state *fiji_ps =
4201 cast_const_phw_fiji_power_state(states->pnew_state);
4202 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4203 uint32_t sclk = fiji_ps->performance_levels
4204 [fiji_ps->performance_level_count - 1].engine_clock;
4205 uint32_t mclk = fiji_ps->performance_levels
4206 [fiji_ps->performance_level_count - 1].memory_clock;
4207 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4209 struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4210 uint32_t dpm_count, clock_percent;
4213 if (0 == data->need_update_smu7_dpm_table)
4216 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4217 dpm_table->sclk_table.dpm_levels
4218 [dpm_table->sclk_table.count - 1].value = sclk;
4220 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4221 PHM_PlatformCaps_OD6PlusinACSupport) ||
4222 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4223 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4224 /* Need to do calculation based on the golden DPM table
4225 * as the Heatmap GPU Clock axis is also based on the default values
4227 PP_ASSERT_WITH_CODE(
4228 (golden_dpm_table->sclk_table.dpm_levels
4229 [golden_dpm_table->sclk_table.count - 1].value != 0),
4232 dpm_count = dpm_table->sclk_table.count < 2 ?
4233 0 : dpm_table->sclk_table.count - 2;
4234 for (i = dpm_count; i > 1; i--) {
4235 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4236 [golden_dpm_table->sclk_table.count-1].value) {
4238 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4239 [golden_dpm_table->sclk_table.count-1].value) * 100) /
4240 golden_dpm_table->sclk_table.dpm_levels
4241 [golden_dpm_table->sclk_table.count-1].value;
4243 dpm_table->sclk_table.dpm_levels[i].value =
4244 golden_dpm_table->sclk_table.dpm_levels[i].value +
4245 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4248 } else if (golden_dpm_table->sclk_table.dpm_levels
4249 [dpm_table->sclk_table.count-1].value > sclk) {
4251 ((golden_dpm_table->sclk_table.dpm_levels
4252 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4254 golden_dpm_table->sclk_table.dpm_levels
4255 [golden_dpm_table->sclk_table.count-1].value;
4257 dpm_table->sclk_table.dpm_levels[i].value =
4258 golden_dpm_table->sclk_table.dpm_levels[i].value -
4259 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4260 clock_percent) / 100;
4262 dpm_table->sclk_table.dpm_levels[i].value =
4263 golden_dpm_table->sclk_table.dpm_levels[i].value;
4268 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4269 dpm_table->mclk_table.dpm_levels
4270 [dpm_table->mclk_table.count - 1].value = mclk;
4271 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4272 PHM_PlatformCaps_OD6PlusinACSupport) ||
4273 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4274 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4276 PP_ASSERT_WITH_CODE(
4277 (golden_dpm_table->mclk_table.dpm_levels
4278 [golden_dpm_table->mclk_table.count-1].value != 0),
4281 dpm_count = dpm_table->mclk_table.count < 2 ?
4282 0 : dpm_table->mclk_table.count - 2;
4283 for (i = dpm_count; i > 1; i--) {
4284 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4285 [golden_dpm_table->mclk_table.count-1].value) {
4286 clock_percent = ((mclk -
4287 golden_dpm_table->mclk_table.dpm_levels
4288 [golden_dpm_table->mclk_table.count-1].value) * 100) /
4289 golden_dpm_table->mclk_table.dpm_levels
4290 [golden_dpm_table->mclk_table.count-1].value;
4292 dpm_table->mclk_table.dpm_levels[i].value =
4293 golden_dpm_table->mclk_table.dpm_levels[i].value +
4294 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4295 clock_percent) / 100;
4297 } else if (golden_dpm_table->mclk_table.dpm_levels
4298 [dpm_table->mclk_table.count-1].value > mclk) {
4299 clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4300 [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4301 golden_dpm_table->mclk_table.dpm_levels
4302 [golden_dpm_table->mclk_table.count-1].value;
4304 dpm_table->mclk_table.dpm_levels[i].value =
4305 golden_dpm_table->mclk_table.dpm_levels[i].value -
4306 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4307 clock_percent) / 100;
4309 dpm_table->mclk_table.dpm_levels[i].value =
4310 golden_dpm_table->mclk_table.dpm_levels[i].value;
4315 if (data->need_update_smu7_dpm_table &
4316 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4317 result = fiji_populate_all_graphic_levels(hwmgr);
4318 PP_ASSERT_WITH_CODE((0 == result),
4319 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4323 if (data->need_update_smu7_dpm_table &
4324 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4325 /*populate MCLK dpm table to SMU7 */
4326 result = fiji_populate_all_memory_levels(hwmgr);
4327 PP_ASSERT_WITH_CODE((0 == result),
4328 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4335 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4336 struct fiji_single_dpm_table * dpm_table,
4337 uint32_t low_limit, uint32_t high_limit)
4341 for (i = 0; i < dpm_table->count; i++) {
4342 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4343 (dpm_table->dpm_levels[i].value > high_limit))
4344 dpm_table->dpm_levels[i].enabled = false;
4346 dpm_table->dpm_levels[i].enabled = true;
4351 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4352 const struct fiji_power_state *fiji_ps)
4355 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4356 uint32_t high_limit_count;
4358 PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4359 "power state did not have any performance level",
4362 high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4364 fiji_trim_single_dpm_states(hwmgr,
4365 &(data->dpm_table.sclk_table),
4366 fiji_ps->performance_levels[0].engine_clock,
4367 fiji_ps->performance_levels[high_limit_count].engine_clock);
4369 fiji_trim_single_dpm_states(hwmgr,
4370 &(data->dpm_table.mclk_table),
4371 fiji_ps->performance_levels[0].memory_clock,
4372 fiji_ps->performance_levels[high_limit_count].memory_clock);
4377 static int fiji_generate_dpm_level_enable_mask(
4378 struct pp_hwmgr *hwmgr, const void *input)
4381 const struct phm_set_power_state_input *states =
4382 (const struct phm_set_power_state_input *)input;
4383 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4384 const struct fiji_power_state *fiji_ps =
4385 cast_const_phw_fiji_power_state(states->pnew_state);
4387 result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4391 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4392 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4393 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4394 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4395 data->last_mclk_dpm_enable_mask =
4396 data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4398 if (data->uvd_enabled) {
4399 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4400 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4403 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4404 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4409 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4411 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4412 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4413 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4416 int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4418 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4419 PPSMC_MSG_VCEDPM_Enable :
4420 PPSMC_MSG_VCEDPM_Disable);
4423 int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4425 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4426 PPSMC_MSG_SAMUDPM_Enable :
4427 PPSMC_MSG_SAMUDPM_Disable);
4430 int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4432 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4433 PPSMC_MSG_ACPDPM_Enable :
4434 PPSMC_MSG_ACPDPM_Disable);
4437 int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4439 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4440 uint32_t mm_boot_level_offset, mm_boot_level_value;
4441 struct phm_ppt_v1_information *table_info =
4442 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4445 data->smc_state_table.UvdBootLevel = 0;
4446 if (table_info->mm_dep_table->count > 0)
4447 data->smc_state_table.UvdBootLevel =
4448 (uint8_t) (table_info->mm_dep_table->count - 1);
4449 mm_boot_level_offset = data->dpm_table_start +
4450 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4451 mm_boot_level_offset /= 4;
4452 mm_boot_level_offset *= 4;
4453 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4454 CGS_IND_REG__SMC, mm_boot_level_offset);
4455 mm_boot_level_value &= 0x00FFFFFF;
4456 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4457 cgs_write_ind_register(hwmgr->device,
4458 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4460 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4461 PHM_PlatformCaps_UVDDPM) ||
4462 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4463 PHM_PlatformCaps_StablePState))
4464 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4465 PPSMC_MSG_UVDDPM_SetEnabledMask,
4466 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4469 return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4472 int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4474 const struct phm_set_power_state_input *states =
4475 (const struct phm_set_power_state_input *)input;
4476 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4477 const struct fiji_power_state *fiji_nps =
4478 cast_const_phw_fiji_power_state(states->pnew_state);
4479 const struct fiji_power_state *fiji_cps =
4480 cast_const_phw_fiji_power_state(states->pcurrent_state);
4482 uint32_t mm_boot_level_offset, mm_boot_level_value;
4483 struct phm_ppt_v1_information *table_info =
4484 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4486 if (fiji_nps->vce_clks.evclk >0 &&
4487 (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4488 data->smc_state_table.VceBootLevel =
4489 (uint8_t) (table_info->mm_dep_table->count - 1);
4491 mm_boot_level_offset = data->dpm_table_start +
4492 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4493 mm_boot_level_offset /= 4;
4494 mm_boot_level_offset *= 4;
4495 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4496 CGS_IND_REG__SMC, mm_boot_level_offset);
4497 mm_boot_level_value &= 0xFF00FFFF;
4498 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4499 cgs_write_ind_register(hwmgr->device,
4500 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4502 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4503 PHM_PlatformCaps_StablePState)) {
4504 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4505 PPSMC_MSG_VCEDPM_SetEnabledMask,
4506 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4508 fiji_enable_disable_vce_dpm(hwmgr, true);
4509 } else if (fiji_nps->vce_clks.evclk == 0 &&
4511 fiji_cps->vce_clks.evclk > 0)
4512 fiji_enable_disable_vce_dpm(hwmgr, false);
4518 int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4520 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4521 uint32_t mm_boot_level_offset, mm_boot_level_value;
4522 struct phm_ppt_v1_information *table_info =
4523 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4526 data->smc_state_table.SamuBootLevel =
4527 (uint8_t) (table_info->mm_dep_table->count - 1);
4528 mm_boot_level_offset = data->dpm_table_start +
4529 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4530 mm_boot_level_offset /= 4;
4531 mm_boot_level_offset *= 4;
4532 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4533 CGS_IND_REG__SMC, mm_boot_level_offset);
4534 mm_boot_level_value &= 0xFFFFFF00;
4535 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4536 cgs_write_ind_register(hwmgr->device,
4537 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4539 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4540 PHM_PlatformCaps_StablePState))
4541 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4542 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4543 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4546 return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4549 int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4551 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4552 uint32_t mm_boot_level_offset, mm_boot_level_value;
4553 struct phm_ppt_v1_information *table_info =
4554 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4557 data->smc_state_table.AcpBootLevel =
4558 (uint8_t) (table_info->mm_dep_table->count - 1);
4559 mm_boot_level_offset = data->dpm_table_start +
4560 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4561 mm_boot_level_offset /= 4;
4562 mm_boot_level_offset *= 4;
4563 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4564 CGS_IND_REG__SMC, mm_boot_level_offset);
4565 mm_boot_level_value &= 0xFFFF00FF;
4566 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4567 cgs_write_ind_register(hwmgr->device,
4568 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4570 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4571 PHM_PlatformCaps_StablePState))
4572 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4573 PPSMC_MSG_ACPDPM_SetEnabledMask,
4574 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4577 return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4580 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4582 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4585 uint32_t low_sclk_interrupt_threshold = 0;
4587 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4588 PHM_PlatformCaps_SclkThrottleLowNotification)
4589 && (hwmgr->gfx_arbiter.sclk_threshold !=
4590 data->low_sclk_interrupt_threshold)) {
4591 data->low_sclk_interrupt_threshold =
4592 hwmgr->gfx_arbiter.sclk_threshold;
4593 low_sclk_interrupt_threshold =
4594 data->low_sclk_interrupt_threshold;
4596 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4598 result = fiji_copy_bytes_to_smc(
4600 data->dpm_table_start +
4601 offsetof(SMU73_Discrete_DpmTable,
4602 LowSclkInterruptThreshold),
4603 (uint8_t *)&low_sclk_interrupt_threshold,
4611 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4613 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4615 if (data->need_update_smu7_dpm_table &
4616 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4617 return fiji_program_memory_timing_parameters(hwmgr);
4622 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4624 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4626 if (0 == data->need_update_smu7_dpm_table)
4629 if ((0 == data->sclk_dpm_key_disabled) &&
4630 (data->need_update_smu7_dpm_table &
4631 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4633 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4634 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4635 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4636 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4637 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4641 if ((0 == data->mclk_dpm_key_disabled) &&
4642 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4644 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4645 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4646 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4647 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4648 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4652 data->need_update_smu7_dpm_table = 0;
4657 /* Look up the voltaged based on DAL's requested level.
4658 * and then send the requested VDDC voltage to SMC
4660 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4665 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4668 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4670 /* Apply minimum voltage based on DAL's request level */
4671 fiji_apply_dal_minimum_voltage_request(hwmgr);
4673 if (0 == data->sclk_dpm_key_disabled) {
4674 /* Checking if DPM is running. If we discover hang because of this,
4675 * we should skip this message.
4677 if (!fiji_is_dpm_running(hwmgr))
4678 printk(KERN_ERR "[ powerplay ] "
4679 "Trying to set Enable Mask when DPM is disabled \n");
4681 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4682 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4683 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4684 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4685 PP_ASSERT_WITH_CODE((0 == result),
4686 "Set Sclk Dpm enable Mask failed", return -1);
4690 if (0 == data->mclk_dpm_key_disabled) {
4691 /* Checking if DPM is running. If we discover hang because of this,
4692 * we should skip this message.
4694 if (!fiji_is_dpm_running(hwmgr))
4695 printk(KERN_ERR "[ powerplay ]"
4696 " Trying to set Enable Mask when DPM is disabled \n");
4698 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4699 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4700 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4701 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4702 PP_ASSERT_WITH_CODE((0 == result),
4703 "Set Mclk Dpm enable Mask failed", return -1);
4710 static int fiji_notify_link_speed_change_after_state_change(
4711 struct pp_hwmgr *hwmgr, const void *input)
4713 const struct phm_set_power_state_input *states =
4714 (const struct phm_set_power_state_input *)input;
4715 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4716 const struct fiji_power_state *fiji_ps =
4717 cast_const_phw_fiji_power_state(states->pnew_state);
4718 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4721 if (data->pspp_notify_required) {
4722 if (target_link_speed == PP_PCIEGen3)
4723 request = PCIE_PERF_REQ_GEN3;
4724 else if (target_link_speed == PP_PCIEGen2)
4725 request = PCIE_PERF_REQ_GEN2;
4727 request = PCIE_PERF_REQ_GEN1;
4729 if(request == PCIE_PERF_REQ_GEN1 &&
4730 fiji_get_current_pcie_speed(hwmgr) > 0)
4733 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4734 if (PP_PCIEGen2 == target_link_speed)
4735 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4737 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4744 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4747 int tmp_result, result = 0;
4749 tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4750 PP_ASSERT_WITH_CODE((0 == tmp_result),
4751 "Failed to find DPM states clocks in DPM table!",
4752 result = tmp_result);
4754 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4755 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4757 fiji_request_link_speed_change_before_state_change(hwmgr, input);
4758 PP_ASSERT_WITH_CODE((0 == tmp_result),
4759 "Failed to request link speed change before state change!",
4760 result = tmp_result);
4763 tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4764 PP_ASSERT_WITH_CODE((0 == tmp_result),
4765 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4767 tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4768 PP_ASSERT_WITH_CODE((0 == tmp_result),
4769 "Failed to populate and upload SCLK MCLK DPM levels!",
4770 result = tmp_result);
4772 tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4773 PP_ASSERT_WITH_CODE((0 == tmp_result),
4774 "Failed to generate DPM level enabled mask!",
4775 result = tmp_result);
4777 tmp_result = fiji_update_vce_dpm(hwmgr, input);
4778 PP_ASSERT_WITH_CODE((0 == tmp_result),
4779 "Failed to update VCE DPM!",
4780 result = tmp_result);
4782 tmp_result = fiji_update_sclk_threshold(hwmgr);
4783 PP_ASSERT_WITH_CODE((0 == tmp_result),
4784 "Failed to update SCLK threshold!",
4785 result = tmp_result);
4787 tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4788 PP_ASSERT_WITH_CODE((0 == tmp_result),
4789 "Failed to program memory timing parameters!",
4790 result = tmp_result);
4792 tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4793 PP_ASSERT_WITH_CODE((0 == tmp_result),
4794 "Failed to unfreeze SCLK MCLK DPM!",
4795 result = tmp_result);
4797 tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4798 PP_ASSERT_WITH_CODE((0 == tmp_result),
4799 "Failed to upload DPM level enabled mask!",
4800 result = tmp_result);
4802 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4803 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4805 fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4806 PP_ASSERT_WITH_CODE((0 == tmp_result),
4807 "Failed to notify link speed change after state change!",
4808 result = tmp_result);
4814 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4816 struct pp_power_state *ps;
4817 struct fiji_power_state *fiji_ps;
4822 ps = hwmgr->request_ps;
4827 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4830 return fiji_ps->performance_levels[0].engine_clock;
4832 return fiji_ps->performance_levels
4833 [fiji_ps->performance_level_count-1].engine_clock;
4836 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4838 struct pp_power_state *ps;
4839 struct fiji_power_state *fiji_ps;
4844 ps = hwmgr->request_ps;
4849 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4852 return fiji_ps->performance_levels[0].memory_clock;
4854 return fiji_ps->performance_levels
4855 [fiji_ps->performance_level_count-1].memory_clock;
4858 static void fiji_print_current_perforce_level(
4859 struct pp_hwmgr *hwmgr, struct seq_file *m)
4861 uint32_t sclk, mclk, activity_percent = 0;
4863 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4865 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4867 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4869 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4871 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4872 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4873 mclk / 100, sclk / 100);
4875 offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
4876 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4877 activity_percent += 0x80;
4878 activity_percent >>= 8;
4880 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4882 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
4884 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
4887 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
4889 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4890 uint32_t num_active_displays = 0;
4891 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4892 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4893 uint32_t display_gap2;
4894 uint32_t pre_vbi_time_in_us;
4895 uint32_t frame_time_in_us;
4897 uint32_t refresh_rate = 0;
4898 struct cgs_display_info info = {0};
4899 struct cgs_mode_info mode_info;
4901 info.mode_info = &mode_info;
4903 cgs_get_active_displays_info(hwmgr->device, &info);
4904 num_active_displays = info.display_count;
4906 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
4907 DISP_GAP, (num_active_displays > 0)?
4908 DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4909 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4910 ixCG_DISPLAY_GAP_CNTL, display_gap);
4912 ref_clock = mode_info.ref_clock;
4913 refresh_rate = mode_info.refresh_rate;
4915 if (refresh_rate == 0)
4918 frame_time_in_us = 1000000 / refresh_rate;
4920 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4921 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4924 ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4926 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4927 data->soft_regs_start +
4928 offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
4930 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4931 data->soft_regs_start +
4932 offsetof(SMU73_SoftRegisters, VBlankTimeout),
4933 (frame_time_in_us - pre_vbi_time_in_us));
4935 if (num_active_displays == 1)
4936 tonga_notify_smc_display_change(hwmgr, true);
4941 int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4943 return fiji_program_display_gap(hwmgr);
4946 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
4947 uint16_t us_max_fan_pwm)
4949 hwmgr->thermal_controller.
4950 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4952 if (phm_is_hw_access_blocked(hwmgr))
4955 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4956 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4959 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
4960 uint16_t us_max_fan_rpm)
4962 hwmgr->thermal_controller.
4963 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4965 if (phm_is_hw_access_blocked(hwmgr))
4968 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4969 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4972 int fiji_dpm_set_interrupt_state(void *private_data,
4973 unsigned src_id, unsigned type,
4976 uint32_t cg_thermal_int;
4977 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
4983 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
4985 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
4986 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
4987 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
4988 cgs_write_ind_register(hwmgr->device,
4989 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
4991 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
4992 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
4993 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
4994 cgs_write_ind_register(hwmgr->device,
4995 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
4999 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5001 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5002 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5003 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5004 cgs_write_ind_register(hwmgr->device,
5005 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5007 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5008 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5009 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5010 cgs_write_ind_register(hwmgr->device,
5011 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5020 int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5021 const void *thermal_interrupt_info)
5024 const struct pp_interrupt_registration_info *info =
5025 (const struct pp_interrupt_registration_info *)
5026 thermal_interrupt_info;
5031 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5032 fiji_dpm_set_interrupt_state,
5033 info->call_back, info->context);
5038 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5039 fiji_dpm_set_interrupt_state,
5040 info->call_back, info->context);
5048 static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5051 /* stop auto-manage */
5052 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5053 PHM_PlatformCaps_MicrocodeFanControl))
5054 fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
5055 fiji_fan_ctrl_set_static_mode(hwmgr, mode);
5057 /* restart auto-manage */
5058 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5063 static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5065 if (hwmgr->fan_ctrl_is_in_default_mode)
5066 return hwmgr->fan_ctrl_default_mode;
5068 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5069 CG_FDO_CTRL2, FDO_PWM_MODE);
5072 static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
5074 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5076 if (!data->soft_pp_table) {
5077 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
5078 hwmgr->soft_pp_table_size,
5080 if (!data->soft_pp_table)
5084 *table = (char *)&data->soft_pp_table;
5086 return hwmgr->soft_pp_table_size;
5089 static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
5091 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5093 if (!data->soft_pp_table) {
5094 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
5095 if (!data->soft_pp_table)
5099 memcpy(data->soft_pp_table, buf, size);
5101 hwmgr->soft_pp_table = data->soft_pp_table;
5103 /* TODO: re-init powerplay to implement modified pptable */
5108 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
5109 enum pp_clock_type type, uint32_t mask)
5111 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5113 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5118 if (!data->sclk_dpm_key_disabled)
5119 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5120 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5121 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5125 if (!data->mclk_dpm_key_disabled)
5126 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5127 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5128 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5133 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5139 if (!data->pcie_dpm_key_disabled)
5140 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5141 PPSMC_MSG_PCIeDPM_ForceLevel,
5152 static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5153 enum pp_clock_type type, char *buf)
5155 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5156 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5157 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5158 struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5159 int i, now, size = 0;
5160 uint32_t clock, pcie_speed;
5164 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5165 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5167 for (i = 0; i < sclk_table->count; i++) {
5168 if (clock > sclk_table->dpm_levels[i].value)
5174 for (i = 0; i < sclk_table->count; i++)
5175 size += sprintf(buf + size, "%d: %uMhz %s\n",
5176 i, sclk_table->dpm_levels[i].value / 100,
5177 (i == now) ? "*" : "");
5180 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5181 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5183 for (i = 0; i < mclk_table->count; i++) {
5184 if (clock > mclk_table->dpm_levels[i].value)
5190 for (i = 0; i < mclk_table->count; i++)
5191 size += sprintf(buf + size, "%d: %uMhz %s\n",
5192 i, mclk_table->dpm_levels[i].value / 100,
5193 (i == now) ? "*" : "");
5196 pcie_speed = fiji_get_current_pcie_speed(hwmgr);
5197 for (i = 0; i < pcie_table->count; i++) {
5198 if (pcie_speed != pcie_table->dpm_levels[i].value)
5204 for (i = 0; i < pcie_table->count; i++)
5205 size += sprintf(buf + size, "%d: %s %s\n", i,
5206 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
5207 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5208 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5209 (i == now) ? "*" : "");
5217 static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5218 const struct fiji_performance_level *pl2)
5220 return ((pl1->memory_clock == pl2->memory_clock) &&
5221 (pl1->engine_clock == pl2->engine_clock) &&
5222 (pl1->pcie_gen == pl2->pcie_gen) &&
5223 (pl1->pcie_lane == pl2->pcie_lane));
5226 int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5228 const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5229 const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5232 if (equal == NULL || psa == NULL || psb == NULL)
5235 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5236 if (psa->performance_level_count != psb->performance_level_count) {
5241 for (i = 0; i < psa->performance_level_count; i++) {
5242 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5243 /* If we have found even one performance level pair that is different the states are different. */
5249 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5250 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5251 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5252 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5253 *equal &= (psa->acp_clk == psb->acp_clk);
5258 bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5260 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5261 bool is_update_required = false;
5262 struct cgs_display_info info = {0,0,NULL};
5264 cgs_get_active_displays_info(hwmgr->device, &info);
5266 if (data->display_timing.num_existing_displays != info.display_count)
5267 is_update_required = true;
5269 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5270 if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
5271 is_update_required = true;
5274 return is_update_required;
5278 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5279 .backend_init = &fiji_hwmgr_backend_init,
5280 .backend_fini = &fiji_hwmgr_backend_fini,
5281 .asic_setup = &fiji_setup_asic_task,
5282 .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
5283 .force_dpm_level = &fiji_dpm_force_dpm_level,
5284 .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
5285 .get_power_state_size = &fiji_get_power_state_size,
5286 .get_pp_table_entry = &fiji_get_pp_table_entry,
5287 .patch_boot_state = &fiji_patch_boot_state,
5288 .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
5289 .power_state_set = &fiji_set_power_state_tasks,
5290 .get_sclk = &fiji_dpm_get_sclk,
5291 .get_mclk = &fiji_dpm_get_mclk,
5292 .print_current_perforce_level = &fiji_print_current_perforce_level,
5293 .powergate_uvd = &fiji_phm_powergate_uvd,
5294 .powergate_vce = &fiji_phm_powergate_vce,
5295 .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
5296 .notify_smc_display_config_after_ps_adjustment =
5297 &tonga_notify_smc_display_config_after_ps_adjustment,
5298 .display_config_changed = &fiji_display_configuration_changed_task,
5299 .set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
5300 .set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
5301 .get_temperature = fiji_thermal_get_temperature,
5302 .stop_thermal_controller = fiji_thermal_stop_thermal_controller,
5303 .get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
5304 .get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
5305 .set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
5306 .reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
5307 .get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
5308 .set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
5309 .uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
5310 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5311 .set_fan_control_mode = fiji_set_fan_control_mode,
5312 .get_fan_control_mode = fiji_get_fan_control_mode,
5313 .check_states_equal = fiji_check_states_equal,
5314 .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5315 .get_pp_table = fiji_get_pp_table,
5316 .set_pp_table = fiji_set_pp_table,
5317 .force_clock_level = fiji_force_clock_level,
5318 .print_clock_levels = fiji_print_clock_levels,
5321 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
5323 struct fiji_hwmgr *data;
5326 data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
5330 hwmgr->backend = data;
5331 hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
5332 hwmgr->pptable_func = &tonga_pptable_funcs;
5333 pp_fiji_thermal_initialize(hwmgr);