drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/delay.h>
  26 #include <linux/kernel.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29 #include <linux/pci.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "power_state.h"
  32 #include "hwmgr.h"
  33 #include "ppsmc.h"
  34 #include "amd_acpi.h"
  35 #include "pp_psm.h"
  36
  37 extern const struct pp_smumgr_func ci_smu_funcs;
  38 extern const struct pp_smumgr_func smu8_smu_funcs;
  39 extern const struct pp_smumgr_func iceland_smu_funcs;
  40 extern const struct pp_smumgr_func tonga_smu_funcs;
  41 extern const struct pp_smumgr_func fiji_smu_funcs;
  42 extern const struct pp_smumgr_func polaris10_smu_funcs;
  43 extern const struct pp_smumgr_func vegam_smu_funcs;
  44 extern const struct pp_smumgr_func vega10_smu_funcs;
  45 extern const struct pp_smumgr_func vega12_smu_funcs;
  46 extern const struct pp_smumgr_func smu10_smu_funcs;
  47 extern const struct pp_smumgr_func vega20_smu_funcs;
  48
  49 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
  50 extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
  51 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
  52 extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
  53 extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
  54 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
  55
  56 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  57 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
  58 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
  59 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  60 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  61 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  62 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
  63
  64
  65 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
  66 {
  67         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
  68         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
  69         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
  70         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
  71         hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
  72
  73         hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
  74         hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
  75         hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
  76         hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
  77         hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
  78 }
  79
  80 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
  81 {
  82         if (!hwmgr)
  83                 return -EINVAL;
  84
  85         hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  86         hwmgr->pp_table_version = PP_TABLE_V1;
  87         hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  88         hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
  89         hwmgr_init_default_caps(hwmgr);
  90         hwmgr_set_user_specify_caps(hwmgr);
  91         hwmgr->fan_ctrl_is_in_default_mode = true;
  92         hwmgr->reload_fw = 1;
  93         hwmgr_init_workload_prority(hwmgr);
  94
  95         switch (hwmgr->chip_family) {
  96         case AMDGPU_FAMILY_CI:
  97                 hwmgr->smumgr_funcs = &ci_smu_funcs;
  98                 ci_set_asic_special_caps(hwmgr);
  99                 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
 100                                          PP_ENABLE_GFX_CG_THRU_SMU |
 101                                          PP_GFXOFF_MASK);
 102                 hwmgr->pp_table_version = PP_TABLE_V0;
 103                 hwmgr->od_enabled = false;
 104                 smu7_init_function_pointers(hwmgr);
 105                 break;
 106         case AMDGPU_FAMILY_CZ:
 107                 hwmgr->od_enabled = false;
 108                 hwmgr->smumgr_funcs = &smu8_smu_funcs;
 109                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 110                 smu8_init_function_pointers(hwmgr);
 111                 break;
 112         case AMDGPU_FAMILY_VI:
 113                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 114                 switch (hwmgr->chip_id) {
 115                 case CHIP_TOPAZ:
 116                         hwmgr->smumgr_funcs = &iceland_smu_funcs;
 117                         topaz_set_asic_special_caps(hwmgr);
 118                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 119                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 120                         hwmgr->pp_table_version = PP_TABLE_V0;
 121                         hwmgr->od_enabled = false;
 122                         break;
 123                 case CHIP_TONGA:
 124                         hwmgr->smumgr_funcs = &tonga_smu_funcs;
 125                         tonga_set_asic_special_caps(hwmgr);
 126                         hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
 127                         break;
 128                 case CHIP_FIJI:
 129                         hwmgr->smumgr_funcs = &fiji_smu_funcs;
 130                         fiji_set_asic_special_caps(hwmgr);
 131                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 132                                                 PP_ENABLE_GFX_CG_THRU_SMU);
 133                         break;
 134                 case CHIP_POLARIS11:
 135                 case CHIP_POLARIS10:
 136                 case CHIP_POLARIS12:
 137                         hwmgr->smumgr_funcs = &polaris10_smu_funcs;
 138                         polaris_set_asic_special_caps(hwmgr);
 139                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 140                         break;
 141                 case CHIP_VEGAM:
 142                         hwmgr->smumgr_funcs = &vegam_smu_funcs;
 143                         polaris_set_asic_special_caps(hwmgr);
 144                         hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
 145                         break;
 146                 default:
 147                         return -EINVAL;
 148                 }
 149                 smu7_init_function_pointers(hwmgr);
 150                 break;
 151         case AMDGPU_FAMILY_AI:
 152                 switch (hwmgr->chip_id) {
 153                 case CHIP_VEGA10:
 154                         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 155                         hwmgr->smumgr_funcs = &vega10_smu_funcs;
 156                         vega10_hwmgr_init(hwmgr);
 157                         break;
 158                 case CHIP_VEGA12:
 159                         hwmgr->smumgr_funcs = &vega12_smu_funcs;
 160                         vega12_hwmgr_init(hwmgr);
 161                         break;
 162                 case CHIP_VEGA20:
 163                         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 164                         hwmgr->smumgr_funcs = &vega20_smu_funcs;
 165                         vega20_hwmgr_init(hwmgr);
 166                         break;
 167                 default:
 168                         return -EINVAL;
 169                 }
 170                 break;
 171         case AMDGPU_FAMILY_RV:
 172                 switch (hwmgr->chip_id) {
 173                 case CHIP_RAVEN:
 174                         hwmgr->od_enabled = false;
 175                         hwmgr->smumgr_funcs = &smu10_smu_funcs;
 176                         smu10_init_function_pointers(hwmgr);
 177                         break;
 178                 default:
 179                         return -EINVAL;
 180                 }
 181                 break;
 182         default:
 183                 return -EINVAL;
 184         }
 185
 186         return 0;
 187 }
 188
 189 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
 190 {
 191         if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
 192                 return -EINVAL;
 193
 194         phm_register_irq_handlers(hwmgr);
 195
 196         return hwmgr->smumgr_funcs->smu_init(hwmgr);
 197 }
 198
 199
 200 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
 201 {
 202         if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
 203                 hwmgr->smumgr_funcs->smu_fini(hwmgr);
 204
 205         return 0;
 206 }
 207
 208 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
 209 {
 210         int ret = 0;
 211
 212         if (!hwmgr || !hwmgr->smumgr_funcs)
 213                 return -EINVAL;
 214
 215         if (hwmgr->smumgr_funcs->start_smu) {
 216                 ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
 217                 if (ret) {
 218                         pr_err("smc start failed\n");
 219                         return -EINVAL;
 220                 }
 221         }
 222
 223         if (!hwmgr->pm_en)
 224                 return 0;
 225
 226         if (!hwmgr->pptable_func ||
 227             !hwmgr->pptable_func->pptable_init ||
 228             !hwmgr->hwmgr_func->backend_init) {
 229                 hwmgr->pm_en = false;
 230                 pr_info("dpm not supported \n");
 231                 return 0;
 232         }
 233
 234         ret = hwmgr->pptable_func->pptable_init(hwmgr);
 235         if (ret)
 236                 goto err;
 237
 238         ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
 239                                 hwmgr->thermal_controller.fanInfo.bNoFan;
 240
 241         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
 242         if (ret)
 243                 goto err1;
 244  /* make sure dc limits are valid */
 245         if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
 246                         (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
 247                         hwmgr->dyn_state.max_clock_voltage_on_dc =
 248                                         hwmgr->dyn_state.max_clock_voltage_on_ac;
 249
 250         ret = psm_init_power_state_table(hwmgr);
 251         if (ret)
 252                 goto err2;
 253
 254         ret = phm_setup_asic(hwmgr);
 255         if (ret)
 256                 goto err2;
 257
 258         ret = phm_enable_dynamic_state_management(hwmgr);
 259         if (ret)
 260                 goto err2;
 261         ret = phm_start_thermal_controller(hwmgr);
 262         ret |= psm_set_performance_states(hwmgr);
 263         if (ret)
 264                 goto err2;
 265
 266         ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
 267
 268         return 0;
 269 err2:
 270         if (hwmgr->hwmgr_func->backend_fini)
 271                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 272 err1:
 273         if (hwmgr->pptable_func->pptable_fini)
 274                 hwmgr->pptable_func->pptable_fini(hwmgr);
 275 err:
 276         return ret;
 277 }
 278
 279 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 280 {
 281         if (!hwmgr || !hwmgr->pm_en)
 282                 return 0;
 283
 284         phm_stop_thermal_controller(hwmgr);
 285         psm_set_boot_states(hwmgr);
 286         psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 287         phm_disable_dynamic_state_management(hwmgr);
 288         phm_disable_clock_power_gatings(hwmgr);
 289
 290         if (hwmgr->hwmgr_func->backend_fini)
 291                 hwmgr->hwmgr_func->backend_fini(hwmgr);
 292         if (hwmgr->pptable_func->pptable_fini)
 293                 hwmgr->pptable_func->pptable_fini(hwmgr);
 294         return psm_fini_power_state_table(hwmgr);
 295 }
 296
 297 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
 298 {
 299         int ret = 0;
 300
 301         if (!hwmgr || !hwmgr->pm_en)
 302                 return 0;
 303
 304         phm_disable_smc_firmware_ctf(hwmgr);
 305         ret = psm_set_boot_states(hwmgr);
 306         if (ret)
 307                 return ret;
 308         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 309         if (ret)
 310                 return ret;
 311         ret = phm_power_down_asic(hwmgr);
 312
 313         return ret;
 314 }
 315
 316 int hwmgr_resume(struct pp_hwmgr *hwmgr)
 317 {
 318         int ret = 0;
 319
 320         if (!hwmgr)
 321                 return -EINVAL;
 322
 323         if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
 324                 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
 325                         pr_err("smc start failed\n");
 326                         return -EINVAL;
 327                 }
 328         }
 329
 330         if (!hwmgr->pm_en)
 331                 return 0;
 332
 333         ret = phm_setup_asic(hwmgr);
 334         if (ret)
 335                 return ret;
 336
 337         ret = phm_enable_dynamic_state_management(hwmgr);
 338         if (ret)
 339                 return ret;
 340         ret = phm_start_thermal_controller(hwmgr);
 341         ret |= psm_set_performance_states(hwmgr);
 342         if (ret)
 343                 return ret;
 344
 345         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 346
 347         return ret;
 348 }
 349
 350 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 351 {
 352         switch (state) {
 353         case POWER_STATE_TYPE_BATTERY:
 354                 return PP_StateUILabel_Battery;
 355         case POWER_STATE_TYPE_BALANCED:
 356                 return PP_StateUILabel_Balanced;
 357         case POWER_STATE_TYPE_PERFORMANCE:
 358                 return PP_StateUILabel_Performance;
 359         default:
 360                 return PP_StateUILabel_None;
 361         }
 362 }
 363
 364 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
 365                 enum amd_pm_state_type *user_state)
 366 {
 367         int ret = 0;
 368
 369         if (hwmgr == NULL)
 370                 return -EINVAL;
 371
 372         switch (task_id) {
 373         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
 374                 ret = phm_set_cpu_power_state(hwmgr);
 375                 if (ret)
 376                         return ret;
 377                 ret = psm_set_performance_states(hwmgr);
 378                 if (ret)
 379                         return ret;
 380                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 381                 break;
 382         case AMD_PP_TASK_ENABLE_USER_STATE:
 383         {
 384                 enum PP_StateUILabel requested_ui_label;
 385                 struct pp_power_state *requested_ps = NULL;
 386
 387                 if (user_state == NULL) {
 388                         ret = -EINVAL;
 389                         break;
 390                 }
 391
 392                 requested_ui_label = power_state_convert(*user_state);
 393                 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
 394                 if (ret)
 395                         return ret;
 396                 ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
 397                 break;
 398         }
 399         case AMD_PP_TASK_COMPLETE_INIT:
 400         case AMD_PP_TASK_READJUST_POWER_STATE:
 401                 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 402                 break;
 403         default:
 404                 break;
 405         }
 406         return ret;
 407 }
 408
 409 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 410 {
 411         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 412
 413         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
 414         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
 415
 416 #if defined(CONFIG_ACPI)
 417         if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
 418                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 419 #endif
 420
 421         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 422                 PHM_PlatformCaps_DynamicPatchPowerState);
 423
 424         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 425                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 426
 427         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 428                         PHM_PlatformCaps_DynamicPowerManagement);
 429
 430         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 431                                         PHM_PlatformCaps_SMC);
 432
 433         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 434                                         PHM_PlatformCaps_DynamicUVDState);
 435
 436         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 437                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 438         return;
 439 }
 440
 441 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 442 {
 443         if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
 444                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 445                         PHM_PlatformCaps_SclkDeepSleep);
 446         else
 447                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 448                         PHM_PlatformCaps_SclkDeepSleep);
 449
 450         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 451                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 452                             PHM_PlatformCaps_PowerContainment);
 453                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 454                         PHM_PlatformCaps_CAC);
 455         } else {
 456                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 457                             PHM_PlatformCaps_PowerContainment);
 458                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 459                         PHM_PlatformCaps_CAC);
 460         }
 461
 462         if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
 463                 hwmgr->od_enabled = true;
 464
 465         return 0;
 466 }
 467
 468 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 469 {
 470         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 471                                                 PHM_PlatformCaps_EVV);
 472         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 473                                                 PHM_PlatformCaps_SQRamping);
 474         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 475                                                 PHM_PlatformCaps_RegulatorHot);
 476
 477         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 478                                         PHM_PlatformCaps_AutomaticDCTransition);
 479
 480         if (hwmgr->chip_id != CHIP_POLARIS10)
 481                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 482                                         PHM_PlatformCaps_SPLLShutdownSupport);
 483
 484         if (hwmgr->chip_id != CHIP_POLARIS11) {
 485                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 486                                                         PHM_PlatformCaps_DBRamping);
 487                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 488                                                         PHM_PlatformCaps_TDRamping);
 489                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 490                                                         PHM_PlatformCaps_TCPRamping);
 491         }
 492         return 0;
 493 }
 494
 495 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 496 {
 497         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 498                                                 PHM_PlatformCaps_EVV);
 499         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 500                         PHM_PlatformCaps_SQRamping);
 501         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 502                         PHM_PlatformCaps_DBRamping);
 503         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 504                         PHM_PlatformCaps_TDRamping);
 505         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 506                         PHM_PlatformCaps_TCPRamping);
 507         return 0;
 508 }
 509
 510 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 511 {
 512         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 513                                                 PHM_PlatformCaps_EVV);
 514         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 515                         PHM_PlatformCaps_SQRamping);
 516         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 517                         PHM_PlatformCaps_DBRamping);
 518         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 519                         PHM_PlatformCaps_TDRamping);
 520         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 521                         PHM_PlatformCaps_TCPRamping);
 522
 523         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 524                       PHM_PlatformCaps_UVDPowerGating);
 525         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 526                       PHM_PlatformCaps_VCEPowerGating);
 527         return 0;
 528 }
 529
 530 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 531 {
 532         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 533                                                 PHM_PlatformCaps_EVV);
 534         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 535                         PHM_PlatformCaps_SQRamping);
 536         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 537                         PHM_PlatformCaps_DBRamping);
 538         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 539                         PHM_PlatformCaps_TDRamping);
 540         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 541                         PHM_PlatformCaps_TCPRamping);
 542         return 0;
 543 }
 544
 545 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 546 {
 547         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 548                         PHM_PlatformCaps_SQRamping);
 549         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 550                         PHM_PlatformCaps_DBRamping);
 551         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 552                         PHM_PlatformCaps_TDRamping);
 553         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 554                         PHM_PlatformCaps_TCPRamping);
 555         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 556                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 557         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 558                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
 559         return 0;
 560 }