2 * Copyright 2017 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "smu10_inc.h"
29 #include "smu10_driver_if.h"
33 #define SMU10_MAX_HARDWARE_POWERLEVELS 8
34 #define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
36 #define DPMFlags_SCLK_Enabled 0x00000001
37 #define DPMFlags_UVD_Enabled 0x00000002
38 #define DPMFlags_VCE_Enabled 0x00000004
39 #define DPMFlags_ACP_Enabled 0x00000008
40 #define DPMFlags_ForceHighestValid 0x40000000
42 /* Do not change the following, it is also defined in SMU8.h */
43 #define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
44 #define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
45 #define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000
46 #define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000
48 #define SMU_PHYID_SHIFT 8
50 #define SMU10_PCIE_POWERGATING_TARGET_GFX 0
51 #define SMU10_PCIE_POWERGATING_TARGET_DDI 1
52 #define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE 2
53 #define SMU10_PCIE_POWERGATING_TARGET_PHY 3
63 #define SUSTAINABLE_SCLK_MASK 0x00ffffff
64 #define SUSTAINABLE_SCLK_SHIFT 0
65 #define SUSTAINABLE_CU_MASK 0xff000000
66 #define SUSTAINABLE_CU_SHIFT 24
68 struct smu10_dpm_entry {
69 uint32_t soft_min_clk;
70 uint32_t hard_min_clk;
71 uint32_t soft_max_clk;
72 uint32_t hard_max_clk;
75 struct smu10_power_level {
76 uint32_t engine_clock;
78 uint8_t ds_divider_index;
79 uint8_t ss_divider_index;
80 uint8_t allow_gnb_slow;
81 uint8_t force_nbp_state;
84 uint8_t num_simd_to_powerdown;
85 uint8_t hysteresis_up;
89 /*used for the nbpsFlags field in smu10_power state*/
90 #define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
91 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
92 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
94 #define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0)
96 struct smu10_uvd_clocks {
99 uint32_t vclk_low_divider;
100 uint32_t vclk_high_divider;
101 uint32_t dclk_low_divider;
102 uint32_t dclk_high_divider;
105 struct pp_disable_nbpslo_flags {
109 uint32_t display : 1;
114 uint32_t reserved: 26;
121 enum smu10_pstate_previous_action {
127 struct smu10_power_state {
130 struct smu10_uvd_clocks uvd_clocks;
135 bool need_dfs_bypass;
139 uint8_t dpm0_pg_nbps_low;
140 uint8_t dpm0_pg_nbps_high;
141 uint8_t dpm_x_nbps_low;
142 uint8_t dpm_x_nbps_high;
144 enum smu10_pstate_previous_action action;
146 struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
147 struct pp_disable_nbpslo_flags nbpslo_flags;
150 #define SMU10_NUM_NBPSTATES 4
151 #define SMU10_NUM_NBPMEMORYCLOCK 2
154 struct smu10_display_phy_info_entry {
156 uint8_t active_lane_mapping;
157 uint8_t display_config_type;
158 uint8_t active_num_of_lanes;
161 #define SMU10_MAX_DISPLAYPHY_IDS 10
163 struct smu10_display_phy_info {
164 bool display_phy_access_initialized;
165 struct smu10_display_phy_info_entry entries[SMU10_MAX_DISPLAYPHY_IDS];
168 #define MAX_DISPLAY_CLOCK_LEVEL 8
170 struct smu10_system_info{
172 uint8_t htc_hyst_lmt;
175 #define MAX_REGULAR_DPM_NUMBER 8
177 struct smu10_mclk_latency_entries {
182 struct smu10_mclk_latency_table {
184 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
187 struct smu10_clock_voltage_dependency_record {
193 struct smu10_voltage_dependency_table {
195 struct smu10_clock_voltage_dependency_record entries[1];
198 struct smu10_clock_voltage_information {
199 struct smu10_voltage_dependency_table *vdd_dep_on_dcefclk;
200 struct smu10_voltage_dependency_table *vdd_dep_on_socclk;
201 struct smu10_voltage_dependency_table *vdd_dep_on_fclk;
202 struct smu10_voltage_dependency_table *vdd_dep_on_mclk;
203 struct smu10_voltage_dependency_table *vdd_dep_on_dispclk;
204 struct smu10_voltage_dependency_table *vdd_dep_on_dppclk;
205 struct smu10_voltage_dependency_table *vdd_dep_on_phyclk;
209 uint32_t disable_driver_thermal_policy;
210 uint32_t thermal_auto_throttling_treshold;
211 struct smu10_system_info sys_info;
212 struct smu10_mclk_latency_table mclk_latency_table;
214 uint32_t ddi_power_gating_disabled;
216 struct smu10_display_phy_info_entry display_phy_info;
217 uint32_t dce_slow_sclk_threshold;
219 bool disp_clk_bypass;
220 bool disp_clk_bypass_pending;
221 uint32_t bapm_enabled;
226 uint32_t is_nb_dpm_enabled;
227 uint32_t is_voltage_island_enabled;
228 uint32_t disable_smu_acp_s3_handshake;
229 uint32_t disable_notify_smu_vpu_recovery;
230 bool in_vpu_recovery;
235 uint32_t power_containment_features;
237 bool disable_uvd_power_tune_feature;
238 bool enable_bapm_feature;
239 bool enable_tdc_limit_feature;
242 /* SMC SRAM Address of firmware header tables */
244 uint32_t dpm_table_start;
245 uint32_t soft_regs_start;
247 /* start of SMU7_Fusion_DpmTable */
249 uint8_t uvd_level_count;
250 uint8_t vce_level_count;
251 uint8_t acp_level_count;
252 uint8_t samu_level_count;
254 uint32_t fps_high_threshold;
255 uint32_t fps_low_threshold;
258 struct smu10_dpm_entry sclk_dpm;
259 struct smu10_dpm_entry uvd_dpm;
260 struct smu10_dpm_entry vce_dpm;
261 struct smu10_dpm_entry acp_dpm;
262 bool acp_power_up_no_dsp;
264 uint32_t max_sclk_level;
265 uint32_t num_of_clk_entries;
267 /* CPU Power State */
268 uint32_t separation_time;
271 bool cc6_setting_changed;
273 uint32_t ulTotalActiveCUs;
275 bool isp_tileA_power_gated;
276 bool isp_tileB_power_gated;
277 uint32_t isp_actual_hard_min_freq;
278 uint32_t soc_actual_hard_min_freq;
279 uint32_t dcf_actual_hard_min_freq;
281 uint32_t f_actual_hard_min_freq;
282 uint32_t fabric_actual_soft_min_freq;
283 uint32_t vclk_soft_min;
284 uint32_t dclk_soft_min;
285 uint32_t gfx_actual_soft_min_freq;
286 uint32_t gfx_min_freq_limit;
287 uint32_t gfx_max_freq_limit;
289 bool vcn_power_gated;
292 bool gfx_off_controled_by_driver;
293 bool water_marks_exist;
294 Watermarks_t water_marks_table;
295 struct smu10_clock_voltage_information clock_vol_info;
296 DpmClocks_t clock_table;
298 uint32_t active_process_mask;
299 bool need_min_deep_sleep_dcefclk;
300 uint32_t deep_sleep_dcefclk;
301 uint32_t num_active_display;
306 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
308 /* UMD PState SMU10 Msg Parameters in MHz */
309 #define SMU10_UMD_PSTATE_GFXCLK 700
310 #define SMU10_UMD_PSTATE_SOCCLK 626
311 #define SMU10_UMD_PSTATE_FCLK 933
312 #define SMU10_UMD_PSTATE_VCE 0x03C00320
314 #define SMU10_UMD_PSTATE_PEAK_SOCCLK 757
315 #define SMU10_UMD_PSTATE_PEAK_FCLK 1200
317 #define SMU10_UMD_PSTATE_MIN_FCLK 400
318 #define SMU10_UMD_PSTATE_MIN_SOCCLK 200
319 #define SMU10_UMD_PSTATE_MIN_VCE 0x0190012C