2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
31 #include "smu/smu_8_0_d.h"
32 #include "smu8_fusion.h"
33 #include "smu/smu_8_0_sh_mask.h"
36 #include "hardwaremanager.h"
38 #include "smu8_hwmgr.h"
39 #include "power_state.h"
40 #include "pp_thermal.h"
42 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
43 #define CURRENT_NB_VID_MASK 0xff000000
44 #define CURRENT_NB_VID__SHIFT 24
45 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048
46 #define CURRENT_GFX_VID_MASK 0xff000000
47 #define CURRENT_GFX_VID__SHIFT 24
49 static const unsigned long smu8_magic = (unsigned long) PHM_Cz_Magic;
51 static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps)
53 if (smu8_magic != hw_ps->magic)
56 return (struct smu8_power_state *)hw_ps;
59 static const struct smu8_power_state *cast_const_smu8_power_state(
60 const struct pp_hw_power_state *hw_ps)
62 if (smu8_magic != hw_ps->magic)
65 return (struct smu8_power_state *)hw_ps;
68 static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr,
69 uint32_t clock, uint32_t msg)
72 struct phm_vce_clock_voltage_dependency_table *ptable =
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
76 case PPSMC_MSG_SetEclkSoftMin:
77 case PPSMC_MSG_SetEclkHardMin:
78 for (i = 0; i < (int)ptable->count; i++) {
79 if (clock <= ptable->entries[i].ecclk)
84 case PPSMC_MSG_SetEclkSoftMax:
85 case PPSMC_MSG_SetEclkHardMax:
86 for (i = ptable->count - 1; i >= 0; i--) {
87 if (clock >= ptable->entries[i].ecclk)
99 static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr,
100 uint32_t clock, uint32_t msg)
103 struct phm_clock_voltage_dependency_table *table =
104 hwmgr->dyn_state.vddc_dependency_on_sclk;
107 case PPSMC_MSG_SetSclkSoftMin:
108 case PPSMC_MSG_SetSclkHardMin:
109 for (i = 0; i < (int)table->count; i++) {
110 if (clock <= table->entries[i].clk)
115 case PPSMC_MSG_SetSclkSoftMax:
116 case PPSMC_MSG_SetSclkHardMax:
117 for (i = table->count - 1; i >= 0; i--) {
118 if (clock >= table->entries[i].clk)
129 static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr,
130 uint32_t clock, uint32_t msg)
133 struct phm_uvd_clock_voltage_dependency_table *ptable =
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
137 case PPSMC_MSG_SetUvdSoftMin:
138 case PPSMC_MSG_SetUvdHardMin:
139 for (i = 0; i < (int)ptable->count; i++) {
140 if (clock <= ptable->entries[i].vclk)
145 case PPSMC_MSG_SetUvdSoftMax:
146 case PPSMC_MSG_SetUvdHardMax:
147 for (i = ptable->count - 1; i >= 0; i--) {
148 if (clock >= ptable->entries[i].vclk)
160 static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr)
162 struct smu8_hwmgr *data = hwmgr->backend;
164 if (data->max_sclk_level == 0) {
165 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
166 data->max_sclk_level = smum_get_argument(hwmgr) + 1;
169 return data->max_sclk_level;
172 static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
174 struct smu8_hwmgr *data = hwmgr->backend;
175 struct amdgpu_device *adev = hwmgr->adev;
177 data->gfx_ramp_step = 256*25/100;
178 data->gfx_ramp_delay = 1; /* by default, we delay 1us */
180 data->mgcg_cgtt_local0 = 0x00000000;
181 data->mgcg_cgtt_local1 = 0x00000000;
182 data->clock_slow_down_freq = 25000;
183 data->skip_clock_slow_down = 1;
184 data->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
185 data->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
186 data->voting_rights_clients = 0x00C00033;
187 data->static_screen_threshold = 8;
188 data->ddi_power_gating_disabled = 0;
189 data->bapm_enabled = 1;
190 data->voltage_drop_threshold = 0;
191 data->gfx_power_gating_threshold = 500;
192 data->vce_slow_sclk_threshold = 20000;
193 data->dce_slow_sclk_threshold = 30000;
194 data->disable_driver_thermal_policy = 1;
195 data->disable_nb_ps3_in_battery = 0;
197 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
198 PHM_PlatformCaps_ABM);
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 PHM_PlatformCaps_NonABMSupportInPPLib);
203 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_DynamicM3Arbiter);
206 data->override_dynamic_mgpg = 1;
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_DynamicPatchPowerState);
211 data->thermal_auto_throttling_treshold = 0;
213 data->disable_gfx_power_gating_in_uvd = 0;
215 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
216 PHM_PlatformCaps_DynamicUVDState);
218 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_UVDDPM);
220 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_VCEDPM);
223 data->cc6_settings.cpu_cc6_disable = false;
224 data->cc6_settings.cpu_pstate_disable = false;
225 data->cc6_settings.nb_pstate_switch_disable = false;
226 data->cc6_settings.cpu_pstate_separation_time = 0;
228 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_DisableVoltageIsland);
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_UVDPowerGating);
233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
234 PHM_PlatformCaps_VCEPowerGating);
236 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_UVDPowerGating);
239 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_VCEPowerGating);
247 /* convert form 8bit vid to real voltage in mV*4 */
248 static uint32_t smu8_convert_8Bit_index_to_voltage(
249 struct pp_hwmgr *hwmgr, uint16_t voltage)
251 return 6200 - (voltage * 25);
254 static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
255 struct phm_clock_and_voltage_limits *table)
257 struct smu8_hwmgr *data = hwmgr->backend;
258 struct smu8_sys_info *sys_info = &data->sys_info;
259 struct phm_clock_voltage_dependency_table *dep_table =
260 hwmgr->dyn_state.vddc_dependency_on_sclk;
262 if (dep_table->count > 0) {
263 table->sclk = dep_table->entries[dep_table->count-1].clk;
264 table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr,
265 (uint16_t)dep_table->entries[dep_table->count-1].v);
267 table->mclk = sys_info->nbp_memory_clock[0];
271 static int smu8_init_dynamic_state_adjustment_rule_settings(
272 struct pp_hwmgr *hwmgr,
273 ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
275 uint32_t table_size =
276 sizeof(struct phm_clock_voltage_dependency_table) +
277 (7 * sizeof(struct phm_clock_voltage_dependency_record));
279 struct phm_clock_voltage_dependency_table *table_clk_vlt =
280 kzalloc(table_size, GFP_KERNEL);
282 if (NULL == table_clk_vlt) {
283 pr_err("Can not allocate memory!\n");
287 table_clk_vlt->count = 8;
288 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
289 table_clk_vlt->entries[0].v = 0;
290 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
291 table_clk_vlt->entries[1].v = 1;
292 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
293 table_clk_vlt->entries[2].v = 2;
294 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
295 table_clk_vlt->entries[3].v = 3;
296 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
297 table_clk_vlt->entries[4].v = 4;
298 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
299 table_clk_vlt->entries[5].v = 5;
300 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
301 table_clk_vlt->entries[6].v = 6;
302 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
303 table_clk_vlt->entries[7].v = 7;
304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
309 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
311 struct smu8_hwmgr *data = hwmgr->backend;
312 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
318 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev,
319 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
320 &size, &frev, &crev);
323 pr_err("Could not retrieve the Integrated System Info Table!\n");
328 pr_err("Unsupported IGP table: %d %d\n", frev, crev);
332 data->sys_info.bootup_uma_clock =
333 le32_to_cpu(info->ulBootUpUMAClock);
335 data->sys_info.bootup_engine_clock =
336 le32_to_cpu(info->ulBootUpEngineClock);
338 data->sys_info.dentist_vco_freq =
339 le32_to_cpu(info->ulDentistVCOFreq);
341 data->sys_info.system_config =
342 le32_to_cpu(info->ulSystemConfig);
344 data->sys_info.bootup_nb_voltage_index =
345 le16_to_cpu(info->usBootUpNBVoltage);
347 data->sys_info.htc_hyst_lmt =
348 (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
350 data->sys_info.htc_tmp_lmt =
351 (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
353 if (data->sys_info.htc_tmp_lmt <=
354 data->sys_info.htc_hyst_lmt) {
355 pr_err("The htcTmpLmt should be larger than htcHystLmt.\n");
359 data->sys_info.nb_dpm_enable =
360 data->enable_nb_ps_policy &&
361 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
363 for (i = 0; i < SMU8_NUM_NBPSTATES; i++) {
364 if (i < SMU8_NUM_NBPMEMORYCLOCK) {
365 data->sys_info.nbp_memory_clock[i] =
366 le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
368 data->sys_info.nbp_n_clock[i] =
369 le32_to_cpu(info->ulNbpStateNClkFreq[i]);
372 for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
373 data->sys_info.display_clock[i] =
374 le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
377 /* Here use 4 levels, make sure not exceed */
378 for (i = 0; i < SMU8_NUM_NBPSTATES; i++) {
379 data->sys_info.nbp_voltage_index[i] =
380 le16_to_cpu(info->usNBPStateVoltage[i]);
383 if (!data->sys_info.nb_dpm_enable) {
384 for (i = 1; i < SMU8_NUM_NBPSTATES; i++) {
385 if (i < SMU8_NUM_NBPMEMORYCLOCK) {
386 data->sys_info.nbp_memory_clock[i] =
387 data->sys_info.nbp_memory_clock[0];
389 data->sys_info.nbp_n_clock[i] =
390 data->sys_info.nbp_n_clock[0];
391 data->sys_info.nbp_voltage_index[i] =
392 data->sys_info.nbp_voltage_index[0];
396 if (le32_to_cpu(info->ulGPUCapInfo) &
397 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
398 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
399 PHM_PlatformCaps_EnableDFSBypass);
402 data->sys_info.uma_channel_number = info->ucUMAChannelNumber;
404 smu8_construct_max_power_limits_table (hwmgr,
405 &hwmgr->dyn_state.max_clock_voltage_on_ac);
407 smu8_init_dynamic_state_adjustment_rule_settings(hwmgr,
408 &info->sDISPCLK_Voltage[0]);
413 static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr)
415 struct smu8_hwmgr *data = hwmgr->backend;
417 data->boot_power_level.engineClock =
418 data->sys_info.bootup_engine_clock;
420 data->boot_power_level.vddcIndex =
421 (uint8_t)data->sys_info.bootup_nb_voltage_index;
423 data->boot_power_level.dsDividerIndex = 0;
424 data->boot_power_level.ssDividerIndex = 0;
425 data->boot_power_level.allowGnbSlow = 1;
426 data->boot_power_level.forceNBPstate = 0;
427 data->boot_power_level.hysteresis_up = 0;
428 data->boot_power_level.numSIMDToPowerDown = 0;
429 data->boot_power_level.display_wm = 0;
430 data->boot_power_level.vce_wm = 0;
435 static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
437 struct SMU8_Fusion_ClkTable *clock_table;
441 pp_atomctrl_clock_dividers_kong dividers;
443 struct phm_clock_voltage_dependency_table *vddc_table =
444 hwmgr->dyn_state.vddc_dependency_on_sclk;
445 struct phm_clock_voltage_dependency_table *vdd_gfx_table =
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
447 struct phm_acp_clock_voltage_dependency_table *acp_table =
448 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
449 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
451 struct phm_vce_clock_voltage_dependency_table *vce_table =
452 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
454 if (!hwmgr->need_pp_table_upload)
457 ret = smum_download_powerplay_table(hwmgr, &table);
459 PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
460 "Fail to get clock table from SMU!", return -EINVAL;);
462 clock_table = (struct SMU8_Fusion_ClkTable *)table;
464 /* patch clock table */
465 PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
466 "Dependency table entry exceeds max limit!", return -EINVAL;);
467 PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
468 "Dependency table entry exceeds max limit!", return -EINVAL;);
469 PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
470 "Dependency table entry exceeds max limit!", return -EINVAL;);
471 PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
472 "Dependency table entry exceeds max limit!", return -EINVAL;);
473 PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
474 "Dependency table entry exceeds max limit!", return -EINVAL;);
476 for (i = 0; i < SMU8_MAX_HARDWARE_POWERLEVELS; i++) {
479 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
480 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
481 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
482 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
484 atomctrl_get_engine_pll_dividers_kong(hwmgr,
485 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
488 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
489 (uint8_t)dividers.pll_post_divider;
492 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
493 (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
496 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
497 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
498 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
499 (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
501 atomctrl_get_engine_pll_dividers_kong(hwmgr,
502 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
505 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
506 (uint8_t)dividers.pll_post_divider;
510 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
511 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
512 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
515 atomctrl_get_engine_pll_dividers_kong(hwmgr,
516 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
519 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
520 (uint8_t)dividers.pll_post_divider;
522 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
523 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
524 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
525 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
527 atomctrl_get_engine_pll_dividers_kong(hwmgr,
528 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
531 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
532 (uint8_t)dividers.pll_post_divider;
535 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
536 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
537 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
538 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
541 atomctrl_get_engine_pll_dividers_kong(hwmgr,
542 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
545 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
546 (uint8_t)dividers.pll_post_divider;
549 ret = smum_upload_powerplay_table(hwmgr);
554 static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr)
556 struct smu8_hwmgr *data = hwmgr->backend;
557 struct phm_clock_voltage_dependency_table *table =
558 hwmgr->dyn_state.vddc_dependency_on_sclk;
559 unsigned long clock = 0, level;
561 if (NULL == table || table->count <= 0)
564 data->sclk_dpm.soft_min_clk = table->entries[0].clk;
565 data->sclk_dpm.hard_min_clk = table->entries[0].clk;
567 level = smu8_get_max_sclk_level(hwmgr) - 1;
569 if (level < table->count)
570 clock = table->entries[level].clk;
572 clock = table->entries[table->count - 1].clk;
574 data->sclk_dpm.soft_max_clk = clock;
575 data->sclk_dpm.hard_max_clk = clock;
580 static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr)
582 struct smu8_hwmgr *data = hwmgr->backend;
583 struct phm_uvd_clock_voltage_dependency_table *table =
584 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
585 unsigned long clock = 0, level;
587 if (NULL == table || table->count <= 0)
590 data->uvd_dpm.soft_min_clk = 0;
591 data->uvd_dpm.hard_min_clk = 0;
593 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
594 level = smum_get_argument(hwmgr);
596 if (level < table->count)
597 clock = table->entries[level].vclk;
599 clock = table->entries[table->count - 1].vclk;
601 data->uvd_dpm.soft_max_clk = clock;
602 data->uvd_dpm.hard_max_clk = clock;
607 static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr)
609 struct smu8_hwmgr *data = hwmgr->backend;
610 struct phm_vce_clock_voltage_dependency_table *table =
611 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
612 unsigned long clock = 0, level;
614 if (NULL == table || table->count <= 0)
617 data->vce_dpm.soft_min_clk = 0;
618 data->vce_dpm.hard_min_clk = 0;
620 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
621 level = smum_get_argument(hwmgr);
623 if (level < table->count)
624 clock = table->entries[level].ecclk;
626 clock = table->entries[table->count - 1].ecclk;
628 data->vce_dpm.soft_max_clk = clock;
629 data->vce_dpm.hard_max_clk = clock;
634 static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr)
636 struct smu8_hwmgr *data = hwmgr->backend;
637 struct phm_acp_clock_voltage_dependency_table *table =
638 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
639 unsigned long clock = 0, level;
641 if (NULL == table || table->count <= 0)
644 data->acp_dpm.soft_min_clk = 0;
645 data->acp_dpm.hard_min_clk = 0;
647 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
648 level = smum_get_argument(hwmgr);
650 if (level < table->count)
651 clock = table->entries[level].acpclk;
653 clock = table->entries[table->count - 1].acpclk;
655 data->acp_dpm.soft_max_clk = clock;
656 data->acp_dpm.hard_max_clk = clock;
660 static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr)
662 struct smu8_hwmgr *data = hwmgr->backend;
664 data->uvd_power_gated = false;
665 data->vce_power_gated = false;
666 data->samu_power_gated = false;
667 #ifdef CONFIG_DRM_AMD_ACP
668 data->acp_power_gated = false;
670 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
671 data->acp_power_gated = true;
676 static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr)
678 struct smu8_hwmgr *data = hwmgr->backend;
680 data->low_sclk_interrupt_threshold = 0;
683 static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr)
685 struct smu8_hwmgr *data = hwmgr->backend;
686 struct phm_clock_voltage_dependency_table *table =
687 hwmgr->dyn_state.vddc_dependency_on_sclk;
689 unsigned long clock = 0;
691 unsigned long stable_pstate_sclk;
692 unsigned long percentage;
694 data->sclk_dpm.soft_min_clk = table->entries[0].clk;
695 level = smu8_get_max_sclk_level(hwmgr) - 1;
697 if (level < table->count)
698 data->sclk_dpm.soft_max_clk = table->entries[level].clk;
700 data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
702 clock = hwmgr->display_config->min_core_set_clock;
704 pr_debug("min_core_set_clock not set\n");
706 if (data->sclk_dpm.hard_min_clk != clock) {
707 data->sclk_dpm.hard_min_clk = clock;
709 smum_send_msg_to_smc_with_parameter(hwmgr,
710 PPSMC_MSG_SetSclkHardMin,
711 smu8_get_sclk_level(hwmgr,
712 data->sclk_dpm.hard_min_clk,
713 PPSMC_MSG_SetSclkHardMin));
716 clock = data->sclk_dpm.soft_min_clk;
718 /* update minimum clocks for Stable P-State feature */
719 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
720 PHM_PlatformCaps_StablePState)) {
722 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
723 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
726 if (clock < stable_pstate_sclk)
727 clock = stable_pstate_sclk;
730 if (data->sclk_dpm.soft_min_clk != clock) {
731 data->sclk_dpm.soft_min_clk = clock;
732 smum_send_msg_to_smc_with_parameter(hwmgr,
733 PPSMC_MSG_SetSclkSoftMin,
734 smu8_get_sclk_level(hwmgr,
735 data->sclk_dpm.soft_min_clk,
736 PPSMC_MSG_SetSclkSoftMin));
739 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
740 PHM_PlatformCaps_StablePState) &&
741 data->sclk_dpm.soft_max_clk != clock) {
742 data->sclk_dpm.soft_max_clk = clock;
743 smum_send_msg_to_smc_with_parameter(hwmgr,
744 PPSMC_MSG_SetSclkSoftMax,
745 smu8_get_sclk_level(hwmgr,
746 data->sclk_dpm.soft_max_clk,
747 PPSMC_MSG_SetSclkSoftMax));
753 static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
755 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
756 PHM_PlatformCaps_SclkDeepSleep)) {
757 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
759 clks = SMU8_MIN_DEEP_SLEEP_SCLK;
761 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
763 smum_send_msg_to_smc_with_parameter(hwmgr,
764 PPSMC_MSG_SetMinDeepSleepSclk,
771 static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr)
773 struct smu8_hwmgr *data =
776 smum_send_msg_to_smc_with_parameter(hwmgr,
777 PPSMC_MSG_SetWatermarkFrequency,
778 data->sclk_dpm.soft_max_clk);
783 static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
785 struct smu8_hwmgr *hw_data = hwmgr->backend;
787 if (hw_data->is_nb_dpm_enabled) {
789 PP_DBG_LOG("enable Low Memory PState.\n");
791 return smum_send_msg_to_smc_with_parameter(hwmgr,
792 PPSMC_MSG_EnableLowMemoryPstate,
795 PP_DBG_LOG("disable Low Memory PState.\n");
797 return smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_DisableLowMemoryPstate,
806 static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr)
810 struct smu8_hwmgr *data = hwmgr->backend;
811 unsigned long dpm_features = 0;
813 if (data->is_nb_dpm_enabled) {
814 smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
815 dpm_features |= NB_DPM_MASK;
816 ret = smum_send_msg_to_smc_with_parameter(
818 PPSMC_MSG_DisableAllSmuFeatures,
821 data->is_nb_dpm_enabled = false;
827 static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr)
831 struct smu8_hwmgr *data = hwmgr->backend;
832 unsigned long dpm_features = 0;
834 if (!data->is_nb_dpm_enabled) {
835 PP_DBG_LOG("enabling ALL SMU features.\n");
836 dpm_features |= NB_DPM_MASK;
837 ret = smum_send_msg_to_smc_with_parameter(
839 PPSMC_MSG_EnableAllSmuFeatures,
842 data->is_nb_dpm_enabled = true;
848 static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
851 bool enable_low_mem_state;
852 struct smu8_hwmgr *hw_data = hwmgr->backend;
853 const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
854 const struct smu8_power_state *pnew_state = cast_const_smu8_power_state(states->pnew_state);
856 if (hw_data->sys_info.nb_dpm_enable) {
857 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
858 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
860 if (pnew_state->action == FORCE_HIGH)
861 smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
862 else if (pnew_state->action == CANCEL_FORCE_HIGH)
863 smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
865 smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
870 static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
874 smu8_update_sclk_limit(hwmgr);
875 smu8_set_deep_sleep_sclk_threshold(hwmgr);
876 smu8_set_watermark_threshold(hwmgr);
877 ret = smu8_enable_nb_dpm(hwmgr);
880 smu8_update_low_mem_pstate(hwmgr, input);
886 static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr)
890 ret = smu8_upload_pptable_to_smu(hwmgr);
893 ret = smu8_init_sclk_limit(hwmgr);
896 ret = smu8_init_uvd_limit(hwmgr);
899 ret = smu8_init_vce_limit(hwmgr);
902 ret = smu8_init_acp_limit(hwmgr);
906 smu8_init_power_gate_state(hwmgr);
907 smu8_init_sclk_threshold(hwmgr);
912 static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
914 struct smu8_hwmgr *hw_data = hwmgr->backend;
916 hw_data->disp_clk_bypass_pending = false;
917 hw_data->disp_clk_bypass = false;
920 static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
922 struct smu8_hwmgr *hw_data = hwmgr->backend;
924 hw_data->is_nb_dpm_enabled = false;
927 static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr)
929 struct smu8_hwmgr *hw_data = hwmgr->backend;
931 hw_data->cc6_settings.cc6_setting_changed = false;
932 hw_data->cc6_settings.cpu_pstate_separation_time = 0;
933 hw_data->cc6_settings.cpu_cc6_disable = false;
934 hw_data->cc6_settings.cpu_pstate_disable = false;
937 static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr)
939 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
940 ixCG_FREQ_TRAN_VOTING_0,
941 SMU8_VOTINGRIGHTSCLIENTS_DFLT0);
944 static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr)
946 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
947 ixCG_FREQ_TRAN_VOTING_0, 0);
950 static int smu8_start_dpm(struct pp_hwmgr *hwmgr)
952 struct smu8_hwmgr *data = hwmgr->backend;
954 data->dpm_flags |= DPMFlags_SCLK_Enabled;
956 return smum_send_msg_to_smc_with_parameter(hwmgr,
957 PPSMC_MSG_EnableAllSmuFeatures,
961 static int smu8_stop_dpm(struct pp_hwmgr *hwmgr)
964 struct smu8_hwmgr *data = hwmgr->backend;
965 unsigned long dpm_features = 0;
967 if (data->dpm_flags & DPMFlags_SCLK_Enabled) {
968 dpm_features |= SCLK_DPM_MASK;
969 data->dpm_flags &= ~DPMFlags_SCLK_Enabled;
970 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
971 PPSMC_MSG_DisableAllSmuFeatures,
977 static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr)
979 struct smu8_hwmgr *data = hwmgr->backend;
981 data->sclk_dpm.soft_min_clk = data->sys_info.bootup_engine_clock;
982 data->sclk_dpm.soft_max_clk = data->sys_info.bootup_engine_clock;
984 smum_send_msg_to_smc_with_parameter(hwmgr,
985 PPSMC_MSG_SetSclkSoftMin,
986 smu8_get_sclk_level(hwmgr,
987 data->sclk_dpm.soft_min_clk,
988 PPSMC_MSG_SetSclkSoftMin));
990 smum_send_msg_to_smc_with_parameter(hwmgr,
991 PPSMC_MSG_SetSclkSoftMax,
992 smu8_get_sclk_level(hwmgr,
993 data->sclk_dpm.soft_max_clk,
994 PPSMC_MSG_SetSclkSoftMax));
999 static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
1001 struct smu8_hwmgr *data = hwmgr->backend;
1003 data->acp_boot_level = 0xff;
1006 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1008 smu8_program_voting_clients(hwmgr);
1009 if (smu8_start_dpm(hwmgr))
1011 smu8_program_bootup_state(hwmgr);
1012 smu8_reset_acp_boot_level(hwmgr);
1017 static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1019 smu8_disable_nb_dpm(hwmgr);
1021 smu8_clear_voting_clients(hwmgr);
1022 if (smu8_stop_dpm(hwmgr))
1028 static int smu8_power_off_asic(struct pp_hwmgr *hwmgr)
1030 smu8_disable_dpm_tasks(hwmgr);
1031 smu8_power_up_display_clock_sys_pll(hwmgr);
1032 smu8_clear_nb_dpm_flag(hwmgr);
1033 smu8_reset_cc6_data(hwmgr);
1037 static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1038 struct pp_power_state *prequest_ps,
1039 const struct pp_power_state *pcurrent_ps)
1041 struct smu8_power_state *smu8_ps =
1042 cast_smu8_power_state(&prequest_ps->hardware);
1044 const struct smu8_power_state *smu8_current_ps =
1045 cast_const_smu8_power_state(&pcurrent_ps->hardware);
1047 struct smu8_hwmgr *data = hwmgr->backend;
1048 struct PP_Clocks clocks = {0, 0, 0, 0};
1051 smu8_ps->need_dfs_bypass = true;
1053 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1055 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
1056 hwmgr->display_config->min_mem_set_clock :
1057 data->sys_info.nbp_memory_clock[1];
1060 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1061 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1063 force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1])
1064 || (hwmgr->display_config->num_display >= 3);
1066 smu8_ps->action = smu8_current_ps->action;
1068 if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1069 smu8_nbdpm_pstate_enable_disable(hwmgr, false, false);
1070 else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
1071 smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
1072 else if (!force_high && (smu8_ps->action == FORCE_HIGH))
1073 smu8_ps->action = CANCEL_FORCE_HIGH;
1074 else if (force_high && (smu8_ps->action != FORCE_HIGH))
1075 smu8_ps->action = FORCE_HIGH;
1077 smu8_ps->action = DO_NOTHING;
1082 static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1085 struct smu8_hwmgr *data;
1087 data = kzalloc(sizeof(struct smu8_hwmgr), GFP_KERNEL);
1091 hwmgr->backend = data;
1093 result = smu8_initialize_dpm_defaults(hwmgr);
1095 pr_err("smu8_initialize_dpm_defaults failed\n");
1099 result = smu8_get_system_info_data(hwmgr);
1101 pr_err("smu8_get_system_info_data failed\n");
1105 smu8_construct_boot_state(hwmgr);
1107 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS;
1112 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1114 if (hwmgr != NULL) {
1115 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
1116 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1118 kfree(hwmgr->backend);
1119 hwmgr->backend = NULL;
1124 static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1126 struct smu8_hwmgr *data = hwmgr->backend;
1128 smum_send_msg_to_smc_with_parameter(hwmgr,
1129 PPSMC_MSG_SetSclkSoftMin,
1130 smu8_get_sclk_level(hwmgr,
1131 data->sclk_dpm.soft_max_clk,
1132 PPSMC_MSG_SetSclkSoftMin));
1134 smum_send_msg_to_smc_with_parameter(hwmgr,
1135 PPSMC_MSG_SetSclkSoftMax,
1136 smu8_get_sclk_level(hwmgr,
1137 data->sclk_dpm.soft_max_clk,
1138 PPSMC_MSG_SetSclkSoftMax));
1143 static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1145 struct smu8_hwmgr *data = hwmgr->backend;
1146 struct phm_clock_voltage_dependency_table *table =
1147 hwmgr->dyn_state.vddc_dependency_on_sclk;
1148 unsigned long clock = 0, level;
1150 if (NULL == table || table->count <= 0)
1153 data->sclk_dpm.soft_min_clk = table->entries[0].clk;
1154 data->sclk_dpm.hard_min_clk = table->entries[0].clk;
1155 hwmgr->pstate_sclk = table->entries[0].clk;
1156 hwmgr->pstate_mclk = 0;
1158 level = smu8_get_max_sclk_level(hwmgr) - 1;
1160 if (level < table->count)
1161 clock = table->entries[level].clk;
1163 clock = table->entries[table->count - 1].clk;
1165 data->sclk_dpm.soft_max_clk = clock;
1166 data->sclk_dpm.hard_max_clk = clock;
1168 smum_send_msg_to_smc_with_parameter(hwmgr,
1169 PPSMC_MSG_SetSclkSoftMin,
1170 smu8_get_sclk_level(hwmgr,
1171 data->sclk_dpm.soft_min_clk,
1172 PPSMC_MSG_SetSclkSoftMin));
1174 smum_send_msg_to_smc_with_parameter(hwmgr,
1175 PPSMC_MSG_SetSclkSoftMax,
1176 smu8_get_sclk_level(hwmgr,
1177 data->sclk_dpm.soft_max_clk,
1178 PPSMC_MSG_SetSclkSoftMax));
1183 static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1185 struct smu8_hwmgr *data = hwmgr->backend;
1187 smum_send_msg_to_smc_with_parameter(hwmgr,
1188 PPSMC_MSG_SetSclkSoftMax,
1189 smu8_get_sclk_level(hwmgr,
1190 data->sclk_dpm.soft_min_clk,
1191 PPSMC_MSG_SetSclkSoftMax));
1193 smum_send_msg_to_smc_with_parameter(hwmgr,
1194 PPSMC_MSG_SetSclkSoftMin,
1195 smu8_get_sclk_level(hwmgr,
1196 data->sclk_dpm.soft_min_clk,
1197 PPSMC_MSG_SetSclkSoftMin));
1202 static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1203 enum amd_dpm_forced_level level)
1208 case AMD_DPM_FORCED_LEVEL_HIGH:
1209 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1210 ret = smu8_phm_force_dpm_highest(hwmgr);
1212 case AMD_DPM_FORCED_LEVEL_LOW:
1213 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1214 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1215 ret = smu8_phm_force_dpm_lowest(hwmgr);
1217 case AMD_DPM_FORCED_LEVEL_AUTO:
1218 ret = smu8_phm_unforce_dpm_levels(hwmgr);
1220 case AMD_DPM_FORCED_LEVEL_MANUAL:
1221 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1229 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1231 if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
1232 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
1236 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1238 if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
1239 return smum_send_msg_to_smc_with_parameter(
1241 PPSMC_MSG_UVDPowerON,
1242 PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0);
1248 static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1250 struct smu8_hwmgr *data = hwmgr->backend;
1251 struct phm_vce_clock_voltage_dependency_table *ptable =
1252 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1254 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1255 if (PP_CAP(PHM_PlatformCaps_StablePState) ||
1256 hwmgr->en_umd_pstate) {
1257 data->vce_dpm.hard_min_clk =
1258 ptable->entries[ptable->count - 1].ecclk;
1260 smum_send_msg_to_smc_with_parameter(hwmgr,
1261 PPSMC_MSG_SetEclkHardMin,
1262 smu8_get_eclk_level(hwmgr,
1263 data->vce_dpm.hard_min_clk,
1264 PPSMC_MSG_SetEclkHardMin));
1267 smum_send_msg_to_smc_with_parameter(hwmgr,
1268 PPSMC_MSG_SetEclkHardMin, 0);
1269 /* disable ECLK DPM 0. Otherwise VCE could hang if
1270 * switching SCLK from DPM 0 to 6/7 */
1271 smum_send_msg_to_smc_with_parameter(hwmgr,
1272 PPSMC_MSG_SetEclkSoftMin, 1);
1277 static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1279 if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
1280 return smum_send_msg_to_smc(hwmgr,
1281 PPSMC_MSG_VCEPowerOFF);
1285 static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1287 if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
1288 return smum_send_msg_to_smc(hwmgr,
1289 PPSMC_MSG_VCEPowerON);
1293 static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1295 struct smu8_hwmgr *data = hwmgr->backend;
1297 return data->sys_info.bootup_uma_clock;
1300 static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1302 struct pp_power_state *ps;
1303 struct smu8_power_state *smu8_ps;
1308 ps = hwmgr->request_ps;
1313 smu8_ps = cast_smu8_power_state(&ps->hardware);
1316 return smu8_ps->levels[0].engineClock;
1318 return smu8_ps->levels[smu8_ps->level-1].engineClock;
1321 static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1322 struct pp_hw_power_state *hw_ps)
1324 struct smu8_hwmgr *data = hwmgr->backend;
1325 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps);
1328 smu8_ps->nbps_flags = 0;
1329 smu8_ps->bapm_flags = 0;
1330 smu8_ps->levels[0] = data->boot_power_level;
1335 static int smu8_dpm_get_pp_table_entry_callback(
1336 struct pp_hwmgr *hwmgr,
1337 struct pp_hw_power_state *hw_ps,
1339 const void *clock_info)
1341 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps);
1343 const ATOM_PPLIB_CZ_CLOCK_INFO *smu8_clock_info = clock_info;
1345 struct phm_clock_voltage_dependency_table *table =
1346 hwmgr->dyn_state.vddc_dependency_on_sclk;
1347 uint8_t clock_info_index = smu8_clock_info->index;
1349 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1350 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1352 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1353 smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1355 smu8_ps->level = index + 1;
1357 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1358 smu8_ps->levels[index].dsDividerIndex = 5;
1359 smu8_ps->levels[index].ssDividerIndex = 5;
1365 static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1368 unsigned long ret = 0;
1370 result = pp_tables_get_num_of_entries(hwmgr, &ret);
1372 return result ? 0 : ret;
1375 static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1376 unsigned long entry, struct pp_power_state *ps)
1379 struct smu8_power_state *smu8_ps;
1381 ps->hardware.magic = smu8_magic;
1383 smu8_ps = cast_smu8_power_state(&(ps->hardware));
1385 result = pp_tables_get_entry(hwmgr, entry, ps,
1386 smu8_dpm_get_pp_table_entry_callback);
1388 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1389 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1394 static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr)
1396 return sizeof(struct smu8_power_state);
1399 static void smu8_hw_print_display_cfg(
1400 const struct cc6_settings *cc6_settings)
1402 PP_DBG_LOG("New Display Configuration:\n");
1404 PP_DBG_LOG(" cpu_cc6_disable: %d\n",
1405 cc6_settings->cpu_cc6_disable);
1406 PP_DBG_LOG(" cpu_pstate_disable: %d\n",
1407 cc6_settings->cpu_pstate_disable);
1408 PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
1409 cc6_settings->nb_pstate_switch_disable);
1410 PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
1411 cc6_settings->cpu_pstate_separation_time);
1414 static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1416 struct smu8_hwmgr *hw_data = hwmgr->backend;
1419 if (hw_data->cc6_settings.cc6_setting_changed) {
1421 hw_data->cc6_settings.cc6_setting_changed = false;
1423 smu8_hw_print_display_cfg(&hw_data->cc6_settings);
1425 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1426 & PWRMGT_SEPARATION_TIME_MASK)
1427 << PWRMGT_SEPARATION_TIME_SHIFT;
1429 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1430 << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1432 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1433 << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1435 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1438 smum_send_msg_to_smc_with_parameter(hwmgr,
1439 PPSMC_MSG_SetDisplaySizePowerParams,
1447 static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1448 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1450 struct smu8_hwmgr *hw_data = hwmgr->backend;
1452 if (separation_time !=
1453 hw_data->cc6_settings.cpu_pstate_separation_time ||
1454 cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1455 pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1456 pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1458 hw_data->cc6_settings.cc6_setting_changed = true;
1460 hw_data->cc6_settings.cpu_pstate_separation_time =
1462 hw_data->cc6_settings.cpu_cc6_disable =
1464 hw_data->cc6_settings.cpu_pstate_disable =
1466 hw_data->cc6_settings.nb_pstate_switch_disable =
1467 pstate_switch_disable;
1474 static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr,
1475 struct amd_pp_simple_clock_info *info)
1478 const struct phm_clock_voltage_dependency_table *table =
1479 hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1480 const struct phm_clock_and_voltage_limits *limits =
1481 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1483 info->engine_max_clock = limits->sclk;
1484 info->memory_max_clock = limits->mclk;
1486 for (i = table->count - 1; i > 0; i--) {
1487 if (limits->vddc >= table->entries[i].v) {
1488 info->level = table->entries[i].clk;
1495 static int smu8_force_clock_level(struct pp_hwmgr *hwmgr,
1496 enum pp_clock_type type, uint32_t mask)
1500 smum_send_msg_to_smc_with_parameter(hwmgr,
1501 PPSMC_MSG_SetSclkSoftMin,
1503 smum_send_msg_to_smc_with_parameter(hwmgr,
1504 PPSMC_MSG_SetSclkSoftMax,
1514 static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
1515 enum pp_clock_type type, char *buf)
1517 struct smu8_hwmgr *data = hwmgr->backend;
1518 struct phm_clock_voltage_dependency_table *sclk_table =
1519 hwmgr->dyn_state.vddc_dependency_on_sclk;
1520 int i, now, size = 0;
1524 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1526 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1527 TARGET_AND_CURRENT_PROFILE_INDEX,
1530 for (i = 0; i < sclk_table->count; i++)
1531 size += sprintf(buf + size, "%d: %uMhz %s\n",
1532 i, sclk_table->entries[i].clk / 100,
1533 (i == now) ? "*" : "");
1536 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1538 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1539 TARGET_AND_CURRENT_PROFILE_INDEX,
1542 for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--)
1543 size += sprintf(buf + size, "%d: %uMhz %s\n",
1544 SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
1545 (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
1553 static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1554 PHM_PerformanceLevelDesignation designation, uint32_t index,
1555 PHM_PerformanceLevel *level)
1557 const struct smu8_power_state *ps;
1558 struct smu8_hwmgr *data;
1559 uint32_t level_index;
1562 if (level == NULL || hwmgr == NULL || state == NULL)
1565 data = hwmgr->backend;
1566 ps = cast_const_smu8_power_state(state);
1568 level_index = index > ps->level - 1 ? ps->level - 1 : index;
1569 level->coreClock = ps->levels[level_index].engineClock;
1571 if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1572 for (i = 1; i < ps->level; i++) {
1573 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1574 level->coreClock = ps->levels[i].engineClock;
1580 if (level_index == 0)
1581 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1];
1583 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1585 level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1586 level->nonLocalMemoryFreq = 0;
1587 level->nonLocalMemoryWidth = 0;
1592 static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1593 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1595 const struct smu8_power_state *ps = cast_const_smu8_power_state(state);
1597 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1598 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1603 static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1604 struct amd_pp_clocks *clocks)
1606 struct smu8_hwmgr *data = hwmgr->backend;
1608 struct phm_clock_voltage_dependency_table *table;
1610 clocks->count = smu8_get_max_sclk_level(hwmgr);
1612 case amd_pp_disp_clock:
1613 for (i = 0; i < clocks->count; i++)
1614 clocks->clock[i] = data->sys_info.display_clock[i] * 10;
1616 case amd_pp_sys_clock:
1617 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1618 for (i = 0; i < clocks->count; i++)
1619 clocks->clock[i] = table->entries[i].clk * 10;
1621 case amd_pp_mem_clock:
1622 clocks->count = SMU8_NUM_NBPMEMORYCLOCK;
1623 for (i = 0; i < clocks->count; i++)
1624 clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;
1633 static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1635 struct phm_clock_voltage_dependency_table *table =
1636 hwmgr->dyn_state.vddc_dependency_on_sclk;
1637 unsigned long level;
1638 const struct phm_clock_and_voltage_limits *limits =
1639 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1641 if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1644 level = smu8_get_max_sclk_level(hwmgr) - 1;
1646 if (level < table->count)
1647 clocks->engine_max_clock = table->entries[level].clk;
1649 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1651 clocks->memory_max_clock = limits->mclk;
1656 static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1658 int actual_temp = 0;
1659 uint32_t val = cgs_read_ind_register(hwmgr->device,
1660 CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1661 uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1663 if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1664 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1666 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1671 static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1672 void *value, int *size)
1674 struct smu8_hwmgr *data = hwmgr->backend;
1676 struct phm_clock_voltage_dependency_table *table =
1677 hwmgr->dyn_state.vddc_dependency_on_sclk;
1679 struct phm_vce_clock_voltage_dependency_table *vce_table =
1680 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1682 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1683 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1685 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1686 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1687 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1688 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1689 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1690 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1692 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1693 uint16_t vddnb, vddgfx;
1696 /* size must be at least 4 bytes for all sensors */
1702 case AMDGPU_PP_SENSOR_GFX_SCLK:
1703 if (sclk_index < NUM_SCLK_LEVELS) {
1704 sclk = table->entries[sclk_index].clk;
1705 *((uint32_t *)value) = sclk;
1709 case AMDGPU_PP_SENSOR_VDDNB:
1710 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1711 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1712 vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4;
1713 *((uint32_t *)value) = vddnb;
1715 case AMDGPU_PP_SENSOR_VDDGFX:
1716 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1717 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1718 vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4;
1719 *((uint32_t *)value) = vddgfx;
1721 case AMDGPU_PP_SENSOR_UVD_VCLK:
1722 if (!data->uvd_power_gated) {
1723 if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
1726 vclk = uvd_table->entries[uvd_index].vclk;
1727 *((uint32_t *)value) = vclk;
1731 *((uint32_t *)value) = 0;
1733 case AMDGPU_PP_SENSOR_UVD_DCLK:
1734 if (!data->uvd_power_gated) {
1735 if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
1738 dclk = uvd_table->entries[uvd_index].dclk;
1739 *((uint32_t *)value) = dclk;
1743 *((uint32_t *)value) = 0;
1745 case AMDGPU_PP_SENSOR_VCE_ECCLK:
1746 if (!data->vce_power_gated) {
1747 if (vce_index >= SMU8_MAX_HARDWARE_POWERLEVELS) {
1750 ecclk = vce_table->entries[vce_index].ecclk;
1751 *((uint32_t *)value) = ecclk;
1755 *((uint32_t *)value) = 0;
1757 case AMDGPU_PP_SENSOR_GPU_LOAD:
1758 result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
1760 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1761 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1763 activity_percent = 50;
1765 *((uint32_t *)value) = activity_percent;
1767 case AMDGPU_PP_SENSOR_UVD_POWER:
1768 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1770 case AMDGPU_PP_SENSOR_VCE_POWER:
1771 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1773 case AMDGPU_PP_SENSOR_GPU_TEMP:
1774 *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr);
1781 static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
1782 uint32_t virtual_addr_low,
1783 uint32_t virtual_addr_hi,
1784 uint32_t mc_addr_low,
1785 uint32_t mc_addr_hi,
1788 smum_send_msg_to_smc_with_parameter(hwmgr,
1789 PPSMC_MSG_DramAddrHiVirtual,
1791 smum_send_msg_to_smc_with_parameter(hwmgr,
1792 PPSMC_MSG_DramAddrLoVirtual,
1794 smum_send_msg_to_smc_with_parameter(hwmgr,
1795 PPSMC_MSG_DramAddrHiPhysical,
1797 smum_send_msg_to_smc_with_parameter(hwmgr,
1798 PPSMC_MSG_DramAddrLoPhysical,
1801 smum_send_msg_to_smc_with_parameter(hwmgr,
1802 PPSMC_MSG_DramBufferSize,
1807 static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
1808 struct PP_TemperatureRange *thermal_data)
1810 struct smu8_hwmgr *data = hwmgr->backend;
1812 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
1814 thermal_data->max = (data->thermal_auto_throttling_treshold +
1815 data->sys_info.htc_hyst_lmt) *
1816 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1821 static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
1823 struct smu8_hwmgr *data = hwmgr->backend;
1824 uint32_t dpm_features = 0;
1827 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1828 PHM_PlatformCaps_UVDDPM)) {
1829 data->dpm_flags |= DPMFlags_UVD_Enabled;
1830 dpm_features |= UVD_DPM_MASK;
1831 smum_send_msg_to_smc_with_parameter(hwmgr,
1832 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
1834 dpm_features |= UVD_DPM_MASK;
1835 data->dpm_flags &= ~DPMFlags_UVD_Enabled;
1836 smum_send_msg_to_smc_with_parameter(hwmgr,
1837 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
1842 int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1844 struct smu8_hwmgr *data = hwmgr->backend;
1845 struct phm_uvd_clock_voltage_dependency_table *ptable =
1846 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1849 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1850 if (PP_CAP(PHM_PlatformCaps_StablePState) ||
1851 hwmgr->en_umd_pstate) {
1852 data->uvd_dpm.hard_min_clk =
1853 ptable->entries[ptable->count - 1].vclk;
1855 smum_send_msg_to_smc_with_parameter(hwmgr,
1856 PPSMC_MSG_SetUvdHardMin,
1857 smu8_get_uvd_level(hwmgr,
1858 data->uvd_dpm.hard_min_clk,
1859 PPSMC_MSG_SetUvdHardMin));
1861 smu8_enable_disable_uvd_dpm(hwmgr, true);
1863 smu8_enable_disable_uvd_dpm(hwmgr, true);
1866 smu8_enable_disable_uvd_dpm(hwmgr, false);
1872 static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1874 struct smu8_hwmgr *data = hwmgr->backend;
1875 uint32_t dpm_features = 0;
1877 if (enable && phm_cap_enabled(
1878 hwmgr->platform_descriptor.platformCaps,
1879 PHM_PlatformCaps_VCEDPM)) {
1880 data->dpm_flags |= DPMFlags_VCE_Enabled;
1881 dpm_features |= VCE_DPM_MASK;
1882 smum_send_msg_to_smc_with_parameter(hwmgr,
1883 PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
1885 dpm_features |= VCE_DPM_MASK;
1886 data->dpm_flags &= ~DPMFlags_VCE_Enabled;
1887 smum_send_msg_to_smc_with_parameter(hwmgr,
1888 PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
1895 static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
1897 struct smu8_hwmgr *data = hwmgr->backend;
1899 if (data->acp_power_gated == bgate)
1903 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
1905 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON);
1908 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
1910 struct smu8_hwmgr *data = hwmgr->backend;
1912 data->uvd_power_gated = bgate;
1915 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1916 AMD_IP_BLOCK_TYPE_UVD,
1918 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
1919 AMD_IP_BLOCK_TYPE_UVD,
1921 smu8_dpm_update_uvd_dpm(hwmgr, true);
1922 smu8_dpm_powerdown_uvd(hwmgr);
1924 smu8_dpm_powerup_uvd(hwmgr);
1925 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
1926 AMD_IP_BLOCK_TYPE_UVD,
1927 AMD_CG_STATE_UNGATE);
1928 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1929 AMD_IP_BLOCK_TYPE_UVD,
1930 AMD_PG_STATE_UNGATE);
1931 smu8_dpm_update_uvd_dpm(hwmgr, false);
1936 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
1938 struct smu8_hwmgr *data = hwmgr->backend;
1941 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1942 AMD_IP_BLOCK_TYPE_VCE,
1944 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
1945 AMD_IP_BLOCK_TYPE_VCE,
1947 smu8_enable_disable_vce_dpm(hwmgr, false);
1948 smu8_dpm_powerdown_vce(hwmgr);
1949 data->vce_power_gated = true;
1951 smu8_dpm_powerup_vce(hwmgr);
1952 data->vce_power_gated = false;
1953 amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
1954 AMD_IP_BLOCK_TYPE_VCE,
1955 AMD_CG_STATE_UNGATE);
1956 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1957 AMD_IP_BLOCK_TYPE_VCE,
1958 AMD_PG_STATE_UNGATE);
1959 smu8_dpm_update_vce_dpm(hwmgr);
1960 smu8_enable_disable_vce_dpm(hwmgr, true);
1964 static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
1965 .backend_init = smu8_hwmgr_backend_init,
1966 .backend_fini = smu8_hwmgr_backend_fini,
1967 .apply_state_adjust_rules = smu8_apply_state_adjust_rules,
1968 .force_dpm_level = smu8_dpm_force_dpm_level,
1969 .get_power_state_size = smu8_get_power_state_size,
1970 .powerdown_uvd = smu8_dpm_powerdown_uvd,
1971 .powergate_uvd = smu8_dpm_powergate_uvd,
1972 .powergate_vce = smu8_dpm_powergate_vce,
1973 .powergate_acp = smu8_dpm_powergate_acp,
1974 .get_mclk = smu8_dpm_get_mclk,
1975 .get_sclk = smu8_dpm_get_sclk,
1976 .patch_boot_state = smu8_dpm_patch_boot_state,
1977 .get_pp_table_entry = smu8_dpm_get_pp_table_entry,
1978 .get_num_of_pp_table_entries = smu8_dpm_get_num_of_pp_table_entries,
1979 .set_cpu_power_state = smu8_set_cpu_power_state,
1980 .store_cc6_data = smu8_store_cc6_data,
1981 .force_clock_level = smu8_force_clock_level,
1982 .print_clock_levels = smu8_print_clock_levels,
1983 .get_dal_power_level = smu8_get_dal_power_level,
1984 .get_performance_level = smu8_get_performance_level,
1985 .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks,
1986 .get_clock_by_type = smu8_get_clock_by_type,
1987 .get_max_high_clocks = smu8_get_max_high_clocks,
1988 .read_sensor = smu8_read_sensor,
1989 .power_off_asic = smu8_power_off_asic,
1990 .asic_setup = smu8_setup_asic_task,
1991 .dynamic_state_management_enable = smu8_enable_dpm_tasks,
1992 .power_state_set = smu8_set_power_state_tasks,
1993 .dynamic_state_management_disable = smu8_disable_dpm_tasks,
1994 .notify_cac_buffer_info = smu8_notify_cac_buffer_info,
1995 .get_thermal_temperature_range = smu8_get_thermal_temperature_range,
1998 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr)
2000 hwmgr->hwmgr_func = &smu8_hwmgr_funcs;
2001 hwmgr->pptable_func = &pptable_funcs;