drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_smumgr.h"
  43 #include "vega10_processpptables.h"
  44 #include "vega10_pptable.h"
  45 #include "vega10_thermal.h"
  46 #include "pp_debug.h"
  47 #include "amd_pcie_helpers.h"
  48 #include "ppinterrupt.h"
  49 #include "pp_overdriver.h"
  50 #include "pp_thermal.h"
  51
  52 #include "smuio/smuio_9_0_offset.h"
  53 #include "smuio/smuio_9_0_sh_mask.h"
  54
  55 #define HBM_MEMORY_CHANNEL_WIDTH    128
  56
  57 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  58
  59 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  60 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  61
  62 //DF_CS_AON0_DramBaseAddress0
  63 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  64 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  65 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  66 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  67 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  68 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  69 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  71 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  72 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  73
  74 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  75
  76 struct vega10_power_state *cast_phw_vega10_power_state(
  77                                   struct pp_hw_power_state *hw_ps)
  78 {
  79         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  80                                 "Invalid Powerstate Type!",
  81                                  return NULL;);
  82
  83         return (struct vega10_power_state *)hw_ps;
  84 }
  85
  86 const struct vega10_power_state *cast_const_phw_vega10_power_state(
  87                                  const struct pp_hw_power_state *hw_ps)
  88 {
  89         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  90                                 "Invalid Powerstate Type!",
  91                                  return NULL;);
  92
  93         return (const struct vega10_power_state *)hw_ps;
  94 }
  95
  96 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
  97 {
  98         struct vega10_hwmgr *data = hwmgr->backend;
  99
 100         data->registry_data.sclk_dpm_key_disabled =
 101                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 102         data->registry_data.socclk_dpm_key_disabled =
 103                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 104         data->registry_data.mclk_dpm_key_disabled =
 105                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 106         data->registry_data.pcie_dpm_key_disabled =
 107                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 108
 109         data->registry_data.dcefclk_dpm_key_disabled =
 110                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 111
 112         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 113                 data->registry_data.power_containment_support = 1;
 114                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 115                 data->registry_data.enable_tdc_limit_feature = 1;
 116         }
 117
 118         data->registry_data.clock_stretcher_support =
 119                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 120
 121         data->registry_data.ulv_support =
 122                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 123
 124         data->registry_data.sclk_deep_sleep_support =
 125                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 126
 127         data->registry_data.disable_water_mark = 0;
 128
 129         data->registry_data.fan_control_support = 1;
 130         data->registry_data.thermal_support = 1;
 131         data->registry_data.fw_ctf_enabled = 1;
 132
 133         data->registry_data.avfs_support =
 134                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 135         data->registry_data.led_dpm_enabled = 1;
 136
 137         data->registry_data.vr0hot_enabled = 1;
 138         data->registry_data.vr1hot_enabled = 1;
 139         data->registry_data.regulator_hot_gpio_support = 1;
 140
 141         data->registry_data.didt_support = 1;
 142         if (data->registry_data.didt_support) {
 143                 data->registry_data.didt_mode = 6;
 144                 data->registry_data.sq_ramping_support = 1;
 145                 data->registry_data.db_ramping_support = 0;
 146                 data->registry_data.td_ramping_support = 0;
 147                 data->registry_data.tcp_ramping_support = 0;
 148                 data->registry_data.dbr_ramping_support = 0;
 149                 data->registry_data.edc_didt_support = 1;
 150                 data->registry_data.gc_didt_support = 0;
 151                 data->registry_data.psm_didt_support = 0;
 152         }
 153
 154         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 155         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 156         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 157         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 158         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 159         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 160         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 161         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 162         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 163         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 164         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 165         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 166         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 167
 168         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 169         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 170         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 171         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 172 }
 173
 174 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 175 {
 176         struct vega10_hwmgr *data = hwmgr->backend;
 177         struct phm_ppt_v2_information *table_info =
 178                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 179         struct amdgpu_device *adev = hwmgr->adev;
 180
 181         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 182                         PHM_PlatformCaps_SclkDeepSleep);
 183
 184         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 185                         PHM_PlatformCaps_DynamicPatchPowerState);
 186
 187         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 188                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 189                                 PHM_PlatformCaps_ControlVDDCI);
 190
 191         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 192                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 193
 194         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 195                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                                 PHM_PlatformCaps_UVDPowerGating);
 197
 198         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 199                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 200                                 PHM_PlatformCaps_VCEPowerGating);
 201
 202         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 203                         PHM_PlatformCaps_UnTabledHardwareInterface);
 204
 205         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 206                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 207
 208         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 209                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 210
 211         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 212                                 PHM_PlatformCaps_DynamicPowerManagement);
 213
 214         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 215                         PHM_PlatformCaps_SMC);
 216
 217         /* power tune caps */
 218         /* assume disabled */
 219         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 220                         PHM_PlatformCaps_PowerContainment);
 221         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_DiDtSupport);
 223         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_SQRamping);
 225         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_DBRamping);
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_TDRamping);
 229         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 230                         PHM_PlatformCaps_TCPRamping);
 231         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_DBRRamping);
 233         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_DiDtEDCEnable);
 235         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 236                         PHM_PlatformCaps_GCEDC);
 237         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 238                         PHM_PlatformCaps_PSM);
 239
 240         if (data->registry_data.didt_support) {
 241                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 242                 if (data->registry_data.sq_ramping_support)
 243                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 244                 if (data->registry_data.db_ramping_support)
 245                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 246                 if (data->registry_data.td_ramping_support)
 247                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 248                 if (data->registry_data.tcp_ramping_support)
 249                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 250                 if (data->registry_data.dbr_ramping_support)
 251                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 252                 if (data->registry_data.edc_didt_support)
 253                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 254                 if (data->registry_data.gc_didt_support)
 255                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 256                 if (data->registry_data.psm_didt_support)
 257                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 258         }
 259
 260         if (data->registry_data.power_containment_support)
 261                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 262                                 PHM_PlatformCaps_PowerContainment);
 263         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 264                         PHM_PlatformCaps_CAC);
 265
 266         if (table_info->tdp_table->usClockStretchAmount &&
 267                         data->registry_data.clock_stretcher_support)
 268                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 269                                 PHM_PlatformCaps_ClockStretcher);
 270
 271         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 272                         PHM_PlatformCaps_RegulatorHot);
 273         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 274                         PHM_PlatformCaps_AutomaticDCTransition);
 275
 276         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 277                         PHM_PlatformCaps_UVDDPM);
 278         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 279                         PHM_PlatformCaps_VCEDPM);
 280
 281         return 0;
 282 }
 283
 284 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 285 {
 286         struct vega10_hwmgr *data = hwmgr->backend;
 287         struct phm_ppt_v2_information *table_info =
 288                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 289         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 290         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 291         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 292         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 293         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 294         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 295         uint32_t i;
 296         int result;
 297
 298         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 299         if (!result) {
 300                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 301                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 302         }
 303
 304         od_lookup_table = &odn_table->vddc_lookup_table;
 305         vddc_lookup_table = table_info->vddc_lookup_table;
 306
 307         for (i = 0; i < vddc_lookup_table->count; i++)
 308                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 309
 310         od_lookup_table->count = vddc_lookup_table->count;
 311
 312         dep_table[0] = table_info->vdd_dep_on_sclk;
 313         dep_table[1] = table_info->vdd_dep_on_mclk;
 314         dep_table[2] = table_info->vdd_dep_on_socclk;
 315         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 316         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 317         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 318
 319         for (i = 0; i < 3; i++)
 320                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 321
 322         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 323                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 324         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 325                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 326
 327         i = od_table[2]->count - 1;
 328         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 329                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 330                                         od_table[2]->entries[i].clk;
 331         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 332                                         odn_table->max_vddc :
 333                                         od_table[2]->entries[i].vddc;
 334
 335         return 0;
 336 }
 337
 338 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 339 {
 340         struct vega10_hwmgr *data = hwmgr->backend;
 341         int i;
 342         uint32_t sub_vendor_id, hw_revision;
 343         struct amdgpu_device *adev = hwmgr->adev;
 344
 345         vega10_initialize_power_tune_defaults(hwmgr);
 346
 347         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 348                 data->smu_features[i].smu_feature_id = 0xffff;
 349                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 350                 data->smu_features[i].enabled = false;
 351                 data->smu_features[i].supported = false;
 352         }
 353
 354         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 355                         FEATURE_DPM_PREFETCHER_BIT;
 356         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 357                         FEATURE_DPM_GFXCLK_BIT;
 358         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 359                         FEATURE_DPM_UCLK_BIT;
 360         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 361                         FEATURE_DPM_SOCCLK_BIT;
 362         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 363                         FEATURE_DPM_UVD_BIT;
 364         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 365                         FEATURE_DPM_VCE_BIT;
 366         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 367                         FEATURE_DPM_MP0CLK_BIT;
 368         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 369                         FEATURE_DPM_LINK_BIT;
 370         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 371                         FEATURE_DPM_DCEFCLK_BIT;
 372         data->smu_features[GNLD_ULV].smu_feature_id =
 373                         FEATURE_ULV_BIT;
 374         data->smu_features[GNLD_AVFS].smu_feature_id =
 375                         FEATURE_AVFS_BIT;
 376         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 377                         FEATURE_DS_GFXCLK_BIT;
 378         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 379                         FEATURE_DS_SOCCLK_BIT;
 380         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 381                         FEATURE_DS_LCLK_BIT;
 382         data->smu_features[GNLD_PPT].smu_feature_id =
 383                         FEATURE_PPT_BIT;
 384         data->smu_features[GNLD_TDC].smu_feature_id =
 385                         FEATURE_TDC_BIT;
 386         data->smu_features[GNLD_THERMAL].smu_feature_id =
 387                         FEATURE_THERMAL_BIT;
 388         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 389                         FEATURE_GFX_PER_CU_CG_BIT;
 390         data->smu_features[GNLD_RM].smu_feature_id =
 391                         FEATURE_RM_BIT;
 392         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 393                         FEATURE_DS_DCEFCLK_BIT;
 394         data->smu_features[GNLD_ACDC].smu_feature_id =
 395                         FEATURE_ACDC_BIT;
 396         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 397                         FEATURE_VR0HOT_BIT;
 398         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 399                         FEATURE_VR1HOT_BIT;
 400         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 401                         FEATURE_FW_CTF_BIT;
 402         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 403                         FEATURE_LED_DISPLAY_BIT;
 404         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 405                         FEATURE_FAN_CONTROL_BIT;
 406         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 407         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 408         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 409
 410         if (!data->registry_data.prefetcher_dpm_key_disabled)
 411                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 412
 413         if (!data->registry_data.sclk_dpm_key_disabled)
 414                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 415
 416         if (!data->registry_data.mclk_dpm_key_disabled)
 417                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 418
 419         if (!data->registry_data.socclk_dpm_key_disabled)
 420                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 421
 422         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 423                 data->smu_features[GNLD_DPM_UVD].supported = true;
 424
 425         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 426                 data->smu_features[GNLD_DPM_VCE].supported = true;
 427
 428         if (!data->registry_data.pcie_dpm_key_disabled)
 429                 data->smu_features[GNLD_DPM_LINK].supported = true;
 430
 431         if (!data->registry_data.dcefclk_dpm_key_disabled)
 432                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 433
 434         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 435             data->registry_data.sclk_deep_sleep_support) {
 436                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 437                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 438                 data->smu_features[GNLD_DS_LCLK].supported = true;
 439                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 440         }
 441
 442         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 443                 data->smu_features[GNLD_PPT].supported = true;
 444
 445         if (data->registry_data.enable_tdc_limit_feature)
 446                 data->smu_features[GNLD_TDC].supported = true;
 447
 448         if (data->registry_data.thermal_support)
 449                 data->smu_features[GNLD_THERMAL].supported = true;
 450
 451         if (data->registry_data.fan_control_support)
 452                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 453
 454         if (data->registry_data.fw_ctf_enabled)
 455                 data->smu_features[GNLD_FW_CTF].supported = true;
 456
 457         if (data->registry_data.avfs_support)
 458                 data->smu_features[GNLD_AVFS].supported = true;
 459
 460         if (data->registry_data.led_dpm_enabled)
 461                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 462
 463         if (data->registry_data.vr1hot_enabled)
 464                 data->smu_features[GNLD_VR1HOT].supported = true;
 465
 466         if (data->registry_data.vr0hot_enabled)
 467                 data->smu_features[GNLD_VR0HOT].supported = true;
 468
 469         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 470         hwmgr->smu_version = smum_get_argument(hwmgr);
 471                 /* ACG firmware has major version 5 */
 472         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 473                 data->smu_features[GNLD_ACG].supported = true;
 474         if (data->registry_data.didt_support)
 475                 data->smu_features[GNLD_DIDT].supported = true;
 476
 477         hw_revision = adev->pdev->revision;
 478         sub_vendor_id = adev->pdev->subsystem_vendor;
 479
 480         if ((hwmgr->chip_id == 0x6862 ||
 481                 hwmgr->chip_id == 0x6861 ||
 482                 hwmgr->chip_id == 0x6868) &&
 483                 (hw_revision == 0) &&
 484                 (sub_vendor_id != 0x1002))
 485                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 486 }
 487
 488 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 489 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 490         phm_ppt_v1_voltage_lookup_table *lookup_table,
 491         uint16_t virtual_voltage_id, int32_t *socclk)
 492 {
 493         uint8_t entry_id;
 494         uint8_t voltage_id;
 495         struct phm_ppt_v2_information *table_info =
 496                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 497
 498         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 499                         "Lookup table is empty",
 500                         return -EINVAL);
 501
 502         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 503         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 504                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 505                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 506                         break;
 507         }
 508
 509         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 510                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 511                         return -EINVAL);
 512
 513         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 514
 515         return 0;
 516 }
 517
 518 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 519 /**
 520 * Get Leakage VDDC based on leakage ID.
 521 *
 522 * @param    hwmgr  the address of the powerplay hardware manager.
 523 * @return   always 0.
 524 */
 525 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 526 {
 527         struct vega10_hwmgr *data = hwmgr->backend;
 528         uint16_t vv_id;
 529         uint32_t vddc = 0;
 530         uint16_t i, j;
 531         uint32_t sclk = 0;
 532         struct phm_ppt_v2_information *table_info =
 533                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 534         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 535                         table_info->vdd_dep_on_socclk;
 536         int result;
 537
 538         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 539                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 540
 541                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 542                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 543                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 544                                 for (j = 1; j < socclk_table->count; j++) {
 545                                         if (socclk_table->entries[j].clk == sclk &&
 546                                                         socclk_table->entries[j].cks_enable == 0) {
 547                                                 sclk += 5000;
 548                                                 break;
 549                                         }
 550                                 }
 551                         }
 552
 553                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 554                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 555                                         "Error retrieving EVV voltage value!",
 556                                         continue);
 557
 558
 559                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 560                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 561                                         "Invalid VDDC value", result = -EINVAL;);
 562
 563                         /* the voltage should not be zero nor equal to leakage ID */
 564                         if (vddc != 0 && vddc != vv_id) {
 565                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 566                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 567                                 data->vddc_leakage.count++;
 568                         }
 569                 }
 570         }
 571
 572         return 0;
 573 }
 574
 575 /**
 576  * Change virtual leakage voltage to actual value.
 577  *
 578  * @param     hwmgr  the address of the powerplay hardware manager.
 579  * @param     pointer to changing voltage
 580  * @param     pointer to leakage table
 581  */
 582 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 583                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 584 {
 585         uint32_t index;
 586
 587         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 588         for (index = 0; index < leakage_table->count; index++) {
 589                 /* if this voltage matches a leakage voltage ID */
 590                 /* patch with actual leakage voltage */
 591                 if (leakage_table->leakage_id[index] == *voltage) {
 592                         *voltage = leakage_table->actual_voltage[index];
 593                         break;
 594                 }
 595         }
 596
 597         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 598                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 599 }
 600
 601 /**
 602 * Patch voltage lookup table by EVV leakages.
 603 *
 604 * @param     hwmgr  the address of the powerplay hardware manager.
 605 * @param     pointer to voltage lookup table
 606 * @param     pointer to leakage table
 607 * @return     always 0
 608 */
 609 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 610                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 611                 struct vega10_leakage_voltage *leakage_table)
 612 {
 613         uint32_t i;
 614
 615         for (i = 0; i < lookup_table->count; i++)
 616                 vega10_patch_with_vdd_leakage(hwmgr,
 617                                 &lookup_table->entries[i].us_vdd, leakage_table);
 618
 619         return 0;
 620 }
 621
 622 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 623                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 624                 uint16_t *vddc)
 625 {
 626         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 627
 628         return 0;
 629 }
 630 #endif
 631
 632 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 633                 struct pp_hwmgr *hwmgr)
 634 {
 635         uint8_t entry_id, voltage_id;
 636         unsigned i;
 637         struct phm_ppt_v2_information *table_info =
 638                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 639         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 640                         table_info->mm_dep_table;
 641         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 642                         table_info->vdd_dep_on_mclk;
 643
 644         for (i = 0; i < 6; i++) {
 645                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 646                 switch (i) {
 647                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 648                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 649                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 650                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 651                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 652                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 653                 }
 654
 655                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 656                         voltage_id = vdt->entries[entry_id].vddInd;
 657                         vdt->entries[entry_id].vddc =
 658                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 659                 }
 660         }
 661
 662         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 663                 voltage_id = mm_table->entries[entry_id].vddcInd;
 664                 mm_table->entries[entry_id].vddc =
 665                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 666         }
 667
 668         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 669                 voltage_id = mclk_table->entries[entry_id].vddInd;
 670                 mclk_table->entries[entry_id].vddc =
 671                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 672                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 673                 mclk_table->entries[entry_id].vddci =
 674                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 675                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 676                 mclk_table->entries[entry_id].mvdd =
 677                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 678         }
 679
 680
 681         return 0;
 682
 683 }
 684
 685 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 686                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 687 {
 688         uint32_t table_size, i, j;
 689         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 690
 691         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 692                 "Lookup table is empty", return -EINVAL);
 693
 694         table_size = lookup_table->count;
 695
 696         /* Sorting voltages */
 697         for (i = 0; i < table_size - 1; i++) {
 698                 for (j = i + 1; j > 0; j--) {
 699                         if (lookup_table->entries[j].us_vdd <
 700                                         lookup_table->entries[j - 1].us_vdd) {
 701                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 702                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 703                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 704                         }
 705                 }
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 712 {
 713         int result = 0;
 714         int tmp_result;
 715         struct phm_ppt_v2_information *table_info =
 716                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 717 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 718         struct vega10_hwmgr *data = hwmgr->backend;
 719
 720         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 721                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 722         if (tmp_result)
 723                 result = tmp_result;
 724
 725         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 726                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 727         if (tmp_result)
 728                 result = tmp_result;
 729 #endif
 730
 731         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 732         if (tmp_result)
 733                 result = tmp_result;
 734
 735         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 736         if (tmp_result)
 737                 result = tmp_result;
 738
 739         return result;
 740 }
 741
 742 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 743 {
 744         struct phm_ppt_v2_information *table_info =
 745                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 746         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 747                         table_info->vdd_dep_on_socclk;
 748         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 749                         table_info->vdd_dep_on_mclk;
 750
 751         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 752                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 753         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 754                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 755
 756         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 757                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 758         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 759                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 760
 761         table_info->max_clock_voltage_on_ac.sclk =
 762                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 763         table_info->max_clock_voltage_on_ac.mclk =
 764                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 765         table_info->max_clock_voltage_on_ac.vddc =
 766                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 767         table_info->max_clock_voltage_on_ac.vddci =
 768                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 769
 770         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 771                 table_info->max_clock_voltage_on_ac.sclk;
 772         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 773                 table_info->max_clock_voltage_on_ac.mclk;
 774         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 775                 table_info->max_clock_voltage_on_ac.vddc;
 776         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 777                 table_info->max_clock_voltage_on_ac.vddci;
 778
 779         return 0;
 780 }
 781
 782 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 783 {
 784         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 785         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 786
 787         kfree(hwmgr->backend);
 788         hwmgr->backend = NULL;
 789
 790         return 0;
 791 }
 792
 793 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 794 {
 795         int result = 0;
 796         struct vega10_hwmgr *data;
 797         uint32_t config_telemetry = 0;
 798         struct pp_atomfwctrl_voltage_table vol_table;
 799         struct amdgpu_device *adev = hwmgr->adev;
 800
 801         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 802         if (data == NULL)
 803                 return -ENOMEM;
 804
 805         hwmgr->backend = data;
 806
 807         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
 808         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 809         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 810
 811         vega10_set_default_registry_data(hwmgr);
 812         data->disable_dpm_mask = 0xff;
 813
 814         /* need to set voltage control types before EVV patching */
 815         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 816         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 817         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 818
 819         /* VDDCR_SOC */
 820         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 821                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 822                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 823                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 824                                 &vol_table)) {
 825                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 826                                         (vol_table.telemetry_offset & 0xff);
 827                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 828                 }
 829         } else {
 830                 kfree(hwmgr->backend);
 831                 hwmgr->backend = NULL;
 832                 PP_ASSERT_WITH_CODE(false,
 833                                 "VDDCR_SOC is not SVID2!",
 834                                 return -1);
 835         }
 836
 837         /* MVDDC */
 838         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 839                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 840                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 841                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 842                                 &vol_table)) {
 843                         config_telemetry |=
 844                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 845                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 846                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 847                 }
 848         }
 849
 850          /* VDDCI_MEM */
 851         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 852                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 853                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 854                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 855         }
 856
 857         data->config_telemetry = config_telemetry;
 858
 859         vega10_set_features_platform_caps(hwmgr);
 860
 861         vega10_init_dpm_defaults(hwmgr);
 862
 863 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 864         /* Get leakage voltage based on leakage ID. */
 865         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 866                         "Get EVV Voltage Failed.  Abort Driver loading!",
 867                         return -1);
 868 #endif
 869
 870         /* Patch our voltage dependency table with actual leakage voltage
 871          * We need to perform leakage translation before it's used by other functions
 872          */
 873         vega10_complete_dependency_tables(hwmgr);
 874
 875         /* Parse pptable data read from VBIOS */
 876         vega10_set_private_data_based_on_pptable(hwmgr);
 877
 878         data->is_tlu_enabled = false;
 879
 880         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 881                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 882         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 883         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 884
 885         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 886         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 887         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 888         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 889
 890         data->total_active_cus = adev->gfx.cu_info.number;
 891         /* Setup default Overdrive Fan control settings */
 892         data->odn_fan_table.target_fan_speed =
 893                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 894         data->odn_fan_table.target_temperature =
 895                         hwmgr->thermal_controller.
 896                         advanceFanControlParameters.ucTargetTemperature;
 897         data->odn_fan_table.min_performance_clock =
 898                         hwmgr->thermal_controller.advanceFanControlParameters.
 899                         ulMinFanSCLKAcousticLimit;
 900         data->odn_fan_table.min_fan_limit =
 901                         hwmgr->thermal_controller.
 902                         advanceFanControlParameters.usFanPWMMinLimit *
 903                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 904
 905         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 906                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 907                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 908         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 909                         "Mem Channel Index Exceeded maximum!",
 910                         return -EINVAL);
 911
 912         return result;
 913 }
 914
 915 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 916 {
 917         struct vega10_hwmgr *data = hwmgr->backend;
 918
 919         data->low_sclk_interrupt_threshold = 0;
 920
 921         return 0;
 922 }
 923
 924 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 925 {
 926         struct vega10_hwmgr *data = hwmgr->backend;
 927         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 928
 929         struct pp_atomfwctrl_voltage_table table;
 930         uint8_t i, j;
 931         uint32_t mask = 0;
 932         uint32_t tmp;
 933         int32_t ret = 0;
 934
 935         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 936                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 937
 938         if (!ret) {
 939                 tmp = table.mask_low;
 940                 for (i = 0, j = 0; i < 32; i++) {
 941                         if (tmp & 1) {
 942                                 mask |= (uint32_t)(i << (8 * j));
 943                                 if (++j >= 3)
 944                                         break;
 945                         }
 946                         tmp >>= 1;
 947                 }
 948         }
 949
 950         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 951         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 952         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 953         return 0;
 954 }
 955
 956 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 957 {
 958         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 959                         "Failed to init sclk threshold!",
 960                         return -EINVAL);
 961
 962         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 963                         "Failed to set up led dpm config!",
 964                         return -EINVAL);
 965
 966         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
 967
 968         return 0;
 969 }
 970
 971 /**
 972 * Remove repeated voltage values and create table with unique values.
 973 *
 974 * @param    hwmgr  the address of the powerplay hardware manager.
 975 * @param    vol_table  the pointer to changing voltage table
 976 * @return    0 in success
 977 */
 978
 979 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
 980                 struct pp_atomfwctrl_voltage_table *vol_table)
 981 {
 982         uint32_t i, j;
 983         uint16_t vvalue;
 984         bool found = false;
 985         struct pp_atomfwctrl_voltage_table *table;
 986
 987         PP_ASSERT_WITH_CODE(vol_table,
 988                         "Voltage Table empty.", return -EINVAL);
 989         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
 990                         GFP_KERNEL);
 991
 992         if (!table)
 993                 return -ENOMEM;
 994
 995         table->mask_low = vol_table->mask_low;
 996         table->phase_delay = vol_table->phase_delay;
 997
 998         for (i = 0; i < vol_table->count; i++) {
 999                 vvalue = vol_table->entries[i].value;
1000                 found = false;
1001
1002                 for (j = 0; j < table->count; j++) {
1003                         if (vvalue == table->entries[j].value) {
1004                                 found = true;
1005                                 break;
1006                         }
1007                 }
1008
1009                 if (!found) {
1010                         table->entries[table->count].value = vvalue;
1011                         table->entries[table->count].smio_low =
1012                                         vol_table->entries[i].smio_low;
1013                         table->count++;
1014                 }
1015         }
1016
1017         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1018         kfree(table);
1019
1020         return 0;
1021 }
1022
1023 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1024                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1025                 struct pp_atomfwctrl_voltage_table *vol_table)
1026 {
1027         int i;
1028
1029         PP_ASSERT_WITH_CODE(dep_table->count,
1030                         "Voltage Dependency Table empty.",
1031                         return -EINVAL);
1032
1033         vol_table->mask_low = 0;
1034         vol_table->phase_delay = 0;
1035         vol_table->count = dep_table->count;
1036
1037         for (i = 0; i < vol_table->count; i++) {
1038                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1039                 vol_table->entries[i].smio_low = 0;
1040         }
1041
1042         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1043                         vol_table),
1044                         "Failed to trim MVDD Table!",
1045                         return -1);
1046
1047         return 0;
1048 }
1049
1050 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1051                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1052                 struct pp_atomfwctrl_voltage_table *vol_table)
1053 {
1054         uint32_t i;
1055
1056         PP_ASSERT_WITH_CODE(dep_table->count,
1057                         "Voltage Dependency Table empty.",
1058                         return -EINVAL);
1059
1060         vol_table->mask_low = 0;
1061         vol_table->phase_delay = 0;
1062         vol_table->count = dep_table->count;
1063
1064         for (i = 0; i < dep_table->count; i++) {
1065                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1066                 vol_table->entries[i].smio_low = 0;
1067         }
1068
1069         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1070                         "Failed to trim VDDCI table.",
1071                         return -1);
1072
1073         return 0;
1074 }
1075
1076 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1077                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1078                 struct pp_atomfwctrl_voltage_table *vol_table)
1079 {
1080         int i;
1081
1082         PP_ASSERT_WITH_CODE(dep_table->count,
1083                         "Voltage Dependency Table empty.",
1084                         return -EINVAL);
1085
1086         vol_table->mask_low = 0;
1087         vol_table->phase_delay = 0;
1088         vol_table->count = dep_table->count;
1089
1090         for (i = 0; i < vol_table->count; i++) {
1091                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1092                 vol_table->entries[i].smio_low = 0;
1093         }
1094
1095         return 0;
1096 }
1097
1098 /* ---- Voltage Tables ----
1099  * If the voltage table would be bigger than
1100  * what will fit into the state table on
1101  * the SMC keep only the higher entries.
1102  */
1103 static void vega10_trim_voltage_table_to_fit_state_table(
1104                 struct pp_hwmgr *hwmgr,
1105                 uint32_t max_vol_steps,
1106                 struct pp_atomfwctrl_voltage_table *vol_table)
1107 {
1108         unsigned int i, diff;
1109
1110         if (vol_table->count <= max_vol_steps)
1111                 return;
1112
1113         diff = vol_table->count - max_vol_steps;
1114
1115         for (i = 0; i < max_vol_steps; i++)
1116                 vol_table->entries[i] = vol_table->entries[i + diff];
1117
1118         vol_table->count = max_vol_steps;
1119 }
1120
1121 /**
1122 * Create Voltage Tables.
1123 *
1124 * @param    hwmgr  the address of the powerplay hardware manager.
1125 * @return   always 0
1126 */
1127 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1128 {
1129         struct vega10_hwmgr *data = hwmgr->backend;
1130         struct phm_ppt_v2_information *table_info =
1131                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1132         int result;
1133
1134         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1135                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1136                 result = vega10_get_mvdd_voltage_table(hwmgr,
1137                                 table_info->vdd_dep_on_mclk,
1138                                 &(data->mvdd_voltage_table));
1139                 PP_ASSERT_WITH_CODE(!result,
1140                                 "Failed to retrieve MVDDC table!",
1141                                 return result);
1142         }
1143
1144         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1145                 result = vega10_get_vddci_voltage_table(hwmgr,
1146                                 table_info->vdd_dep_on_mclk,
1147                                 &(data->vddci_voltage_table));
1148                 PP_ASSERT_WITH_CODE(!result,
1149                                 "Failed to retrieve VDDCI_MEM table!",
1150                                 return result);
1151         }
1152
1153         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1154                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1155                 result = vega10_get_vdd_voltage_table(hwmgr,
1156                                 table_info->vdd_dep_on_sclk,
1157                                 &(data->vddc_voltage_table));
1158                 PP_ASSERT_WITH_CODE(!result,
1159                                 "Failed to retrieve VDDCR_SOC table!",
1160                                 return result);
1161         }
1162
1163         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1164                         "Too many voltage values for VDDC. Trimming to fit state table.",
1165                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1166                                         16, &(data->vddc_voltage_table)));
1167
1168         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1169                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1170                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1171                                         16, &(data->vddci_voltage_table)));
1172
1173         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1174                         "Too many voltage values for MVDD. Trimming to fit state table.",
1175                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1176                                         16, &(data->mvdd_voltage_table)));
1177
1178
1179         return 0;
1180 }
1181
1182 /*
1183  * @fn vega10_init_dpm_state
1184  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1185  *
1186  * @param    dpm_state - the address of the DPM Table to initiailize.
1187  * @return   None.
1188  */
1189 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1190 {
1191         dpm_state->soft_min_level = 0xff;
1192         dpm_state->soft_max_level = 0xff;
1193         dpm_state->hard_min_level = 0xff;
1194         dpm_state->hard_max_level = 0xff;
1195 }
1196
1197 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1198                 struct vega10_single_dpm_table *dpm_table,
1199                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1200 {
1201         int i;
1202
1203         dpm_table->count = 0;
1204
1205         for (i = 0; i < dep_table->count; i++) {
1206                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1207                                 dep_table->entries[i].clk) {
1208                         dpm_table->dpm_levels[dpm_table->count].value =
1209                                         dep_table->entries[i].clk;
1210                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1211                         dpm_table->count++;
1212                 }
1213         }
1214 }
1215 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1216 {
1217         struct vega10_hwmgr *data = hwmgr->backend;
1218         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1219         struct phm_ppt_v2_information *table_info =
1220                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1221         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1222                         table_info->pcie_table;
1223         uint32_t i;
1224
1225         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1226                         "Incorrect number of PCIE States from VBIOS!",
1227                         return -1);
1228
1229         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1230                 if (data->registry_data.pcieSpeedOverride)
1231                         pcie_table->pcie_gen[i] =
1232                                         data->registry_data.pcieSpeedOverride;
1233                 else
1234                         pcie_table->pcie_gen[i] =
1235                                         bios_pcie_table->entries[i].gen_speed;
1236
1237                 if (data->registry_data.pcieLaneOverride)
1238                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1239                                         data->registry_data.pcieLaneOverride);
1240                 else
1241                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1242                                                         bios_pcie_table->entries[i].lane_width);
1243                 if (data->registry_data.pcieClockOverride)
1244                         pcie_table->lclk[i] =
1245                                         data->registry_data.pcieClockOverride;
1246                 else
1247                         pcie_table->lclk[i] =
1248                                         bios_pcie_table->entries[i].pcie_sclk;
1249         }
1250
1251         pcie_table->count = NUM_LINK_LEVELS;
1252
1253         return 0;
1254 }
1255
1256 /*
1257  * This function is to initialize all DPM state tables
1258  * for SMU based on the dependency table.
1259  * Dynamic state patching function will then trim these
1260  * state tables to the allowed range based
1261  * on the power policy or external client requests,
1262  * such as UVD request, etc.
1263  */
1264 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1265 {
1266         struct vega10_hwmgr *data = hwmgr->backend;
1267         struct phm_ppt_v2_information *table_info =
1268                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1269         struct vega10_single_dpm_table *dpm_table;
1270         uint32_t i;
1271
1272         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1273                         table_info->vdd_dep_on_socclk;
1274         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1275                         table_info->vdd_dep_on_sclk;
1276         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1277                         table_info->vdd_dep_on_mclk;
1278         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1279                         table_info->mm_dep_table;
1280         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1281                         table_info->vdd_dep_on_dcefclk;
1282         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1283                         table_info->vdd_dep_on_pixclk;
1284         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1285                         table_info->vdd_dep_on_dispclk;
1286         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1287                         table_info->vdd_dep_on_phyclk;
1288
1289         PP_ASSERT_WITH_CODE(dep_soc_table,
1290                         "SOCCLK dependency table is missing. This table is mandatory",
1291                         return -EINVAL);
1292         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1293                         "SOCCLK dependency table is empty. This table is mandatory",
1294                         return -EINVAL);
1295
1296         PP_ASSERT_WITH_CODE(dep_gfx_table,
1297                         "GFXCLK dependency table is missing. This table is mandatory",
1298                         return -EINVAL);
1299         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1300                         "GFXCLK dependency table is empty. This table is mandatory",
1301                         return -EINVAL);
1302
1303         PP_ASSERT_WITH_CODE(dep_mclk_table,
1304                         "MCLK dependency table is missing. This table is mandatory",
1305                         return -EINVAL);
1306         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1307                         "MCLK dependency table has to have is missing. This table is mandatory",
1308                         return -EINVAL);
1309
1310         /* Initialize Sclk DPM table based on allow Sclk values */
1311         dpm_table = &(data->dpm_table.soc_table);
1312         vega10_setup_default_single_dpm_table(hwmgr,
1313                         dpm_table,
1314                         dep_soc_table);
1315
1316         vega10_init_dpm_state(&(dpm_table->dpm_state));
1317
1318         dpm_table = &(data->dpm_table.gfx_table);
1319         vega10_setup_default_single_dpm_table(hwmgr,
1320                         dpm_table,
1321                         dep_gfx_table);
1322         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1323                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1324                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1325         vega10_init_dpm_state(&(dpm_table->dpm_state));
1326
1327         /* Initialize Mclk DPM table based on allow Mclk values */
1328         data->dpm_table.mem_table.count = 0;
1329         dpm_table = &(data->dpm_table.mem_table);
1330         vega10_setup_default_single_dpm_table(hwmgr,
1331                         dpm_table,
1332                         dep_mclk_table);
1333         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1334                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1335                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1336
1337         vega10_init_dpm_state(&(dpm_table->dpm_state));
1338
1339         data->dpm_table.eclk_table.count = 0;
1340         dpm_table = &(data->dpm_table.eclk_table);
1341         for (i = 0; i < dep_mm_table->count; i++) {
1342                 if (i == 0 || dpm_table->dpm_levels
1343                                 [dpm_table->count - 1].value <=
1344                                                 dep_mm_table->entries[i].eclk) {
1345                         dpm_table->dpm_levels[dpm_table->count].value =
1346                                         dep_mm_table->entries[i].eclk;
1347                         dpm_table->dpm_levels[dpm_table->count].enabled =
1348                                         (i == 0) ? true : false;
1349                         dpm_table->count++;
1350                 }
1351         }
1352         vega10_init_dpm_state(&(dpm_table->dpm_state));
1353
1354         data->dpm_table.vclk_table.count = 0;
1355         data->dpm_table.dclk_table.count = 0;
1356         dpm_table = &(data->dpm_table.vclk_table);
1357         for (i = 0; i < dep_mm_table->count; i++) {
1358                 if (i == 0 || dpm_table->dpm_levels
1359                                 [dpm_table->count - 1].value <=
1360                                                 dep_mm_table->entries[i].vclk) {
1361                         dpm_table->dpm_levels[dpm_table->count].value =
1362                                         dep_mm_table->entries[i].vclk;
1363                         dpm_table->dpm_levels[dpm_table->count].enabled =
1364                                         (i == 0) ? true : false;
1365                         dpm_table->count++;
1366                 }
1367         }
1368         vega10_init_dpm_state(&(dpm_table->dpm_state));
1369
1370         dpm_table = &(data->dpm_table.dclk_table);
1371         for (i = 0; i < dep_mm_table->count; i++) {
1372                 if (i == 0 || dpm_table->dpm_levels
1373                                 [dpm_table->count - 1].value <=
1374                                                 dep_mm_table->entries[i].dclk) {
1375                         dpm_table->dpm_levels[dpm_table->count].value =
1376                                         dep_mm_table->entries[i].dclk;
1377                         dpm_table->dpm_levels[dpm_table->count].enabled =
1378                                         (i == 0) ? true : false;
1379                         dpm_table->count++;
1380                 }
1381         }
1382         vega10_init_dpm_state(&(dpm_table->dpm_state));
1383
1384         /* Assume there is no headless Vega10 for now */
1385         dpm_table = &(data->dpm_table.dcef_table);
1386         vega10_setup_default_single_dpm_table(hwmgr,
1387                         dpm_table,
1388                         dep_dcef_table);
1389
1390         vega10_init_dpm_state(&(dpm_table->dpm_state));
1391
1392         dpm_table = &(data->dpm_table.pixel_table);
1393         vega10_setup_default_single_dpm_table(hwmgr,
1394                         dpm_table,
1395                         dep_pix_table);
1396
1397         vega10_init_dpm_state(&(dpm_table->dpm_state));
1398
1399         dpm_table = &(data->dpm_table.display_table);
1400         vega10_setup_default_single_dpm_table(hwmgr,
1401                         dpm_table,
1402                         dep_disp_table);
1403
1404         vega10_init_dpm_state(&(dpm_table->dpm_state));
1405
1406         dpm_table = &(data->dpm_table.phy_table);
1407         vega10_setup_default_single_dpm_table(hwmgr,
1408                         dpm_table,
1409                         dep_phy_table);
1410
1411         vega10_init_dpm_state(&(dpm_table->dpm_state));
1412
1413         vega10_setup_default_pcie_table(hwmgr);
1414
1415         /* save a copy of the default DPM table */
1416         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1417                         sizeof(struct vega10_dpm_table));
1418
1419         return 0;
1420 }
1421
1422 /*
1423  * @fn vega10_populate_ulv_state
1424  * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1425  *
1426  * @param    hwmgr - the address of the hardware manager.
1427  * @return   Always 0.
1428  */
1429 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1430 {
1431         struct vega10_hwmgr *data = hwmgr->backend;
1432         struct phm_ppt_v2_information *table_info =
1433                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1434
1435         data->smc_state_table.pp_table.UlvOffsetVid =
1436                         (uint8_t)table_info->us_ulv_voltage_offset;
1437
1438         data->smc_state_table.pp_table.UlvSmnclkDid =
1439                         (uint8_t)(table_info->us_ulv_smnclk_did);
1440         data->smc_state_table.pp_table.UlvMp1clkDid =
1441                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1442         data->smc_state_table.pp_table.UlvGfxclkBypass =
1443                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1444         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1445                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1446         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1447                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1448
1449         return 0;
1450 }
1451
1452 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1453                 uint32_t lclock, uint8_t *curr_lclk_did)
1454 {
1455         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1456
1457         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1458                         hwmgr,
1459                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1460                         lclock, &dividers),
1461                         "Failed to get LCLK clock settings from VBIOS!",
1462                         return -1);
1463
1464         *curr_lclk_did = dividers.ulDid;
1465
1466         return 0;
1467 }
1468
1469 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1470 {
1471         int result = -1;
1472         struct vega10_hwmgr *data = hwmgr->backend;
1473         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1474         struct vega10_pcie_table *pcie_table =
1475                         &(data->dpm_table.pcie_table);
1476         uint32_t i, j;
1477
1478         for (i = 0; i < pcie_table->count; i++) {
1479                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1480                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1481
1482                 result = vega10_populate_single_lclk_level(hwmgr,
1483                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1484                 if (result) {
1485                         pr_info("Populate LClock Level %d Failed!\n", i);
1486                         return result;
1487                 }
1488         }
1489
1490         j = i - 1;
1491         while (i < NUM_LINK_LEVELS) {
1492                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1493                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1494
1495                 result = vega10_populate_single_lclk_level(hwmgr,
1496                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1497                 if (result) {
1498                         pr_info("Populate LClock Level %d Failed!\n", i);
1499                         return result;
1500                 }
1501                 i++;
1502         }
1503
1504         return result;
1505 }
1506
1507 /**
1508 * Populates single SMC GFXSCLK structure using the provided engine clock
1509 *
1510 * @param    hwmgr      the address of the hardware manager
1511 * @param    gfx_clock  the GFX clock to use to populate the structure.
1512 * @param    current_gfxclk_level  location in PPTable for the SMC GFXCLK structure.
1513 */
1514
1515 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1516                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1517                 uint32_t *acg_freq)
1518 {
1519         struct phm_ppt_v2_information *table_info =
1520                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1521         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1522         struct vega10_hwmgr *data = hwmgr->backend;
1523         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1524         uint32_t gfx_max_clock =
1525                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1526         uint32_t i = 0;
1527
1528         if (hwmgr->od_enabled)
1529                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1530                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1531         else
1532                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1533
1534         PP_ASSERT_WITH_CODE(dep_on_sclk,
1535                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1536                         return -EINVAL);
1537
1538         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1539                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1540         else {
1541                 for (i = 0; i < dep_on_sclk->count; i++) {
1542                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1543                                 break;
1544                 }
1545                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1546                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1547                                 return -EINVAL);
1548         }
1549
1550         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1551                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1552                         gfx_clock, &dividers),
1553                         "Failed to get GFX Clock settings from VBIOS!",
1554                         return -EINVAL);
1555
1556         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1557         current_gfxclk_level->FbMult =
1558                         cpu_to_le32(dividers.ulPll_fb_mult);
1559         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1560         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1561         current_gfxclk_level->SsFbMult =
1562                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1563         current_gfxclk_level->SsSlewFrac =
1564                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1565         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1566
1567         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1568
1569         return 0;
1570 }
1571
1572 /**
1573  * @brief Populates single SMC SOCCLK structure using the provided clock.
1574  *
1575  * @param    hwmgr - the address of the hardware manager.
1576  * @param    soc_clock - the SOC clock to use to populate the structure.
1577  * @param    current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1578  * @return   0 on success..
1579  */
1580 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1581                 uint32_t soc_clock, uint8_t *current_soc_did,
1582                 uint8_t *current_vol_index)
1583 {
1584         struct vega10_hwmgr *data = hwmgr->backend;
1585         struct phm_ppt_v2_information *table_info =
1586                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1587         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1588         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1589         uint32_t i;
1590
1591         if (hwmgr->od_enabled) {
1592                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1593                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1594                 for (i = 0; i < dep_on_soc->count; i++) {
1595                         if (dep_on_soc->entries[i].clk >= soc_clock)
1596                                 break;
1597                 }
1598         } else {
1599                 dep_on_soc = table_info->vdd_dep_on_socclk;
1600                 for (i = 0; i < dep_on_soc->count; i++) {
1601                         if (dep_on_soc->entries[i].clk == soc_clock)
1602                                 break;
1603                 }
1604         }
1605
1606         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1607                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1608                         return -EINVAL);
1609
1610         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1611                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1612                         soc_clock, &dividers),
1613                         "Failed to get SOC Clock settings from VBIOS!",
1614                         return -EINVAL);
1615
1616         *current_soc_did = (uint8_t)dividers.ulDid;
1617         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1618         return 0;
1619 }
1620
1621 /**
1622 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1623 *
1624 * @param    hwmgr      the address of the hardware manager
1625 */
1626 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1627 {
1628         struct vega10_hwmgr *data = hwmgr->backend;
1629         struct phm_ppt_v2_information *table_info =
1630                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1631         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1632         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1633         int result = 0;
1634         uint32_t i, j;
1635
1636         for (i = 0; i < dpm_table->count; i++) {
1637                 result = vega10_populate_single_gfx_level(hwmgr,
1638                                 dpm_table->dpm_levels[i].value,
1639                                 &(pp_table->GfxclkLevel[i]),
1640                                 &(pp_table->AcgFreqTable[i]));
1641                 if (result)
1642                         return result;
1643         }
1644
1645         j = i - 1;
1646         while (i < NUM_GFXCLK_DPM_LEVELS) {
1647                 result = vega10_populate_single_gfx_level(hwmgr,
1648                                 dpm_table->dpm_levels[j].value,
1649                                 &(pp_table->GfxclkLevel[i]),
1650                                 &(pp_table->AcgFreqTable[i]));
1651                 if (result)
1652                         return result;
1653                 i++;
1654         }
1655
1656         pp_table->GfxclkSlewRate =
1657                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1658
1659         dpm_table = &(data->dpm_table.soc_table);
1660         for (i = 0; i < dpm_table->count; i++) {
1661                 result = vega10_populate_single_soc_level(hwmgr,
1662                                 dpm_table->dpm_levels[i].value,
1663                                 &(pp_table->SocclkDid[i]),
1664                                 &(pp_table->SocDpmVoltageIndex[i]));
1665                 if (result)
1666                         return result;
1667         }
1668
1669         j = i - 1;
1670         while (i < NUM_SOCCLK_DPM_LEVELS) {
1671                 result = vega10_populate_single_soc_level(hwmgr,
1672                                 dpm_table->dpm_levels[j].value,
1673                                 &(pp_table->SocclkDid[i]),
1674                                 &(pp_table->SocDpmVoltageIndex[i]));
1675                 if (result)
1676                         return result;
1677                 i++;
1678         }
1679
1680         return result;
1681 }
1682
1683 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1684 {
1685         struct vega10_hwmgr *data = hwmgr->backend;
1686         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1687         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1688         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1689
1690         uint8_t soc_vid = 0;
1691         uint32_t i, max_vddc_level;
1692
1693         if (hwmgr->od_enabled)
1694                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1695         else
1696                 vddc_lookup_table = table_info->vddc_lookup_table;
1697
1698         max_vddc_level = vddc_lookup_table->count;
1699         for (i = 0; i < max_vddc_level; i++) {
1700                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1701                 pp_table->SocVid[i] = soc_vid;
1702         }
1703         while (i < MAX_REGULAR_DPM_NUMBER) {
1704                 pp_table->SocVid[i] = soc_vid;
1705                 i++;
1706         }
1707 }
1708
1709 /**
1710  * @brief Populates single SMC GFXCLK structure using the provided clock.
1711  *
1712  * @param    hwmgr - the address of the hardware manager.
1713  * @param    mem_clock - the memory clock to use to populate the structure.
1714  * @return   0 on success..
1715  */
1716 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1717                 uint32_t mem_clock, uint8_t *current_mem_vid,
1718                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1719 {
1720         struct vega10_hwmgr *data = hwmgr->backend;
1721         struct phm_ppt_v2_information *table_info =
1722                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1723         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1724         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1725         uint32_t mem_max_clock =
1726                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1727         uint32_t i = 0;
1728
1729         if (hwmgr->od_enabled)
1730                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1731                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1732         else
1733                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1734
1735         PP_ASSERT_WITH_CODE(dep_on_mclk,
1736                         "Invalid SOC_VDD-UCLK Dependency Table!",
1737                         return -EINVAL);
1738
1739         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1740                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1741         } else {
1742                 for (i = 0; i < dep_on_mclk->count; i++) {
1743                         if (dep_on_mclk->entries[i].clk == mem_clock)
1744                                 break;
1745                 }
1746                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1747                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1748                                 return -EINVAL);
1749         }
1750
1751         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1752                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1753                         "Failed to get UCLK settings from VBIOS!",
1754                         return -1);
1755
1756         *current_mem_vid =
1757                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1758         *current_mem_soc_vind =
1759                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1760         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1761         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1762
1763         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1764                         "Invalid Divider ID!",
1765                         return -EINVAL);
1766
1767         return 0;
1768 }
1769
1770 /**
1771  * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1772  *
1773  * @param    pHwMgr - the address of the hardware manager.
1774  * @return   PP_Result_OK on success.
1775  */
1776 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1777 {
1778         struct vega10_hwmgr *data = hwmgr->backend;
1779         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1780         struct vega10_single_dpm_table *dpm_table =
1781                         &(data->dpm_table.mem_table);
1782         int result = 0;
1783         uint32_t i, j;
1784
1785         for (i = 0; i < dpm_table->count; i++) {
1786                 result = vega10_populate_single_memory_level(hwmgr,
1787                                 dpm_table->dpm_levels[i].value,
1788                                 &(pp_table->MemVid[i]),
1789                                 &(pp_table->UclkLevel[i]),
1790                                 &(pp_table->MemSocVoltageIndex[i]));
1791                 if (result)
1792                         return result;
1793         }
1794
1795         j = i - 1;
1796         while (i < NUM_UCLK_DPM_LEVELS) {
1797                 result = vega10_populate_single_memory_level(hwmgr,
1798                                 dpm_table->dpm_levels[j].value,
1799                                 &(pp_table->MemVid[i]),
1800                                 &(pp_table->UclkLevel[i]),
1801                                 &(pp_table->MemSocVoltageIndex[i]));
1802                 if (result)
1803                         return result;
1804                 i++;
1805         }
1806
1807         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1808         pp_table->MemoryChannelWidth =
1809                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1810                                         channel_number[data->mem_channels]);
1811
1812         pp_table->LowestUclkReservedForUlv =
1813                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1814
1815         return result;
1816 }
1817
1818 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1819                 DSPCLK_e disp_clock)
1820 {
1821         struct vega10_hwmgr *data = hwmgr->backend;
1822         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1823         struct phm_ppt_v2_information *table_info =
1824                         (struct phm_ppt_v2_information *)
1825                         (hwmgr->pptable);
1826         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1827         uint32_t i;
1828         uint16_t clk = 0, vddc = 0;
1829         uint8_t vid = 0;
1830
1831         switch (disp_clock) {
1832         case DSPCLK_DCEFCLK:
1833                 dep_table = table_info->vdd_dep_on_dcefclk;
1834                 break;
1835         case DSPCLK_DISPCLK:
1836                 dep_table = table_info->vdd_dep_on_dispclk;
1837                 break;
1838         case DSPCLK_PIXCLK:
1839                 dep_table = table_info->vdd_dep_on_pixclk;
1840                 break;
1841         case DSPCLK_PHYCLK:
1842                 dep_table = table_info->vdd_dep_on_phyclk;
1843                 break;
1844         default:
1845                 return -1;
1846         }
1847
1848         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1849                         "Number Of Entries Exceeded maximum!",
1850                         return -1);
1851
1852         for (i = 0; i < dep_table->count; i++) {
1853                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1854                 vddc = table_info->vddc_lookup_table->
1855                                 entries[dep_table->entries[i].vddInd].us_vdd;
1856                 vid = (uint8_t)convert_to_vid(vddc);
1857                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1858                                 cpu_to_le16(clk);
1859                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1860                                 cpu_to_le16(vid);
1861         }
1862
1863         while (i < NUM_DSPCLK_LEVELS) {
1864                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1865                                 cpu_to_le16(clk);
1866                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1867                                 cpu_to_le16(vid);
1868                 i++;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1875 {
1876         uint32_t i;
1877
1878         for (i = 0; i < DSPCLK_COUNT; i++) {
1879                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1880                                 "Failed to populate Clock in DisplayClockTable!",
1881                                 return -1);
1882         }
1883
1884         return 0;
1885 }
1886
1887 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1888                 uint32_t eclock, uint8_t *current_eclk_did,
1889                 uint8_t *current_soc_vol)
1890 {
1891         struct phm_ppt_v2_information *table_info =
1892                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1893         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1894                         table_info->mm_dep_table;
1895         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1896         uint32_t i;
1897
1898         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1899                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1900                         eclock, &dividers),
1901                         "Failed to get ECLK clock settings from VBIOS!",
1902                         return -1);
1903
1904         *current_eclk_did = (uint8_t)dividers.ulDid;
1905
1906         for (i = 0; i < dep_table->count; i++) {
1907                 if (dep_table->entries[i].eclk == eclock)
1908                         *current_soc_vol = dep_table->entries[i].vddcInd;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1915 {
1916         struct vega10_hwmgr *data = hwmgr->backend;
1917         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1918         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1919         int result = -EINVAL;
1920         uint32_t i, j;
1921
1922         for (i = 0; i < dpm_table->count; i++) {
1923                 result = vega10_populate_single_eclock_level(hwmgr,
1924                                 dpm_table->dpm_levels[i].value,
1925                                 &(pp_table->EclkDid[i]),
1926                                 &(pp_table->VceDpmVoltageIndex[i]));
1927                 if (result)
1928                         return result;
1929         }
1930
1931         j = i - 1;
1932         while (i < NUM_VCE_DPM_LEVELS) {
1933                 result = vega10_populate_single_eclock_level(hwmgr,
1934                                 dpm_table->dpm_levels[j].value,
1935                                 &(pp_table->EclkDid[i]),
1936                                 &(pp_table->VceDpmVoltageIndex[i]));
1937                 if (result)
1938                         return result;
1939                 i++;
1940         }
1941
1942         return result;
1943 }
1944
1945 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
1946                 uint32_t vclock, uint8_t *current_vclk_did)
1947 {
1948         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1949
1950         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1951                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1952                         vclock, &dividers),
1953                         "Failed to get VCLK clock settings from VBIOS!",
1954                         return -EINVAL);
1955
1956         *current_vclk_did = (uint8_t)dividers.ulDid;
1957
1958         return 0;
1959 }
1960
1961 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
1962                 uint32_t dclock, uint8_t *current_dclk_did)
1963 {
1964         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1965
1966         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1967                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1968                         dclock, &dividers),
1969                         "Failed to get DCLK clock settings from VBIOS!",
1970                         return -EINVAL);
1971
1972         *current_dclk_did = (uint8_t)dividers.ulDid;
1973
1974         return 0;
1975 }
1976
1977 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
1978 {
1979         struct vega10_hwmgr *data = hwmgr->backend;
1980         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1981         struct vega10_single_dpm_table *vclk_dpm_table =
1982                         &(data->dpm_table.vclk_table);
1983         struct vega10_single_dpm_table *dclk_dpm_table =
1984                         &(data->dpm_table.dclk_table);
1985         struct phm_ppt_v2_information *table_info =
1986                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1987         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1988                         table_info->mm_dep_table;
1989         int result = -EINVAL;
1990         uint32_t i, j;
1991
1992         for (i = 0; i < vclk_dpm_table->count; i++) {
1993                 result = vega10_populate_single_vclock_level(hwmgr,
1994                                 vclk_dpm_table->dpm_levels[i].value,
1995                                 &(pp_table->VclkDid[i]));
1996                 if (result)
1997                         return result;
1998         }
1999
2000         j = i - 1;
2001         while (i < NUM_UVD_DPM_LEVELS) {
2002                 result = vega10_populate_single_vclock_level(hwmgr,
2003                                 vclk_dpm_table->dpm_levels[j].value,
2004                                 &(pp_table->VclkDid[i]));
2005                 if (result)
2006                         return result;
2007                 i++;
2008         }
2009
2010         for (i = 0; i < dclk_dpm_table->count; i++) {
2011                 result = vega10_populate_single_dclock_level(hwmgr,
2012                                 dclk_dpm_table->dpm_levels[i].value,
2013                                 &(pp_table->DclkDid[i]));
2014                 if (result)
2015                         return result;
2016         }
2017
2018         j = i - 1;
2019         while (i < NUM_UVD_DPM_LEVELS) {
2020                 result = vega10_populate_single_dclock_level(hwmgr,
2021                                 dclk_dpm_table->dpm_levels[j].value,
2022                                 &(pp_table->DclkDid[i]));
2023                 if (result)
2024                         return result;
2025                 i++;
2026         }
2027
2028         for (i = 0; i < dep_table->count; i++) {
2029                 if (dep_table->entries[i].vclk ==
2030                                 vclk_dpm_table->dpm_levels[i].value &&
2031                         dep_table->entries[i].dclk ==
2032                                 dclk_dpm_table->dpm_levels[i].value)
2033                         pp_table->UvdDpmVoltageIndex[i] =
2034                                         dep_table->entries[i].vddcInd;
2035                 else
2036                         return -1;
2037         }
2038
2039         j = i - 1;
2040         while (i < NUM_UVD_DPM_LEVELS) {
2041                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2042                 i++;
2043         }
2044
2045         return 0;
2046 }
2047
2048 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2049 {
2050         struct vega10_hwmgr *data = hwmgr->backend;
2051         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2052         struct phm_ppt_v2_information *table_info =
2053                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2054         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2055                         table_info->vdd_dep_on_sclk;
2056         uint32_t i;
2057
2058         for (i = 0; i < dep_table->count; i++) {
2059                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2060                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2061                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2062         }
2063
2064         return 0;
2065 }
2066
2067 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2068 {
2069         struct vega10_hwmgr *data = hwmgr->backend;
2070         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2071         struct phm_ppt_v2_information *table_info =
2072                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2073         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2074                         table_info->vdd_dep_on_sclk;
2075         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2076         int result = 0;
2077         uint32_t i;
2078
2079         pp_table->MinVoltageVid = (uint8_t)0xff;
2080         pp_table->MaxVoltageVid = (uint8_t)0;
2081
2082         if (data->smu_features[GNLD_AVFS].supported) {
2083                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2084                 if (!result) {
2085                         pp_table->MinVoltageVid = (uint8_t)
2086                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2087                         pp_table->MaxVoltageVid = (uint8_t)
2088                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2089
2090                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2091                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2092                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2093                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2094                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2095                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2096                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2097
2098                         pp_table->BtcGbVdroopTableCksOff.a0 =
2099                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2100                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2101                         pp_table->BtcGbVdroopTableCksOff.a1 =
2102                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2103                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2104                         pp_table->BtcGbVdroopTableCksOff.a2 =
2105                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2106                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2107
2108                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2109                         pp_table->BtcGbVdroopTableCksOn.a0 =
2110                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2111                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2112                         pp_table->BtcGbVdroopTableCksOn.a1 =
2113                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2114                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2115                         pp_table->BtcGbVdroopTableCksOn.a2 =
2116                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2117                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2118
2119                         pp_table->AvfsGbCksOn.m1 =
2120                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2121                         pp_table->AvfsGbCksOn.m2 =
2122                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2123                         pp_table->AvfsGbCksOn.b =
2124                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2125                         pp_table->AvfsGbCksOn.m1_shift = 24;
2126                         pp_table->AvfsGbCksOn.m2_shift = 12;
2127                         pp_table->AvfsGbCksOn.b_shift = 0;
2128
2129                         pp_table->OverrideAvfsGbCksOn =
2130                                         avfs_params.ucEnableGbFuseTableCkson;
2131                         pp_table->AvfsGbCksOff.m1 =
2132                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2133                         pp_table->AvfsGbCksOff.m2 =
2134                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2135                         pp_table->AvfsGbCksOff.b =
2136                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2137                         pp_table->AvfsGbCksOff.m1_shift = 24;
2138                         pp_table->AvfsGbCksOff.m2_shift = 12;
2139                         pp_table->AvfsGbCksOff.b_shift = 0;
2140
2141                         for (i = 0; i < dep_table->count; i++)
2142                                 pp_table->StaticVoltageOffsetVid[i] =
2143                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2144
2145                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2146                                         data->disp_clk_quad_eqn_a) &&
2147                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2148                                         data->disp_clk_quad_eqn_b)) {
2149                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2150                                                 (int32_t)data->disp_clk_quad_eqn_a;
2151                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2152                                                 (int32_t)data->disp_clk_quad_eqn_b;
2153                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2154                                                 (int32_t)data->disp_clk_quad_eqn_c;
2155                         } else {
2156                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2157                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2158                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2159                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2160                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2161                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2162                         }
2163
2164                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2165                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2166                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2167
2168                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2169                                         data->dcef_clk_quad_eqn_a) &&
2170                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2171                                         data->dcef_clk_quad_eqn_b)) {
2172                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2173                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2174                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2175                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2176                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2177                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2178                         } else {
2179                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2180                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2181                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2182                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2183                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2184                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2185                         }
2186
2187                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2188                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2189                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2190
2191                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2192                                         data->pixel_clk_quad_eqn_a) &&
2193                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2194                                         data->pixel_clk_quad_eqn_b)) {
2195                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2196                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2197                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2198                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2199                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2200                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2201                         } else {
2202                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2203                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2204                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2205                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2206                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2207                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2208                         }
2209
2210                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2211                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2212                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2213                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2214                                         data->phy_clk_quad_eqn_a) &&
2215                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2216                                         data->phy_clk_quad_eqn_b)) {
2217                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2218                                                 (int32_t)data->phy_clk_quad_eqn_a;
2219                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2220                                                 (int32_t)data->phy_clk_quad_eqn_b;
2221                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2222                                                 (int32_t)data->phy_clk_quad_eqn_c;
2223                         } else {
2224                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2225                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2226                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2227                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2228                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2229                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2230                         }
2231
2232                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2233                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2234                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2235
2236                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2237                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2238                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2239                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2240                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2241                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2242
2243                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2244                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2245                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2246                         pp_table->AcgAvfsGb.m1_shift             = 0;
2247                         pp_table->AcgAvfsGb.m2_shift             = 0;
2248                         pp_table->AcgAvfsGb.b_shift              = 0;
2249
2250                 } else {
2251                         data->smu_features[GNLD_AVFS].supported = false;
2252                 }
2253         }
2254
2255         return 0;
2256 }
2257
2258 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2259 {
2260         struct vega10_hwmgr *data = hwmgr->backend;
2261         uint32_t agc_btc_response;
2262
2263         if (data->smu_features[GNLD_ACG].supported) {
2264                 if (0 == vega10_enable_smc_features(hwmgr, true,
2265                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2266                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2267
2268                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
2269
2270                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
2271                 agc_btc_response = smum_get_argument(hwmgr);
2272
2273                 if (1 == agc_btc_response) {
2274                         if (1 == data->acg_loop_state)
2275                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
2276                         else if (2 == data->acg_loop_state)
2277                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
2278                         if (0 == vega10_enable_smc_features(hwmgr, true,
2279                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2280                                         data->smu_features[GNLD_ACG].enabled = true;
2281                 } else {
2282                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2283                         data->smu_features[GNLD_ACG].enabled = false;
2284                 }
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2291 {
2292         struct vega10_hwmgr *data = hwmgr->backend;
2293
2294         if (data->smu_features[GNLD_ACG].supported &&
2295             data->smu_features[GNLD_ACG].enabled)
2296                 if (!vega10_enable_smc_features(hwmgr, false,
2297                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2298                         data->smu_features[GNLD_ACG].enabled = false;
2299
2300         return 0;
2301 }
2302
2303 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2304 {
2305         struct vega10_hwmgr *data = hwmgr->backend;
2306         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2307         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2308         int result;
2309
2310         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2311         if (!result) {
2312                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2313                     data->registry_data.regulator_hot_gpio_support) {
2314                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2315                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2316                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2317                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2318                 } else {
2319                         pp_table->VR0HotGpio = 0;
2320                         pp_table->VR0HotPolarity = 0;
2321                         pp_table->VR1HotGpio = 0;
2322                         pp_table->VR1HotPolarity = 0;
2323                 }
2324
2325                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2326                     data->registry_data.ac_dc_switch_gpio_support) {
2327                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2328                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2329                 } else {
2330                         pp_table->AcDcGpio = 0;
2331                         pp_table->AcDcPolarity = 0;
2332                 }
2333         }
2334
2335         return result;
2336 }
2337
2338 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2339 {
2340         struct vega10_hwmgr *data = hwmgr->backend;
2341
2342         if (data->smu_features[GNLD_AVFS].supported) {
2343                 if (enable) {
2344                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2345                                         true,
2346                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2347                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2348                                         return -1);
2349                         data->smu_features[GNLD_AVFS].enabled = true;
2350                 } else {
2351                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2352                                         false,
2353                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2354                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2355                                         return -1);
2356                         data->smu_features[GNLD_AVFS].enabled = false;
2357                 }
2358         }
2359
2360         return 0;
2361 }
2362
2363 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2364 {
2365         struct vega10_hwmgr *data = hwmgr->backend;
2366
2367         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2368                 vega10_avfs_enable(hwmgr, false);
2369         } else if (data->need_update_dpm_table) {
2370                 vega10_avfs_enable(hwmgr, false);
2371                 vega10_avfs_enable(hwmgr, true);
2372         } else {
2373                 vega10_avfs_enable(hwmgr, true);
2374         }
2375
2376         return 0;
2377 }
2378
2379 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2380 {
2381         int result = 0;
2382
2383         uint64_t serial_number = 0;
2384         uint32_t top32, bottom32;
2385         struct phm_fuses_default fuse;
2386
2387         struct vega10_hwmgr *data = hwmgr->backend;
2388         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2389
2390         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
2391         top32 = smum_get_argument(hwmgr);
2392
2393         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
2394         bottom32 = smum_get_argument(hwmgr);
2395
2396         serial_number = ((uint64_t)bottom32 << 32) | top32;
2397
2398         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2399                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2400                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2401                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2402                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2403                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2404                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2405                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2406                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2407                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2408                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2409                                                 AVFSFUSETABLE, false);
2410                 PP_ASSERT_WITH_CODE(!result,
2411                         "Failed to upload FuseOVerride!",
2412                         );
2413         }
2414
2415         return result;
2416 }
2417
2418 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2419 {
2420         struct vega10_hwmgr *data = hwmgr->backend;
2421         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2422         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2423         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2424         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2425         uint32_t i;
2426
2427         dep_table = table_info->vdd_dep_on_mclk;
2428         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2429
2430         for (i = 0; i < dep_table->count; i++) {
2431                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2432                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2433                         return;
2434                 }
2435         }
2436
2437         dep_table = table_info->vdd_dep_on_sclk;
2438         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2439         for (i = 0; i < dep_table->count; i++) {
2440                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2441                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2442                         return;
2443                 }
2444         }
2445
2446         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2447                 data->need_update_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
2448                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2449         }
2450 }
2451
2452 /**
2453 * Initializes the SMC table and uploads it
2454 *
2455 * @param    hwmgr  the address of the powerplay hardware manager.
2456 * @param    pInput  the pointer to input data (PowerState)
2457 * @return   always 0
2458 */
2459 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2460 {
2461         int result;
2462         struct vega10_hwmgr *data = hwmgr->backend;
2463         struct phm_ppt_v2_information *table_info =
2464                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2465         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2466         struct pp_atomfwctrl_voltage_table voltage_table;
2467         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2468         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2469
2470         result = vega10_setup_default_dpm_tables(hwmgr);
2471         PP_ASSERT_WITH_CODE(!result,
2472                         "Failed to setup default DPM tables!",
2473                         return result);
2474
2475         /* initialize ODN table */
2476         if (hwmgr->od_enabled) {
2477                 if (odn_table->max_vddc) {
2478                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2479                         vega10_check_dpm_table_updated(hwmgr);
2480                 } else {
2481                         vega10_odn_initial_default_setting(hwmgr);
2482                 }
2483         }
2484
2485         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2486                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2487         pp_table->MaxVidStep = voltage_table.max_vid_step;
2488
2489         pp_table->GfxDpmVoltageMode =
2490                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2491         pp_table->SocDpmVoltageMode =
2492                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2493         pp_table->UclkDpmVoltageMode =
2494                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2495         pp_table->UvdDpmVoltageMode =
2496                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2497         pp_table->VceDpmVoltageMode =
2498                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2499         pp_table->Mp0DpmVoltageMode =
2500                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2501
2502         pp_table->DisplayDpmVoltageMode =
2503                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2504
2505         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2506         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2507
2508         if (data->registry_data.ulv_support &&
2509                         table_info->us_ulv_voltage_offset) {
2510                 result = vega10_populate_ulv_state(hwmgr);
2511                 PP_ASSERT_WITH_CODE(!result,
2512                                 "Failed to initialize ULV state!",
2513                                 return result);
2514         }
2515
2516         result = vega10_populate_smc_link_levels(hwmgr);
2517         PP_ASSERT_WITH_CODE(!result,
2518                         "Failed to initialize Link Level!",
2519                         return result);
2520
2521         result = vega10_populate_all_graphic_levels(hwmgr);
2522         PP_ASSERT_WITH_CODE(!result,
2523                         "Failed to initialize Graphics Level!",
2524                         return result);
2525
2526         result = vega10_populate_all_memory_levels(hwmgr);
2527         PP_ASSERT_WITH_CODE(!result,
2528                         "Failed to initialize Memory Level!",
2529                         return result);
2530
2531         vega10_populate_vddc_soc_levels(hwmgr);
2532
2533         result = vega10_populate_all_display_clock_levels(hwmgr);
2534         PP_ASSERT_WITH_CODE(!result,
2535                         "Failed to initialize Display Level!",
2536                         return result);
2537
2538         result = vega10_populate_smc_vce_levels(hwmgr);
2539         PP_ASSERT_WITH_CODE(!result,
2540                         "Failed to initialize VCE Level!",
2541                         return result);
2542
2543         result = vega10_populate_smc_uvd_levels(hwmgr);
2544         PP_ASSERT_WITH_CODE(!result,
2545                         "Failed to initialize UVD Level!",
2546                         return result);
2547
2548         if (data->registry_data.clock_stretcher_support) {
2549                 result = vega10_populate_clock_stretcher_table(hwmgr);
2550                 PP_ASSERT_WITH_CODE(!result,
2551                                 "Failed to populate Clock Stretcher Table!",
2552                                 return result);
2553         }
2554
2555         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2556         if (!result) {
2557                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2558                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2559                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2560                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2561                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2562                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2563                                 SMU9_SYSPLL0_SOCCLK_ID, &boot_up_values.ulSocClk);
2564
2565                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2566                                 SMU9_SYSPLL0_DCEFCLK_ID, &boot_up_values.ulDCEFClk);
2567
2568                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2569                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2570                 if (0 != boot_up_values.usVddc) {
2571                         smum_send_msg_to_smc_with_parameter(hwmgr,
2572                                                 PPSMC_MSG_SetFloorSocVoltage,
2573                                                 (boot_up_values.usVddc * 4));
2574                         data->vbios_boot_state.bsoc_vddc_lock = true;
2575                 } else {
2576                         data->vbios_boot_state.bsoc_vddc_lock = false;
2577                 }
2578                 smum_send_msg_to_smc_with_parameter(hwmgr,
2579                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2580                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
2581         }
2582
2583         result = vega10_populate_avfs_parameters(hwmgr);
2584         PP_ASSERT_WITH_CODE(!result,
2585                         "Failed to initialize AVFS Parameters!",
2586                         return result);
2587
2588         result = vega10_populate_gpio_parameters(hwmgr);
2589         PP_ASSERT_WITH_CODE(!result,
2590                         "Failed to initialize GPIO Parameters!",
2591                         return result);
2592
2593         pp_table->GfxclkAverageAlpha = (uint8_t)
2594                         (data->gfxclk_average_alpha);
2595         pp_table->SocclkAverageAlpha = (uint8_t)
2596                         (data->socclk_average_alpha);
2597         pp_table->UclkAverageAlpha = (uint8_t)
2598                         (data->uclk_average_alpha);
2599         pp_table->GfxActivityAverageAlpha = (uint8_t)
2600                         (data->gfx_activity_average_alpha);
2601
2602         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2603
2604         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2605
2606         PP_ASSERT_WITH_CODE(!result,
2607                         "Failed to upload PPtable!", return result);
2608
2609         result = vega10_avfs_enable(hwmgr, true);
2610         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2611                                         return result);
2612         vega10_acg_enable(hwmgr);
2613
2614         return 0;
2615 }
2616
2617 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2618 {
2619         struct vega10_hwmgr *data = hwmgr->backend;
2620
2621         if (data->smu_features[GNLD_THERMAL].supported) {
2622                 if (data->smu_features[GNLD_THERMAL].enabled)
2623                         pr_info("THERMAL Feature Already enabled!");
2624
2625                 PP_ASSERT_WITH_CODE(
2626                                 !vega10_enable_smc_features(hwmgr,
2627                                 true,
2628                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2629                                 "Enable THERMAL Feature Failed!",
2630                                 return -1);
2631                 data->smu_features[GNLD_THERMAL].enabled = true;
2632         }
2633
2634         return 0;
2635 }
2636
2637 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2638 {
2639         struct vega10_hwmgr *data = hwmgr->backend;
2640
2641         if (data->smu_features[GNLD_THERMAL].supported) {
2642                 if (!data->smu_features[GNLD_THERMAL].enabled)
2643                         pr_info("THERMAL Feature Already disabled!");
2644
2645                 PP_ASSERT_WITH_CODE(
2646                                 !vega10_enable_smc_features(hwmgr,
2647                                 false,
2648                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2649                                 "disable THERMAL Feature Failed!",
2650                                 return -1);
2651                 data->smu_features[GNLD_THERMAL].enabled = false;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2658 {
2659         struct vega10_hwmgr *data = hwmgr->backend;
2660
2661         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2662                 if (data->smu_features[GNLD_VR0HOT].supported) {
2663                         PP_ASSERT_WITH_CODE(
2664                                         !vega10_enable_smc_features(hwmgr,
2665                                         true,
2666                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2667                                         "Attempt to Enable VR0 Hot feature Failed!",
2668                                         return -1);
2669                         data->smu_features[GNLD_VR0HOT].enabled = true;
2670                 } else {
2671                         if (data->smu_features[GNLD_VR1HOT].supported) {
2672                                 PP_ASSERT_WITH_CODE(
2673                                                 !vega10_enable_smc_features(hwmgr,
2674                                                 true,
2675                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2676                                                 "Attempt to Enable VR0 Hot feature Failed!",
2677                                                 return -1);
2678                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2679                         }
2680                 }
2681         }
2682         return 0;
2683 }
2684
2685 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2686 {
2687         struct vega10_hwmgr *data = hwmgr->backend;
2688
2689         if (data->registry_data.ulv_support) {
2690                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2691                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2692                                 "Enable ULV Feature Failed!",
2693                                 return -1);
2694                 data->smu_features[GNLD_ULV].enabled = true;
2695         }
2696
2697         return 0;
2698 }
2699
2700 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2701 {
2702         struct vega10_hwmgr *data = hwmgr->backend;
2703
2704         if (data->registry_data.ulv_support) {
2705                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2706                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2707                                 "disable ULV Feature Failed!",
2708                                 return -EINVAL);
2709                 data->smu_features[GNLD_ULV].enabled = false;
2710         }
2711
2712         return 0;
2713 }
2714
2715 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2716 {
2717         struct vega10_hwmgr *data = hwmgr->backend;
2718
2719         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2720                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2721                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2722                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2723                                 return -EINVAL);
2724                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2725         }
2726
2727         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2728                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2729                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2730                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2731                                 return -EINVAL);
2732                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2733         }
2734
2735         if (data->smu_features[GNLD_DS_LCLK].supported) {
2736                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2737                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2738                                 "Attempt to Enable DS_LCLK Feature Failed!",
2739                                 return -EINVAL);
2740                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2741         }
2742
2743         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2744                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2745                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2746                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2747                                 return -EINVAL);
2748                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2749         }
2750
2751         return 0;
2752 }
2753
2754 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2755 {
2756         struct vega10_hwmgr *data = hwmgr->backend;
2757
2758         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2759                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2760                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2761                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2762                                 return -EINVAL);
2763                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2764         }
2765
2766         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2767                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2768                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2769                                 "Attempt to disable DS_ Feature Failed!",
2770                                 return -EINVAL);
2771                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2772         }
2773
2774         if (data->smu_features[GNLD_DS_LCLK].supported) {
2775                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2776                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2777                                 "Attempt to disable DS_LCLK Feature Failed!",
2778                                 return -EINVAL);
2779                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2780         }
2781
2782         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2783                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2784                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2785                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2786                                 return -EINVAL);
2787                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2788         }
2789
2790         return 0;
2791 }
2792
2793 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2794 {
2795         struct vega10_hwmgr *data = hwmgr->backend;
2796         uint32_t i, feature_mask = 0;
2797
2798
2799         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2800                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2801                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2802                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2803                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2804         }
2805
2806         for (i = 0; i < GNLD_DPM_MAX; i++) {
2807                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2808                         if (data->smu_features[i].supported) {
2809                                 if (data->smu_features[i].enabled) {
2810                                         feature_mask |= data->smu_features[i].
2811                                                         smu_feature_bitmap;
2812                                         data->smu_features[i].enabled = false;
2813                                 }
2814                         }
2815                 }
2816         }
2817
2818         vega10_enable_smc_features(hwmgr, false, feature_mask);
2819
2820         return 0;
2821 }
2822
2823 /**
2824  * @brief Tell SMC to enabled the supported DPMs.
2825  *
2826  * @param    hwmgr - the address of the powerplay hardware manager.
2827  * @Param    bitmap - bitmap for the features to enabled.
2828  * @return   0 on at least one DPM is successfully enabled.
2829  */
2830 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2831 {
2832         struct vega10_hwmgr *data = hwmgr->backend;
2833         uint32_t i, feature_mask = 0;
2834
2835         for (i = 0; i < GNLD_DPM_MAX; i++) {
2836                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2837                         if (data->smu_features[i].supported) {
2838                                 if (!data->smu_features[i].enabled) {
2839                                         feature_mask |= data->smu_features[i].
2840                                                         smu_feature_bitmap;
2841                                         data->smu_features[i].enabled = true;
2842                                 }
2843                         }
2844                 }
2845         }
2846
2847         if (vega10_enable_smc_features(hwmgr,
2848                         true, feature_mask)) {
2849                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2850                         if (data->smu_features[i].smu_feature_bitmap &
2851                                         feature_mask)
2852                                 data->smu_features[i].enabled = false;
2853                 }
2854         }
2855
2856         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2857                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2858                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2859                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2860                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2861         }
2862
2863         if (data->vbios_boot_state.bsoc_vddc_lock) {
2864                 smum_send_msg_to_smc_with_parameter(hwmgr,
2865                                                 PPSMC_MSG_SetFloorSocVoltage, 0);
2866                 data->vbios_boot_state.bsoc_vddc_lock = false;
2867         }
2868
2869         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2870                 if (data->smu_features[GNLD_ACDC].supported) {
2871                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2872                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2873                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2874                                         return -1);
2875                         data->smu_features[GNLD_ACDC].enabled = true;
2876                 }
2877         }
2878
2879         return 0;
2880 }
2881
2882 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2883 {
2884         struct vega10_hwmgr *data = hwmgr->backend;
2885
2886         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2887                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2888                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2889                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2890                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2891                                 "Attempt to Enable PCC Limit feature Failed!",
2892                                 return -EINVAL);
2893                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
2894         }
2895
2896         return 0;
2897 }
2898
2899 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2900 {
2901         struct vega10_hwmgr *data = hwmgr->backend;
2902         int tmp_result, result = 0;
2903
2904         vega10_enable_disable_PCC_limit_feature(hwmgr, true);
2905
2906         smum_send_msg_to_smc_with_parameter(hwmgr,
2907                 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2908
2909         tmp_result = vega10_construct_voltage_tables(hwmgr);
2910         PP_ASSERT_WITH_CODE(!tmp_result,
2911                         "Failed to construct voltage tables!",
2912                         result = tmp_result);
2913
2914         tmp_result = vega10_init_smc_table(hwmgr);
2915         PP_ASSERT_WITH_CODE(!tmp_result,
2916                         "Failed to initialize SMC table!",
2917                         result = tmp_result);
2918
2919         if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
2920                 tmp_result = vega10_enable_thermal_protection(hwmgr);
2921                 PP_ASSERT_WITH_CODE(!tmp_result,
2922                                 "Failed to enable thermal protection!",
2923                                 result = tmp_result);
2924         }
2925
2926         tmp_result = vega10_enable_vrhot_feature(hwmgr);
2927         PP_ASSERT_WITH_CODE(!tmp_result,
2928                         "Failed to enable VR hot feature!",
2929                         result = tmp_result);
2930
2931         tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
2932         PP_ASSERT_WITH_CODE(!tmp_result,
2933                         "Failed to enable deep sleep master switch!",
2934                         result = tmp_result);
2935
2936         tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
2937         PP_ASSERT_WITH_CODE(!tmp_result,
2938                         "Failed to start DPM!", result = tmp_result);
2939
2940         /* enable didt, do not abort if failed didt */
2941         tmp_result = vega10_enable_didt_config(hwmgr);
2942         PP_ASSERT(!tmp_result,
2943                         "Failed to enable didt config!");
2944
2945         tmp_result = vega10_enable_power_containment(hwmgr);
2946         PP_ASSERT_WITH_CODE(!tmp_result,
2947                         "Failed to enable power containment!",
2948                         result = tmp_result);
2949
2950         tmp_result = vega10_power_control_set_level(hwmgr);
2951         PP_ASSERT_WITH_CODE(!tmp_result,
2952                         "Failed to power control set level!",
2953                         result = tmp_result);
2954
2955         tmp_result = vega10_enable_ulv(hwmgr);
2956         PP_ASSERT_WITH_CODE(!tmp_result,
2957                         "Failed to enable ULV!",
2958                         result = tmp_result);
2959
2960         return result;
2961 }
2962
2963 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
2964 {
2965         return sizeof(struct vega10_power_state);
2966 }
2967
2968 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
2969                 void *state, struct pp_power_state *power_state,
2970                 void *pp_table, uint32_t classification_flag)
2971 {
2972         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
2973         struct vega10_power_state *vega10_power_state =
2974                         cast_phw_vega10_power_state(&(power_state->hardware));
2975         struct vega10_performance_level *performance_level;
2976         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
2977         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
2978                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
2979         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
2980                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
2981                         (((unsigned long)powerplay_table) +
2982                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
2983         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
2984                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
2985                         (((unsigned long)powerplay_table) +
2986                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
2987         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
2988                         (ATOM_Vega10_MCLK_Dependency_Table *)
2989                         (((unsigned long)powerplay_table) +
2990                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2991
2992
2993         /* The following fields are not initialized here:
2994          * id orderedList allStatesList
2995          */
2996         power_state->classification.ui_label =
2997                         (le16_to_cpu(state_entry->usClassification) &
2998                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2999                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3000         power_state->classification.flags = classification_flag;
3001         /* NOTE: There is a classification2 flag in BIOS
3002          * that is not being used right now
3003          */
3004         power_state->classification.temporary_state = false;
3005         power_state->classification.to_be_deleted = false;
3006
3007         power_state->validation.disallowOnDC =
3008                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3009                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3010
3011         power_state->display.disableFrameModulation = false;
3012         power_state->display.limitRefreshrate = false;
3013         power_state->display.enableVariBright =
3014                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3015                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3016
3017         power_state->validation.supportedPowerLevels = 0;
3018         power_state->uvd_clocks.VCLK = 0;
3019         power_state->uvd_clocks.DCLK = 0;
3020         power_state->temperatures.min = 0;
3021         power_state->temperatures.max = 0;
3022
3023         performance_level = &(vega10_power_state->performance_levels
3024                         [vega10_power_state->performance_level_count++]);
3025
3026         PP_ASSERT_WITH_CODE(
3027                         (vega10_power_state->performance_level_count <
3028                                         NUM_GFXCLK_DPM_LEVELS),
3029                         "Performance levels exceeds SMC limit!",
3030                         return -1);
3031
3032         PP_ASSERT_WITH_CODE(
3033                         (vega10_power_state->performance_level_count <=
3034                                         hwmgr->platform_descriptor.
3035                                         hardwareActivityPerformanceLevels),
3036                         "Performance levels exceeds Driver limit!",
3037                         return -1);
3038
3039         /* Performance levels are arranged from low to high. */
3040         performance_level->soc_clock = socclk_dep_table->entries
3041                         [state_entry->ucSocClockIndexLow].ulClk;
3042         performance_level->gfx_clock = gfxclk_dep_table->entries
3043                         [state_entry->ucGfxClockIndexLow].ulClk;
3044         performance_level->mem_clock = mclk_dep_table->entries
3045                         [state_entry->ucMemClockIndexLow].ulMemClk;
3046
3047         performance_level = &(vega10_power_state->performance_levels
3048                                 [vega10_power_state->performance_level_count++]);
3049         performance_level->soc_clock = socclk_dep_table->entries
3050                                 [state_entry->ucSocClockIndexHigh].ulClk;
3051         if (gfxclk_dep_table->ucRevId == 0) {
3052                 performance_level->gfx_clock = gfxclk_dep_table->entries
3053                         [state_entry->ucGfxClockIndexHigh].ulClk;
3054         } else if (gfxclk_dep_table->ucRevId == 1) {
3055                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3056                 performance_level->gfx_clock = patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3057         }
3058
3059         performance_level->mem_clock = mclk_dep_table->entries
3060                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3061         return 0;
3062 }
3063
3064 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3065                 unsigned long entry_index, struct pp_power_state *state)
3066 {
3067         int result;
3068         struct vega10_power_state *ps;
3069
3070         state->hardware.magic = PhwVega10_Magic;
3071
3072         ps = cast_phw_vega10_power_state(&state->hardware);
3073
3074         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3075                         vega10_get_pp_table_entry_callback_func);
3076
3077         /*
3078          * This is the earliest time we have all the dependency table
3079          * and the VBIOS boot state
3080          */
3081         /* set DC compatible flag if this state supports DC */
3082         if (!state->validation.disallowOnDC)
3083                 ps->dc_compatible = true;
3084
3085         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3086         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3087
3088         return 0;
3089 }
3090
3091 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3092              struct pp_hw_power_state *hw_ps)
3093 {
3094         return 0;
3095 }
3096
3097 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3098                                 struct pp_power_state  *request_ps,
3099                         const struct pp_power_state *current_ps)
3100 {
3101         struct amdgpu_device *adev = hwmgr->adev;
3102         struct vega10_power_state *vega10_ps =
3103                                 cast_phw_vega10_power_state(&request_ps->hardware);
3104         uint32_t sclk;
3105         uint32_t mclk;
3106         struct PP_Clocks minimum_clocks = {0};
3107         bool disable_mclk_switching;
3108         bool disable_mclk_switching_for_frame_lock;
3109         bool disable_mclk_switching_for_vr;
3110         bool force_mclk_high;
3111         const struct phm_clock_and_voltage_limits *max_limits;
3112         uint32_t i;
3113         struct vega10_hwmgr *data = hwmgr->backend;
3114         struct phm_ppt_v2_information *table_info =
3115                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3116         int32_t count;
3117         uint32_t stable_pstate_sclk_dpm_percentage;
3118         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3119         uint32_t latency;
3120
3121         data->battery_state = (PP_StateUILabel_Battery ==
3122                         request_ps->classification.ui_label);
3123
3124         if (vega10_ps->performance_level_count != 2)
3125                 pr_info("VI should always have 2 performance levels");
3126
3127         max_limits = adev->pm.ac_power ?
3128                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3129                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3130
3131         /* Cap clock DPM tables at DC MAX if it is in DC. */
3132         if (!adev->pm.ac_power) {
3133                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3134                         if (vega10_ps->performance_levels[i].mem_clock >
3135                                 max_limits->mclk)
3136                                 vega10_ps->performance_levels[i].mem_clock =
3137                                                 max_limits->mclk;
3138                         if (vega10_ps->performance_levels[i].gfx_clock >
3139                                 max_limits->sclk)
3140                                 vega10_ps->performance_levels[i].gfx_clock =
3141                                                 max_limits->sclk;
3142                 }
3143         }
3144
3145         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3146         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3147         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3148
3149         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3150                 stable_pstate_sclk_dpm_percentage =
3151                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3152                 PP_ASSERT_WITH_CODE(
3153                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3154                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3155                         "percent sclk value must range from 1% to 100%, setting default value",
3156                         stable_pstate_sclk_dpm_percentage = 75);
3157
3158                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3159                 stable_pstate_sclk = (max_limits->sclk *
3160                                 stable_pstate_sclk_dpm_percentage) / 100;
3161
3162                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3163                                 count >= 0; count--) {
3164                         if (stable_pstate_sclk >=
3165                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3166                                 stable_pstate_sclk =
3167                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3168                                 break;
3169                         }
3170                 }
3171
3172                 if (count < 0)
3173                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3174
3175                 stable_pstate_mclk = max_limits->mclk;
3176
3177                 minimum_clocks.engineClock = stable_pstate_sclk;
3178                 minimum_clocks.memoryClock = stable_pstate_mclk;
3179         }
3180
3181         disable_mclk_switching_for_frame_lock =
3182                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3183         disable_mclk_switching_for_vr =
3184                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3185         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3186
3187         if (hwmgr->display_config->num_display == 0)
3188                 disable_mclk_switching = false;
3189         else
3190                 disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
3191                         disable_mclk_switching_for_frame_lock ||
3192                         disable_mclk_switching_for_vr ||
3193                         force_mclk_high;
3194
3195         sclk = vega10_ps->performance_levels[0].gfx_clock;
3196         mclk = vega10_ps->performance_levels[0].mem_clock;
3197
3198         if (sclk < minimum_clocks.engineClock)
3199                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3200                                 max_limits->sclk : minimum_clocks.engineClock;
3201
3202         if (mclk < minimum_clocks.memoryClock)
3203                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3204                                 max_limits->mclk : minimum_clocks.memoryClock;
3205
3206         vega10_ps->performance_levels[0].gfx_clock = sclk;
3207         vega10_ps->performance_levels[0].mem_clock = mclk;
3208
3209         if (vega10_ps->performance_levels[1].gfx_clock <
3210                         vega10_ps->performance_levels[0].gfx_clock)
3211                 vega10_ps->performance_levels[0].gfx_clock =
3212                                 vega10_ps->performance_levels[1].gfx_clock;
3213
3214         if (disable_mclk_switching) {
3215                 /* Set Mclk the max of level 0 and level 1 */
3216                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3217                         mclk = vega10_ps->performance_levels[1].mem_clock;
3218
3219                 /* Find the lowest MCLK frequency that is within
3220                  * the tolerable latency defined in DAL
3221                  */
3222                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3223                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3224                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3225                                 (data->mclk_latency_table.entries[i].frequency >=
3226                                                 vega10_ps->performance_levels[0].mem_clock) &&
3227                                 (data->mclk_latency_table.entries[i].frequency <=
3228                                                 vega10_ps->performance_levels[1].mem_clock))
3229                                 mclk = data->mclk_latency_table.entries[i].frequency;
3230                 }
3231                 vega10_ps->performance_levels[0].mem_clock = mclk;
3232         } else {
3233                 if (vega10_ps->performance_levels[1].mem_clock <
3234                                 vega10_ps->performance_levels[0].mem_clock)
3235                         vega10_ps->performance_levels[0].mem_clock =
3236                                         vega10_ps->performance_levels[1].mem_clock;
3237         }
3238
3239         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3240                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3241                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3242                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3243                 }
3244         }
3245
3246         return 0;
3247 }
3248
3249 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3250 {
3251         struct vega10_hwmgr *data = hwmgr->backend;
3252
3253         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3254                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3255
3256         return 0;
3257 }
3258
3259 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3260                 struct pp_hwmgr *hwmgr, const void *input)
3261 {
3262         int result = 0;
3263         struct vega10_hwmgr *data = hwmgr->backend;
3264         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3265         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3266         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3267         int count;
3268
3269         if (!data->need_update_dpm_table)
3270                 return 0;
3271
3272         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3273                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3274                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3275         }
3276
3277         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3278         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3279                 for (count = 0; count < dpm_table->mem_table.count; count++)
3280                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3281         }
3282
3283         if (data->need_update_dpm_table &
3284                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {
3285                 result = vega10_populate_all_graphic_levels(hwmgr);
3286                 PP_ASSERT_WITH_CODE((0 == result),
3287                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3288                                 return result);
3289         }
3290
3291         if (data->need_update_dpm_table &
3292                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3293                 result = vega10_populate_all_memory_levels(hwmgr);
3294                 PP_ASSERT_WITH_CODE((0 == result),
3295                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3296                                 return result);
3297         }
3298
3299         vega10_populate_vddc_soc_levels(hwmgr);
3300
3301         return result;
3302 }
3303
3304 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3305                 struct vega10_single_dpm_table *dpm_table,
3306                 uint32_t low_limit, uint32_t high_limit)
3307 {
3308         uint32_t i;
3309
3310         for (i = 0; i < dpm_table->count; i++) {
3311                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3312                     (dpm_table->dpm_levels[i].value > high_limit))
3313                         dpm_table->dpm_levels[i].enabled = false;
3314                 else
3315                         dpm_table->dpm_levels[i].enabled = true;
3316         }
3317         return 0;
3318 }
3319
3320 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3321                 struct vega10_single_dpm_table *dpm_table,
3322                 uint32_t low_limit, uint32_t high_limit,
3323                 uint32_t disable_dpm_mask)
3324 {
3325         uint32_t i;
3326
3327         for (i = 0; i < dpm_table->count; i++) {
3328                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3329                     (dpm_table->dpm_levels[i].value > high_limit))
3330                         dpm_table->dpm_levels[i].enabled = false;
3331                 else if (!((1 << i) & disable_dpm_mask))
3332                         dpm_table->dpm_levels[i].enabled = false;
3333                 else
3334                         dpm_table->dpm_levels[i].enabled = true;
3335         }
3336         return 0;
3337 }
3338
3339 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3340                 const struct vega10_power_state *vega10_ps)
3341 {
3342         struct vega10_hwmgr *data = hwmgr->backend;
3343         uint32_t high_limit_count;
3344
3345         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3346                         "power state did not have any performance level",
3347                         return -1);
3348
3349         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3350
3351         vega10_trim_single_dpm_states(hwmgr,
3352                         &(data->dpm_table.soc_table),
3353                         vega10_ps->performance_levels[0].soc_clock,
3354                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3355
3356         vega10_trim_single_dpm_states_with_mask(hwmgr,
3357                         &(data->dpm_table.gfx_table),
3358                         vega10_ps->performance_levels[0].gfx_clock,
3359                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3360                         data->disable_dpm_mask);
3361
3362         vega10_trim_single_dpm_states(hwmgr,
3363                         &(data->dpm_table.mem_table),
3364                         vega10_ps->performance_levels[0].mem_clock,
3365                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3366
3367         return 0;
3368 }
3369
3370 static uint32_t vega10_find_lowest_dpm_level(
3371                 struct vega10_single_dpm_table *table)
3372 {
3373         uint32_t i;
3374
3375         for (i = 0; i < table->count; i++) {
3376                 if (table->dpm_levels[i].enabled)
3377                         break;
3378         }
3379
3380         return i;
3381 }
3382
3383 static uint32_t vega10_find_highest_dpm_level(
3384                 struct vega10_single_dpm_table *table)
3385 {
3386         uint32_t i = 0;
3387
3388         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3389                 for (i = table->count; i > 0; i--) {
3390                         if (table->dpm_levels[i - 1].enabled)
3391                                 return i - 1;
3392                 }
3393         } else {
3394                 pr_info("DPM Table Has Too Many Entries!");
3395                 return MAX_REGULAR_DPM_NUMBER - 1;
3396         }
3397
3398         return i;
3399 }
3400
3401 static void vega10_apply_dal_minimum_voltage_request(
3402                 struct pp_hwmgr *hwmgr)
3403 {
3404         return;
3405 }
3406
3407 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3408 {
3409         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3410         struct phm_ppt_v2_information *table_info =
3411                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3412
3413         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3414
3415         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3416 }
3417
3418 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3419 {
3420         struct vega10_hwmgr *data = hwmgr->backend;
3421         uint32_t socclk_idx;
3422
3423         vega10_apply_dal_minimum_voltage_request(hwmgr);
3424
3425         if (!data->registry_data.sclk_dpm_key_disabled) {
3426                 if (data->smc_state_table.gfx_boot_level !=
3427                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3428                         smum_send_msg_to_smc_with_parameter(hwmgr,
3429                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3430                                 data->smc_state_table.gfx_boot_level);
3431                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3432                                         data->smc_state_table.gfx_boot_level;
3433                 }
3434         }
3435
3436         if (!data->registry_data.mclk_dpm_key_disabled) {
3437                 if (data->smc_state_table.mem_boot_level !=
3438                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3439                         if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
3440                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3441                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3442                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3443                                                 socclk_idx);
3444                         } else {
3445                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3446                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3447                                                 data->smc_state_table.mem_boot_level);
3448                         }
3449                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3450                                         data->smc_state_table.mem_boot_level;
3451                 }
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3458 {
3459         struct vega10_hwmgr *data = hwmgr->backend;
3460
3461         vega10_apply_dal_minimum_voltage_request(hwmgr);
3462
3463         if (!data->registry_data.sclk_dpm_key_disabled) {
3464                 if (data->smc_state_table.gfx_max_level !=
3465                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3466                         smum_send_msg_to_smc_with_parameter(hwmgr,
3467                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3468                                 data->smc_state_table.gfx_max_level);
3469                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3470                                         data->smc_state_table.gfx_max_level;
3471                 }
3472         }
3473
3474         if (!data->registry_data.mclk_dpm_key_disabled) {
3475                 if (data->smc_state_table.mem_max_level !=
3476                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3477                         smum_send_msg_to_smc_with_parameter(hwmgr,
3478                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3479                                         data->smc_state_table.mem_max_level);
3480                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3481                                         data->smc_state_table.mem_max_level;
3482                 }
3483         }
3484
3485         return 0;
3486 }
3487
3488 static int vega10_generate_dpm_level_enable_mask(
3489                 struct pp_hwmgr *hwmgr, const void *input)
3490 {
3491         struct vega10_hwmgr *data = hwmgr->backend;
3492         const struct phm_set_power_state_input *states =
3493                         (const struct phm_set_power_state_input *)input;
3494         const struct vega10_power_state *vega10_ps =
3495                         cast_const_phw_vega10_power_state(states->pnew_state);
3496         int i;
3497
3498         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3499                         "Attempt to Trim DPM States Failed!",
3500                         return -1);
3501
3502         data->smc_state_table.gfx_boot_level =
3503                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3504         data->smc_state_table.gfx_max_level =
3505                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3506         data->smc_state_table.mem_boot_level =
3507                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3508         data->smc_state_table.mem_max_level =
3509                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3510
3511         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3512                         "Attempt to upload DPM Bootup Levels Failed!",
3513                         return -1);
3514         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3515                         "Attempt to upload DPM Max Levels Failed!",
3516                         return -1);
3517         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3518                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3519
3520
3521         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3522                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3523
3524         return 0;
3525 }
3526
3527 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3528 {
3529         struct vega10_hwmgr *data = hwmgr->backend;
3530
3531         if (data->smu_features[GNLD_DPM_VCE].supported) {
3532                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3533                                 enable,
3534                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3535                                 "Attempt to Enable/Disable DPM VCE Failed!",
3536                                 return -1);
3537                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3538         }
3539
3540         return 0;
3541 }
3542
3543 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3544 {
3545         struct vega10_hwmgr *data = hwmgr->backend;
3546         uint32_t low_sclk_interrupt_threshold = 0;
3547
3548         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3549                 (data->low_sclk_interrupt_threshold != 0)) {
3550                 low_sclk_interrupt_threshold =
3551                                 data->low_sclk_interrupt_threshold;
3552
3553                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3554                                 cpu_to_le32(low_sclk_interrupt_threshold);
3555
3556                 /* This message will also enable SmcToHost Interrupt */
3557                 smum_send_msg_to_smc_with_parameter(hwmgr,
3558                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3559                                 (uint32_t)low_sclk_interrupt_threshold);
3560         }
3561
3562         return 0;
3563 }
3564
3565 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3566                 const void *input)
3567 {
3568         int tmp_result, result = 0;
3569         struct vega10_hwmgr *data = hwmgr->backend;
3570         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3571
3572         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3573         PP_ASSERT_WITH_CODE(!tmp_result,
3574                         "Failed to find DPM states clocks in DPM table!",
3575                         result = tmp_result);
3576
3577         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3578         PP_ASSERT_WITH_CODE(!tmp_result,
3579                         "Failed to populate and upload SCLK MCLK DPM levels!",
3580                         result = tmp_result);
3581
3582         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3583         PP_ASSERT_WITH_CODE(!tmp_result,
3584                         "Failed to generate DPM level enabled mask!",
3585                         result = tmp_result);
3586
3587         tmp_result = vega10_update_sclk_threshold(hwmgr);
3588         PP_ASSERT_WITH_CODE(!tmp_result,
3589                         "Failed to update SCLK threshold!",
3590                         result = tmp_result);
3591
3592         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3593         PP_ASSERT_WITH_CODE(!result,
3594                         "Failed to upload PPtable!", return result);
3595
3596         vega10_update_avfs(hwmgr);
3597
3598         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3599
3600         return 0;
3601 }
3602
3603 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3604 {
3605         struct pp_power_state *ps;
3606         struct vega10_power_state *vega10_ps;
3607
3608         if (hwmgr == NULL)
3609                 return -EINVAL;
3610
3611         ps = hwmgr->request_ps;
3612
3613         if (ps == NULL)
3614                 return -EINVAL;
3615
3616         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3617
3618         if (low)
3619                 return vega10_ps->performance_levels[0].gfx_clock;
3620         else
3621                 return vega10_ps->performance_levels
3622                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3623 }
3624
3625 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3626 {
3627         struct pp_power_state *ps;
3628         struct vega10_power_state *vega10_ps;
3629
3630         if (hwmgr == NULL)
3631                 return -EINVAL;
3632
3633         ps = hwmgr->request_ps;
3634
3635         if (ps == NULL)
3636                 return -EINVAL;
3637
3638         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3639
3640         if (low)
3641                 return vega10_ps->performance_levels[0].mem_clock;
3642         else
3643                 return vega10_ps->performance_levels
3644                                 [vega10_ps->performance_level_count-1].mem_clock;
3645 }
3646
3647 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3648                 uint32_t *query)
3649 {
3650         uint32_t value;
3651
3652         if (!query)
3653                 return -EINVAL;
3654
3655         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
3656         value = smum_get_argument(hwmgr);
3657
3658         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3659         *query = value << 8;
3660
3661         return 0;
3662 }
3663
3664 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3665                               void *value, int *size)
3666 {
3667         struct amdgpu_device *adev = hwmgr->adev;
3668         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3669         struct vega10_hwmgr *data = hwmgr->backend;
3670         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3671         int ret = 0;
3672         uint32_t val_vid;
3673
3674         switch (idx) {
3675         case AMDGPU_PP_SENSOR_GFX_SCLK:
3676                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
3677                 sclk_mhz = smum_get_argument(hwmgr);
3678                 *((uint32_t *)value) = sclk_mhz * 100;
3679                 break;
3680         case AMDGPU_PP_SENSOR_GFX_MCLK:
3681                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
3682                 mclk_idx = smum_get_argument(hwmgr);
3683                 if (mclk_idx < dpm_table->mem_table.count) {
3684                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3685                         *size = 4;
3686                 } else {
3687                         ret = -EINVAL;
3688                 }
3689                 break;
3690         case AMDGPU_PP_SENSOR_GPU_LOAD:
3691                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3692                 activity_percent = smum_get_argument(hwmgr);
3693                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3694                 *size = 4;
3695                 break;
3696         case AMDGPU_PP_SENSOR_GPU_TEMP:
3697                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3698                 *size = 4;
3699                 break;
3700         case AMDGPU_PP_SENSOR_UVD_POWER:
3701                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3702                 *size = 4;
3703                 break;
3704         case AMDGPU_PP_SENSOR_VCE_POWER:
3705                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3706                 *size = 4;
3707                 break;
3708         case AMDGPU_PP_SENSOR_GPU_POWER:
3709                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3710                 break;
3711         case AMDGPU_PP_SENSOR_VDDGFX:
3712                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3713                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3714                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3715                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3716                 return 0;
3717         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3718                 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3719                 if (!ret)
3720                         *size = 8;
3721                 break;
3722         default:
3723                 ret = -EINVAL;
3724                 break;
3725         }
3726
3727         return ret;
3728 }
3729
3730 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3731                 bool has_disp)
3732 {
3733         smum_send_msg_to_smc_with_parameter(hwmgr,
3734                         PPSMC_MSG_SetUclkFastSwitch,
3735                         has_disp ? 1 : 0);
3736 }
3737
3738 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3739                 struct pp_display_clock_request *clock_req)
3740 {
3741         int result = 0;
3742         enum amd_pp_clock_type clk_type = clock_req->clock_type;
3743         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3744         DSPCLK_e clk_select = 0;
3745         uint32_t clk_request = 0;
3746
3747         switch (clk_type) {
3748         case amd_pp_dcef_clock:
3749                 clk_select = DSPCLK_DCEFCLK;
3750                 break;
3751         case amd_pp_disp_clock:
3752                 clk_select = DSPCLK_DISPCLK;
3753                 break;
3754         case amd_pp_pixel_clock:
3755                 clk_select = DSPCLK_PIXCLK;
3756                 break;
3757         case amd_pp_phy_clock:
3758                 clk_select = DSPCLK_PHYCLK;
3759                 break;
3760         default:
3761                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3762                 result = -1;
3763                 break;
3764         }
3765
3766         if (!result) {
3767                 clk_request = (clk_freq << 16) | clk_select;
3768                 smum_send_msg_to_smc_with_parameter(hwmgr,
3769                                 PPSMC_MSG_RequestDisplayClockByFreq,
3770                                 clk_request);
3771         }
3772
3773         return result;
3774 }
3775
3776 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
3777                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
3778                                                 uint32_t frequency)
3779 {
3780         uint8_t count;
3781         uint8_t i;
3782
3783         if (mclk_table == NULL || mclk_table->count == 0)
3784                 return 0;
3785
3786         count = (uint8_t)(mclk_table->count);
3787
3788         for(i = 0; i < count; i++) {
3789                 if(mclk_table->entries[i].clk >= frequency)
3790                         return i;
3791         }
3792
3793         return i-1;
3794 }
3795
3796 static int vega10_notify_smc_display_config_after_ps_adjustment(
3797                 struct pp_hwmgr *hwmgr)
3798 {
3799         struct vega10_hwmgr *data = hwmgr->backend;
3800         struct vega10_single_dpm_table *dpm_table =
3801                         &data->dpm_table.dcef_table;
3802         struct phm_ppt_v2_information *table_info =
3803                         (struct phm_ppt_v2_information *)hwmgr->pptable;
3804         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
3805         uint32_t idx;
3806         struct PP_Clocks min_clocks = {0};
3807         uint32_t i;
3808         struct pp_display_clock_request clock_req;
3809
3810         if ((hwmgr->display_config->num_display > 1) &&
3811              !hwmgr->display_config->multi_monitor_in_sync &&
3812              !hwmgr->display_config->nb_pstate_switch_disable)
3813                 vega10_notify_smc_display_change(hwmgr, false);
3814         else
3815                 vega10_notify_smc_display_change(hwmgr, true);
3816
3817         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3818         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3819         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3820
3821         for (i = 0; i < dpm_table->count; i++) {
3822                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
3823                         break;
3824         }
3825
3826         if (i < dpm_table->count) {
3827                 clock_req.clock_type = amd_pp_dcef_clock;
3828                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
3829                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
3830                         smum_send_msg_to_smc_with_parameter(
3831                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
3832                                         min_clocks.dcefClockInSR / 100);
3833                 } else {
3834                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3835                 }
3836         } else {
3837                 pr_debug("Cannot find requested DCEFCLK!");
3838         }
3839
3840         if (min_clocks.memoryClock != 0) {
3841                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
3842                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
3843                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
3844         }
3845
3846         return 0;
3847 }
3848
3849 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3850 {
3851         struct vega10_hwmgr *data = hwmgr->backend;
3852
3853         data->smc_state_table.gfx_boot_level =
3854         data->smc_state_table.gfx_max_level =
3855                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3856         data->smc_state_table.mem_boot_level =
3857         data->smc_state_table.mem_max_level =
3858                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3859
3860         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3861                         "Failed to upload boot level to highest!",
3862                         return -1);
3863
3864         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3865                         "Failed to upload dpm max level to highest!",
3866                         return -1);
3867
3868         return 0;
3869 }
3870
3871 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3872 {
3873         struct vega10_hwmgr *data = hwmgr->backend;
3874
3875         data->smc_state_table.gfx_boot_level =
3876         data->smc_state_table.gfx_max_level =
3877                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3878         data->smc_state_table.mem_boot_level =
3879         data->smc_state_table.mem_max_level =
3880                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3881
3882         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3883                         "Failed to upload boot level to highest!",
3884                         return -1);
3885
3886         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3887                         "Failed to upload dpm max level to highest!",
3888                         return -1);
3889
3890         return 0;
3891
3892 }
3893
3894 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3895 {
3896         struct vega10_hwmgr *data = hwmgr->backend;
3897
3898         data->smc_state_table.gfx_boot_level =
3899                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3900         data->smc_state_table.gfx_max_level =
3901                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3902         data->smc_state_table.mem_boot_level =
3903                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3904         data->smc_state_table.mem_max_level =
3905                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3906
3907         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3908                         "Failed to upload DPM Bootup Levels!",
3909                         return -1);
3910
3911         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3912                         "Failed to upload DPM Max Levels!",
3913                         return -1);
3914         return 0;
3915 }
3916
3917 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3918                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
3919 {
3920         struct phm_ppt_v2_information *table_info =
3921                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3922
3923         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3924                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
3925                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3926                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
3927                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
3928                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
3929                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3930                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3931         }
3932
3933         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3934                 *sclk_mask = 0;
3935         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3936                 *mclk_mask = 0;
3937         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3938                 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3939                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
3940                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
3941         }
3942         return 0;
3943 }
3944
3945 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
3946 {
3947         switch (mode) {
3948         case AMD_FAN_CTRL_NONE:
3949                 vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
3950                 break;
3951         case AMD_FAN_CTRL_MANUAL:
3952                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3953                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
3954                 break;
3955         case AMD_FAN_CTRL_AUTO:
3956                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3957                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
3958                 break;
3959         default:
3960                 break;
3961         }
3962 }
3963
3964 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
3965                 enum pp_clock_type type, uint32_t mask)
3966 {
3967         struct vega10_hwmgr *data = hwmgr->backend;
3968
3969         switch (type) {
3970         case PP_SCLK:
3971                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
3972                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
3973
3974                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3975                         "Failed to upload boot level to lowest!",
3976                         return -EINVAL);
3977
3978                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3979                         "Failed to upload dpm max level to highest!",
3980                         return -EINVAL);
3981                 break;
3982
3983         case PP_MCLK:
3984                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
3985                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
3986
3987                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3988                         "Failed to upload boot level to lowest!",
3989                         return -EINVAL);
3990
3991                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3992                         "Failed to upload dpm max level to highest!",
3993                         return -EINVAL);
3994
3995                 break;
3996
3997         case PP_PCIE:
3998         default:
3999                 break;
4000         }
4001
4002         return 0;
4003 }
4004
4005 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4006                                 enum amd_dpm_forced_level level)
4007 {
4008         int ret = 0;
4009         uint32_t sclk_mask = 0;
4010         uint32_t mclk_mask = 0;
4011         uint32_t soc_mask = 0;
4012
4013         if (hwmgr->pstate_sclk == 0)
4014                 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4015
4016         switch (level) {
4017         case AMD_DPM_FORCED_LEVEL_HIGH:
4018                 ret = vega10_force_dpm_highest(hwmgr);
4019                 break;
4020         case AMD_DPM_FORCED_LEVEL_LOW:
4021                 ret = vega10_force_dpm_lowest(hwmgr);
4022                 break;
4023         case AMD_DPM_FORCED_LEVEL_AUTO:
4024                 ret = vega10_unforce_dpm_levels(hwmgr);
4025                 break;
4026         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4027         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4028         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4029         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4030                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4031                 if (ret)
4032                         return ret;
4033                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4034                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4035                 break;
4036         case AMD_DPM_FORCED_LEVEL_MANUAL:
4037         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4038         default:
4039                 break;
4040         }
4041
4042         if (!ret) {
4043                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4044                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4045                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4046                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4047         }
4048
4049         return ret;
4050 }
4051
4052 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4053 {
4054         struct vega10_hwmgr *data = hwmgr->backend;
4055
4056         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4057                 return AMD_FAN_CTRL_MANUAL;
4058         else
4059                 return AMD_FAN_CTRL_AUTO;
4060 }
4061
4062 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4063                 struct amd_pp_simple_clock_info *info)
4064 {
4065         struct phm_ppt_v2_information *table_info =
4066                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4067         struct phm_clock_and_voltage_limits *max_limits =
4068                         &table_info->max_clock_voltage_on_ac;
4069
4070         info->engine_max_clock = max_limits->sclk;
4071         info->memory_max_clock = max_limits->mclk;
4072
4073         return 0;
4074 }
4075
4076 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4077                 struct pp_clock_levels_with_latency *clocks)
4078 {
4079         struct phm_ppt_v2_information *table_info =
4080                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4081         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4082                         table_info->vdd_dep_on_sclk;
4083         uint32_t i;
4084
4085         clocks->num_levels = 0;
4086         for (i = 0; i < dep_table->count; i++) {
4087                 if (dep_table->entries[i].clk) {
4088                         clocks->data[clocks->num_levels].clocks_in_khz =
4089                                         dep_table->entries[i].clk * 10;
4090                         clocks->num_levels++;
4091                 }
4092         }
4093
4094 }
4095
4096 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4097                 struct pp_clock_levels_with_latency *clocks)
4098 {
4099         struct phm_ppt_v2_information *table_info =
4100                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4101         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4102                         table_info->vdd_dep_on_mclk;
4103         struct vega10_hwmgr *data = hwmgr->backend;
4104         uint32_t j = 0;
4105         uint32_t i;
4106
4107         for (i = 0; i < dep_table->count; i++) {
4108                 if (dep_table->entries[i].clk) {
4109
4110                         clocks->data[j].clocks_in_khz =
4111                                                 dep_table->entries[i].clk * 10;
4112                         data->mclk_latency_table.entries[j].frequency =
4113                                                         dep_table->entries[i].clk;
4114                         clocks->data[j].latency_in_us =
4115                                 data->mclk_latency_table.entries[j].latency = 25;
4116                         j++;
4117                 }
4118         }
4119         clocks->num_levels = data->mclk_latency_table.count = j;
4120 }
4121
4122 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4123                 struct pp_clock_levels_with_latency *clocks)
4124 {
4125         struct phm_ppt_v2_information *table_info =
4126                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4127         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4128                         table_info->vdd_dep_on_dcefclk;
4129         uint32_t i;
4130
4131         for (i = 0; i < dep_table->count; i++) {
4132                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4133                 clocks->data[i].latency_in_us = 0;
4134                 clocks->num_levels++;
4135         }
4136 }
4137
4138 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4139                 struct pp_clock_levels_with_latency *clocks)
4140 {
4141         struct phm_ppt_v2_information *table_info =
4142                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4143         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4144                         table_info->vdd_dep_on_socclk;
4145         uint32_t i;
4146
4147         for (i = 0; i < dep_table->count; i++) {
4148                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4149                 clocks->data[i].latency_in_us = 0;
4150                 clocks->num_levels++;
4151         }
4152 }
4153
4154 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4155                 enum amd_pp_clock_type type,
4156                 struct pp_clock_levels_with_latency *clocks)
4157 {
4158         switch (type) {
4159         case amd_pp_sys_clock:
4160                 vega10_get_sclks(hwmgr, clocks);
4161                 break;
4162         case amd_pp_mem_clock:
4163                 vega10_get_memclocks(hwmgr, clocks);
4164                 break;
4165         case amd_pp_dcef_clock:
4166                 vega10_get_dcefclocks(hwmgr, clocks);
4167                 break;
4168         case amd_pp_soc_clock:
4169                 vega10_get_socclocks(hwmgr, clocks);
4170                 break;
4171         default:
4172                 return -1;
4173         }
4174
4175         return 0;
4176 }
4177
4178 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4179                 enum amd_pp_clock_type type,
4180                 struct pp_clock_levels_with_voltage *clocks)
4181 {
4182         struct phm_ppt_v2_information *table_info =
4183                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4184         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4185         uint32_t i;
4186
4187         switch (type) {
4188         case amd_pp_mem_clock:
4189                 dep_table = table_info->vdd_dep_on_mclk;
4190                 break;
4191         case amd_pp_dcef_clock:
4192                 dep_table = table_info->vdd_dep_on_dcefclk;
4193                 break;
4194         case amd_pp_disp_clock:
4195                 dep_table = table_info->vdd_dep_on_dispclk;
4196                 break;
4197         case amd_pp_pixel_clock:
4198                 dep_table = table_info->vdd_dep_on_pixclk;
4199                 break;
4200         case amd_pp_phy_clock:
4201                 dep_table = table_info->vdd_dep_on_phyclk;
4202                 break;
4203         default:
4204                 return -1;
4205         }
4206
4207         for (i = 0; i < dep_table->count; i++) {
4208                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4209                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4210                                 entries[dep_table->entries[i].vddInd].us_vdd);
4211                 clocks->num_levels++;
4212         }
4213
4214         if (i < dep_table->count)
4215                 return -1;
4216
4217         return 0;
4218 }
4219
4220 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4221                                                         void *clock_range)
4222 {
4223         struct vega10_hwmgr *data = hwmgr->backend;
4224         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4225         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4226         int result = 0;
4227
4228         if (!data->registry_data.disable_water_mark) {
4229                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4230                 data->water_marks_bitmap = WaterMarksExist;
4231         }
4232
4233         return result;
4234 }
4235
4236 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4237                 enum pp_clock_type type, char *buf)
4238 {
4239         struct vega10_hwmgr *data = hwmgr->backend;
4240         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4241         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4242         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4243         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4244
4245         int i, now, size = 0;
4246
4247         switch (type) {
4248         case PP_SCLK:
4249                 if (data->registry_data.sclk_dpm_key_disabled)
4250                         break;
4251
4252                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
4253                 now = smum_get_argument(hwmgr);
4254
4255                 for (i = 0; i < sclk_table->count; i++)
4256                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4257                                         i, sclk_table->dpm_levels[i].value / 100,
4258                                         (i == now) ? "*" : "");
4259                 break;
4260         case PP_MCLK:
4261                 if (data->registry_data.mclk_dpm_key_disabled)
4262                         break;
4263
4264                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
4265                 now = smum_get_argument(hwmgr);
4266
4267                 for (i = 0; i < mclk_table->count; i++)
4268                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4269                                         i, mclk_table->dpm_levels[i].value / 100,
4270                                         (i == now) ? "*" : "");
4271                 break;
4272         case PP_PCIE:
4273                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
4274                 now = smum_get_argument(hwmgr);
4275
4276                 for (i = 0; i < pcie_table->count; i++)
4277                         size += sprintf(buf + size, "%d: %s %s\n", i,
4278                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
4279                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
4280                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
4281                                         (i == now) ? "*" : "");
4282                 break;
4283         case OD_SCLK:
4284                 if (hwmgr->od_enabled) {
4285                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4286                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4287                         for (i = 0; i < podn_vdd_dep->count; i++)
4288                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4289                                         i, podn_vdd_dep->entries[i].clk / 100,
4290                                                 podn_vdd_dep->entries[i].vddc);
4291                 }
4292                 break;
4293         case OD_MCLK:
4294                 if (hwmgr->od_enabled) {
4295                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4296                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4297                         for (i = 0; i < podn_vdd_dep->count; i++)
4298                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4299                                         i, podn_vdd_dep->entries[i].clk/100,
4300                                                 podn_vdd_dep->entries[i].vddc);
4301                 }
4302                 break;
4303         case OD_RANGE:
4304                 if (hwmgr->od_enabled) {
4305                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4306                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4307                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4308                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4309                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4310                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4311                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4312                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4313                                 data->odn_dpm_table.min_vddc,
4314                                 data->odn_dpm_table.max_vddc);
4315                 }
4316                 break;
4317         default:
4318                 break;
4319         }
4320         return size;
4321 }
4322
4323 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4324 {
4325         struct vega10_hwmgr *data = hwmgr->backend;
4326         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4327         int result = 0;
4328
4329         if ((data->water_marks_bitmap & WaterMarksExist) &&
4330                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4331                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4332                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4333                 data->water_marks_bitmap |= WaterMarksLoaded;
4334         }
4335
4336         if (data->water_marks_bitmap & WaterMarksLoaded) {
4337                 smum_send_msg_to_smc_with_parameter(hwmgr,
4338                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
4339         }
4340
4341         return result;
4342 }
4343
4344 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4345 {
4346         struct vega10_hwmgr *data = hwmgr->backend;
4347
4348         if (data->smu_features[GNLD_DPM_UVD].supported) {
4349                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4350                                 enable,
4351                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4352                                 "Attempt to Enable/Disable DPM UVD Failed!",
4353                                 return -1);
4354                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4355         }
4356         return 0;
4357 }
4358
4359 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4360 {
4361         struct vega10_hwmgr *data = hwmgr->backend;
4362
4363         data->vce_power_gated = bgate;
4364         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4365 }
4366
4367 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4368 {
4369         struct vega10_hwmgr *data = hwmgr->backend;
4370
4371         data->uvd_power_gated = bgate;
4372         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4373 }
4374
4375 static inline bool vega10_are_power_levels_equal(
4376                                 const struct vega10_performance_level *pl1,
4377                                 const struct vega10_performance_level *pl2)
4378 {
4379         return ((pl1->soc_clock == pl2->soc_clock) &&
4380                         (pl1->gfx_clock == pl2->gfx_clock) &&
4381                         (pl1->mem_clock == pl2->mem_clock));
4382 }
4383
4384 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4385                                 const struct pp_hw_power_state *pstate1,
4386                         const struct pp_hw_power_state *pstate2, bool *equal)
4387 {
4388         const struct vega10_power_state *psa;
4389         const struct vega10_power_state *psb;
4390         int i;
4391
4392         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4393                 return -EINVAL;
4394
4395         psa = cast_const_phw_vega10_power_state(pstate1);
4396         psb = cast_const_phw_vega10_power_state(pstate2);
4397         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4398         if (psa->performance_level_count != psb->performance_level_count) {
4399                 *equal = false;
4400                 return 0;
4401         }
4402
4403         for (i = 0; i < psa->performance_level_count; i++) {
4404                 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4405                         /* If we have found even one performance level pair that is different the states are different. */
4406                         *equal = false;
4407                         return 0;
4408                 }
4409         }
4410
4411         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4412         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4413         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4414         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4415
4416         return 0;
4417 }
4418
4419 static bool
4420 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4421 {
4422         struct vega10_hwmgr *data = hwmgr->backend;
4423         bool is_update_required = false;
4424
4425         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4426                 is_update_required = true;
4427
4428         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4429                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4430                         is_update_required = true;
4431         }
4432
4433         return is_update_required;
4434 }
4435
4436 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4437 {
4438         int tmp_result, result = 0;
4439
4440         if (PP_CAP(PHM_PlatformCaps_ThermalController))
4441                 vega10_disable_thermal_protection(hwmgr);
4442
4443         tmp_result = vega10_disable_power_containment(hwmgr);
4444         PP_ASSERT_WITH_CODE((tmp_result == 0),
4445                         "Failed to disable power containment!", result = tmp_result);
4446
4447         tmp_result = vega10_disable_didt_config(hwmgr);
4448         PP_ASSERT_WITH_CODE((tmp_result == 0),
4449                         "Failed to disable didt config!", result = tmp_result);
4450
4451         tmp_result = vega10_avfs_enable(hwmgr, false);
4452         PP_ASSERT_WITH_CODE((tmp_result == 0),
4453                         "Failed to disable AVFS!", result = tmp_result);
4454
4455         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
4456         PP_ASSERT_WITH_CODE((tmp_result == 0),
4457                         "Failed to stop DPM!", result = tmp_result);
4458
4459         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
4460         PP_ASSERT_WITH_CODE((tmp_result == 0),
4461                         "Failed to disable deep sleep!", result = tmp_result);
4462
4463         tmp_result = vega10_disable_ulv(hwmgr);
4464         PP_ASSERT_WITH_CODE((tmp_result == 0),
4465                         "Failed to disable ulv!", result = tmp_result);
4466
4467         tmp_result =  vega10_acg_disable(hwmgr);
4468         PP_ASSERT_WITH_CODE((tmp_result == 0),
4469                         "Failed to disable acg!", result = tmp_result);
4470
4471         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
4472         return result;
4473 }
4474
4475 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4476 {
4477         struct vega10_hwmgr *data = hwmgr->backend;
4478         int result;
4479
4480         result = vega10_disable_dpm_tasks(hwmgr);
4481         PP_ASSERT_WITH_CODE((0 == result),
4482                         "[disable_dpm_tasks] Failed to disable DPM!",
4483                         );
4484         data->water_marks_bitmap &= ~(WaterMarksLoaded);
4485
4486         return result;
4487 }
4488
4489 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4490 {
4491         struct vega10_hwmgr *data = hwmgr->backend;
4492         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4493         struct vega10_single_dpm_table *golden_sclk_table =
4494                         &(data->golden_dpm_table.gfx_table);
4495         int value;
4496
4497         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4498                         golden_sclk_table->dpm_levels
4499                         [golden_sclk_table->count - 1].value) *
4500                         100 /
4501                         golden_sclk_table->dpm_levels
4502                         [golden_sclk_table->count - 1].value;
4503
4504         return value;
4505 }
4506
4507 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4508 {
4509         struct vega10_hwmgr *data = hwmgr->backend;
4510         struct vega10_single_dpm_table *golden_sclk_table =
4511                         &(data->golden_dpm_table.gfx_table);
4512         struct pp_power_state *ps;
4513         struct vega10_power_state *vega10_ps;
4514
4515         ps = hwmgr->request_ps;
4516
4517         if (ps == NULL)
4518                 return -EINVAL;
4519
4520         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4521
4522         vega10_ps->performance_levels
4523         [vega10_ps->performance_level_count - 1].gfx_clock =
4524                         golden_sclk_table->dpm_levels
4525                         [golden_sclk_table->count - 1].value *
4526                         value / 100 +
4527                         golden_sclk_table->dpm_levels
4528                         [golden_sclk_table->count - 1].value;
4529
4530         if (vega10_ps->performance_levels
4531                         [vega10_ps->performance_level_count - 1].gfx_clock >
4532                         hwmgr->platform_descriptor.overdriveLimit.engineClock)
4533                 vega10_ps->performance_levels
4534                 [vega10_ps->performance_level_count - 1].gfx_clock =
4535                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
4536
4537         return 0;
4538 }
4539
4540 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4541 {
4542         struct vega10_hwmgr *data = hwmgr->backend;
4543         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4544         struct vega10_single_dpm_table *golden_mclk_table =
4545                         &(data->golden_dpm_table.mem_table);
4546         int value;
4547
4548         value = (mclk_table->dpm_levels
4549                         [mclk_table->count - 1].value -
4550                         golden_mclk_table->dpm_levels
4551                         [golden_mclk_table->count - 1].value) *
4552                         100 /
4553                         golden_mclk_table->dpm_levels
4554                         [golden_mclk_table->count - 1].value;
4555
4556         return value;
4557 }
4558
4559 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4560 {
4561         struct vega10_hwmgr *data = hwmgr->backend;
4562         struct vega10_single_dpm_table *golden_mclk_table =
4563                         &(data->golden_dpm_table.mem_table);
4564         struct pp_power_state  *ps;
4565         struct vega10_power_state  *vega10_ps;
4566
4567         ps = hwmgr->request_ps;
4568
4569         if (ps == NULL)
4570                 return -EINVAL;
4571
4572         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4573
4574         vega10_ps->performance_levels
4575         [vega10_ps->performance_level_count - 1].mem_clock =
4576                         golden_mclk_table->dpm_levels
4577                         [golden_mclk_table->count - 1].value *
4578                         value / 100 +
4579                         golden_mclk_table->dpm_levels
4580                         [golden_mclk_table->count - 1].value;
4581
4582         if (vega10_ps->performance_levels
4583                         [vega10_ps->performance_level_count - 1].mem_clock >
4584                         hwmgr->platform_descriptor.overdriveLimit.memoryClock)
4585                 vega10_ps->performance_levels
4586                 [vega10_ps->performance_level_count - 1].mem_clock =
4587                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4588
4589         return 0;
4590 }
4591
4592 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4593                                         uint32_t virtual_addr_low,
4594                                         uint32_t virtual_addr_hi,
4595                                         uint32_t mc_addr_low,
4596                                         uint32_t mc_addr_hi,
4597                                         uint32_t size)
4598 {
4599         smum_send_msg_to_smc_with_parameter(hwmgr,
4600                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4601                                         virtual_addr_hi);
4602         smum_send_msg_to_smc_with_parameter(hwmgr,
4603                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4604                                         virtual_addr_low);
4605         smum_send_msg_to_smc_with_parameter(hwmgr,
4606                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4607                                         mc_addr_hi);
4608
4609         smum_send_msg_to_smc_with_parameter(hwmgr,
4610                                         PPSMC_MSG_DramLogSetDramAddrLow,
4611                                         mc_addr_low);
4612
4613         smum_send_msg_to_smc_with_parameter(hwmgr,
4614                                         PPSMC_MSG_DramLogSetDramSize,
4615                                         size);
4616         return 0;
4617 }
4618
4619 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4620                 struct PP_TemperatureRange *thermal_data)
4621 {
4622         struct phm_ppt_v2_information *table_info =
4623                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4624
4625         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4626
4627         thermal_data->max = table_info->tdp_table->usSoftwareShutdownTemp *
4628                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4629
4630         return 0;
4631 }
4632
4633 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4634 {
4635         struct vega10_hwmgr *data = hwmgr->backend;
4636         uint32_t i, size = 0;
4637         static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
4638                                                 {90, 60, 0, 0,},
4639                                                 {70, 60, 0, 0,},
4640                                                 {70, 90, 0, 0,},
4641                                                 {30, 60, 0, 6,},
4642                                                 };
4643         static const char *profile_name[6] = {"3D_FULL_SCREEN",
4644                                         "POWER_SAVING",
4645                                         "VIDEO",
4646                                         "VR",
4647                                         "COMPUTE",
4648                                         "CUSTOM"};
4649         static const char *title[6] = {"NUM",
4650                         "MODE_NAME",
4651                         "BUSY_SET_POINT",
4652                         "FPS",
4653                         "USE_RLC_BUSY",
4654                         "MIN_ACTIVE_LEVEL"};
4655
4656         if (!buf)
4657                 return -EINVAL;
4658
4659         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
4660                         title[1], title[2], title[3], title[4], title[5]);
4661
4662         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
4663                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
4664                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4665                         profile_mode_setting[i][0], profile_mode_setting[i][1],
4666                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
4667         size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
4668                         profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4669                         data->custom_profile_mode[0], data->custom_profile_mode[1],
4670                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
4671         return size;
4672 }
4673
4674 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4675 {
4676         struct vega10_hwmgr *data = hwmgr->backend;
4677         uint8_t busy_set_point;
4678         uint8_t FPS;
4679         uint8_t use_rlc_busy;
4680         uint8_t min_active_level;
4681
4682         hwmgr->power_profile_mode = input[size];
4683
4684         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4685                                                 1<<hwmgr->power_profile_mode);
4686
4687         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4688                 if (size == 0 || size > 4)
4689                         return -EINVAL;
4690
4691                 data->custom_profile_mode[0] = busy_set_point = input[0];
4692                 data->custom_profile_mode[1] = FPS = input[1];
4693                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
4694                 data->custom_profile_mode[3] = min_active_level = input[3];
4695                 smum_send_msg_to_smc_with_parameter(hwmgr,
4696                                         PPSMC_MSG_SetCustomGfxDpmParameters,
4697                                         busy_set_point | FPS<<8 |
4698                                         use_rlc_busy << 16 | min_active_level<<24);
4699         }
4700
4701         return 0;
4702 }
4703
4704
4705 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4706                                         enum PP_OD_DPM_TABLE_COMMAND type,
4707                                         uint32_t clk,
4708                                         uint32_t voltage)
4709 {
4710         struct vega10_hwmgr *data = hwmgr->backend;
4711         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4712         struct vega10_single_dpm_table *golden_table;
4713
4714         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
4715                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
4716                 return false;
4717         }
4718
4719         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4720                 golden_table = &(data->golden_dpm_table.gfx_table);
4721                 if (golden_table->dpm_levels[0].value > clk ||
4722                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4723                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4724                                 golden_table->dpm_levels[0].value/100,
4725                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4726                         return false;
4727                 }
4728         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4729                 golden_table = &(data->golden_dpm_table.mem_table);
4730                 if (golden_table->dpm_levels[0].value > clk ||
4731                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4732                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4733                                 golden_table->dpm_levels[0].value/100,
4734                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4735                         return false;
4736                 }
4737         } else {
4738                 return false;
4739         }
4740
4741         return true;
4742 }
4743
4744 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
4745                                                 enum PP_OD_DPM_TABLE_COMMAND type)
4746 {
4747         struct vega10_hwmgr *data = hwmgr->backend;
4748         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
4749         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
4750         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.soc_table;
4751
4752         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
4753                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
4754         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
4755
4756         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
4757         uint8_t i, j;
4758
4759         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4760                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4761                 for (i = 0; i < podn_vdd_dep->count - 1; i++)
4762                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4763                 if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
4764                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4765         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4766                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4767                 for (i = 0; i < dpm_table->count; i++) {
4768                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
4769                                 if (od_vddc_lookup_table->entries[j].us_vdd >
4770                                         podn_vdd_dep->entries[i].vddc)
4771                                         break;
4772                         }
4773                         if (j == od_vddc_lookup_table->count) {
4774                                 od_vddc_lookup_table->entries[j-1].us_vdd =
4775                                         podn_vdd_dep->entries[i].vddc;
4776                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4777                         }
4778                         podn_vdd_dep->entries[i].vddInd = j;
4779                 }
4780                 dpm_table = &data->dpm_table.soc_table;
4781                 for (i = 0; i < dep_table->count; i++) {
4782                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[dep_table->count-1].vddInd &&
4783                                         dep_table->entries[i].clk < podn_vdd_dep->entries[dep_table->count-1].clk) {
4784                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4785                                 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4786                                 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
4787                         }
4788                 }
4789                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
4790                                         podn_vdd_dep->entries[dep_table->count-1].clk) {
4791                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4792                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4793                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = podn_vdd_dep->entries[dep_table->count-1].clk;
4794                 }
4795                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
4796                                         podn_vdd_dep->entries[dep_table->count-1].vddInd) {
4797                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4798                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = podn_vdd_dep->entries[dep_table->count-1].vddInd;
4799                 }
4800         }
4801 }
4802
4803 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4804                                         enum PP_OD_DPM_TABLE_COMMAND type,
4805                                         long *input, uint32_t size)
4806 {
4807         struct vega10_hwmgr *data = hwmgr->backend;
4808         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
4809         struct vega10_single_dpm_table *dpm_table;
4810
4811         uint32_t input_clk;
4812         uint32_t input_vol;
4813         uint32_t input_level;
4814         uint32_t i;
4815
4816         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4817                                 return -EINVAL);
4818
4819         if (!hwmgr->od_enabled) {
4820                 pr_info("OverDrive feature not enabled\n");
4821                 return -EINVAL;
4822         }
4823
4824         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4825                 dpm_table = &data->dpm_table.gfx_table;
4826                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
4827                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4828         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4829                 dpm_table = &data->dpm_table.mem_table;
4830                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
4831                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4832         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4833                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
4834                 vega10_odn_initial_default_setting(hwmgr);
4835                 return 0;
4836         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4837                 vega10_check_dpm_table_updated(hwmgr);
4838                 return 0;
4839         } else {
4840                 return -EINVAL;
4841         }
4842
4843         for (i = 0; i < size; i += 3) {
4844                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
4845                         pr_info("invalid clock voltage input\n");
4846                         return 0;
4847                 }
4848                 input_level = input[i];
4849                 input_clk = input[i+1] * 100;
4850                 input_vol = input[i+2];
4851
4852                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4853                         dpm_table->dpm_levels[input_level].value = input_clk;
4854                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
4855                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
4856                 } else {
4857                         return -EINVAL;
4858                 }
4859         }
4860         vega10_odn_update_soc_table(hwmgr, type);
4861         return 0;
4862 }
4863
4864 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
4865                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
4866                                 PHM_PerformanceLevel *level)
4867 {
4868         const struct vega10_power_state *ps;
4869         struct vega10_hwmgr *data;
4870         uint32_t i;
4871
4872         if (level == NULL || hwmgr == NULL || state == NULL)
4873                 return -EINVAL;
4874
4875         data = hwmgr->backend;
4876         ps = cast_const_phw_vega10_power_state(state);
4877
4878         i = index > ps->performance_level_count - 1 ?
4879                         ps->performance_level_count - 1 : index;
4880
4881         level->coreClock = ps->performance_levels[i].gfx_clock;
4882         level->memory_clock = ps->performance_levels[i].mem_clock;
4883
4884         return 0;
4885 }
4886
4887 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
4888         .backend_init = vega10_hwmgr_backend_init,
4889         .backend_fini = vega10_hwmgr_backend_fini,
4890         .asic_setup = vega10_setup_asic_task,
4891         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
4892         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
4893         .get_num_of_pp_table_entries =
4894                         vega10_get_number_of_powerplay_table_entries,
4895         .get_power_state_size = vega10_get_power_state_size,
4896         .get_pp_table_entry = vega10_get_pp_table_entry,
4897         .patch_boot_state = vega10_patch_boot_state,
4898         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
4899         .power_state_set = vega10_set_power_state_tasks,
4900         .get_sclk = vega10_dpm_get_sclk,
4901         .get_mclk = vega10_dpm_get_mclk,
4902         .notify_smc_display_config_after_ps_adjustment =
4903                         vega10_notify_smc_display_config_after_ps_adjustment,
4904         .force_dpm_level = vega10_dpm_force_dpm_level,
4905         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
4906         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
4907         .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
4908         .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
4909         .reset_fan_speed_to_default =
4910                         vega10_fan_ctrl_reset_fan_speed_to_default,
4911         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
4912         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
4913         .uninitialize_thermal_controller =
4914                         vega10_thermal_ctrl_uninitialize_thermal_controller,
4915         .set_fan_control_mode = vega10_set_fan_control_mode,
4916         .get_fan_control_mode = vega10_get_fan_control_mode,
4917         .read_sensor = vega10_read_sensor,
4918         .get_dal_power_level = vega10_get_dal_power_level,
4919         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
4920         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
4921         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
4922         .display_clock_voltage_request = vega10_display_clock_voltage_request,
4923         .force_clock_level = vega10_force_clock_level,
4924         .print_clock_levels = vega10_print_clock_levels,
4925         .display_config_changed = vega10_display_configuration_changed_task,
4926         .powergate_uvd = vega10_power_gate_uvd,
4927         .powergate_vce = vega10_power_gate_vce,
4928         .check_states_equal = vega10_check_states_equal,
4929         .check_smc_update_required_for_display_configuration =
4930                         vega10_check_smc_update_required_for_display_configuration,
4931         .power_off_asic = vega10_power_off_asic,
4932         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
4933         .get_sclk_od = vega10_get_sclk_od,
4934         .set_sclk_od = vega10_set_sclk_od,
4935         .get_mclk_od = vega10_get_mclk_od,
4936         .set_mclk_od = vega10_set_mclk_od,
4937         .avfs_control = vega10_avfs_enable,
4938         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
4939         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
4940         .register_irq_handlers = smu9_register_irq_handlers,
4941         .start_thermal_controller = vega10_start_thermal_controller,
4942         .get_power_profile_mode = vega10_get_power_profile_mode,
4943         .set_power_profile_mode = vega10_set_power_profile_mode,
4944         .set_power_limit = vega10_set_power_limit,
4945         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
4946         .get_performance_level = vega10_get_performance_level,
4947 };
4948
4949 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
4950 {
4951         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
4952         hwmgr->pptable_func = &vega10_pptable_funcs;
4953
4954         return 0;
4955 }