drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomfwctrl.h"
  33 #include "atomfirmware.h"
  34 #include "cgs_common.h"
  35 #include "vega10_powertune.h"
  36 #include "smu9.h"
  37 #include "smu9_driver_if.h"
  38 #include "vega10_inc.h"
  39 #include "soc15_common.h"
  40 #include "pppcielanes.h"
  41 #include "vega10_hwmgr.h"
  42 #include "vega10_processpptables.h"
  43 #include "vega10_pptable.h"
  44 #include "vega10_thermal.h"
  45 #include "pp_debug.h"
  46 #include "amd_pcie_helpers.h"
  47 #include "ppinterrupt.h"
  48 #include "pp_overdriver.h"
  49 #include "pp_thermal.h"
  50
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53
  54 #define HBM_MEMORY_CHANNEL_WIDTH    128
  55
  56 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  57
  58 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
  59 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
  60
  61 //DF_CS_AON0_DramBaseAddress0
  62 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
  63 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
  64 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
  65 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
  66 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
  67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
  68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
  69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
  70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
  71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
  72
  73 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
  74
  75 struct vega10_power_state *cast_phw_vega10_power_state(
  76                                   struct pp_hw_power_state *hw_ps)
  77 {
  78         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  79                                 "Invalid Powerstate Type!",
  80                                  return NULL;);
  81
  82         return (struct vega10_power_state *)hw_ps;
  83 }
  84
  85 const struct vega10_power_state *cast_const_phw_vega10_power_state(
  86                                  const struct pp_hw_power_state *hw_ps)
  87 {
  88         PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
  89                                 "Invalid Powerstate Type!",
  90                                  return NULL;);
  91
  92         return (const struct vega10_power_state *)hw_ps;
  93 }
  94
  95 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
  96 {
  97         struct vega10_hwmgr *data = hwmgr->backend;
  98
  99         data->registry_data.sclk_dpm_key_disabled =
 100                         hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
 101         data->registry_data.socclk_dpm_key_disabled =
 102                         hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
 103         data->registry_data.mclk_dpm_key_disabled =
 104                         hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
 105         data->registry_data.pcie_dpm_key_disabled =
 106                         hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
 107
 108         data->registry_data.dcefclk_dpm_key_disabled =
 109                         hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
 110
 111         if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
 112                 data->registry_data.power_containment_support = 1;
 113                 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
 114                 data->registry_data.enable_tdc_limit_feature = 1;
 115         }
 116
 117         data->registry_data.clock_stretcher_support =
 118                         hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 119
 120         data->registry_data.ulv_support =
 121                         hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 122
 123         data->registry_data.sclk_deep_sleep_support =
 124                         hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
 125
 126         data->registry_data.disable_water_mark = 0;
 127
 128         data->registry_data.fan_control_support = 1;
 129         data->registry_data.thermal_support = 1;
 130         data->registry_data.fw_ctf_enabled = 1;
 131
 132         data->registry_data.avfs_support =
 133                 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
 134         data->registry_data.led_dpm_enabled = 1;
 135
 136         data->registry_data.vr0hot_enabled = 1;
 137         data->registry_data.vr1hot_enabled = 1;
 138         data->registry_data.regulator_hot_gpio_support = 1;
 139
 140         data->registry_data.didt_support = 1;
 141         if (data->registry_data.didt_support) {
 142                 data->registry_data.didt_mode = 6;
 143                 data->registry_data.sq_ramping_support = 1;
 144                 data->registry_data.db_ramping_support = 0;
 145                 data->registry_data.td_ramping_support = 0;
 146                 data->registry_data.tcp_ramping_support = 0;
 147                 data->registry_data.dbr_ramping_support = 0;
 148                 data->registry_data.edc_didt_support = 1;
 149                 data->registry_data.gc_didt_support = 0;
 150                 data->registry_data.psm_didt_support = 0;
 151         }
 152
 153         data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
 154         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 155         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 156         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 157         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 158         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 159         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 160         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 161         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 162         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 163         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 164         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 165         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
 166
 167         data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
 168         data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
 169         data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
 170         data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
 171 }
 172
 173 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 174 {
 175         struct vega10_hwmgr *data = hwmgr->backend;
 176         struct phm_ppt_v2_information *table_info =
 177                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 178         struct amdgpu_device *adev = hwmgr->adev;
 179
 180         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 181                         PHM_PlatformCaps_SclkDeepSleep);
 182
 183         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 184                         PHM_PlatformCaps_DynamicPatchPowerState);
 185
 186         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
 187                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 188                                 PHM_PlatformCaps_ControlVDDCI);
 189
 190         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 191                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 192
 193         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 194                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 195                                 PHM_PlatformCaps_UVDPowerGating);
 196
 197         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 198                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 199                                 PHM_PlatformCaps_VCEPowerGating);
 200
 201         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 202                         PHM_PlatformCaps_UnTabledHardwareInterface);
 203
 204         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 206
 207         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 208                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 209
 210         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 211                                 PHM_PlatformCaps_DynamicPowerManagement);
 212
 213         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 214                         PHM_PlatformCaps_SMC);
 215
 216         /* power tune caps */
 217         /* assume disabled */
 218         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 219                         PHM_PlatformCaps_PowerContainment);
 220         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 221                         PHM_PlatformCaps_DiDtSupport);
 222         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_SQRamping);
 224         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_DBRamping);
 226         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_TDRamping);
 228         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 229                         PHM_PlatformCaps_TCPRamping);
 230         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 231                         PHM_PlatformCaps_DBRRamping);
 232         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 233                         PHM_PlatformCaps_DiDtEDCEnable);
 234         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 235                         PHM_PlatformCaps_GCEDC);
 236         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 237                         PHM_PlatformCaps_PSM);
 238
 239         if (data->registry_data.didt_support) {
 240                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 241                 if (data->registry_data.sq_ramping_support)
 242                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 243                 if (data->registry_data.db_ramping_support)
 244                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 245                 if (data->registry_data.td_ramping_support)
 246                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 247                 if (data->registry_data.tcp_ramping_support)
 248                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 249                 if (data->registry_data.dbr_ramping_support)
 250                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 251                 if (data->registry_data.edc_didt_support)
 252                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 253                 if (data->registry_data.gc_didt_support)
 254                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 255                 if (data->registry_data.psm_didt_support)
 256                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 257         }
 258
 259         if (data->registry_data.power_containment_support)
 260                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 261                                 PHM_PlatformCaps_PowerContainment);
 262         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 263                         PHM_PlatformCaps_CAC);
 264
 265         if (table_info->tdp_table->usClockStretchAmount &&
 266                         data->registry_data.clock_stretcher_support)
 267                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                 PHM_PlatformCaps_ClockStretcher);
 269
 270         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 271                         PHM_PlatformCaps_RegulatorHot);
 272         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 273                         PHM_PlatformCaps_AutomaticDCTransition);
 274
 275         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 276                         PHM_PlatformCaps_UVDDPM);
 277         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 278                         PHM_PlatformCaps_VCEDPM);
 279
 280         return 0;
 281 }
 282
 283 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 284 {
 285         struct vega10_hwmgr *data = hwmgr->backend;
 286         struct phm_ppt_v2_information *table_info =
 287                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 288         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 289         struct vega10_odn_vddc_lookup_table *od_lookup_table;
 290         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 291         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
 292         struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
 293         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
 294         uint32_t i;
 295         int result;
 296
 297         result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
 298         if (!result) {
 299                 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
 300                 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
 301         }
 302
 303         od_lookup_table = &odn_table->vddc_lookup_table;
 304         vddc_lookup_table = table_info->vddc_lookup_table;
 305
 306         for (i = 0; i < vddc_lookup_table->count; i++)
 307                 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
 308
 309         od_lookup_table->count = vddc_lookup_table->count;
 310
 311         dep_table[0] = table_info->vdd_dep_on_sclk;
 312         dep_table[1] = table_info->vdd_dep_on_mclk;
 313         dep_table[2] = table_info->vdd_dep_on_socclk;
 314         od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
 315         od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
 316         od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
 317
 318         for (i = 0; i < 3; i++)
 319                 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
 320
 321         if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
 322                 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
 323         if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
 324                 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
 325
 326         i = od_table[2]->count - 1;
 327         od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
 328                                         hwmgr->platform_descriptor.overdriveLimit.memoryClock :
 329                                         od_table[2]->entries[i].clk;
 330         od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
 331                                         odn_table->max_vddc :
 332                                         od_table[2]->entries[i].vddc;
 333
 334         return 0;
 335 }
 336
 337 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 338 {
 339         struct vega10_hwmgr *data = hwmgr->backend;
 340         int i;
 341         uint32_t sub_vendor_id, hw_revision;
 342         struct amdgpu_device *adev = hwmgr->adev;
 343
 344         vega10_initialize_power_tune_defaults(hwmgr);
 345
 346         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 347                 data->smu_features[i].smu_feature_id = 0xffff;
 348                 data->smu_features[i].smu_feature_bitmap = 1 << i;
 349                 data->smu_features[i].enabled = false;
 350                 data->smu_features[i].supported = false;
 351         }
 352
 353         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 354                         FEATURE_DPM_PREFETCHER_BIT;
 355         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 356                         FEATURE_DPM_GFXCLK_BIT;
 357         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 358                         FEATURE_DPM_UCLK_BIT;
 359         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 360                         FEATURE_DPM_SOCCLK_BIT;
 361         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 362                         FEATURE_DPM_UVD_BIT;
 363         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 364                         FEATURE_DPM_VCE_BIT;
 365         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 366                         FEATURE_DPM_MP0CLK_BIT;
 367         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 368                         FEATURE_DPM_LINK_BIT;
 369         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 370                         FEATURE_DPM_DCEFCLK_BIT;
 371         data->smu_features[GNLD_ULV].smu_feature_id =
 372                         FEATURE_ULV_BIT;
 373         data->smu_features[GNLD_AVFS].smu_feature_id =
 374                         FEATURE_AVFS_BIT;
 375         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 376                         FEATURE_DS_GFXCLK_BIT;
 377         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 378                         FEATURE_DS_SOCCLK_BIT;
 379         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 380                         FEATURE_DS_LCLK_BIT;
 381         data->smu_features[GNLD_PPT].smu_feature_id =
 382                         FEATURE_PPT_BIT;
 383         data->smu_features[GNLD_TDC].smu_feature_id =
 384                         FEATURE_TDC_BIT;
 385         data->smu_features[GNLD_THERMAL].smu_feature_id =
 386                         FEATURE_THERMAL_BIT;
 387         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 388                         FEATURE_GFX_PER_CU_CG_BIT;
 389         data->smu_features[GNLD_RM].smu_feature_id =
 390                         FEATURE_RM_BIT;
 391         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 392                         FEATURE_DS_DCEFCLK_BIT;
 393         data->smu_features[GNLD_ACDC].smu_feature_id =
 394                         FEATURE_ACDC_BIT;
 395         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 396                         FEATURE_VR0HOT_BIT;
 397         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 398                         FEATURE_VR1HOT_BIT;
 399         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 400                         FEATURE_FW_CTF_BIT;
 401         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 402                         FEATURE_LED_DISPLAY_BIT;
 403         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 404                         FEATURE_FAN_CONTROL_BIT;
 405         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 406         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 407         data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
 408
 409         if (!data->registry_data.prefetcher_dpm_key_disabled)
 410                 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
 411
 412         if (!data->registry_data.sclk_dpm_key_disabled)
 413                 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
 414
 415         if (!data->registry_data.mclk_dpm_key_disabled)
 416                 data->smu_features[GNLD_DPM_UCLK].supported = true;
 417
 418         if (!data->registry_data.socclk_dpm_key_disabled)
 419                 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
 420
 421         if (PP_CAP(PHM_PlatformCaps_UVDDPM))
 422                 data->smu_features[GNLD_DPM_UVD].supported = true;
 423
 424         if (PP_CAP(PHM_PlatformCaps_VCEDPM))
 425                 data->smu_features[GNLD_DPM_VCE].supported = true;
 426
 427         if (!data->registry_data.pcie_dpm_key_disabled)
 428                 data->smu_features[GNLD_DPM_LINK].supported = true;
 429
 430         if (!data->registry_data.dcefclk_dpm_key_disabled)
 431                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
 432
 433         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
 434             data->registry_data.sclk_deep_sleep_support) {
 435                 data->smu_features[GNLD_DS_GFXCLK].supported = true;
 436                 data->smu_features[GNLD_DS_SOCCLK].supported = true;
 437                 data->smu_features[GNLD_DS_LCLK].supported = true;
 438                 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
 439         }
 440
 441         if (data->registry_data.enable_pkg_pwr_tracking_feature)
 442                 data->smu_features[GNLD_PPT].supported = true;
 443
 444         if (data->registry_data.enable_tdc_limit_feature)
 445                 data->smu_features[GNLD_TDC].supported = true;
 446
 447         if (data->registry_data.thermal_support)
 448                 data->smu_features[GNLD_THERMAL].supported = true;
 449
 450         if (data->registry_data.fan_control_support)
 451                 data->smu_features[GNLD_FAN_CONTROL].supported = true;
 452
 453         if (data->registry_data.fw_ctf_enabled)
 454                 data->smu_features[GNLD_FW_CTF].supported = true;
 455
 456         if (data->registry_data.avfs_support)
 457                 data->smu_features[GNLD_AVFS].supported = true;
 458
 459         if (data->registry_data.led_dpm_enabled)
 460                 data->smu_features[GNLD_LED_DISPLAY].supported = true;
 461
 462         if (data->registry_data.vr1hot_enabled)
 463                 data->smu_features[GNLD_VR1HOT].supported = true;
 464
 465         if (data->registry_data.vr0hot_enabled)
 466                 data->smu_features[GNLD_VR0HOT].supported = true;
 467
 468         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
 469         hwmgr->smu_version = smum_get_argument(hwmgr);
 470                 /* ACG firmware has major version 5 */
 471         if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
 472                 data->smu_features[GNLD_ACG].supported = true;
 473         if (data->registry_data.didt_support)
 474                 data->smu_features[GNLD_DIDT].supported = true;
 475
 476         hw_revision = adev->pdev->revision;
 477         sub_vendor_id = adev->pdev->subsystem_vendor;
 478
 479         if ((hwmgr->chip_id == 0x6862 ||
 480                 hwmgr->chip_id == 0x6861 ||
 481                 hwmgr->chip_id == 0x6868) &&
 482                 (hw_revision == 0) &&
 483                 (sub_vendor_id != 0x1002))
 484                 data->smu_features[GNLD_PCC_LIMIT].supported = true;
 485 }
 486
 487 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 488 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 489         phm_ppt_v1_voltage_lookup_table *lookup_table,
 490         uint16_t virtual_voltage_id, int32_t *socclk)
 491 {
 492         uint8_t entry_id;
 493         uint8_t voltage_id;
 494         struct phm_ppt_v2_information *table_info =
 495                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 496
 497         PP_ASSERT_WITH_CODE(lookup_table->count != 0,
 498                         "Lookup table is empty",
 499                         return -EINVAL);
 500
 501         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
 502         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 503                 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
 504                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 505                         break;
 506         }
 507
 508         PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
 509                         "Can't find requested voltage id in vdd_dep_on_socclk table!",
 510                         return -EINVAL);
 511
 512         *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
 513
 514         return 0;
 515 }
 516
 517 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
 518 /**
 519 * Get Leakage VDDC based on leakage ID.
 520 *
 521 * @param    hwmgr  the address of the powerplay hardware manager.
 522 * @return   always 0.
 523 */
 524 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
 525 {
 526         struct vega10_hwmgr *data = hwmgr->backend;
 527         uint16_t vv_id;
 528         uint32_t vddc = 0;
 529         uint16_t i, j;
 530         uint32_t sclk = 0;
 531         struct phm_ppt_v2_information *table_info =
 532                         (struct phm_ppt_v2_information *)hwmgr->pptable;
 533         struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
 534                         table_info->vdd_dep_on_socclk;
 535         int result;
 536
 537         for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
 538                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 539
 540                 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
 541                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 542                         if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
 543                                 for (j = 1; j < socclk_table->count; j++) {
 544                                         if (socclk_table->entries[j].clk == sclk &&
 545                                                         socclk_table->entries[j].cks_enable == 0) {
 546                                                 sclk += 5000;
 547                                                 break;
 548                                         }
 549                                 }
 550                         }
 551
 552                         PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
 553                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
 554                                         "Error retrieving EVV voltage value!",
 555                                         continue);
 556
 557
 558                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 559                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
 560                                         "Invalid VDDC value", result = -EINVAL;);
 561
 562                         /* the voltage should not be zero nor equal to leakage ID */
 563                         if (vddc != 0 && vddc != vv_id) {
 564                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
 565                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
 566                                 data->vddc_leakage.count++;
 567                         }
 568                 }
 569         }
 570
 571         return 0;
 572 }
 573
 574 /**
 575  * Change virtual leakage voltage to actual value.
 576  *
 577  * @param     hwmgr  the address of the powerplay hardware manager.
 578  * @param     pointer to changing voltage
 579  * @param     pointer to leakage table
 580  */
 581 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 582                 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
 583 {
 584         uint32_t index;
 585
 586         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 587         for (index = 0; index < leakage_table->count; index++) {
 588                 /* if this voltage matches a leakage voltage ID */
 589                 /* patch with actual leakage voltage */
 590                 if (leakage_table->leakage_id[index] == *voltage) {
 591                         *voltage = leakage_table->actual_voltage[index];
 592                         break;
 593                 }
 594         }
 595
 596         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 597                 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
 598 }
 599
 600 /**
 601 * Patch voltage lookup table by EVV leakages.
 602 *
 603 * @param     hwmgr  the address of the powerplay hardware manager.
 604 * @param     pointer to voltage lookup table
 605 * @param     pointer to leakage table
 606 * @return     always 0
 607 */
 608 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 609                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 610                 struct vega10_leakage_voltage *leakage_table)
 611 {
 612         uint32_t i;
 613
 614         for (i = 0; i < lookup_table->count; i++)
 615                 vega10_patch_with_vdd_leakage(hwmgr,
 616                                 &lookup_table->entries[i].us_vdd, leakage_table);
 617
 618         return 0;
 619 }
 620
 621 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
 622                 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
 623                 uint16_t *vddc)
 624 {
 625         vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 626
 627         return 0;
 628 }
 629 #endif
 630
 631 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
 632                 struct pp_hwmgr *hwmgr)
 633 {
 634         uint8_t entry_id, voltage_id;
 635         unsigned i;
 636         struct phm_ppt_v2_information *table_info =
 637                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 638         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 639                         table_info->mm_dep_table;
 640         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 641                         table_info->vdd_dep_on_mclk;
 642
 643         for (i = 0; i < 6; i++) {
 644                 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
 645                 switch (i) {
 646                         case 0: vdt = table_info->vdd_dep_on_socclk; break;
 647                         case 1: vdt = table_info->vdd_dep_on_sclk; break;
 648                         case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
 649                         case 3: vdt = table_info->vdd_dep_on_pixclk; break;
 650                         case 4: vdt = table_info->vdd_dep_on_dispclk; break;
 651                         case 5: vdt = table_info->vdd_dep_on_phyclk; break;
 652                 }
 653
 654                 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
 655                         voltage_id = vdt->entries[entry_id].vddInd;
 656                         vdt->entries[entry_id].vddc =
 657                                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 658                 }
 659         }
 660
 661         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
 662                 voltage_id = mm_table->entries[entry_id].vddcInd;
 663                 mm_table->entries[entry_id].vddc =
 664                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 665         }
 666
 667         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
 668                 voltage_id = mclk_table->entries[entry_id].vddInd;
 669                 mclk_table->entries[entry_id].vddc =
 670                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
 671                 voltage_id = mclk_table->entries[entry_id].vddciInd;
 672                 mclk_table->entries[entry_id].vddci =
 673                                 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
 674                 voltage_id = mclk_table->entries[entry_id].mvddInd;
 675                 mclk_table->entries[entry_id].mvdd =
 676                                 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
 677         }
 678
 679
 680         return 0;
 681
 682 }
 683
 684 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
 685                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 686 {
 687         uint32_t table_size, i, j;
 688         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 689
 690         PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
 691                 "Lookup table is empty", return -EINVAL);
 692
 693         table_size = lookup_table->count;
 694
 695         /* Sorting voltages */
 696         for (i = 0; i < table_size - 1; i++) {
 697                 for (j = i + 1; j > 0; j--) {
 698                         if (lookup_table->entries[j].us_vdd <
 699                                         lookup_table->entries[j - 1].us_vdd) {
 700                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 701                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 702                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 703                         }
 704                 }
 705         }
 706
 707         return 0;
 708 }
 709
 710 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 711 {
 712         int result = 0;
 713         int tmp_result;
 714         struct phm_ppt_v2_information *table_info =
 715                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 716 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 717         struct vega10_hwmgr *data = hwmgr->backend;
 718
 719         tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
 720                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 721         if (tmp_result)
 722                 result = tmp_result;
 723
 724         tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 725                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 726         if (tmp_result)
 727                 result = tmp_result;
 728 #endif
 729
 730         tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 731         if (tmp_result)
 732                 result = tmp_result;
 733
 734         tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 735         if (tmp_result)
 736                 result = tmp_result;
 737
 738         return result;
 739 }
 740
 741 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 742 {
 743         struct phm_ppt_v2_information *table_info =
 744                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
 745         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 746                         table_info->vdd_dep_on_socclk;
 747         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 748                         table_info->vdd_dep_on_mclk;
 749
 750         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
 751                 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
 752         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 753                 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
 754
 755         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
 756                 "VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
 757         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 758                 "VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
 759
 760         table_info->max_clock_voltage_on_ac.sclk =
 761                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 762         table_info->max_clock_voltage_on_ac.mclk =
 763                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 764         table_info->max_clock_voltage_on_ac.vddc =
 765                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 766         table_info->max_clock_voltage_on_ac.vddci =
 767                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 768
 769         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 770                 table_info->max_clock_voltage_on_ac.sclk;
 771         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 772                 table_info->max_clock_voltage_on_ac.mclk;
 773         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 774                 table_info->max_clock_voltage_on_ac.vddc;
 775         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 776                 table_info->max_clock_voltage_on_ac.vddci;
 777
 778         return 0;
 779 }
 780
 781 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 782 {
 783         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 784         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 785
 786         kfree(hwmgr->backend);
 787         hwmgr->backend = NULL;
 788
 789         return 0;
 790 }
 791
 792 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 793 {
 794         int result = 0;
 795         struct vega10_hwmgr *data;
 796         uint32_t config_telemetry = 0;
 797         struct pp_atomfwctrl_voltage_table vol_table;
 798         struct amdgpu_device *adev = hwmgr->adev;
 799
 800         data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
 801         if (data == NULL)
 802                 return -ENOMEM;
 803
 804         hwmgr->backend = data;
 805
 806         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
 807         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 808         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
 809
 810         vega10_set_default_registry_data(hwmgr);
 811         data->disable_dpm_mask = 0xff;
 812
 813         /* need to set voltage control types before EVV patching */
 814         data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
 815         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
 816         data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
 817
 818         /* VDDCR_SOC */
 819         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 820                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
 821                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 822                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
 823                                 &vol_table)) {
 824                         config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
 825                                         (vol_table.telemetry_offset & 0xff);
 826                         data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 827                 }
 828         } else {
 829                 kfree(hwmgr->backend);
 830                 hwmgr->backend = NULL;
 831                 PP_ASSERT_WITH_CODE(false,
 832                                 "VDDCR_SOC is not SVID2!",
 833                                 return -1);
 834         }
 835
 836         /* MVDDC */
 837         if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 838                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
 839                 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
 840                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
 841                                 &vol_table)) {
 842                         config_telemetry |=
 843                                         ((vol_table.telemetry_slope << 24) & 0xff000000) |
 844                                         ((vol_table.telemetry_offset << 16) & 0xff0000);
 845                         data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
 846                 }
 847         }
 848
 849          /* VDDCI_MEM */
 850         if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
 851                 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
 852                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 853                         data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
 854         }
 855
 856         data->config_telemetry = config_telemetry;
 857
 858         vega10_set_features_platform_caps(hwmgr);
 859
 860         vega10_init_dpm_defaults(hwmgr);
 861
 862 #ifdef PPLIB_VEGA10_EVV_SUPPORT
 863         /* Get leakage voltage based on leakage ID. */
 864         PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
 865                         "Get EVV Voltage Failed.  Abort Driver loading!",
 866                         return -1);
 867 #endif
 868
 869         /* Patch our voltage dependency table with actual leakage voltage
 870          * We need to perform leakage translation before it's used by other functions
 871          */
 872         vega10_complete_dependency_tables(hwmgr);
 873
 874         /* Parse pptable data read from VBIOS */
 875         vega10_set_private_data_based_on_pptable(hwmgr);
 876
 877         data->is_tlu_enabled = false;
 878
 879         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 880                         VEGA10_MAX_HARDWARE_POWERLEVELS;
 881         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 882         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 883
 884         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 885         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 886         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 887         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 888
 889         data->total_active_cus = adev->gfx.cu_info.number;
 890         /* Setup default Overdrive Fan control settings */
 891         data->odn_fan_table.target_fan_speed =
 892                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 893         data->odn_fan_table.target_temperature =
 894                         hwmgr->thermal_controller.
 895                         advanceFanControlParameters.ucTargetTemperature;
 896         data->odn_fan_table.min_performance_clock =
 897                         hwmgr->thermal_controller.advanceFanControlParameters.
 898                         ulMinFanSCLKAcousticLimit;
 899         data->odn_fan_table.min_fan_limit =
 900                         hwmgr->thermal_controller.
 901                         advanceFanControlParameters.usFanPWMMinLimit *
 902                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 903
 904         data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
 905                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
 906                         DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 907         PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
 908                         "Mem Channel Index Exceeded maximum!",
 909                         return -EINVAL);
 910
 911         return result;
 912 }
 913
 914 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 915 {
 916         struct vega10_hwmgr *data = hwmgr->backend;
 917
 918         data->low_sclk_interrupt_threshold = 0;
 919
 920         return 0;
 921 }
 922
 923 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
 924 {
 925         struct vega10_hwmgr *data = hwmgr->backend;
 926         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 927
 928         struct pp_atomfwctrl_voltage_table table;
 929         uint8_t i, j;
 930         uint32_t mask = 0;
 931         uint32_t tmp;
 932         int32_t ret = 0;
 933
 934         ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
 935                                                 VOLTAGE_OBJ_GPIO_LUT, &table);
 936
 937         if (!ret) {
 938                 tmp = table.mask_low;
 939                 for (i = 0, j = 0; i < 32; i++) {
 940                         if (tmp & 1) {
 941                                 mask |= (uint32_t)(i << (8 * j));
 942                                 if (++j >= 3)
 943                                         break;
 944                         }
 945                         tmp >>= 1;
 946                 }
 947         }
 948
 949         pp_table->LedPin0 = (uint8_t)(mask & 0xff);
 950         pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
 951         pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
 952         return 0;
 953 }
 954
 955 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
 956 {
 957         PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
 958                         "Failed to init sclk threshold!",
 959                         return -EINVAL);
 960
 961         PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
 962                         "Failed to set up led dpm config!",
 963                         return -EINVAL);
 964
 965         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
 966
 967         return 0;
 968 }
 969
 970 /**
 971 * Remove repeated voltage values and create table with unique values.
 972 *
 973 * @param    hwmgr  the address of the powerplay hardware manager.
 974 * @param    vol_table  the pointer to changing voltage table
 975 * @return    0 in success
 976 */
 977
 978 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
 979                 struct pp_atomfwctrl_voltage_table *vol_table)
 980 {
 981         uint32_t i, j;
 982         uint16_t vvalue;
 983         bool found = false;
 984         struct pp_atomfwctrl_voltage_table *table;
 985
 986         PP_ASSERT_WITH_CODE(vol_table,
 987                         "Voltage Table empty.", return -EINVAL);
 988         table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
 989                         GFP_KERNEL);
 990
 991         if (!table)
 992                 return -ENOMEM;
 993
 994         table->mask_low = vol_table->mask_low;
 995         table->phase_delay = vol_table->phase_delay;
 996
 997         for (i = 0; i < vol_table->count; i++) {
 998                 vvalue = vol_table->entries[i].value;
 999                 found = false;
1000
1001                 for (j = 0; j < table->count; j++) {
1002                         if (vvalue == table->entries[j].value) {
1003                                 found = true;
1004                                 break;
1005                         }
1006                 }
1007
1008                 if (!found) {
1009                         table->entries[table->count].value = vvalue;
1010                         table->entries[table->count].smio_low =
1011                                         vol_table->entries[i].smio_low;
1012                         table->count++;
1013                 }
1014         }
1015
1016         memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1017         kfree(table);
1018
1019         return 0;
1020 }
1021
1022 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1023                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1024                 struct pp_atomfwctrl_voltage_table *vol_table)
1025 {
1026         int i;
1027
1028         PP_ASSERT_WITH_CODE(dep_table->count,
1029                         "Voltage Dependency Table empty.",
1030                         return -EINVAL);
1031
1032         vol_table->mask_low = 0;
1033         vol_table->phase_delay = 0;
1034         vol_table->count = dep_table->count;
1035
1036         for (i = 0; i < vol_table->count; i++) {
1037                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1038                 vol_table->entries[i].smio_low = 0;
1039         }
1040
1041         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1042                         vol_table),
1043                         "Failed to trim MVDD Table!",
1044                         return -1);
1045
1046         return 0;
1047 }
1048
1049 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1050                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1051                 struct pp_atomfwctrl_voltage_table *vol_table)
1052 {
1053         uint32_t i;
1054
1055         PP_ASSERT_WITH_CODE(dep_table->count,
1056                         "Voltage Dependency Table empty.",
1057                         return -EINVAL);
1058
1059         vol_table->mask_low = 0;
1060         vol_table->phase_delay = 0;
1061         vol_table->count = dep_table->count;
1062
1063         for (i = 0; i < dep_table->count; i++) {
1064                 vol_table->entries[i].value = dep_table->entries[i].vddci;
1065                 vol_table->entries[i].smio_low = 0;
1066         }
1067
1068         PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1069                         "Failed to trim VDDCI table.",
1070                         return -1);
1071
1072         return 0;
1073 }
1074
1075 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1076                 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1077                 struct pp_atomfwctrl_voltage_table *vol_table)
1078 {
1079         int i;
1080
1081         PP_ASSERT_WITH_CODE(dep_table->count,
1082                         "Voltage Dependency Table empty.",
1083                         return -EINVAL);
1084
1085         vol_table->mask_low = 0;
1086         vol_table->phase_delay = 0;
1087         vol_table->count = dep_table->count;
1088
1089         for (i = 0; i < vol_table->count; i++) {
1090                 vol_table->entries[i].value = dep_table->entries[i].vddc;
1091                 vol_table->entries[i].smio_low = 0;
1092         }
1093
1094         return 0;
1095 }
1096
1097 /* ---- Voltage Tables ----
1098  * If the voltage table would be bigger than
1099  * what will fit into the state table on
1100  * the SMC keep only the higher entries.
1101  */
1102 static void vega10_trim_voltage_table_to_fit_state_table(
1103                 struct pp_hwmgr *hwmgr,
1104                 uint32_t max_vol_steps,
1105                 struct pp_atomfwctrl_voltage_table *vol_table)
1106 {
1107         unsigned int i, diff;
1108
1109         if (vol_table->count <= max_vol_steps)
1110                 return;
1111
1112         diff = vol_table->count - max_vol_steps;
1113
1114         for (i = 0; i < max_vol_steps; i++)
1115                 vol_table->entries[i] = vol_table->entries[i + diff];
1116
1117         vol_table->count = max_vol_steps;
1118 }
1119
1120 /**
1121 * Create Voltage Tables.
1122 *
1123 * @param    hwmgr  the address of the powerplay hardware manager.
1124 * @return   always 0
1125 */
1126 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1127 {
1128         struct vega10_hwmgr *data = hwmgr->backend;
1129         struct phm_ppt_v2_information *table_info =
1130                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1131         int result;
1132
1133         if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1134                         data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1135                 result = vega10_get_mvdd_voltage_table(hwmgr,
1136                                 table_info->vdd_dep_on_mclk,
1137                                 &(data->mvdd_voltage_table));
1138                 PP_ASSERT_WITH_CODE(!result,
1139                                 "Failed to retrieve MVDDC table!",
1140                                 return result);
1141         }
1142
1143         if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1144                 result = vega10_get_vddci_voltage_table(hwmgr,
1145                                 table_info->vdd_dep_on_mclk,
1146                                 &(data->vddci_voltage_table));
1147                 PP_ASSERT_WITH_CODE(!result,
1148                                 "Failed to retrieve VDDCI_MEM table!",
1149                                 return result);
1150         }
1151
1152         if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1153                         data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1154                 result = vega10_get_vdd_voltage_table(hwmgr,
1155                                 table_info->vdd_dep_on_sclk,
1156                                 &(data->vddc_voltage_table));
1157                 PP_ASSERT_WITH_CODE(!result,
1158                                 "Failed to retrieve VDDCR_SOC table!",
1159                                 return result);
1160         }
1161
1162         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1163                         "Too many voltage values for VDDC. Trimming to fit state table.",
1164                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1165                                         16, &(data->vddc_voltage_table)));
1166
1167         PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1168                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1169                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1170                                         16, &(data->vddci_voltage_table)));
1171
1172         PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1173                         "Too many voltage values for MVDD. Trimming to fit state table.",
1174                         vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1175                                         16, &(data->mvdd_voltage_table)));
1176
1177
1178         return 0;
1179 }
1180
1181 /*
1182  * @fn vega10_init_dpm_state
1183  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1184  *
1185  * @param    dpm_state - the address of the DPM Table to initiailize.
1186  * @return   None.
1187  */
1188 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1189 {
1190         dpm_state->soft_min_level = 0xff;
1191         dpm_state->soft_max_level = 0xff;
1192         dpm_state->hard_min_level = 0xff;
1193         dpm_state->hard_max_level = 0xff;
1194 }
1195
1196 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1197                 struct vega10_single_dpm_table *dpm_table,
1198                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1199 {
1200         int i;
1201
1202         dpm_table->count = 0;
1203
1204         for (i = 0; i < dep_table->count; i++) {
1205                 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1206                                 dep_table->entries[i].clk) {
1207                         dpm_table->dpm_levels[dpm_table->count].value =
1208                                         dep_table->entries[i].clk;
1209                         dpm_table->dpm_levels[dpm_table->count].enabled = true;
1210                         dpm_table->count++;
1211                 }
1212         }
1213 }
1214 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1215 {
1216         struct vega10_hwmgr *data = hwmgr->backend;
1217         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1218         struct phm_ppt_v2_information *table_info =
1219                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1220         struct phm_ppt_v1_pcie_table *bios_pcie_table =
1221                         table_info->pcie_table;
1222         uint32_t i;
1223
1224         PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1225                         "Incorrect number of PCIE States from VBIOS!",
1226                         return -1);
1227
1228         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1229                 if (data->registry_data.pcieSpeedOverride)
1230                         pcie_table->pcie_gen[i] =
1231                                         data->registry_data.pcieSpeedOverride;
1232                 else
1233                         pcie_table->pcie_gen[i] =
1234                                         bios_pcie_table->entries[i].gen_speed;
1235
1236                 if (data->registry_data.pcieLaneOverride)
1237                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1238                                         data->registry_data.pcieLaneOverride);
1239                 else
1240                         pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1241                                                         bios_pcie_table->entries[i].lane_width);
1242                 if (data->registry_data.pcieClockOverride)
1243                         pcie_table->lclk[i] =
1244                                         data->registry_data.pcieClockOverride;
1245                 else
1246                         pcie_table->lclk[i] =
1247                                         bios_pcie_table->entries[i].pcie_sclk;
1248         }
1249
1250         pcie_table->count = NUM_LINK_LEVELS;
1251
1252         return 0;
1253 }
1254
1255 /*
1256  * This function is to initialize all DPM state tables
1257  * for SMU based on the dependency table.
1258  * Dynamic state patching function will then trim these
1259  * state tables to the allowed range based
1260  * on the power policy or external client requests,
1261  * such as UVD request, etc.
1262  */
1263 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1264 {
1265         struct vega10_hwmgr *data = hwmgr->backend;
1266         struct phm_ppt_v2_information *table_info =
1267                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1268         struct vega10_single_dpm_table *dpm_table;
1269         uint32_t i;
1270
1271         struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1272                         table_info->vdd_dep_on_socclk;
1273         struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1274                         table_info->vdd_dep_on_sclk;
1275         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1276                         table_info->vdd_dep_on_mclk;
1277         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1278                         table_info->mm_dep_table;
1279         struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1280                         table_info->vdd_dep_on_dcefclk;
1281         struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1282                         table_info->vdd_dep_on_pixclk;
1283         struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1284                         table_info->vdd_dep_on_dispclk;
1285         struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1286                         table_info->vdd_dep_on_phyclk;
1287
1288         PP_ASSERT_WITH_CODE(dep_soc_table,
1289                         "SOCCLK dependency table is missing. This table is mandatory",
1290                         return -EINVAL);
1291         PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1292                         "SOCCLK dependency table is empty. This table is mandatory",
1293                         return -EINVAL);
1294
1295         PP_ASSERT_WITH_CODE(dep_gfx_table,
1296                         "GFXCLK dependency table is missing. This table is mandatory",
1297                         return -EINVAL);
1298         PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1299                         "GFXCLK dependency table is empty. This table is mandatory",
1300                         return -EINVAL);
1301
1302         PP_ASSERT_WITH_CODE(dep_mclk_table,
1303                         "MCLK dependency table is missing. This table is mandatory",
1304                         return -EINVAL);
1305         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1306                         "MCLK dependency table has to have is missing. This table is mandatory",
1307                         return -EINVAL);
1308
1309         /* Initialize Sclk DPM table based on allow Sclk values */
1310         dpm_table = &(data->dpm_table.soc_table);
1311         vega10_setup_default_single_dpm_table(hwmgr,
1312                         dpm_table,
1313                         dep_soc_table);
1314
1315         vega10_init_dpm_state(&(dpm_table->dpm_state));
1316
1317         dpm_table = &(data->dpm_table.gfx_table);
1318         vega10_setup_default_single_dpm_table(hwmgr,
1319                         dpm_table,
1320                         dep_gfx_table);
1321         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1322                 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1323                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1324         vega10_init_dpm_state(&(dpm_table->dpm_state));
1325
1326         /* Initialize Mclk DPM table based on allow Mclk values */
1327         data->dpm_table.mem_table.count = 0;
1328         dpm_table = &(data->dpm_table.mem_table);
1329         vega10_setup_default_single_dpm_table(hwmgr,
1330                         dpm_table,
1331                         dep_mclk_table);
1332         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1333                 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1334                                         dpm_table->dpm_levels[dpm_table->count-1].value;
1335
1336         vega10_init_dpm_state(&(dpm_table->dpm_state));
1337
1338         data->dpm_table.eclk_table.count = 0;
1339         dpm_table = &(data->dpm_table.eclk_table);
1340         for (i = 0; i < dep_mm_table->count; i++) {
1341                 if (i == 0 || dpm_table->dpm_levels
1342                                 [dpm_table->count - 1].value <=
1343                                                 dep_mm_table->entries[i].eclk) {
1344                         dpm_table->dpm_levels[dpm_table->count].value =
1345                                         dep_mm_table->entries[i].eclk;
1346                         dpm_table->dpm_levels[dpm_table->count].enabled =
1347                                         (i == 0) ? true : false;
1348                         dpm_table->count++;
1349                 }
1350         }
1351         vega10_init_dpm_state(&(dpm_table->dpm_state));
1352
1353         data->dpm_table.vclk_table.count = 0;
1354         data->dpm_table.dclk_table.count = 0;
1355         dpm_table = &(data->dpm_table.vclk_table);
1356         for (i = 0; i < dep_mm_table->count; i++) {
1357                 if (i == 0 || dpm_table->dpm_levels
1358                                 [dpm_table->count - 1].value <=
1359                                                 dep_mm_table->entries[i].vclk) {
1360                         dpm_table->dpm_levels[dpm_table->count].value =
1361                                         dep_mm_table->entries[i].vclk;
1362                         dpm_table->dpm_levels[dpm_table->count].enabled =
1363                                         (i == 0) ? true : false;
1364                         dpm_table->count++;
1365                 }
1366         }
1367         vega10_init_dpm_state(&(dpm_table->dpm_state));
1368
1369         dpm_table = &(data->dpm_table.dclk_table);
1370         for (i = 0; i < dep_mm_table->count; i++) {
1371                 if (i == 0 || dpm_table->dpm_levels
1372                                 [dpm_table->count - 1].value <=
1373                                                 dep_mm_table->entries[i].dclk) {
1374                         dpm_table->dpm_levels[dpm_table->count].value =
1375                                         dep_mm_table->entries[i].dclk;
1376                         dpm_table->dpm_levels[dpm_table->count].enabled =
1377                                         (i == 0) ? true : false;
1378                         dpm_table->count++;
1379                 }
1380         }
1381         vega10_init_dpm_state(&(dpm_table->dpm_state));
1382
1383         /* Assume there is no headless Vega10 for now */
1384         dpm_table = &(data->dpm_table.dcef_table);
1385         vega10_setup_default_single_dpm_table(hwmgr,
1386                         dpm_table,
1387                         dep_dcef_table);
1388
1389         vega10_init_dpm_state(&(dpm_table->dpm_state));
1390
1391         dpm_table = &(data->dpm_table.pixel_table);
1392         vega10_setup_default_single_dpm_table(hwmgr,
1393                         dpm_table,
1394                         dep_pix_table);
1395
1396         vega10_init_dpm_state(&(dpm_table->dpm_state));
1397
1398         dpm_table = &(data->dpm_table.display_table);
1399         vega10_setup_default_single_dpm_table(hwmgr,
1400                         dpm_table,
1401                         dep_disp_table);
1402
1403         vega10_init_dpm_state(&(dpm_table->dpm_state));
1404
1405         dpm_table = &(data->dpm_table.phy_table);
1406         vega10_setup_default_single_dpm_table(hwmgr,
1407                         dpm_table,
1408                         dep_phy_table);
1409
1410         vega10_init_dpm_state(&(dpm_table->dpm_state));
1411
1412         vega10_setup_default_pcie_table(hwmgr);
1413
1414         /* save a copy of the default DPM table */
1415         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1416                         sizeof(struct vega10_dpm_table));
1417
1418         return 0;
1419 }
1420
1421 /*
1422  * @fn vega10_populate_ulv_state
1423  * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1424  *
1425  * @param    hwmgr - the address of the hardware manager.
1426  * @return   Always 0.
1427  */
1428 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1429 {
1430         struct vega10_hwmgr *data = hwmgr->backend;
1431         struct phm_ppt_v2_information *table_info =
1432                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1433
1434         data->smc_state_table.pp_table.UlvOffsetVid =
1435                         (uint8_t)table_info->us_ulv_voltage_offset;
1436
1437         data->smc_state_table.pp_table.UlvSmnclkDid =
1438                         (uint8_t)(table_info->us_ulv_smnclk_did);
1439         data->smc_state_table.pp_table.UlvMp1clkDid =
1440                         (uint8_t)(table_info->us_ulv_mp1clk_did);
1441         data->smc_state_table.pp_table.UlvGfxclkBypass =
1442                         (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1443         data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1444                         (uint8_t)(data->vddc_voltage_table.psi0_enable);
1445         data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1446                         (uint8_t)(data->vddc_voltage_table.psi1_enable);
1447
1448         return 0;
1449 }
1450
1451 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1452                 uint32_t lclock, uint8_t *curr_lclk_did)
1453 {
1454         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1455
1456         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1457                         hwmgr,
1458                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1459                         lclock, &dividers),
1460                         "Failed to get LCLK clock settings from VBIOS!",
1461                         return -1);
1462
1463         *curr_lclk_did = dividers.ulDid;
1464
1465         return 0;
1466 }
1467
1468 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1469 {
1470         int result = -1;
1471         struct vega10_hwmgr *data = hwmgr->backend;
1472         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1473         struct vega10_pcie_table *pcie_table =
1474                         &(data->dpm_table.pcie_table);
1475         uint32_t i, j;
1476
1477         for (i = 0; i < pcie_table->count; i++) {
1478                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1479                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1480
1481                 result = vega10_populate_single_lclk_level(hwmgr,
1482                                 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1483                 if (result) {
1484                         pr_info("Populate LClock Level %d Failed!\n", i);
1485                         return result;
1486                 }
1487         }
1488
1489         j = i - 1;
1490         while (i < NUM_LINK_LEVELS) {
1491                 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1492                 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1493
1494                 result = vega10_populate_single_lclk_level(hwmgr,
1495                                 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1496                 if (result) {
1497                         pr_info("Populate LClock Level %d Failed!\n", i);
1498                         return result;
1499                 }
1500                 i++;
1501         }
1502
1503         return result;
1504 }
1505
1506 /**
1507 * Populates single SMC GFXSCLK structure using the provided engine clock
1508 *
1509 * @param    hwmgr      the address of the hardware manager
1510 * @param    gfx_clock  the GFX clock to use to populate the structure.
1511 * @param    current_gfxclk_level  location in PPTable for the SMC GFXCLK structure.
1512 */
1513
1514 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1515                 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1516                 uint32_t *acg_freq)
1517 {
1518         struct phm_ppt_v2_information *table_info =
1519                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1520         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1521         struct vega10_hwmgr *data = hwmgr->backend;
1522         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1523         uint32_t gfx_max_clock =
1524                         hwmgr->platform_descriptor.overdriveLimit.engineClock;
1525         uint32_t i = 0;
1526
1527         if (hwmgr->od_enabled)
1528                 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1529                                                 &(data->odn_dpm_table.vdd_dep_on_sclk);
1530         else
1531                 dep_on_sclk = table_info->vdd_dep_on_sclk;
1532
1533         PP_ASSERT_WITH_CODE(dep_on_sclk,
1534                         "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1535                         return -EINVAL);
1536
1537         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1538                 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1539         else {
1540                 for (i = 0; i < dep_on_sclk->count; i++) {
1541                         if (dep_on_sclk->entries[i].clk == gfx_clock)
1542                                 break;
1543                 }
1544                 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1545                                 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1546                                 return -EINVAL);
1547         }
1548
1549         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1550                         COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1551                         gfx_clock, &dividers),
1552                         "Failed to get GFX Clock settings from VBIOS!",
1553                         return -EINVAL);
1554
1555         /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1556         current_gfxclk_level->FbMult =
1557                         cpu_to_le32(dividers.ulPll_fb_mult);
1558         /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1559         current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1560         current_gfxclk_level->SsFbMult =
1561                         cpu_to_le32(dividers.ulPll_ss_fbsmult);
1562         current_gfxclk_level->SsSlewFrac =
1563                         cpu_to_le16(dividers.usPll_ss_slew_frac);
1564         current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1565
1566         *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1567
1568         return 0;
1569 }
1570
1571 /**
1572  * @brief Populates single SMC SOCCLK structure using the provided clock.
1573  *
1574  * @param    hwmgr - the address of the hardware manager.
1575  * @param    soc_clock - the SOC clock to use to populate the structure.
1576  * @param    current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1577  * @return   0 on success..
1578  */
1579 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1580                 uint32_t soc_clock, uint8_t *current_soc_did,
1581                 uint8_t *current_vol_index)
1582 {
1583         struct vega10_hwmgr *data = hwmgr->backend;
1584         struct phm_ppt_v2_information *table_info =
1585                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1586         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1587         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1588         uint32_t i;
1589
1590         if (hwmgr->od_enabled) {
1591                 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1592                                                 &data->odn_dpm_table.vdd_dep_on_socclk;
1593                 for (i = 0; i < dep_on_soc->count; i++) {
1594                         if (dep_on_soc->entries[i].clk >= soc_clock)
1595                                 break;
1596                 }
1597         } else {
1598                 dep_on_soc = table_info->vdd_dep_on_socclk;
1599                 for (i = 0; i < dep_on_soc->count; i++) {
1600                         if (dep_on_soc->entries[i].clk == soc_clock)
1601                                 break;
1602                 }
1603         }
1604
1605         PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1606                         "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1607                         return -EINVAL);
1608
1609         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1610                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1611                         soc_clock, &dividers),
1612                         "Failed to get SOC Clock settings from VBIOS!",
1613                         return -EINVAL);
1614
1615         *current_soc_did = (uint8_t)dividers.ulDid;
1616         *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1617         return 0;
1618 }
1619
1620 /**
1621 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1622 *
1623 * @param    hwmgr      the address of the hardware manager
1624 */
1625 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1626 {
1627         struct vega10_hwmgr *data = hwmgr->backend;
1628         struct phm_ppt_v2_information *table_info =
1629                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1630         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1631         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1632         int result = 0;
1633         uint32_t i, j;
1634
1635         for (i = 0; i < dpm_table->count; i++) {
1636                 result = vega10_populate_single_gfx_level(hwmgr,
1637                                 dpm_table->dpm_levels[i].value,
1638                                 &(pp_table->GfxclkLevel[i]),
1639                                 &(pp_table->AcgFreqTable[i]));
1640                 if (result)
1641                         return result;
1642         }
1643
1644         j = i - 1;
1645         while (i < NUM_GFXCLK_DPM_LEVELS) {
1646                 result = vega10_populate_single_gfx_level(hwmgr,
1647                                 dpm_table->dpm_levels[j].value,
1648                                 &(pp_table->GfxclkLevel[i]),
1649                                 &(pp_table->AcgFreqTable[i]));
1650                 if (result)
1651                         return result;
1652                 i++;
1653         }
1654
1655         pp_table->GfxclkSlewRate =
1656                         cpu_to_le16(table_info->us_gfxclk_slew_rate);
1657
1658         dpm_table = &(data->dpm_table.soc_table);
1659         for (i = 0; i < dpm_table->count; i++) {
1660                 result = vega10_populate_single_soc_level(hwmgr,
1661                                 dpm_table->dpm_levels[i].value,
1662                                 &(pp_table->SocclkDid[i]),
1663                                 &(pp_table->SocDpmVoltageIndex[i]));
1664                 if (result)
1665                         return result;
1666         }
1667
1668         j = i - 1;
1669         while (i < NUM_SOCCLK_DPM_LEVELS) {
1670                 result = vega10_populate_single_soc_level(hwmgr,
1671                                 dpm_table->dpm_levels[j].value,
1672                                 &(pp_table->SocclkDid[i]),
1673                                 &(pp_table->SocDpmVoltageIndex[i]));
1674                 if (result)
1675                         return result;
1676                 i++;
1677         }
1678
1679         return result;
1680 }
1681
1682 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1683 {
1684         struct vega10_hwmgr *data = hwmgr->backend;
1685         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1686         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1687         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1688
1689         uint8_t soc_vid = 0;
1690         uint32_t i, max_vddc_level;
1691
1692         if (hwmgr->od_enabled)
1693                 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1694         else
1695                 vddc_lookup_table = table_info->vddc_lookup_table;
1696
1697         max_vddc_level = vddc_lookup_table->count;
1698         for (i = 0; i < max_vddc_level; i++) {
1699                 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1700                 pp_table->SocVid[i] = soc_vid;
1701         }
1702         while (i < MAX_REGULAR_DPM_NUMBER) {
1703                 pp_table->SocVid[i] = soc_vid;
1704                 i++;
1705         }
1706 }
1707
1708 /**
1709  * @brief Populates single SMC GFXCLK structure using the provided clock.
1710  *
1711  * @param    hwmgr - the address of the hardware manager.
1712  * @param    mem_clock - the memory clock to use to populate the structure.
1713  * @return   0 on success..
1714  */
1715 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1716                 uint32_t mem_clock, uint8_t *current_mem_vid,
1717                 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1718 {
1719         struct vega10_hwmgr *data = hwmgr->backend;
1720         struct phm_ppt_v2_information *table_info =
1721                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1722         struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1723         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1724         uint32_t mem_max_clock =
1725                         hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1726         uint32_t i = 0;
1727
1728         if (hwmgr->od_enabled)
1729                 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1730                                         &data->odn_dpm_table.vdd_dep_on_mclk;
1731         else
1732                 dep_on_mclk = table_info->vdd_dep_on_mclk;
1733
1734         PP_ASSERT_WITH_CODE(dep_on_mclk,
1735                         "Invalid SOC_VDD-UCLK Dependency Table!",
1736                         return -EINVAL);
1737
1738         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1739                 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1740         } else {
1741                 for (i = 0; i < dep_on_mclk->count; i++) {
1742                         if (dep_on_mclk->entries[i].clk == mem_clock)
1743                                 break;
1744                 }
1745                 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1746                                 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1747                                 return -EINVAL);
1748         }
1749
1750         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1751                         hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1752                         "Failed to get UCLK settings from VBIOS!",
1753                         return -1);
1754
1755         *current_mem_vid =
1756                         (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1757         *current_mem_soc_vind =
1758                         (uint8_t)(dep_on_mclk->entries[i].vddInd);
1759         current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1760         current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1761
1762         PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1763                         "Invalid Divider ID!",
1764                         return -EINVAL);
1765
1766         return 0;
1767 }
1768
1769 /**
1770  * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1771  *
1772  * @param    pHwMgr - the address of the hardware manager.
1773  * @return   PP_Result_OK on success.
1774  */
1775 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1776 {
1777         struct vega10_hwmgr *data = hwmgr->backend;
1778         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1779         struct vega10_single_dpm_table *dpm_table =
1780                         &(data->dpm_table.mem_table);
1781         int result = 0;
1782         uint32_t i, j;
1783
1784         for (i = 0; i < dpm_table->count; i++) {
1785                 result = vega10_populate_single_memory_level(hwmgr,
1786                                 dpm_table->dpm_levels[i].value,
1787                                 &(pp_table->MemVid[i]),
1788                                 &(pp_table->UclkLevel[i]),
1789                                 &(pp_table->MemSocVoltageIndex[i]));
1790                 if (result)
1791                         return result;
1792         }
1793
1794         j = i - 1;
1795         while (i < NUM_UCLK_DPM_LEVELS) {
1796                 result = vega10_populate_single_memory_level(hwmgr,
1797                                 dpm_table->dpm_levels[j].value,
1798                                 &(pp_table->MemVid[i]),
1799                                 &(pp_table->UclkLevel[i]),
1800                                 &(pp_table->MemSocVoltageIndex[i]));
1801                 if (result)
1802                         return result;
1803                 i++;
1804         }
1805
1806         pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1807         pp_table->MemoryChannelWidth =
1808                         (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1809                                         channel_number[data->mem_channels]);
1810
1811         pp_table->LowestUclkReservedForUlv =
1812                         (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1813
1814         return result;
1815 }
1816
1817 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1818                 DSPCLK_e disp_clock)
1819 {
1820         struct vega10_hwmgr *data = hwmgr->backend;
1821         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1822         struct phm_ppt_v2_information *table_info =
1823                         (struct phm_ppt_v2_information *)
1824                         (hwmgr->pptable);
1825         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1826         uint32_t i;
1827         uint16_t clk = 0, vddc = 0;
1828         uint8_t vid = 0;
1829
1830         switch (disp_clock) {
1831         case DSPCLK_DCEFCLK:
1832                 dep_table = table_info->vdd_dep_on_dcefclk;
1833                 break;
1834         case DSPCLK_DISPCLK:
1835                 dep_table = table_info->vdd_dep_on_dispclk;
1836                 break;
1837         case DSPCLK_PIXCLK:
1838                 dep_table = table_info->vdd_dep_on_pixclk;
1839                 break;
1840         case DSPCLK_PHYCLK:
1841                 dep_table = table_info->vdd_dep_on_phyclk;
1842                 break;
1843         default:
1844                 return -1;
1845         }
1846
1847         PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1848                         "Number Of Entries Exceeded maximum!",
1849                         return -1);
1850
1851         for (i = 0; i < dep_table->count; i++) {
1852                 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1853                 vddc = table_info->vddc_lookup_table->
1854                                 entries[dep_table->entries[i].vddInd].us_vdd;
1855                 vid = (uint8_t)convert_to_vid(vddc);
1856                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1857                                 cpu_to_le16(clk);
1858                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1859                                 cpu_to_le16(vid);
1860         }
1861
1862         while (i < NUM_DSPCLK_LEVELS) {
1863                 pp_table->DisplayClockTable[disp_clock][i].Freq =
1864                                 cpu_to_le16(clk);
1865                 pp_table->DisplayClockTable[disp_clock][i].Vid =
1866                                 cpu_to_le16(vid);
1867                 i++;
1868         }
1869
1870         return 0;
1871 }
1872
1873 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1874 {
1875         uint32_t i;
1876
1877         for (i = 0; i < DSPCLK_COUNT; i++) {
1878                 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1879                                 "Failed to populate Clock in DisplayClockTable!",
1880                                 return -1);
1881         }
1882
1883         return 0;
1884 }
1885
1886 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1887                 uint32_t eclock, uint8_t *current_eclk_did,
1888                 uint8_t *current_soc_vol)
1889 {
1890         struct phm_ppt_v2_information *table_info =
1891                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1892         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1893                         table_info->mm_dep_table;
1894         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1895         uint32_t i;
1896
1897         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1898                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1899                         eclock, &dividers),
1900                         "Failed to get ECLK clock settings from VBIOS!",
1901                         return -1);
1902
1903         *current_eclk_did = (uint8_t)dividers.ulDid;
1904
1905         for (i = 0; i < dep_table->count; i++) {
1906                 if (dep_table->entries[i].eclk == eclock)
1907                         *current_soc_vol = dep_table->entries[i].vddcInd;
1908         }
1909
1910         return 0;
1911 }
1912
1913 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1914 {
1915         struct vega10_hwmgr *data = hwmgr->backend;
1916         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1917         struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1918         int result = -EINVAL;
1919         uint32_t i, j;
1920
1921         for (i = 0; i < dpm_table->count; i++) {
1922                 result = vega10_populate_single_eclock_level(hwmgr,
1923                                 dpm_table->dpm_levels[i].value,
1924                                 &(pp_table->EclkDid[i]),
1925                                 &(pp_table->VceDpmVoltageIndex[i]));
1926                 if (result)
1927                         return result;
1928         }
1929
1930         j = i - 1;
1931         while (i < NUM_VCE_DPM_LEVELS) {
1932                 result = vega10_populate_single_eclock_level(hwmgr,
1933                                 dpm_table->dpm_levels[j].value,
1934                                 &(pp_table->EclkDid[i]),
1935                                 &(pp_table->VceDpmVoltageIndex[i]));
1936                 if (result)
1937                         return result;
1938                 i++;
1939         }
1940
1941         return result;
1942 }
1943
1944 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
1945                 uint32_t vclock, uint8_t *current_vclk_did)
1946 {
1947         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1948
1949         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1950                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1951                         vclock, &dividers),
1952                         "Failed to get VCLK clock settings from VBIOS!",
1953                         return -EINVAL);
1954
1955         *current_vclk_did = (uint8_t)dividers.ulDid;
1956
1957         return 0;
1958 }
1959
1960 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
1961                 uint32_t dclock, uint8_t *current_dclk_did)
1962 {
1963         struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1964
1965         PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1966                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1967                         dclock, &dividers),
1968                         "Failed to get DCLK clock settings from VBIOS!",
1969                         return -EINVAL);
1970
1971         *current_dclk_did = (uint8_t)dividers.ulDid;
1972
1973         return 0;
1974 }
1975
1976 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
1977 {
1978         struct vega10_hwmgr *data = hwmgr->backend;
1979         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1980         struct vega10_single_dpm_table *vclk_dpm_table =
1981                         &(data->dpm_table.vclk_table);
1982         struct vega10_single_dpm_table *dclk_dpm_table =
1983                         &(data->dpm_table.dclk_table);
1984         struct phm_ppt_v2_information *table_info =
1985                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1986         struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1987                         table_info->mm_dep_table;
1988         int result = -EINVAL;
1989         uint32_t i, j;
1990
1991         for (i = 0; i < vclk_dpm_table->count; i++) {
1992                 result = vega10_populate_single_vclock_level(hwmgr,
1993                                 vclk_dpm_table->dpm_levels[i].value,
1994                                 &(pp_table->VclkDid[i]));
1995                 if (result)
1996                         return result;
1997         }
1998
1999         j = i - 1;
2000         while (i < NUM_UVD_DPM_LEVELS) {
2001                 result = vega10_populate_single_vclock_level(hwmgr,
2002                                 vclk_dpm_table->dpm_levels[j].value,
2003                                 &(pp_table->VclkDid[i]));
2004                 if (result)
2005                         return result;
2006                 i++;
2007         }
2008
2009         for (i = 0; i < dclk_dpm_table->count; i++) {
2010                 result = vega10_populate_single_dclock_level(hwmgr,
2011                                 dclk_dpm_table->dpm_levels[i].value,
2012                                 &(pp_table->DclkDid[i]));
2013                 if (result)
2014                         return result;
2015         }
2016
2017         j = i - 1;
2018         while (i < NUM_UVD_DPM_LEVELS) {
2019                 result = vega10_populate_single_dclock_level(hwmgr,
2020                                 dclk_dpm_table->dpm_levels[j].value,
2021                                 &(pp_table->DclkDid[i]));
2022                 if (result)
2023                         return result;
2024                 i++;
2025         }
2026
2027         for (i = 0; i < dep_table->count; i++) {
2028                 if (dep_table->entries[i].vclk ==
2029                                 vclk_dpm_table->dpm_levels[i].value &&
2030                         dep_table->entries[i].dclk ==
2031                                 dclk_dpm_table->dpm_levels[i].value)
2032                         pp_table->UvdDpmVoltageIndex[i] =
2033                                         dep_table->entries[i].vddcInd;
2034                 else
2035                         return -1;
2036         }
2037
2038         j = i - 1;
2039         while (i < NUM_UVD_DPM_LEVELS) {
2040                 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2041                 i++;
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2048 {
2049         struct vega10_hwmgr *data = hwmgr->backend;
2050         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2051         struct phm_ppt_v2_information *table_info =
2052                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2053         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2054                         table_info->vdd_dep_on_sclk;
2055         uint32_t i;
2056
2057         for (i = 0; i < dep_table->count; i++) {
2058                 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2059                 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2060                                 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2067 {
2068         struct vega10_hwmgr *data = hwmgr->backend;
2069         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2070         struct phm_ppt_v2_information *table_info =
2071                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2072         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2073                         table_info->vdd_dep_on_sclk;
2074         struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2075         int result = 0;
2076         uint32_t i;
2077
2078         pp_table->MinVoltageVid = (uint8_t)0xff;
2079         pp_table->MaxVoltageVid = (uint8_t)0;
2080
2081         if (data->smu_features[GNLD_AVFS].supported) {
2082                 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2083                 if (!result) {
2084                         pp_table->MinVoltageVid = (uint8_t)
2085                                         convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2086                         pp_table->MaxVoltageVid = (uint8_t)
2087                                         convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2088
2089                         pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2090                         pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2091                         pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2092                         pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2093                         pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2094                         pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2095                         pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2096
2097                         pp_table->BtcGbVdroopTableCksOff.a0 =
2098                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2099                         pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2100                         pp_table->BtcGbVdroopTableCksOff.a1 =
2101                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2102                         pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2103                         pp_table->BtcGbVdroopTableCksOff.a2 =
2104                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2105                         pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2106
2107                         pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2108                         pp_table->BtcGbVdroopTableCksOn.a0 =
2109                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2110                         pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2111                         pp_table->BtcGbVdroopTableCksOn.a1 =
2112                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2113                         pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2114                         pp_table->BtcGbVdroopTableCksOn.a2 =
2115                                         cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2116                         pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2117
2118                         pp_table->AvfsGbCksOn.m1 =
2119                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2120                         pp_table->AvfsGbCksOn.m2 =
2121                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2122                         pp_table->AvfsGbCksOn.b =
2123                                         cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2124                         pp_table->AvfsGbCksOn.m1_shift = 24;
2125                         pp_table->AvfsGbCksOn.m2_shift = 12;
2126                         pp_table->AvfsGbCksOn.b_shift = 0;
2127
2128                         pp_table->OverrideAvfsGbCksOn =
2129                                         avfs_params.ucEnableGbFuseTableCkson;
2130                         pp_table->AvfsGbCksOff.m1 =
2131                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2132                         pp_table->AvfsGbCksOff.m2 =
2133                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2134                         pp_table->AvfsGbCksOff.b =
2135                                         cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2136                         pp_table->AvfsGbCksOff.m1_shift = 24;
2137                         pp_table->AvfsGbCksOff.m2_shift = 12;
2138                         pp_table->AvfsGbCksOff.b_shift = 0;
2139
2140                         for (i = 0; i < dep_table->count; i++)
2141                                 pp_table->StaticVoltageOffsetVid[i] =
2142                                                 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2143
2144                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2145                                         data->disp_clk_quad_eqn_a) &&
2146                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2147                                         data->disp_clk_quad_eqn_b)) {
2148                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2149                                                 (int32_t)data->disp_clk_quad_eqn_a;
2150                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2151                                                 (int32_t)data->disp_clk_quad_eqn_b;
2152                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2153                                                 (int32_t)data->disp_clk_quad_eqn_c;
2154                         } else {
2155                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2156                                                 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2157                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2158                                                 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2159                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2160                                                 (int32_t)avfs_params.ulDispclk2GfxclkB;
2161                         }
2162
2163                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2164                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2165                         pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2166
2167                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2168                                         data->dcef_clk_quad_eqn_a) &&
2169                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2170                                         data->dcef_clk_quad_eqn_b)) {
2171                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2172                                                 (int32_t)data->dcef_clk_quad_eqn_a;
2173                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2174                                                 (int32_t)data->dcef_clk_quad_eqn_b;
2175                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2176                                                 (int32_t)data->dcef_clk_quad_eqn_c;
2177                         } else {
2178                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2179                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2180                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2181                                                 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2182                                 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2183                                                 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2184                         }
2185
2186                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2187                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2188                         pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2189
2190                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2191                                         data->pixel_clk_quad_eqn_a) &&
2192                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2193                                         data->pixel_clk_quad_eqn_b)) {
2194                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2195                                                 (int32_t)data->pixel_clk_quad_eqn_a;
2196                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2197                                                 (int32_t)data->pixel_clk_quad_eqn_b;
2198                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2199                                                 (int32_t)data->pixel_clk_quad_eqn_c;
2200                         } else {
2201                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2202                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2203                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2204                                                 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2205                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2206                                                 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2207                         }
2208
2209                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2210                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2211                         pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2212                         if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2213                                         data->phy_clk_quad_eqn_a) &&
2214                                 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2215                                         data->phy_clk_quad_eqn_b)) {
2216                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2217                                                 (int32_t)data->phy_clk_quad_eqn_a;
2218                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2219                                                 (int32_t)data->phy_clk_quad_eqn_b;
2220                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2221                                                 (int32_t)data->phy_clk_quad_eqn_c;
2222                         } else {
2223                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2224                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2225                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2226                                                 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2227                                 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2228                                                 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2229                         }
2230
2231                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2232                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2233                         pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2234
2235                         pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2236                         pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2237                         pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2238                         pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2239                         pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2240                         pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2241
2242                         pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2243                         pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2244                         pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2245                         pp_table->AcgAvfsGb.m1_shift             = 0;
2246                         pp_table->AcgAvfsGb.m2_shift             = 0;
2247                         pp_table->AcgAvfsGb.b_shift              = 0;
2248
2249                 } else {
2250                         data->smu_features[GNLD_AVFS].supported = false;
2251                 }
2252         }
2253
2254         return 0;
2255 }
2256
2257 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2258 {
2259         struct vega10_hwmgr *data = hwmgr->backend;
2260         uint32_t agc_btc_response;
2261
2262         if (data->smu_features[GNLD_ACG].supported) {
2263                 if (0 == vega10_enable_smc_features(hwmgr, true,
2264                                         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2265                         data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2266
2267                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
2268
2269                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
2270                 agc_btc_response = smum_get_argument(hwmgr);
2271
2272                 if (1 == agc_btc_response) {
2273                         if (1 == data->acg_loop_state)
2274                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
2275                         else if (2 == data->acg_loop_state)
2276                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
2277                         if (0 == vega10_enable_smc_features(hwmgr, true,
2278                                 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2279                                         data->smu_features[GNLD_ACG].enabled = true;
2280                 } else {
2281                         pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2282                         data->smu_features[GNLD_ACG].enabled = false;
2283                 }
2284         }
2285
2286         return 0;
2287 }
2288
2289 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2290 {
2291         struct vega10_hwmgr *data = hwmgr->backend;
2292
2293         if (data->smu_features[GNLD_ACG].supported &&
2294             data->smu_features[GNLD_ACG].enabled)
2295                 if (!vega10_enable_smc_features(hwmgr, false,
2296                         data->smu_features[GNLD_ACG].smu_feature_bitmap))
2297                         data->smu_features[GNLD_ACG].enabled = false;
2298
2299         return 0;
2300 }
2301
2302 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2303 {
2304         struct vega10_hwmgr *data = hwmgr->backend;
2305         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2306         struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2307         int result;
2308
2309         result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2310         if (!result) {
2311                 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2312                     data->registry_data.regulator_hot_gpio_support) {
2313                         pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2314                         pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2315                         pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2316                         pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2317                 } else {
2318                         pp_table->VR0HotGpio = 0;
2319                         pp_table->VR0HotPolarity = 0;
2320                         pp_table->VR1HotGpio = 0;
2321                         pp_table->VR1HotPolarity = 0;
2322                 }
2323
2324                 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2325                     data->registry_data.ac_dc_switch_gpio_support) {
2326                         pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2327                         pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2328                 } else {
2329                         pp_table->AcDcGpio = 0;
2330                         pp_table->AcDcPolarity = 0;
2331                 }
2332         }
2333
2334         return result;
2335 }
2336
2337 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2338 {
2339         struct vega10_hwmgr *data = hwmgr->backend;
2340
2341         if (data->smu_features[GNLD_AVFS].supported) {
2342                 if (enable) {
2343                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2344                                         true,
2345                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2346                                         "[avfs_control] Attempt to Enable AVFS feature Failed!",
2347                                         return -1);
2348                         data->smu_features[GNLD_AVFS].enabled = true;
2349                 } else {
2350                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2351                                         false,
2352                                         data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2353                                         "[avfs_control] Attempt to Disable AVFS feature Failed!",
2354                                         return -1);
2355                         data->smu_features[GNLD_AVFS].enabled = false;
2356                 }
2357         }
2358
2359         return 0;
2360 }
2361
2362 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2363 {
2364         struct vega10_hwmgr *data = hwmgr->backend;
2365
2366         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2367                 vega10_avfs_enable(hwmgr, false);
2368         } else if (data->need_update_dpm_table) {
2369                 vega10_avfs_enable(hwmgr, false);
2370                 vega10_avfs_enable(hwmgr, true);
2371         } else {
2372                 vega10_avfs_enable(hwmgr, true);
2373         }
2374
2375         return 0;
2376 }
2377
2378 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2379 {
2380         int result = 0;
2381
2382         uint64_t serial_number = 0;
2383         uint32_t top32, bottom32;
2384         struct phm_fuses_default fuse;
2385
2386         struct vega10_hwmgr *data = hwmgr->backend;
2387         AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2388
2389         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
2390         top32 = smum_get_argument(hwmgr);
2391
2392         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
2393         bottom32 = smum_get_argument(hwmgr);
2394
2395         serial_number = ((uint64_t)bottom32 << 32) | top32;
2396
2397         if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2398                 avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2399                 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2400                 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2401                 avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2402                 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2403                 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2404                 avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2405                 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2406                 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2407                 result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2408                                                 AVFSFUSETABLE, false);
2409                 PP_ASSERT_WITH_CODE(!result,
2410                         "Failed to upload FuseOVerride!",
2411                         );
2412         }
2413
2414         return result;
2415 }
2416
2417 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2418 {
2419         struct vega10_hwmgr *data = hwmgr->backend;
2420         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2421         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2422         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2423         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2424         uint32_t i;
2425
2426         dep_table = table_info->vdd_dep_on_mclk;
2427         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2428
2429         for (i = 0; i < dep_table->count; i++) {
2430                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2431                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2432                         return;
2433                 }
2434         }
2435
2436         dep_table = table_info->vdd_dep_on_sclk;
2437         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2438         for (i = 0; i < dep_table->count; i++) {
2439                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2440                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2441                         return;
2442                 }
2443         }
2444
2445         if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2446                 data->need_update_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
2447                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2448         }
2449 }
2450
2451 /**
2452 * Initializes the SMC table and uploads it
2453 *
2454 * @param    hwmgr  the address of the powerplay hardware manager.
2455 * @param    pInput  the pointer to input data (PowerState)
2456 * @return   always 0
2457 */
2458 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2459 {
2460         int result;
2461         struct vega10_hwmgr *data = hwmgr->backend;
2462         struct phm_ppt_v2_information *table_info =
2463                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
2464         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2465         struct pp_atomfwctrl_voltage_table voltage_table;
2466         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2467         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2468
2469         result = vega10_setup_default_dpm_tables(hwmgr);
2470         PP_ASSERT_WITH_CODE(!result,
2471                         "Failed to setup default DPM tables!",
2472                         return result);
2473
2474         /* initialize ODN table */
2475         if (hwmgr->od_enabled) {
2476                 if (odn_table->max_vddc) {
2477                         data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2478                         vega10_check_dpm_table_updated(hwmgr);
2479                 } else {
2480                         vega10_odn_initial_default_setting(hwmgr);
2481                 }
2482         }
2483
2484         pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2485                         VOLTAGE_OBJ_SVID2,  &voltage_table);
2486         pp_table->MaxVidStep = voltage_table.max_vid_step;
2487
2488         pp_table->GfxDpmVoltageMode =
2489                         (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2490         pp_table->SocDpmVoltageMode =
2491                         (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2492         pp_table->UclkDpmVoltageMode =
2493                         (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2494         pp_table->UvdDpmVoltageMode =
2495                         (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2496         pp_table->VceDpmVoltageMode =
2497                         (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2498         pp_table->Mp0DpmVoltageMode =
2499                         (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2500
2501         pp_table->DisplayDpmVoltageMode =
2502                         (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2503
2504         data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2505         data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2506
2507         if (data->registry_data.ulv_support &&
2508                         table_info->us_ulv_voltage_offset) {
2509                 result = vega10_populate_ulv_state(hwmgr);
2510                 PP_ASSERT_WITH_CODE(!result,
2511                                 "Failed to initialize ULV state!",
2512                                 return result);
2513         }
2514
2515         result = vega10_populate_smc_link_levels(hwmgr);
2516         PP_ASSERT_WITH_CODE(!result,
2517                         "Failed to initialize Link Level!",
2518                         return result);
2519
2520         result = vega10_populate_all_graphic_levels(hwmgr);
2521         PP_ASSERT_WITH_CODE(!result,
2522                         "Failed to initialize Graphics Level!",
2523                         return result);
2524
2525         result = vega10_populate_all_memory_levels(hwmgr);
2526         PP_ASSERT_WITH_CODE(!result,
2527                         "Failed to initialize Memory Level!",
2528                         return result);
2529
2530         vega10_populate_vddc_soc_levels(hwmgr);
2531
2532         result = vega10_populate_all_display_clock_levels(hwmgr);
2533         PP_ASSERT_WITH_CODE(!result,
2534                         "Failed to initialize Display Level!",
2535                         return result);
2536
2537         result = vega10_populate_smc_vce_levels(hwmgr);
2538         PP_ASSERT_WITH_CODE(!result,
2539                         "Failed to initialize VCE Level!",
2540                         return result);
2541
2542         result = vega10_populate_smc_uvd_levels(hwmgr);
2543         PP_ASSERT_WITH_CODE(!result,
2544                         "Failed to initialize UVD Level!",
2545                         return result);
2546
2547         if (data->registry_data.clock_stretcher_support) {
2548                 result = vega10_populate_clock_stretcher_table(hwmgr);
2549                 PP_ASSERT_WITH_CODE(!result,
2550                                 "Failed to populate Clock Stretcher Table!",
2551                                 return result);
2552         }
2553
2554         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2555         if (!result) {
2556                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2557                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2558                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2559                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2560                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2561                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2562                                 SMU9_SYSPLL0_SOCCLK_ID, &boot_up_values.ulSocClk);
2563
2564                 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2565                                 SMU9_SYSPLL0_DCEFCLK_ID, &boot_up_values.ulDCEFClk);
2566
2567                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2568                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2569                 if (0 != boot_up_values.usVddc) {
2570                         smum_send_msg_to_smc_with_parameter(hwmgr,
2571                                                 PPSMC_MSG_SetFloorSocVoltage,
2572                                                 (boot_up_values.usVddc * 4));
2573                         data->vbios_boot_state.bsoc_vddc_lock = true;
2574                 } else {
2575                         data->vbios_boot_state.bsoc_vddc_lock = false;
2576                 }
2577                 smum_send_msg_to_smc_with_parameter(hwmgr,
2578                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
2579                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
2580         }
2581
2582         result = vega10_populate_avfs_parameters(hwmgr);
2583         PP_ASSERT_WITH_CODE(!result,
2584                         "Failed to initialize AVFS Parameters!",
2585                         return result);
2586
2587         result = vega10_populate_gpio_parameters(hwmgr);
2588         PP_ASSERT_WITH_CODE(!result,
2589                         "Failed to initialize GPIO Parameters!",
2590                         return result);
2591
2592         pp_table->GfxclkAverageAlpha = (uint8_t)
2593                         (data->gfxclk_average_alpha);
2594         pp_table->SocclkAverageAlpha = (uint8_t)
2595                         (data->socclk_average_alpha);
2596         pp_table->UclkAverageAlpha = (uint8_t)
2597                         (data->uclk_average_alpha);
2598         pp_table->GfxActivityAverageAlpha = (uint8_t)
2599                         (data->gfx_activity_average_alpha);
2600
2601         vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2602
2603         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2604
2605         PP_ASSERT_WITH_CODE(!result,
2606                         "Failed to upload PPtable!", return result);
2607
2608         result = vega10_avfs_enable(hwmgr, true);
2609         PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2610                                         return result);
2611         vega10_acg_enable(hwmgr);
2612
2613         return 0;
2614 }
2615
2616 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2617 {
2618         struct vega10_hwmgr *data = hwmgr->backend;
2619
2620         if (data->smu_features[GNLD_THERMAL].supported) {
2621                 if (data->smu_features[GNLD_THERMAL].enabled)
2622                         pr_info("THERMAL Feature Already enabled!");
2623
2624                 PP_ASSERT_WITH_CODE(
2625                                 !vega10_enable_smc_features(hwmgr,
2626                                 true,
2627                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2628                                 "Enable THERMAL Feature Failed!",
2629                                 return -1);
2630                 data->smu_features[GNLD_THERMAL].enabled = true;
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2637 {
2638         struct vega10_hwmgr *data = hwmgr->backend;
2639
2640         if (data->smu_features[GNLD_THERMAL].supported) {
2641                 if (!data->smu_features[GNLD_THERMAL].enabled)
2642                         pr_info("THERMAL Feature Already disabled!");
2643
2644                 PP_ASSERT_WITH_CODE(
2645                                 !vega10_enable_smc_features(hwmgr,
2646                                 false,
2647                                 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2648                                 "disable THERMAL Feature Failed!",
2649                                 return -1);
2650                 data->smu_features[GNLD_THERMAL].enabled = false;
2651         }
2652
2653         return 0;
2654 }
2655
2656 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2657 {
2658         struct vega10_hwmgr *data = hwmgr->backend;
2659
2660         if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2661                 if (data->smu_features[GNLD_VR0HOT].supported) {
2662                         PP_ASSERT_WITH_CODE(
2663                                         !vega10_enable_smc_features(hwmgr,
2664                                         true,
2665                                         data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2666                                         "Attempt to Enable VR0 Hot feature Failed!",
2667                                         return -1);
2668                         data->smu_features[GNLD_VR0HOT].enabled = true;
2669                 } else {
2670                         if (data->smu_features[GNLD_VR1HOT].supported) {
2671                                 PP_ASSERT_WITH_CODE(
2672                                                 !vega10_enable_smc_features(hwmgr,
2673                                                 true,
2674                                                 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2675                                                 "Attempt to Enable VR0 Hot feature Failed!",
2676                                                 return -1);
2677                                 data->smu_features[GNLD_VR1HOT].enabled = true;
2678                         }
2679                 }
2680         }
2681         return 0;
2682 }
2683
2684 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2685 {
2686         struct vega10_hwmgr *data = hwmgr->backend;
2687
2688         if (data->registry_data.ulv_support) {
2689                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2690                                 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2691                                 "Enable ULV Feature Failed!",
2692                                 return -1);
2693                 data->smu_features[GNLD_ULV].enabled = true;
2694         }
2695
2696         return 0;
2697 }
2698
2699 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2700 {
2701         struct vega10_hwmgr *data = hwmgr->backend;
2702
2703         if (data->registry_data.ulv_support) {
2704                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2705                                 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2706                                 "disable ULV Feature Failed!",
2707                                 return -EINVAL);
2708                 data->smu_features[GNLD_ULV].enabled = false;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2715 {
2716         struct vega10_hwmgr *data = hwmgr->backend;
2717
2718         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2719                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2720                                 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2721                                 "Attempt to Enable DS_GFXCLK Feature Failed!",
2722                                 return -EINVAL);
2723                 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2724         }
2725
2726         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2727                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2728                                 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2729                                 "Attempt to Enable DS_SOCCLK Feature Failed!",
2730                                 return -EINVAL);
2731                 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2732         }
2733
2734         if (data->smu_features[GNLD_DS_LCLK].supported) {
2735                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2736                                 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2737                                 "Attempt to Enable DS_LCLK Feature Failed!",
2738                                 return -EINVAL);
2739                 data->smu_features[GNLD_DS_LCLK].enabled = true;
2740         }
2741
2742         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2743                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2744                                 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2745                                 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2746                                 return -EINVAL);
2747                 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2748         }
2749
2750         return 0;
2751 }
2752
2753 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2754 {
2755         struct vega10_hwmgr *data = hwmgr->backend;
2756
2757         if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2758                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2759                                 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2760                                 "Attempt to disable DS_GFXCLK Feature Failed!",
2761                                 return -EINVAL);
2762                 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2763         }
2764
2765         if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2766                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2767                                 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2768                                 "Attempt to disable DS_ Feature Failed!",
2769                                 return -EINVAL);
2770                 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2771         }
2772
2773         if (data->smu_features[GNLD_DS_LCLK].supported) {
2774                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2775                                 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2776                                 "Attempt to disable DS_LCLK Feature Failed!",
2777                                 return -EINVAL);
2778                 data->smu_features[GNLD_DS_LCLK].enabled = false;
2779         }
2780
2781         if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2782                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2783                                 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2784                                 "Attempt to disable DS_DCEFCLK Feature Failed!",
2785                                 return -EINVAL);
2786                 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2787         }
2788
2789         return 0;
2790 }
2791
2792 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2793 {
2794         struct vega10_hwmgr *data = hwmgr->backend;
2795         uint32_t i, feature_mask = 0;
2796
2797
2798         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2799                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2800                                 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2801                 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2802                 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2803         }
2804
2805         for (i = 0; i < GNLD_DPM_MAX; i++) {
2806                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2807                         if (data->smu_features[i].supported) {
2808                                 if (data->smu_features[i].enabled) {
2809                                         feature_mask |= data->smu_features[i].
2810                                                         smu_feature_bitmap;
2811                                         data->smu_features[i].enabled = false;
2812                                 }
2813                         }
2814                 }
2815         }
2816
2817         vega10_enable_smc_features(hwmgr, false, feature_mask);
2818
2819         return 0;
2820 }
2821
2822 /**
2823  * @brief Tell SMC to enabled the supported DPMs.
2824  *
2825  * @param    hwmgr - the address of the powerplay hardware manager.
2826  * @Param    bitmap - bitmap for the features to enabled.
2827  * @return   0 on at least one DPM is successfully enabled.
2828  */
2829 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2830 {
2831         struct vega10_hwmgr *data = hwmgr->backend;
2832         uint32_t i, feature_mask = 0;
2833
2834         for (i = 0; i < GNLD_DPM_MAX; i++) {
2835                 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2836                         if (data->smu_features[i].supported) {
2837                                 if (!data->smu_features[i].enabled) {
2838                                         feature_mask |= data->smu_features[i].
2839                                                         smu_feature_bitmap;
2840                                         data->smu_features[i].enabled = true;
2841                                 }
2842                         }
2843                 }
2844         }
2845
2846         if (vega10_enable_smc_features(hwmgr,
2847                         true, feature_mask)) {
2848                 for (i = 0; i < GNLD_DPM_MAX; i++) {
2849                         if (data->smu_features[i].smu_feature_bitmap &
2850                                         feature_mask)
2851                                 data->smu_features[i].enabled = false;
2852                 }
2853         }
2854
2855         if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2856                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2857                                 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2858                 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2859                 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2860         }
2861
2862         if (data->vbios_boot_state.bsoc_vddc_lock) {
2863                 smum_send_msg_to_smc_with_parameter(hwmgr,
2864                                                 PPSMC_MSG_SetFloorSocVoltage, 0);
2865                 data->vbios_boot_state.bsoc_vddc_lock = false;
2866         }
2867
2868         if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2869                 if (data->smu_features[GNLD_ACDC].supported) {
2870                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2871                                         true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2872                                         "Attempt to Enable DS_GFXCLK Feature Failed!",
2873                                         return -1);
2874                         data->smu_features[GNLD_ACDC].enabled = true;
2875                 }
2876         }
2877
2878         return 0;
2879 }
2880
2881 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2882 {
2883         struct vega10_hwmgr *data = hwmgr->backend;
2884
2885         if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2886                 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2887                         pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2888                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2889                                 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2890                                 "Attempt to Enable PCC Limit feature Failed!",
2891                                 return -EINVAL);
2892                 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
2893         }
2894
2895         return 0;
2896 }
2897
2898 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2899 {
2900         struct vega10_hwmgr *data = hwmgr->backend;
2901         int tmp_result, result = 0;
2902
2903         vega10_enable_disable_PCC_limit_feature(hwmgr, true);
2904
2905         smum_send_msg_to_smc_with_parameter(hwmgr,
2906                 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2907
2908         tmp_result = vega10_construct_voltage_tables(hwmgr);
2909         PP_ASSERT_WITH_CODE(!tmp_result,
2910                         "Failed to construct voltage tables!",
2911                         result = tmp_result);
2912
2913         tmp_result = vega10_init_smc_table(hwmgr);
2914         PP_ASSERT_WITH_CODE(!tmp_result,
2915                         "Failed to initialize SMC table!",
2916                         result = tmp_result);
2917
2918         if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
2919                 tmp_result = vega10_enable_thermal_protection(hwmgr);
2920                 PP_ASSERT_WITH_CODE(!tmp_result,
2921                                 "Failed to enable thermal protection!",
2922                                 result = tmp_result);
2923         }
2924
2925         tmp_result = vega10_enable_vrhot_feature(hwmgr);
2926         PP_ASSERT_WITH_CODE(!tmp_result,
2927                         "Failed to enable VR hot feature!",
2928                         result = tmp_result);
2929
2930         tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
2931         PP_ASSERT_WITH_CODE(!tmp_result,
2932                         "Failed to enable deep sleep master switch!",
2933                         result = tmp_result);
2934
2935         tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
2936         PP_ASSERT_WITH_CODE(!tmp_result,
2937                         "Failed to start DPM!", result = tmp_result);
2938
2939         /* enable didt, do not abort if failed didt */
2940         tmp_result = vega10_enable_didt_config(hwmgr);
2941         PP_ASSERT(!tmp_result,
2942                         "Failed to enable didt config!");
2943
2944         tmp_result = vega10_enable_power_containment(hwmgr);
2945         PP_ASSERT_WITH_CODE(!tmp_result,
2946                         "Failed to enable power containment!",
2947                         result = tmp_result);
2948
2949         tmp_result = vega10_power_control_set_level(hwmgr);
2950         PP_ASSERT_WITH_CODE(!tmp_result,
2951                         "Failed to power control set level!",
2952                         result = tmp_result);
2953
2954         tmp_result = vega10_enable_ulv(hwmgr);
2955         PP_ASSERT_WITH_CODE(!tmp_result,
2956                         "Failed to enable ULV!",
2957                         result = tmp_result);
2958
2959         return result;
2960 }
2961
2962 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
2963 {
2964         return sizeof(struct vega10_power_state);
2965 }
2966
2967 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
2968                 void *state, struct pp_power_state *power_state,
2969                 void *pp_table, uint32_t classification_flag)
2970 {
2971         ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
2972         struct vega10_power_state *vega10_power_state =
2973                         cast_phw_vega10_power_state(&(power_state->hardware));
2974         struct vega10_performance_level *performance_level;
2975         ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
2976         ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
2977                         (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
2978         ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
2979                         (ATOM_Vega10_SOCCLK_Dependency_Table *)
2980                         (((unsigned long)powerplay_table) +
2981                         le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
2982         ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
2983                         (ATOM_Vega10_GFXCLK_Dependency_Table *)
2984                         (((unsigned long)powerplay_table) +
2985                         le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
2986         ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
2987                         (ATOM_Vega10_MCLK_Dependency_Table *)
2988                         (((unsigned long)powerplay_table) +
2989                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2990
2991
2992         /* The following fields are not initialized here:
2993          * id orderedList allStatesList
2994          */
2995         power_state->classification.ui_label =
2996                         (le16_to_cpu(state_entry->usClassification) &
2997                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2998                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2999         power_state->classification.flags = classification_flag;
3000         /* NOTE: There is a classification2 flag in BIOS
3001          * that is not being used right now
3002          */
3003         power_state->classification.temporary_state = false;
3004         power_state->classification.to_be_deleted = false;
3005
3006         power_state->validation.disallowOnDC =
3007                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3008                                         ATOM_Vega10_DISALLOW_ON_DC) != 0);
3009
3010         power_state->display.disableFrameModulation = false;
3011         power_state->display.limitRefreshrate = false;
3012         power_state->display.enableVariBright =
3013                         ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3014                                         ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3015
3016         power_state->validation.supportedPowerLevels = 0;
3017         power_state->uvd_clocks.VCLK = 0;
3018         power_state->uvd_clocks.DCLK = 0;
3019         power_state->temperatures.min = 0;
3020         power_state->temperatures.max = 0;
3021
3022         performance_level = &(vega10_power_state->performance_levels
3023                         [vega10_power_state->performance_level_count++]);
3024
3025         PP_ASSERT_WITH_CODE(
3026                         (vega10_power_state->performance_level_count <
3027                                         NUM_GFXCLK_DPM_LEVELS),
3028                         "Performance levels exceeds SMC limit!",
3029                         return -1);
3030
3031         PP_ASSERT_WITH_CODE(
3032                         (vega10_power_state->performance_level_count <=
3033                                         hwmgr->platform_descriptor.
3034                                         hardwareActivityPerformanceLevels),
3035                         "Performance levels exceeds Driver limit!",
3036                         return -1);
3037
3038         /* Performance levels are arranged from low to high. */
3039         performance_level->soc_clock = socclk_dep_table->entries
3040                         [state_entry->ucSocClockIndexLow].ulClk;
3041         performance_level->gfx_clock = gfxclk_dep_table->entries
3042                         [state_entry->ucGfxClockIndexLow].ulClk;
3043         performance_level->mem_clock = mclk_dep_table->entries
3044                         [state_entry->ucMemClockIndexLow].ulMemClk;
3045
3046         performance_level = &(vega10_power_state->performance_levels
3047                                 [vega10_power_state->performance_level_count++]);
3048         performance_level->soc_clock = socclk_dep_table->entries
3049                                 [state_entry->ucSocClockIndexHigh].ulClk;
3050         if (gfxclk_dep_table->ucRevId == 0) {
3051                 performance_level->gfx_clock = gfxclk_dep_table->entries
3052                         [state_entry->ucGfxClockIndexHigh].ulClk;
3053         } else if (gfxclk_dep_table->ucRevId == 1) {
3054                 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3055                 performance_level->gfx_clock = patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3056         }
3057
3058         performance_level->mem_clock = mclk_dep_table->entries
3059                         [state_entry->ucMemClockIndexHigh].ulMemClk;
3060         return 0;
3061 }
3062
3063 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3064                 unsigned long entry_index, struct pp_power_state *state)
3065 {
3066         int result;
3067         struct vega10_power_state *ps;
3068
3069         state->hardware.magic = PhwVega10_Magic;
3070
3071         ps = cast_phw_vega10_power_state(&state->hardware);
3072
3073         result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3074                         vega10_get_pp_table_entry_callback_func);
3075
3076         /*
3077          * This is the earliest time we have all the dependency table
3078          * and the VBIOS boot state
3079          */
3080         /* set DC compatible flag if this state supports DC */
3081         if (!state->validation.disallowOnDC)
3082                 ps->dc_compatible = true;
3083
3084         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3085         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3086
3087         return 0;
3088 }
3089
3090 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3091              struct pp_hw_power_state *hw_ps)
3092 {
3093         return 0;
3094 }
3095
3096 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3097                                 struct pp_power_state  *request_ps,
3098                         const struct pp_power_state *current_ps)
3099 {
3100         struct amdgpu_device *adev = hwmgr->adev;
3101         struct vega10_power_state *vega10_ps =
3102                                 cast_phw_vega10_power_state(&request_ps->hardware);
3103         uint32_t sclk;
3104         uint32_t mclk;
3105         struct PP_Clocks minimum_clocks = {0};
3106         bool disable_mclk_switching;
3107         bool disable_mclk_switching_for_frame_lock;
3108         bool disable_mclk_switching_for_vr;
3109         bool force_mclk_high;
3110         const struct phm_clock_and_voltage_limits *max_limits;
3111         uint32_t i;
3112         struct vega10_hwmgr *data = hwmgr->backend;
3113         struct phm_ppt_v2_information *table_info =
3114                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3115         int32_t count;
3116         uint32_t stable_pstate_sclk_dpm_percentage;
3117         uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3118         uint32_t latency;
3119
3120         data->battery_state = (PP_StateUILabel_Battery ==
3121                         request_ps->classification.ui_label);
3122
3123         if (vega10_ps->performance_level_count != 2)
3124                 pr_info("VI should always have 2 performance levels");
3125
3126         max_limits = adev->pm.ac_power ?
3127                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3128                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3129
3130         /* Cap clock DPM tables at DC MAX if it is in DC. */
3131         if (!adev->pm.ac_power) {
3132                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3133                         if (vega10_ps->performance_levels[i].mem_clock >
3134                                 max_limits->mclk)
3135                                 vega10_ps->performance_levels[i].mem_clock =
3136                                                 max_limits->mclk;
3137                         if (vega10_ps->performance_levels[i].gfx_clock >
3138                                 max_limits->sclk)
3139                                 vega10_ps->performance_levels[i].gfx_clock =
3140                                                 max_limits->sclk;
3141                 }
3142         }
3143
3144         /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3145         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3146         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3147
3148         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3149                 stable_pstate_sclk_dpm_percentage =
3150                         data->registry_data.stable_pstate_sclk_dpm_percentage;
3151                 PP_ASSERT_WITH_CODE(
3152                         data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3153                         data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3154                         "percent sclk value must range from 1% to 100%, setting default value",
3155                         stable_pstate_sclk_dpm_percentage = 75);
3156
3157                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3158                 stable_pstate_sclk = (max_limits->sclk *
3159                                 stable_pstate_sclk_dpm_percentage) / 100;
3160
3161                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3162                                 count >= 0; count--) {
3163                         if (stable_pstate_sclk >=
3164                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3165                                 stable_pstate_sclk =
3166                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3167                                 break;
3168                         }
3169                 }
3170
3171                 if (count < 0)
3172                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3173
3174                 stable_pstate_mclk = max_limits->mclk;
3175
3176                 minimum_clocks.engineClock = stable_pstate_sclk;
3177                 minimum_clocks.memoryClock = stable_pstate_mclk;
3178         }
3179
3180         disable_mclk_switching_for_frame_lock =
3181                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3182         disable_mclk_switching_for_vr =
3183                 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3184         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3185
3186         if (hwmgr->display_config->num_display == 0)
3187                 disable_mclk_switching = false;
3188         else
3189                 disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
3190                         disable_mclk_switching_for_frame_lock ||
3191                         disable_mclk_switching_for_vr ||
3192                         force_mclk_high;
3193
3194         sclk = vega10_ps->performance_levels[0].gfx_clock;
3195         mclk = vega10_ps->performance_levels[0].mem_clock;
3196
3197         if (sclk < minimum_clocks.engineClock)
3198                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3199                                 max_limits->sclk : minimum_clocks.engineClock;
3200
3201         if (mclk < minimum_clocks.memoryClock)
3202                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3203                                 max_limits->mclk : minimum_clocks.memoryClock;
3204
3205         vega10_ps->performance_levels[0].gfx_clock = sclk;
3206         vega10_ps->performance_levels[0].mem_clock = mclk;
3207
3208         if (vega10_ps->performance_levels[1].gfx_clock <
3209                         vega10_ps->performance_levels[0].gfx_clock)
3210                 vega10_ps->performance_levels[0].gfx_clock =
3211                                 vega10_ps->performance_levels[1].gfx_clock;
3212
3213         if (disable_mclk_switching) {
3214                 /* Set Mclk the max of level 0 and level 1 */
3215                 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3216                         mclk = vega10_ps->performance_levels[1].mem_clock;
3217
3218                 /* Find the lowest MCLK frequency that is within
3219                  * the tolerable latency defined in DAL
3220                  */
3221                 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3222                 for (i = 0; i < data->mclk_latency_table.count; i++) {
3223                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3224                                 (data->mclk_latency_table.entries[i].frequency >=
3225                                                 vega10_ps->performance_levels[0].mem_clock) &&
3226                                 (data->mclk_latency_table.entries[i].frequency <=
3227                                                 vega10_ps->performance_levels[1].mem_clock))
3228                                 mclk = data->mclk_latency_table.entries[i].frequency;
3229                 }
3230                 vega10_ps->performance_levels[0].mem_clock = mclk;
3231         } else {
3232                 if (vega10_ps->performance_levels[1].mem_clock <
3233                                 vega10_ps->performance_levels[0].mem_clock)
3234                         vega10_ps->performance_levels[0].mem_clock =
3235                                         vega10_ps->performance_levels[1].mem_clock;
3236         }
3237
3238         if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3239                 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3240                         vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3241                         vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3242                 }
3243         }
3244
3245         return 0;
3246 }
3247
3248 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3249 {
3250         struct vega10_hwmgr *data = hwmgr->backend;
3251
3252         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3253                 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3254
3255         return 0;
3256 }
3257
3258 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3259                 struct pp_hwmgr *hwmgr, const void *input)
3260 {
3261         int result = 0;
3262         struct vega10_hwmgr *data = hwmgr->backend;
3263         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3264         struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3265         struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3266         int count;
3267
3268         if (!data->need_update_dpm_table)
3269                 return 0;
3270
3271         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3272                 for (count = 0; count < dpm_table->gfx_table.count; count++)
3273                         dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3274         }
3275
3276         odn_clk_table = &odn_table->vdd_dep_on_mclk;
3277         if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3278                 for (count = 0; count < dpm_table->mem_table.count; count++)
3279                         dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3280         }
3281
3282         if (data->need_update_dpm_table &
3283                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {
3284                 result = vega10_populate_all_graphic_levels(hwmgr);
3285                 PP_ASSERT_WITH_CODE((0 == result),
3286                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3287                                 return result);
3288         }
3289
3290         if (data->need_update_dpm_table &
3291                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3292                 result = vega10_populate_all_memory_levels(hwmgr);
3293                 PP_ASSERT_WITH_CODE((0 == result),
3294                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3295                                 return result);
3296         }
3297
3298         vega10_populate_vddc_soc_levels(hwmgr);
3299
3300         return result;
3301 }
3302
3303 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3304                 struct vega10_single_dpm_table *dpm_table,
3305                 uint32_t low_limit, uint32_t high_limit)
3306 {
3307         uint32_t i;
3308
3309         for (i = 0; i < dpm_table->count; i++) {
3310                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3311                     (dpm_table->dpm_levels[i].value > high_limit))
3312                         dpm_table->dpm_levels[i].enabled = false;
3313                 else
3314                         dpm_table->dpm_levels[i].enabled = true;
3315         }
3316         return 0;
3317 }
3318
3319 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3320                 struct vega10_single_dpm_table *dpm_table,
3321                 uint32_t low_limit, uint32_t high_limit,
3322                 uint32_t disable_dpm_mask)
3323 {
3324         uint32_t i;
3325
3326         for (i = 0; i < dpm_table->count; i++) {
3327                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3328                     (dpm_table->dpm_levels[i].value > high_limit))
3329                         dpm_table->dpm_levels[i].enabled = false;
3330                 else if (!((1 << i) & disable_dpm_mask))
3331                         dpm_table->dpm_levels[i].enabled = false;
3332                 else
3333                         dpm_table->dpm_levels[i].enabled = true;
3334         }
3335         return 0;
3336 }
3337
3338 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3339                 const struct vega10_power_state *vega10_ps)
3340 {
3341         struct vega10_hwmgr *data = hwmgr->backend;
3342         uint32_t high_limit_count;
3343
3344         PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3345                         "power state did not have any performance level",
3346                         return -1);
3347
3348         high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3349
3350         vega10_trim_single_dpm_states(hwmgr,
3351                         &(data->dpm_table.soc_table),
3352                         vega10_ps->performance_levels[0].soc_clock,
3353                         vega10_ps->performance_levels[high_limit_count].soc_clock);
3354
3355         vega10_trim_single_dpm_states_with_mask(hwmgr,
3356                         &(data->dpm_table.gfx_table),
3357                         vega10_ps->performance_levels[0].gfx_clock,
3358                         vega10_ps->performance_levels[high_limit_count].gfx_clock,
3359                         data->disable_dpm_mask);
3360
3361         vega10_trim_single_dpm_states(hwmgr,
3362                         &(data->dpm_table.mem_table),
3363                         vega10_ps->performance_levels[0].mem_clock,
3364                         vega10_ps->performance_levels[high_limit_count].mem_clock);
3365
3366         return 0;
3367 }
3368
3369 static uint32_t vega10_find_lowest_dpm_level(
3370                 struct vega10_single_dpm_table *table)
3371 {
3372         uint32_t i;
3373
3374         for (i = 0; i < table->count; i++) {
3375                 if (table->dpm_levels[i].enabled)
3376                         break;
3377         }
3378
3379         return i;
3380 }
3381
3382 static uint32_t vega10_find_highest_dpm_level(
3383                 struct vega10_single_dpm_table *table)
3384 {
3385         uint32_t i = 0;
3386
3387         if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3388                 for (i = table->count; i > 0; i--) {
3389                         if (table->dpm_levels[i - 1].enabled)
3390                                 return i - 1;
3391                 }
3392         } else {
3393                 pr_info("DPM Table Has Too Many Entries!");
3394                 return MAX_REGULAR_DPM_NUMBER - 1;
3395         }
3396
3397         return i;
3398 }
3399
3400 static void vega10_apply_dal_minimum_voltage_request(
3401                 struct pp_hwmgr *hwmgr)
3402 {
3403         return;
3404 }
3405
3406 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3407 {
3408         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3409         struct phm_ppt_v2_information *table_info =
3410                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3411
3412         vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3413
3414         return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3415 }
3416
3417 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3418 {
3419         struct vega10_hwmgr *data = hwmgr->backend;
3420         uint32_t socclk_idx;
3421
3422         vega10_apply_dal_minimum_voltage_request(hwmgr);
3423
3424         if (!data->registry_data.sclk_dpm_key_disabled) {
3425                 if (data->smc_state_table.gfx_boot_level !=
3426                                 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3427                         smum_send_msg_to_smc_with_parameter(hwmgr,
3428                                 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3429                                 data->smc_state_table.gfx_boot_level);
3430                         data->dpm_table.gfx_table.dpm_state.soft_min_level =
3431                                         data->smc_state_table.gfx_boot_level;
3432                 }
3433         }
3434
3435         if (!data->registry_data.mclk_dpm_key_disabled) {
3436                 if (data->smc_state_table.mem_boot_level !=
3437                                 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3438                         if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
3439                                 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3440                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3441                                                 PPSMC_MSG_SetSoftMinSocclkByIndex,
3442                                                 socclk_idx);
3443                         } else {
3444                                 smum_send_msg_to_smc_with_parameter(hwmgr,
3445                                                 PPSMC_MSG_SetSoftMinUclkByIndex,
3446                                                 data->smc_state_table.mem_boot_level);
3447                         }
3448                         data->dpm_table.mem_table.dpm_state.soft_min_level =
3449                                         data->smc_state_table.mem_boot_level;
3450                 }
3451         }
3452
3453         return 0;
3454 }
3455
3456 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3457 {
3458         struct vega10_hwmgr *data = hwmgr->backend;
3459
3460         vega10_apply_dal_minimum_voltage_request(hwmgr);
3461
3462         if (!data->registry_data.sclk_dpm_key_disabled) {
3463                 if (data->smc_state_table.gfx_max_level !=
3464                         data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3465                         smum_send_msg_to_smc_with_parameter(hwmgr,
3466                                 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3467                                 data->smc_state_table.gfx_max_level);
3468                         data->dpm_table.gfx_table.dpm_state.soft_max_level =
3469                                         data->smc_state_table.gfx_max_level;
3470                 }
3471         }
3472
3473         if (!data->registry_data.mclk_dpm_key_disabled) {
3474                 if (data->smc_state_table.mem_max_level !=
3475                         data->dpm_table.mem_table.dpm_state.soft_max_level) {
3476                         smum_send_msg_to_smc_with_parameter(hwmgr,
3477                                         PPSMC_MSG_SetSoftMaxUclkByIndex,
3478                                         data->smc_state_table.mem_max_level);
3479                         data->dpm_table.mem_table.dpm_state.soft_max_level =
3480                                         data->smc_state_table.mem_max_level;
3481                 }
3482         }
3483
3484         return 0;
3485 }
3486
3487 static int vega10_generate_dpm_level_enable_mask(
3488                 struct pp_hwmgr *hwmgr, const void *input)
3489 {
3490         struct vega10_hwmgr *data = hwmgr->backend;
3491         const struct phm_set_power_state_input *states =
3492                         (const struct phm_set_power_state_input *)input;
3493         const struct vega10_power_state *vega10_ps =
3494                         cast_const_phw_vega10_power_state(states->pnew_state);
3495         int i;
3496
3497         PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3498                         "Attempt to Trim DPM States Failed!",
3499                         return -1);
3500
3501         data->smc_state_table.gfx_boot_level =
3502                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3503         data->smc_state_table.gfx_max_level =
3504                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3505         data->smc_state_table.mem_boot_level =
3506                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3507         data->smc_state_table.mem_max_level =
3508                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3509
3510         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3511                         "Attempt to upload DPM Bootup Levels Failed!",
3512                         return -1);
3513         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3514                         "Attempt to upload DPM Max Levels Failed!",
3515                         return -1);
3516         for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3517                 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3518
3519
3520         for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3521                 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3522
3523         return 0;
3524 }
3525
3526 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3527 {
3528         struct vega10_hwmgr *data = hwmgr->backend;
3529
3530         if (data->smu_features[GNLD_DPM_VCE].supported) {
3531                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3532                                 enable,
3533                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3534                                 "Attempt to Enable/Disable DPM VCE Failed!",
3535                                 return -1);
3536                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3537         }
3538
3539         return 0;
3540 }
3541
3542 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3543 {
3544         struct vega10_hwmgr *data = hwmgr->backend;
3545         uint32_t low_sclk_interrupt_threshold = 0;
3546
3547         if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3548                 (data->low_sclk_interrupt_threshold != 0)) {
3549                 low_sclk_interrupt_threshold =
3550                                 data->low_sclk_interrupt_threshold;
3551
3552                 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3553                                 cpu_to_le32(low_sclk_interrupt_threshold);
3554
3555                 /* This message will also enable SmcToHost Interrupt */
3556                 smum_send_msg_to_smc_with_parameter(hwmgr,
3557                                 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3558                                 (uint32_t)low_sclk_interrupt_threshold);
3559         }
3560
3561         return 0;
3562 }
3563
3564 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3565                 const void *input)
3566 {
3567         int tmp_result, result = 0;
3568         struct vega10_hwmgr *data = hwmgr->backend;
3569         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3570
3571         tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3572         PP_ASSERT_WITH_CODE(!tmp_result,
3573                         "Failed to find DPM states clocks in DPM table!",
3574                         result = tmp_result);
3575
3576         tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3577         PP_ASSERT_WITH_CODE(!tmp_result,
3578                         "Failed to populate and upload SCLK MCLK DPM levels!",
3579                         result = tmp_result);
3580
3581         tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3582         PP_ASSERT_WITH_CODE(!tmp_result,
3583                         "Failed to generate DPM level enabled mask!",
3584                         result = tmp_result);
3585
3586         tmp_result = vega10_update_sclk_threshold(hwmgr);
3587         PP_ASSERT_WITH_CODE(!tmp_result,
3588                         "Failed to update SCLK threshold!",
3589                         result = tmp_result);
3590
3591         result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3592         PP_ASSERT_WITH_CODE(!result,
3593                         "Failed to upload PPtable!", return result);
3594
3595         vega10_update_avfs(hwmgr);
3596
3597         data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3598
3599         return 0;
3600 }
3601
3602 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3603 {
3604         struct pp_power_state *ps;
3605         struct vega10_power_state *vega10_ps;
3606
3607         if (hwmgr == NULL)
3608                 return -EINVAL;
3609
3610         ps = hwmgr->request_ps;
3611
3612         if (ps == NULL)
3613                 return -EINVAL;
3614
3615         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3616
3617         if (low)
3618                 return vega10_ps->performance_levels[0].gfx_clock;
3619         else
3620                 return vega10_ps->performance_levels
3621                                 [vega10_ps->performance_level_count - 1].gfx_clock;
3622 }
3623
3624 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3625 {
3626         struct pp_power_state *ps;
3627         struct vega10_power_state *vega10_ps;
3628
3629         if (hwmgr == NULL)
3630                 return -EINVAL;
3631
3632         ps = hwmgr->request_ps;
3633
3634         if (ps == NULL)
3635                 return -EINVAL;
3636
3637         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3638
3639         if (low)
3640                 return vega10_ps->performance_levels[0].mem_clock;
3641         else
3642                 return vega10_ps->performance_levels
3643                                 [vega10_ps->performance_level_count-1].mem_clock;
3644 }
3645
3646 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3647                 uint32_t *query)
3648 {
3649         uint32_t value;
3650
3651         if (!query)
3652                 return -EINVAL;
3653
3654         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
3655         value = smum_get_argument(hwmgr);
3656
3657         /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3658         *query = value << 8;
3659
3660         return 0;
3661 }
3662
3663 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3664                               void *value, int *size)
3665 {
3666         struct amdgpu_device *adev = hwmgr->adev;
3667         uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3668         struct vega10_hwmgr *data = hwmgr->backend;
3669         struct vega10_dpm_table *dpm_table = &data->dpm_table;
3670         int ret = 0;
3671         uint32_t val_vid;
3672
3673         switch (idx) {
3674         case AMDGPU_PP_SENSOR_GFX_SCLK:
3675                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
3676                 sclk_mhz = smum_get_argument(hwmgr);
3677                 *((uint32_t *)value) = sclk_mhz * 100;
3678                 break;
3679         case AMDGPU_PP_SENSOR_GFX_MCLK:
3680                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
3681                 mclk_idx = smum_get_argument(hwmgr);
3682                 if (mclk_idx < dpm_table->mem_table.count) {
3683                         *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3684                         *size = 4;
3685                 } else {
3686                         ret = -EINVAL;
3687                 }
3688                 break;
3689         case AMDGPU_PP_SENSOR_GPU_LOAD:
3690                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3691                 activity_percent = smum_get_argument(hwmgr);
3692                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3693                 *size = 4;
3694                 break;
3695         case AMDGPU_PP_SENSOR_GPU_TEMP:
3696                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3697                 *size = 4;
3698                 break;
3699         case AMDGPU_PP_SENSOR_UVD_POWER:
3700                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3701                 *size = 4;
3702                 break;
3703         case AMDGPU_PP_SENSOR_VCE_POWER:
3704                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3705                 *size = 4;
3706                 break;
3707         case AMDGPU_PP_SENSOR_GPU_POWER:
3708                 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3709                 break;
3710         case AMDGPU_PP_SENSOR_VDDGFX:
3711                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3712                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3713                         SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3714                 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3715                 return 0;
3716         default:
3717                 ret = -EINVAL;
3718                 break;
3719         }
3720
3721         return ret;
3722 }
3723
3724 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3725                 bool has_disp)
3726 {
3727         smum_send_msg_to_smc_with_parameter(hwmgr,
3728                         PPSMC_MSG_SetUclkFastSwitch,
3729                         has_disp ? 1 : 0);
3730 }
3731
3732 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3733                 struct pp_display_clock_request *clock_req)
3734 {
3735         int result = 0;
3736         enum amd_pp_clock_type clk_type = clock_req->clock_type;
3737         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3738         DSPCLK_e clk_select = 0;
3739         uint32_t clk_request = 0;
3740
3741         switch (clk_type) {
3742         case amd_pp_dcef_clock:
3743                 clk_select = DSPCLK_DCEFCLK;
3744                 break;
3745         case amd_pp_disp_clock:
3746                 clk_select = DSPCLK_DISPCLK;
3747                 break;
3748         case amd_pp_pixel_clock:
3749                 clk_select = DSPCLK_PIXCLK;
3750                 break;
3751         case amd_pp_phy_clock:
3752                 clk_select = DSPCLK_PHYCLK;
3753                 break;
3754         default:
3755                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3756                 result = -1;
3757                 break;
3758         }
3759
3760         if (!result) {
3761                 clk_request = (clk_freq << 16) | clk_select;
3762                 smum_send_msg_to_smc_with_parameter(hwmgr,
3763                                 PPSMC_MSG_RequestDisplayClockByFreq,
3764                                 clk_request);
3765         }
3766
3767         return result;
3768 }
3769
3770 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
3771                         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
3772                                                 uint32_t frequency)
3773 {
3774         uint8_t count;
3775         uint8_t i;
3776
3777         if (mclk_table == NULL || mclk_table->count == 0)
3778                 return 0;
3779
3780         count = (uint8_t)(mclk_table->count);
3781
3782         for(i = 0; i < count; i++) {
3783                 if(mclk_table->entries[i].clk >= frequency)
3784                         return i;
3785         }
3786
3787         return i-1;
3788 }
3789
3790 static int vega10_notify_smc_display_config_after_ps_adjustment(
3791                 struct pp_hwmgr *hwmgr)
3792 {
3793         struct vega10_hwmgr *data = hwmgr->backend;
3794         struct vega10_single_dpm_table *dpm_table =
3795                         &data->dpm_table.dcef_table;
3796         struct phm_ppt_v2_information *table_info =
3797                         (struct phm_ppt_v2_information *)hwmgr->pptable;
3798         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
3799         uint32_t idx;
3800         struct PP_Clocks min_clocks = {0};
3801         uint32_t i;
3802         struct pp_display_clock_request clock_req;
3803
3804         if ((hwmgr->display_config->num_display > 1) &&
3805              !hwmgr->display_config->multi_monitor_in_sync &&
3806              !hwmgr->display_config->nb_pstate_switch_disable)
3807                 vega10_notify_smc_display_change(hwmgr, false);
3808         else
3809                 vega10_notify_smc_display_change(hwmgr, true);
3810
3811         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3812         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3813         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3814
3815         for (i = 0; i < dpm_table->count; i++) {
3816                 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
3817                         break;
3818         }
3819
3820         if (i < dpm_table->count) {
3821                 clock_req.clock_type = amd_pp_dcef_clock;
3822                 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
3823                 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
3824                         smum_send_msg_to_smc_with_parameter(
3825                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
3826                                         min_clocks.dcefClockInSR / 100);
3827                 } else {
3828                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3829                 }
3830         } else {
3831                 pr_debug("Cannot find requested DCEFCLK!");
3832         }
3833
3834         if (min_clocks.memoryClock != 0) {
3835                 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
3836                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
3837                 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
3838         }
3839
3840         return 0;
3841 }
3842
3843 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3844 {
3845         struct vega10_hwmgr *data = hwmgr->backend;
3846
3847         data->smc_state_table.gfx_boot_level =
3848         data->smc_state_table.gfx_max_level =
3849                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3850         data->smc_state_table.mem_boot_level =
3851         data->smc_state_table.mem_max_level =
3852                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3853
3854         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3855                         "Failed to upload boot level to highest!",
3856                         return -1);
3857
3858         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3859                         "Failed to upload dpm max level to highest!",
3860                         return -1);
3861
3862         return 0;
3863 }
3864
3865 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3866 {
3867         struct vega10_hwmgr *data = hwmgr->backend;
3868
3869         data->smc_state_table.gfx_boot_level =
3870         data->smc_state_table.gfx_max_level =
3871                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3872         data->smc_state_table.mem_boot_level =
3873         data->smc_state_table.mem_max_level =
3874                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3875
3876         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3877                         "Failed to upload boot level to highest!",
3878                         return -1);
3879
3880         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3881                         "Failed to upload dpm max level to highest!",
3882                         return -1);
3883
3884         return 0;
3885
3886 }
3887
3888 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3889 {
3890         struct vega10_hwmgr *data = hwmgr->backend;
3891
3892         data->smc_state_table.gfx_boot_level =
3893                         vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3894         data->smc_state_table.gfx_max_level =
3895                         vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3896         data->smc_state_table.mem_boot_level =
3897                         vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3898         data->smc_state_table.mem_max_level =
3899                         vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3900
3901         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3902                         "Failed to upload DPM Bootup Levels!",
3903                         return -1);
3904
3905         PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3906                         "Failed to upload DPM Max Levels!",
3907                         return -1);
3908         return 0;
3909 }
3910
3911 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
3912                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
3913 {
3914         struct phm_ppt_v2_information *table_info =
3915                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
3916
3917         if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3918                 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
3919                 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3920                 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
3921                 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
3922                 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
3923                 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3924                 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3925         }
3926
3927         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3928                 *sclk_mask = 0;
3929         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3930                 *mclk_mask = 0;
3931         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3932                 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
3933                 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
3934                 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
3935         }
3936         return 0;
3937 }
3938
3939 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
3940 {
3941         switch (mode) {
3942         case AMD_FAN_CTRL_NONE:
3943                 vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
3944                 break;
3945         case AMD_FAN_CTRL_MANUAL:
3946                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3947                         vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
3948                 break;
3949         case AMD_FAN_CTRL_AUTO:
3950                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
3951                         vega10_fan_ctrl_start_smc_fan_control(hwmgr);
3952                 break;
3953         default:
3954                 break;
3955         }
3956 }
3957
3958 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
3959                 enum pp_clock_type type, uint32_t mask)
3960 {
3961         struct vega10_hwmgr *data = hwmgr->backend;
3962
3963         switch (type) {
3964         case PP_SCLK:
3965                 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
3966                 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
3967
3968                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3969                         "Failed to upload boot level to lowest!",
3970                         return -EINVAL);
3971
3972                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3973                         "Failed to upload dpm max level to highest!",
3974                         return -EINVAL);
3975                 break;
3976
3977         case PP_MCLK:
3978                 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
3979                 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
3980
3981                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3982                         "Failed to upload boot level to lowest!",
3983                         return -EINVAL);
3984
3985                 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3986                         "Failed to upload dpm max level to highest!",
3987                         return -EINVAL);
3988
3989                 break;
3990
3991         case PP_PCIE:
3992         default:
3993                 break;
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4000                                 enum amd_dpm_forced_level level)
4001 {
4002         int ret = 0;
4003         uint32_t sclk_mask = 0;
4004         uint32_t mclk_mask = 0;
4005         uint32_t soc_mask = 0;
4006
4007         if (hwmgr->pstate_sclk == 0)
4008                 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4009
4010         switch (level) {
4011         case AMD_DPM_FORCED_LEVEL_HIGH:
4012                 ret = vega10_force_dpm_highest(hwmgr);
4013                 break;
4014         case AMD_DPM_FORCED_LEVEL_LOW:
4015                 ret = vega10_force_dpm_lowest(hwmgr);
4016                 break;
4017         case AMD_DPM_FORCED_LEVEL_AUTO:
4018                 ret = vega10_unforce_dpm_levels(hwmgr);
4019                 break;
4020         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4021         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4022         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4023         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4024                 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4025                 if (ret)
4026                         return ret;
4027                 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4028                 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4029                 break;
4030         case AMD_DPM_FORCED_LEVEL_MANUAL:
4031         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4032         default:
4033                 break;
4034         }
4035
4036         if (!ret) {
4037                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4038                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4039                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4040                         vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4041         }
4042
4043         return ret;
4044 }
4045
4046 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4047 {
4048         struct vega10_hwmgr *data = hwmgr->backend;
4049
4050         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4051                 return AMD_FAN_CTRL_MANUAL;
4052         else
4053                 return AMD_FAN_CTRL_AUTO;
4054 }
4055
4056 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4057                 struct amd_pp_simple_clock_info *info)
4058 {
4059         struct phm_ppt_v2_information *table_info =
4060                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4061         struct phm_clock_and_voltage_limits *max_limits =
4062                         &table_info->max_clock_voltage_on_ac;
4063
4064         info->engine_max_clock = max_limits->sclk;
4065         info->memory_max_clock = max_limits->mclk;
4066
4067         return 0;
4068 }
4069
4070 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4071                 struct pp_clock_levels_with_latency *clocks)
4072 {
4073         struct phm_ppt_v2_information *table_info =
4074                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4075         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4076                         table_info->vdd_dep_on_sclk;
4077         uint32_t i;
4078
4079         clocks->num_levels = 0;
4080         for (i = 0; i < dep_table->count; i++) {
4081                 if (dep_table->entries[i].clk) {
4082                         clocks->data[clocks->num_levels].clocks_in_khz =
4083                                         dep_table->entries[i].clk * 10;
4084                         clocks->num_levels++;
4085                 }
4086         }
4087
4088 }
4089
4090 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4091                 struct pp_clock_levels_with_latency *clocks)
4092 {
4093         struct phm_ppt_v2_information *table_info =
4094                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4095         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4096                         table_info->vdd_dep_on_mclk;
4097         struct vega10_hwmgr *data = hwmgr->backend;
4098         uint32_t j = 0;
4099         uint32_t i;
4100
4101         for (i = 0; i < dep_table->count; i++) {
4102                 if (dep_table->entries[i].clk) {
4103
4104                         clocks->data[j].clocks_in_khz =
4105                                                 dep_table->entries[i].clk * 10;
4106                         data->mclk_latency_table.entries[j].frequency =
4107                                                         dep_table->entries[i].clk;
4108                         clocks->data[j].latency_in_us =
4109                                 data->mclk_latency_table.entries[j].latency = 25;
4110                         j++;
4111                 }
4112         }
4113         clocks->num_levels = data->mclk_latency_table.count = j;
4114 }
4115
4116 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4117                 struct pp_clock_levels_with_latency *clocks)
4118 {
4119         struct phm_ppt_v2_information *table_info =
4120                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4121         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4122                         table_info->vdd_dep_on_dcefclk;
4123         uint32_t i;
4124
4125         for (i = 0; i < dep_table->count; i++) {
4126                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4127                 clocks->data[i].latency_in_us = 0;
4128                 clocks->num_levels++;
4129         }
4130 }
4131
4132 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4133                 struct pp_clock_levels_with_latency *clocks)
4134 {
4135         struct phm_ppt_v2_information *table_info =
4136                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4137         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4138                         table_info->vdd_dep_on_socclk;
4139         uint32_t i;
4140
4141         for (i = 0; i < dep_table->count; i++) {
4142                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4143                 clocks->data[i].latency_in_us = 0;
4144                 clocks->num_levels++;
4145         }
4146 }
4147
4148 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4149                 enum amd_pp_clock_type type,
4150                 struct pp_clock_levels_with_latency *clocks)
4151 {
4152         switch (type) {
4153         case amd_pp_sys_clock:
4154                 vega10_get_sclks(hwmgr, clocks);
4155                 break;
4156         case amd_pp_mem_clock:
4157                 vega10_get_memclocks(hwmgr, clocks);
4158                 break;
4159         case amd_pp_dcef_clock:
4160                 vega10_get_dcefclocks(hwmgr, clocks);
4161                 break;
4162         case amd_pp_soc_clock:
4163                 vega10_get_socclocks(hwmgr, clocks);
4164                 break;
4165         default:
4166                 return -1;
4167         }
4168
4169         return 0;
4170 }
4171
4172 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4173                 enum amd_pp_clock_type type,
4174                 struct pp_clock_levels_with_voltage *clocks)
4175 {
4176         struct phm_ppt_v2_information *table_info =
4177                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4178         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4179         uint32_t i;
4180
4181         switch (type) {
4182         case amd_pp_mem_clock:
4183                 dep_table = table_info->vdd_dep_on_mclk;
4184                 break;
4185         case amd_pp_dcef_clock:
4186                 dep_table = table_info->vdd_dep_on_dcefclk;
4187                 break;
4188         case amd_pp_disp_clock:
4189                 dep_table = table_info->vdd_dep_on_dispclk;
4190                 break;
4191         case amd_pp_pixel_clock:
4192                 dep_table = table_info->vdd_dep_on_pixclk;
4193                 break;
4194         case amd_pp_phy_clock:
4195                 dep_table = table_info->vdd_dep_on_phyclk;
4196                 break;
4197         default:
4198                 return -1;
4199         }
4200
4201         for (i = 0; i < dep_table->count; i++) {
4202                 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4203                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4204                                 entries[dep_table->entries[i].vddInd].us_vdd);
4205                 clocks->num_levels++;
4206         }
4207
4208         if (i < dep_table->count)
4209                 return -1;
4210
4211         return 0;
4212 }
4213
4214 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4215                                                         void *clock_range)
4216 {
4217         struct vega10_hwmgr *data = hwmgr->backend;
4218         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4219         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4220         int result = 0;
4221
4222         if (!data->registry_data.disable_water_mark) {
4223                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4224                 data->water_marks_bitmap = WaterMarksExist;
4225         }
4226
4227         return result;
4228 }
4229
4230 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4231                 enum pp_clock_type type, char *buf)
4232 {
4233         struct vega10_hwmgr *data = hwmgr->backend;
4234         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4235         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4236         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4237         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4238
4239         int i, now, size = 0;
4240
4241         switch (type) {
4242         case PP_SCLK:
4243                 if (data->registry_data.sclk_dpm_key_disabled)
4244                         break;
4245
4246                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
4247                 now = smum_get_argument(hwmgr);
4248
4249                 for (i = 0; i < sclk_table->count; i++)
4250                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4251                                         i, sclk_table->dpm_levels[i].value / 100,
4252                                         (i == now) ? "*" : "");
4253                 break;
4254         case PP_MCLK:
4255                 if (data->registry_data.mclk_dpm_key_disabled)
4256                         break;
4257
4258                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
4259                 now = smum_get_argument(hwmgr);
4260
4261                 for (i = 0; i < mclk_table->count; i++)
4262                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4263                                         i, mclk_table->dpm_levels[i].value / 100,
4264                                         (i == now) ? "*" : "");
4265                 break;
4266         case PP_PCIE:
4267                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
4268                 now = smum_get_argument(hwmgr);
4269
4270                 for (i = 0; i < pcie_table->count; i++)
4271                         size += sprintf(buf + size, "%d: %s %s\n", i,
4272                                         (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
4273                                         (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
4274                                         (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
4275                                         (i == now) ? "*" : "");
4276                 break;
4277         case OD_SCLK:
4278                 if (hwmgr->od_enabled) {
4279                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4280                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4281                         for (i = 0; i < podn_vdd_dep->count; i++)
4282                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4283                                         i, podn_vdd_dep->entries[i].clk / 100,
4284                                                 podn_vdd_dep->entries[i].vddc);
4285                 }
4286                 break;
4287         case OD_MCLK:
4288                 if (hwmgr->od_enabled) {
4289                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4290                         podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4291                         for (i = 0; i < podn_vdd_dep->count; i++)
4292                                 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4293                                         i, podn_vdd_dep->entries[i].clk/100,
4294                                                 podn_vdd_dep->entries[i].vddc);
4295                 }
4296                 break;
4297         case OD_RANGE:
4298                 if (hwmgr->od_enabled) {
4299                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4300                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4301                                 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4302                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4303                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4304                                 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4305                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4306                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4307                                 data->odn_dpm_table.min_vddc,
4308                                 data->odn_dpm_table.max_vddc);
4309                 }
4310                 break;
4311         default:
4312                 break;
4313         }
4314         return size;
4315 }
4316
4317 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4318 {
4319         struct vega10_hwmgr *data = hwmgr->backend;
4320         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4321         int result = 0;
4322
4323         if ((data->water_marks_bitmap & WaterMarksExist) &&
4324                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
4325                 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4326                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4327                 data->water_marks_bitmap |= WaterMarksLoaded;
4328         }
4329
4330         if (data->water_marks_bitmap & WaterMarksLoaded) {
4331                 smum_send_msg_to_smc_with_parameter(hwmgr,
4332                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
4333         }
4334
4335         return result;
4336 }
4337
4338 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4339 {
4340         struct vega10_hwmgr *data = hwmgr->backend;
4341
4342         if (data->smu_features[GNLD_DPM_UVD].supported) {
4343                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4344                                 enable,
4345                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4346                                 "Attempt to Enable/Disable DPM UVD Failed!",
4347                                 return -1);
4348                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4349         }
4350         return 0;
4351 }
4352
4353 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4354 {
4355         struct vega10_hwmgr *data = hwmgr->backend;
4356
4357         data->vce_power_gated = bgate;
4358         vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4359 }
4360
4361 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4362 {
4363         struct vega10_hwmgr *data = hwmgr->backend;
4364
4365         data->uvd_power_gated = bgate;
4366         vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4367 }
4368
4369 static inline bool vega10_are_power_levels_equal(
4370                                 const struct vega10_performance_level *pl1,
4371                                 const struct vega10_performance_level *pl2)
4372 {
4373         return ((pl1->soc_clock == pl2->soc_clock) &&
4374                         (pl1->gfx_clock == pl2->gfx_clock) &&
4375                         (pl1->mem_clock == pl2->mem_clock));
4376 }
4377
4378 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4379                                 const struct pp_hw_power_state *pstate1,
4380                         const struct pp_hw_power_state *pstate2, bool *equal)
4381 {
4382         const struct vega10_power_state *psa;
4383         const struct vega10_power_state *psb;
4384         int i;
4385
4386         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4387                 return -EINVAL;
4388
4389         psa = cast_const_phw_vega10_power_state(pstate1);
4390         psb = cast_const_phw_vega10_power_state(pstate2);
4391         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4392         if (psa->performance_level_count != psb->performance_level_count) {
4393                 *equal = false;
4394                 return 0;
4395         }
4396
4397         for (i = 0; i < psa->performance_level_count; i++) {
4398                 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4399                         /* If we have found even one performance level pair that is different the states are different. */
4400                         *equal = false;
4401                         return 0;
4402                 }
4403         }
4404
4405         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4406         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4407         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4408         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4409
4410         return 0;
4411 }
4412
4413 static bool
4414 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4415 {
4416         struct vega10_hwmgr *data = hwmgr->backend;
4417         bool is_update_required = false;
4418
4419         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4420                 is_update_required = true;
4421
4422         if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4423                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4424                         is_update_required = true;
4425         }
4426
4427         return is_update_required;
4428 }
4429
4430 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4431 {
4432         int tmp_result, result = 0;
4433
4434         if (PP_CAP(PHM_PlatformCaps_ThermalController))
4435                 vega10_disable_thermal_protection(hwmgr);
4436
4437         tmp_result = vega10_disable_power_containment(hwmgr);
4438         PP_ASSERT_WITH_CODE((tmp_result == 0),
4439                         "Failed to disable power containment!", result = tmp_result);
4440
4441         tmp_result = vega10_disable_didt_config(hwmgr);
4442         PP_ASSERT_WITH_CODE((tmp_result == 0),
4443                         "Failed to disable didt config!", result = tmp_result);
4444
4445         tmp_result = vega10_avfs_enable(hwmgr, false);
4446         PP_ASSERT_WITH_CODE((tmp_result == 0),
4447                         "Failed to disable AVFS!", result = tmp_result);
4448
4449         tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
4450         PP_ASSERT_WITH_CODE((tmp_result == 0),
4451                         "Failed to stop DPM!", result = tmp_result);
4452
4453         tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
4454         PP_ASSERT_WITH_CODE((tmp_result == 0),
4455                         "Failed to disable deep sleep!", result = tmp_result);
4456
4457         tmp_result = vega10_disable_ulv(hwmgr);
4458         PP_ASSERT_WITH_CODE((tmp_result == 0),
4459                         "Failed to disable ulv!", result = tmp_result);
4460
4461         tmp_result =  vega10_acg_disable(hwmgr);
4462         PP_ASSERT_WITH_CODE((tmp_result == 0),
4463                         "Failed to disable acg!", result = tmp_result);
4464
4465         vega10_enable_disable_PCC_limit_feature(hwmgr, false);
4466         return result;
4467 }
4468
4469 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4470 {
4471         struct vega10_hwmgr *data = hwmgr->backend;
4472         int result;
4473
4474         result = vega10_disable_dpm_tasks(hwmgr);
4475         PP_ASSERT_WITH_CODE((0 == result),
4476                         "[disable_dpm_tasks] Failed to disable DPM!",
4477                         );
4478         data->water_marks_bitmap &= ~(WaterMarksLoaded);
4479
4480         return result;
4481 }
4482
4483 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4484 {
4485         struct vega10_hwmgr *data = hwmgr->backend;
4486         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4487         struct vega10_single_dpm_table *golden_sclk_table =
4488                         &(data->golden_dpm_table.gfx_table);
4489         int value;
4490
4491         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4492                         golden_sclk_table->dpm_levels
4493                         [golden_sclk_table->count - 1].value) *
4494                         100 /
4495                         golden_sclk_table->dpm_levels
4496                         [golden_sclk_table->count - 1].value;
4497
4498         return value;
4499 }
4500
4501 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4502 {
4503         struct vega10_hwmgr *data = hwmgr->backend;
4504         struct vega10_single_dpm_table *golden_sclk_table =
4505                         &(data->golden_dpm_table.gfx_table);
4506         struct pp_power_state *ps;
4507         struct vega10_power_state *vega10_ps;
4508
4509         ps = hwmgr->request_ps;
4510
4511         if (ps == NULL)
4512                 return -EINVAL;
4513
4514         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4515
4516         vega10_ps->performance_levels
4517         [vega10_ps->performance_level_count - 1].gfx_clock =
4518                         golden_sclk_table->dpm_levels
4519                         [golden_sclk_table->count - 1].value *
4520                         value / 100 +
4521                         golden_sclk_table->dpm_levels
4522                         [golden_sclk_table->count - 1].value;
4523
4524         if (vega10_ps->performance_levels
4525                         [vega10_ps->performance_level_count - 1].gfx_clock >
4526                         hwmgr->platform_descriptor.overdriveLimit.engineClock)
4527                 vega10_ps->performance_levels
4528                 [vega10_ps->performance_level_count - 1].gfx_clock =
4529                                 hwmgr->platform_descriptor.overdriveLimit.engineClock;
4530
4531         return 0;
4532 }
4533
4534 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4535 {
4536         struct vega10_hwmgr *data = hwmgr->backend;
4537         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4538         struct vega10_single_dpm_table *golden_mclk_table =
4539                         &(data->golden_dpm_table.mem_table);
4540         int value;
4541
4542         value = (mclk_table->dpm_levels
4543                         [mclk_table->count - 1].value -
4544                         golden_mclk_table->dpm_levels
4545                         [golden_mclk_table->count - 1].value) *
4546                         100 /
4547                         golden_mclk_table->dpm_levels
4548                         [golden_mclk_table->count - 1].value;
4549
4550         return value;
4551 }
4552
4553 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4554 {
4555         struct vega10_hwmgr *data = hwmgr->backend;
4556         struct vega10_single_dpm_table *golden_mclk_table =
4557                         &(data->golden_dpm_table.mem_table);
4558         struct pp_power_state  *ps;
4559         struct vega10_power_state  *vega10_ps;
4560
4561         ps = hwmgr->request_ps;
4562
4563         if (ps == NULL)
4564                 return -EINVAL;
4565
4566         vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4567
4568         vega10_ps->performance_levels
4569         [vega10_ps->performance_level_count - 1].mem_clock =
4570                         golden_mclk_table->dpm_levels
4571                         [golden_mclk_table->count - 1].value *
4572                         value / 100 +
4573                         golden_mclk_table->dpm_levels
4574                         [golden_mclk_table->count - 1].value;
4575
4576         if (vega10_ps->performance_levels
4577                         [vega10_ps->performance_level_count - 1].mem_clock >
4578                         hwmgr->platform_descriptor.overdriveLimit.memoryClock)
4579                 vega10_ps->performance_levels
4580                 [vega10_ps->performance_level_count - 1].mem_clock =
4581                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4582
4583         return 0;
4584 }
4585
4586 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4587                                         uint32_t virtual_addr_low,
4588                                         uint32_t virtual_addr_hi,
4589                                         uint32_t mc_addr_low,
4590                                         uint32_t mc_addr_hi,
4591                                         uint32_t size)
4592 {
4593         smum_send_msg_to_smc_with_parameter(hwmgr,
4594                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4595                                         virtual_addr_hi);
4596         smum_send_msg_to_smc_with_parameter(hwmgr,
4597                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4598                                         virtual_addr_low);
4599         smum_send_msg_to_smc_with_parameter(hwmgr,
4600                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4601                                         mc_addr_hi);
4602
4603         smum_send_msg_to_smc_with_parameter(hwmgr,
4604                                         PPSMC_MSG_DramLogSetDramAddrLow,
4605                                         mc_addr_low);
4606
4607         smum_send_msg_to_smc_with_parameter(hwmgr,
4608                                         PPSMC_MSG_DramLogSetDramSize,
4609                                         size);
4610         return 0;
4611 }
4612
4613 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4614                 struct PP_TemperatureRange *thermal_data)
4615 {
4616         struct phm_ppt_v2_information *table_info =
4617                         (struct phm_ppt_v2_information *)hwmgr->pptable;
4618
4619         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4620
4621         thermal_data->max = table_info->tdp_table->usSoftwareShutdownTemp *
4622                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4623
4624         return 0;
4625 }
4626
4627 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4628 {
4629         struct vega10_hwmgr *data = hwmgr->backend;
4630         uint32_t i, size = 0;
4631         static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
4632                                                 {90, 60, 0, 0,},
4633                                                 {70, 60, 0, 0,},
4634                                                 {70, 90, 0, 0,},
4635                                                 {30, 60, 0, 6,},
4636                                                 };
4637         static const char *profile_name[6] = {"3D_FULL_SCREEN",
4638                                         "POWER_SAVING",
4639                                         "VIDEO",
4640                                         "VR",
4641                                         "COMPUTE",
4642                                         "CUSTOM"};
4643         static const char *title[6] = {"NUM",
4644                         "MODE_NAME",
4645                         "BUSY_SET_POINT",
4646                         "FPS",
4647                         "USE_RLC_BUSY",
4648                         "MIN_ACTIVE_LEVEL"};
4649
4650         if (!buf)
4651                 return -EINVAL;
4652
4653         size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
4654                         title[1], title[2], title[3], title[4], title[5]);
4655
4656         for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
4657                 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
4658                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4659                         profile_mode_setting[i][0], profile_mode_setting[i][1],
4660                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
4661         size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
4662                         profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4663                         data->custom_profile_mode[0], data->custom_profile_mode[1],
4664                         data->custom_profile_mode[2], data->custom_profile_mode[3]);
4665         return size;
4666 }
4667
4668 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4669 {
4670         struct vega10_hwmgr *data = hwmgr->backend;
4671         uint8_t busy_set_point;
4672         uint8_t FPS;
4673         uint8_t use_rlc_busy;
4674         uint8_t min_active_level;
4675
4676         hwmgr->power_profile_mode = input[size];
4677
4678         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4679                                                 1<<hwmgr->power_profile_mode);
4680
4681         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4682                 if (size == 0 || size > 4)
4683                         return -EINVAL;
4684
4685                 data->custom_profile_mode[0] = busy_set_point = input[0];
4686                 data->custom_profile_mode[1] = FPS = input[1];
4687                 data->custom_profile_mode[2] = use_rlc_busy = input[2];
4688                 data->custom_profile_mode[3] = min_active_level = input[3];
4689                 smum_send_msg_to_smc_with_parameter(hwmgr,
4690                                         PPSMC_MSG_SetCustomGfxDpmParameters,
4691                                         busy_set_point | FPS<<8 |
4692                                         use_rlc_busy << 16 | min_active_level<<24);
4693         }
4694
4695         return 0;
4696 }
4697
4698
4699 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4700                                         enum PP_OD_DPM_TABLE_COMMAND type,
4701                                         uint32_t clk,
4702                                         uint32_t voltage)
4703 {
4704         struct vega10_hwmgr *data = hwmgr->backend;
4705         struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4706         struct vega10_single_dpm_table *golden_table;
4707
4708         if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
4709                 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
4710                 return false;
4711         }
4712
4713         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4714                 golden_table = &(data->golden_dpm_table.gfx_table);
4715                 if (golden_table->dpm_levels[0].value > clk ||
4716                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4717                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4718                                 golden_table->dpm_levels[0].value/100,
4719                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4720                         return false;
4721                 }
4722         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4723                 golden_table = &(data->golden_dpm_table.mem_table);
4724                 if (golden_table->dpm_levels[0].value > clk ||
4725                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4726                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4727                                 golden_table->dpm_levels[0].value/100,
4728                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4729                         return false;
4730                 }
4731         } else {
4732                 return false;
4733         }
4734
4735         return true;
4736 }
4737
4738 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
4739                                                 enum PP_OD_DPM_TABLE_COMMAND type)
4740 {
4741         struct vega10_hwmgr *data = hwmgr->backend;
4742         struct phm_ppt_v2_information *table_info = hwmgr->pptable;
4743         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
4744         struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.soc_table;
4745
4746         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
4747                                                         &data->odn_dpm_table.vdd_dep_on_socclk;
4748         struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
4749
4750         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
4751         uint8_t i, j;
4752
4753         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4754                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4755                 for (i = 0; i < podn_vdd_dep->count - 1; i++)
4756                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4757                 if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
4758                         od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
4759         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4760                 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4761                 for (i = 0; i < dpm_table->count; i++) {
4762                         for (j = 0; j < od_vddc_lookup_table->count; j++) {
4763                                 if (od_vddc_lookup_table->entries[j].us_vdd >
4764                                         podn_vdd_dep->entries[i].vddc)
4765                                         break;
4766                         }
4767                         if (j == od_vddc_lookup_table->count) {
4768                                 od_vddc_lookup_table->entries[j-1].us_vdd =
4769                                         podn_vdd_dep->entries[i].vddc;
4770                                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4771                         }
4772                         podn_vdd_dep->entries[i].vddInd = j;
4773                 }
4774                 dpm_table = &data->dpm_table.soc_table;
4775                 for (i = 0; i < dep_table->count; i++) {
4776                         if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[dep_table->count-1].vddInd &&
4777                                         dep_table->entries[i].clk < podn_vdd_dep->entries[dep_table->count-1].clk) {
4778                                 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4779                                 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4780                                 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
4781                         }
4782                 }
4783                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
4784                                         podn_vdd_dep->entries[dep_table->count-1].clk) {
4785                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4786                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
4787                         dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = podn_vdd_dep->entries[dep_table->count-1].clk;
4788                 }
4789                 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
4790                                         podn_vdd_dep->entries[dep_table->count-1].vddInd) {
4791                         data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
4792                         podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = podn_vdd_dep->entries[dep_table->count-1].vddInd;
4793                 }
4794         }
4795 }
4796
4797 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4798                                         enum PP_OD_DPM_TABLE_COMMAND type,
4799                                         long *input, uint32_t size)
4800 {
4801         struct vega10_hwmgr *data = hwmgr->backend;
4802         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
4803         struct vega10_single_dpm_table *dpm_table;
4804
4805         uint32_t input_clk;
4806         uint32_t input_vol;
4807         uint32_t input_level;
4808         uint32_t i;
4809
4810         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4811                                 return -EINVAL);
4812
4813         if (!hwmgr->od_enabled) {
4814                 pr_info("OverDrive feature not enabled\n");
4815                 return -EINVAL;
4816         }
4817
4818         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4819                 dpm_table = &data->dpm_table.gfx_table;
4820                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
4821                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4822         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4823                 dpm_table = &data->dpm_table.mem_table;
4824                 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
4825                 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4826         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4827                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
4828                 vega10_odn_initial_default_setting(hwmgr);
4829                 return 0;
4830         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4831                 vega10_check_dpm_table_updated(hwmgr);
4832                 return 0;
4833         } else {
4834                 return -EINVAL;
4835         }
4836
4837         for (i = 0; i < size; i += 3) {
4838                 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
4839                         pr_info("invalid clock voltage input\n");
4840                         return 0;
4841                 }
4842                 input_level = input[i];
4843                 input_clk = input[i+1] * 100;
4844                 input_vol = input[i+2];
4845
4846                 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4847                         dpm_table->dpm_levels[input_level].value = input_clk;
4848                         podn_vdd_dep_table->entries[input_level].clk = input_clk;
4849                         podn_vdd_dep_table->entries[input_level].vddc = input_vol;
4850                 } else {
4851                         return -EINVAL;
4852                 }
4853         }
4854         vega10_odn_update_soc_table(hwmgr, type);
4855         return 0;
4856 }
4857
4858 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
4859                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
4860                                 PHM_PerformanceLevel *level)
4861 {
4862         const struct vega10_power_state *ps;
4863         struct vega10_hwmgr *data;
4864         uint32_t i;
4865
4866         if (level == NULL || hwmgr == NULL || state == NULL)
4867                 return -EINVAL;
4868
4869         data = hwmgr->backend;
4870         ps = cast_const_phw_vega10_power_state(state);
4871
4872         i = index > ps->performance_level_count - 1 ?
4873                         ps->performance_level_count - 1 : index;
4874
4875         level->coreClock = ps->performance_levels[i].gfx_clock;
4876         level->memory_clock = ps->performance_levels[i].mem_clock;
4877
4878         return 0;
4879 }
4880
4881 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
4882         .backend_init = vega10_hwmgr_backend_init,
4883         .backend_fini = vega10_hwmgr_backend_fini,
4884         .asic_setup = vega10_setup_asic_task,
4885         .dynamic_state_management_enable = vega10_enable_dpm_tasks,
4886         .dynamic_state_management_disable = vega10_disable_dpm_tasks,
4887         .get_num_of_pp_table_entries =
4888                         vega10_get_number_of_powerplay_table_entries,
4889         .get_power_state_size = vega10_get_power_state_size,
4890         .get_pp_table_entry = vega10_get_pp_table_entry,
4891         .patch_boot_state = vega10_patch_boot_state,
4892         .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
4893         .power_state_set = vega10_set_power_state_tasks,
4894         .get_sclk = vega10_dpm_get_sclk,
4895         .get_mclk = vega10_dpm_get_mclk,
4896         .notify_smc_display_config_after_ps_adjustment =
4897                         vega10_notify_smc_display_config_after_ps_adjustment,
4898         .force_dpm_level = vega10_dpm_force_dpm_level,
4899         .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
4900         .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
4901         .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
4902         .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
4903         .reset_fan_speed_to_default =
4904                         vega10_fan_ctrl_reset_fan_speed_to_default,
4905         .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
4906         .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
4907         .uninitialize_thermal_controller =
4908                         vega10_thermal_ctrl_uninitialize_thermal_controller,
4909         .set_fan_control_mode = vega10_set_fan_control_mode,
4910         .get_fan_control_mode = vega10_get_fan_control_mode,
4911         .read_sensor = vega10_read_sensor,
4912         .get_dal_power_level = vega10_get_dal_power_level,
4913         .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
4914         .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
4915         .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
4916         .display_clock_voltage_request = vega10_display_clock_voltage_request,
4917         .force_clock_level = vega10_force_clock_level,
4918         .print_clock_levels = vega10_print_clock_levels,
4919         .display_config_changed = vega10_display_configuration_changed_task,
4920         .powergate_uvd = vega10_power_gate_uvd,
4921         .powergate_vce = vega10_power_gate_vce,
4922         .check_states_equal = vega10_check_states_equal,
4923         .check_smc_update_required_for_display_configuration =
4924                         vega10_check_smc_update_required_for_display_configuration,
4925         .power_off_asic = vega10_power_off_asic,
4926         .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
4927         .get_sclk_od = vega10_get_sclk_od,
4928         .set_sclk_od = vega10_set_sclk_od,
4929         .get_mclk_od = vega10_get_mclk_od,
4930         .set_mclk_od = vega10_set_mclk_od,
4931         .avfs_control = vega10_avfs_enable,
4932         .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
4933         .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
4934         .register_irq_handlers = smu9_register_irq_handlers,
4935         .start_thermal_controller = vega10_start_thermal_controller,
4936         .get_power_profile_mode = vega10_get_power_profile_mode,
4937         .set_power_profile_mode = vega10_set_power_profile_mode,
4938         .set_power_limit = vega10_set_power_limit,
4939         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
4940         .get_performance_level = vega10_get_performance_level,
4941 };
4942
4943 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
4944                 bool enable, uint32_t feature_mask)
4945 {
4946         int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
4947                         PPSMC_MSG_DisableSmuFeatures;
4948
4949         return smum_send_msg_to_smc_with_parameter(hwmgr,
4950                         msg, feature_mask);
4951 }
4952
4953 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
4954 {
4955         hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
4956         hwmgr->pptable_func = &vega10_pptable_funcs;
4957
4958         return 0;
4959 }