2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "vega10_thermal.h"
25 #include "vega10_hwmgr.h"
26 #include "vega10_smumgr.h"
27 #include "vega10_ppsmc.h"
28 #include "vega10_inc.h"
29 #include "soc15_common.h"
32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
35 *current_rpm = smum_get_argument(hwmgr);
39 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
40 struct phm_fan_speed_info *fan_speed_info)
43 if (hwmgr->thermal_controller.fanInfo.bNoFan)
46 fan_speed_info->supports_percent_read = true;
47 fan_speed_info->supports_percent_write = true;
48 fan_speed_info->min_percent = 0;
49 fan_speed_info->max_percent = 100;
51 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
52 hwmgr->thermal_controller.fanInfo.
53 ucTachometerPulsesPerRevolution) {
54 fan_speed_info->supports_rpm_read = true;
55 fan_speed_info->supports_rpm_write = true;
56 fan_speed_info->min_rpm =
57 hwmgr->thermal_controller.fanInfo.ulMinRPM;
58 fan_speed_info->max_rpm =
59 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
61 fan_speed_info->min_rpm = 0;
62 fan_speed_info->max_rpm = 0;
68 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
74 if (hwmgr->thermal_controller.fanInfo.bNoFan)
77 if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
80 if (hwmgr->thermal_controller.
81 advanceFanControlParameters.usMaxFanRPM != 0)
82 percent = current_rpm * 100 /
83 hwmgr->thermal_controller.
84 advanceFanControlParameters.usMaxFanRPM;
86 *speed = percent > 100 ? 100 : percent;
91 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
93 struct amdgpu_device *adev = hwmgr->adev;
94 struct vega10_hwmgr *data = hwmgr->backend;
96 uint32_t crystal_clock_freq;
99 if (hwmgr->thermal_controller.fanInfo.bNoFan)
102 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
103 result = vega10_get_current_rpm(hwmgr, speed);
106 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
110 if (tach_period == 0)
113 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
115 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
122 * Set Fan Speed Control to static mode,
123 * so that the user can decide what speed to use.
124 * @param hwmgr the address of the powerplay hardware manager.
125 * mode the fan control mode, 0 default, 1 by percent, 5, by RPM
126 * @exception Should always succeed.
128 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
130 struct amdgpu_device *adev = hwmgr->adev;
132 if (hwmgr->fan_ctrl_is_in_default_mode) {
133 hwmgr->fan_ctrl_default_mode =
134 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
135 CG_FDO_CTRL2, FDO_PWM_MODE);
137 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
139 hwmgr->fan_ctrl_is_in_default_mode = false;
142 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
143 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
144 CG_FDO_CTRL2, TMIN, 0));
145 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
146 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
147 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
153 * Reset Fan Speed Control to default mode.
154 * @param hwmgr the address of the powerplay hardware manager.
155 * @exception Should always succeed.
157 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
159 struct amdgpu_device *adev = hwmgr->adev;
161 if (!hwmgr->fan_ctrl_is_in_default_mode) {
162 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
164 CG_FDO_CTRL2, FDO_PWM_MODE,
165 hwmgr->fan_ctrl_default_mode));
166 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
167 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
169 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
170 hwmgr->fan_ctrl_is_in_default_mode = true;
177 * @fn vega10_enable_fan_control_feature
178 * @brief Enables the SMC Fan Control Feature.
180 * @param hwmgr - the address of the powerplay hardware manager.
181 * @return 0 on success. -1 otherwise.
183 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
185 struct vega10_hwmgr *data = hwmgr->backend;
187 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
188 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
190 data->smu_features[GNLD_FAN_CONTROL].
192 "Attempt to Enable FAN CONTROL feature Failed!",
194 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
200 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
202 struct vega10_hwmgr *data = hwmgr->backend;
204 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
205 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
207 data->smu_features[GNLD_FAN_CONTROL].
209 "Attempt to Enable FAN CONTROL feature Failed!",
211 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
217 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
219 if (hwmgr->thermal_controller.fanInfo.bNoFan)
222 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
223 "Attempt to Enable SMC FAN CONTROL Feature Failed!",
230 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
232 struct vega10_hwmgr *data = hwmgr->backend;
234 if (hwmgr->thermal_controller.fanInfo.bNoFan)
237 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
238 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
239 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
246 * Set Fan Speed in percent.
247 * @param hwmgr the address of the powerplay hardware manager.
248 * @param speed is the percentage value (0% - 100%) to be set.
249 * @exception Fails is the 100% setting appears to be 0.
251 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
254 struct amdgpu_device *adev = hwmgr->adev;
259 if (hwmgr->thermal_controller.fanInfo.bNoFan)
265 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
266 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
268 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
269 CG_FDO_CTRL1, FMAX_DUTY100);
274 tmp64 = (uint64_t)speed * duty100;
276 duty = (uint32_t)tmp64;
278 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
279 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
280 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
282 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
286 * Reset Fan Speed to default.
287 * @param hwmgr the address of the powerplay hardware manager.
288 * @exception Always succeeds.
290 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
292 if (hwmgr->thermal_controller.fanInfo.bNoFan)
295 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
296 return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
298 return vega10_fan_ctrl_set_default_mode(hwmgr);
302 * Set Fan Speed in RPM.
303 * @param hwmgr the address of the powerplay hardware manager.
304 * @param speed is the percentage value (min - max) to be set.
305 * @exception Fails is the speed not lie between min and max.
307 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
309 struct amdgpu_device *adev = hwmgr->adev;
310 uint32_t tach_period;
311 uint32_t crystal_clock_freq;
314 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
315 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
316 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
319 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
320 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
323 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
324 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
325 WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,
326 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
327 CG_TACH_STATUS, TACH_PERIOD,
330 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
334 * Reads the remote temperature from the SIslands thermal controller.
336 * @param hwmgr The address of the hardware manager.
338 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
340 struct amdgpu_device *adev = hwmgr->adev;
343 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
345 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
346 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
350 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
356 * Set the requested temperature range for high and low alert signals
358 * @param hwmgr The address of the hardware manager.
359 * @param range Temperature range to be programmed for
360 * high and low alert signals
361 * @exception PP_Result_BadInput if the input data is not valid.
363 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
364 struct PP_TemperatureRange *range)
366 struct amdgpu_device *adev = hwmgr->adev;
367 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
368 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
369 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
370 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
373 if (low < range->min)
375 if (high > range->max)
381 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
383 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
384 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
385 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
386 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
387 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
388 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
389 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
391 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
397 * Programs thermal controller one-time setting registers
399 * @param hwmgr The address of the hardware manager.
401 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
403 struct amdgpu_device *adev = hwmgr->adev;
405 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
406 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
407 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
408 CG_TACH_CTRL, EDGE_PER_REV,
409 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
412 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
413 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
414 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
420 * Enable thermal alerts on the RV770 thermal controller.
422 * @param hwmgr The address of the hardware manager.
424 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
426 struct amdgpu_device *adev = hwmgr->adev;
427 struct vega10_hwmgr *data = hwmgr->backend;
430 if (data->smu_features[GNLD_FW_CTF].supported) {
431 if (data->smu_features[GNLD_FW_CTF].enabled)
432 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
434 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
436 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
437 "Attempt to Enable FW CTF feature Failed!",
439 data->smu_features[GNLD_FW_CTF].enabled = true;
442 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
443 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
444 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
446 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
452 * Disable thermal alerts on the RV770 thermal controller.
453 * @param hwmgr The address of the hardware manager.
455 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
457 struct amdgpu_device *adev = hwmgr->adev;
458 struct vega10_hwmgr *data = hwmgr->backend;
460 if (data->smu_features[GNLD_FW_CTF].supported) {
461 if (!data->smu_features[GNLD_FW_CTF].enabled)
462 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
465 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
467 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
468 "Attempt to disable FW CTF feature Failed!",
470 data->smu_features[GNLD_FW_CTF].enabled = false;
473 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
479 * Uninitialize the thermal controller.
480 * Currently just disables alerts.
481 * @param hwmgr The address of the hardware manager.
483 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
485 int result = vega10_thermal_disable_alert(hwmgr);
487 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
488 vega10_fan_ctrl_set_default_mode(hwmgr);
494 * Set up the fan table to control the fan using the SMC.
495 * @param hwmgr the address of the powerplay hardware manager.
496 * @param pInput the pointer to input data
497 * @param pOutput the pointer to output data
498 * @param pStorage the pointer to temporary storage
499 * @param Result the last failure code
500 * @return result from set temperature range routine
502 int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
505 struct vega10_hwmgr *data = hwmgr->backend;
506 PPTable_t *table = &(data->smc_state_table.pp_table);
508 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
511 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
512 advanceFanControlParameters.usMaxFanRPM;
513 table->FanThrottlingRpm = hwmgr->thermal_controller.
514 advanceFanControlParameters.usFanRPMMaxLimit;
515 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
516 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
517 table->FanTargetTemperature = hwmgr->thermal_controller.
518 advanceFanControlParameters.usTMax;
520 smum_send_msg_to_smc_with_parameter(hwmgr,
521 PPSMC_MSG_SetFanTemperatureTarget,
522 (uint32_t)table->FanTargetTemperature);
524 table->FanPwmMin = hwmgr->thermal_controller.
525 advanceFanControlParameters.usPWMMin * 255 / 100;
526 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
527 advanceFanControlParameters.ulTargetGfxClk);
528 table->FanGainEdge = hwmgr->thermal_controller.
529 advanceFanControlParameters.usFanGainEdge;
530 table->FanGainHotspot = hwmgr->thermal_controller.
531 advanceFanControlParameters.usFanGainHotspot;
532 table->FanGainLiquid = hwmgr->thermal_controller.
533 advanceFanControlParameters.usFanGainLiquid;
534 table->FanGainVrVddc = hwmgr->thermal_controller.
535 advanceFanControlParameters.usFanGainVrVddc;
536 table->FanGainVrMvdd = hwmgr->thermal_controller.
537 advanceFanControlParameters.usFanGainVrMvdd;
538 table->FanGainPlx = hwmgr->thermal_controller.
539 advanceFanControlParameters.usFanGainPlx;
540 table->FanGainHbm = hwmgr->thermal_controller.
541 advanceFanControlParameters.usFanGainHbm;
542 table->FanZeroRpmEnable = hwmgr->thermal_controller.
543 advanceFanControlParameters.ucEnableZeroRPM;
544 table->FanStopTemp = hwmgr->thermal_controller.
545 advanceFanControlParameters.usZeroRPMStopTemperature;
546 table->FanStartTemp = hwmgr->thermal_controller.
547 advanceFanControlParameters.usZeroRPMStartTemperature;
549 ret = smum_smc_table_manager(hwmgr,
550 (uint8_t *)(&(data->smc_state_table.pp_table)),
553 pr_info("Failed to update Fan Control Table in PPTable!");
559 * Start the fan control on the SMC.
560 * @param hwmgr the address of the powerplay hardware manager.
561 * @param pInput the pointer to input data
562 * @param pOutput the pointer to output data
563 * @param pStorage the pointer to temporary storage
564 * @param Result the last failure code
565 * @return result from set temperature range routine
567 int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
569 /* If the fantable setup has failed we could have disabled
570 * PHM_PlatformCaps_MicrocodeFanControl even after
571 * this function was included in the table.
572 * Make sure that we still think controlling the fan is OK.
574 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
575 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
581 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
582 struct PP_TemperatureRange *range)
589 vega10_thermal_initialize(hwmgr);
590 ret = vega10_thermal_set_temperature_range(hwmgr, range);
594 vega10_thermal_enable_alert(hwmgr);
595 /* We should restrict performance levels to low before we halt the SMC.
596 * On the other hand we are still in boot state when we do this
597 * so it would be pointless.
598 * If this assumption changes we have to revisit this table.
600 ret = vega10_thermal_setup_fan_table(hwmgr);
604 vega10_thermal_start_smc_fan_control(hwmgr);
612 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
614 if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
615 vega10_fan_ctrl_set_default_mode(hwmgr);
616 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);