drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "vega20_baco.h"
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53 #include "nbio/nbio_7_4_sh_mask.h"
  54
  55 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  56 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  57
  58 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  59 {
  60         struct vega20_hwmgr *data =
  61                         (struct vega20_hwmgr *)(hwmgr->backend);
  62
  63         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  64         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  65         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  66         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  67         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  68
  69         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  70         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  78         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  81         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  82
  83         /*
  84          * Disable the following features for now:
  85          *   GFXCLK DS
  86          *   SOCLK DS
  87          *   LCLK DS
  88          *   DCEFCLK DS
  89          *   FCLK DS
  90          *   MP1CLK DS
  91          *   MP0CLK DS
  92          */
  93         data->registry_data.disallowed_features = 0xE0041C00;
  94         data->registry_data.od_state_in_dc_support = 0;
  95         data->registry_data.thermal_support = 1;
  96         data->registry_data.skip_baco_hardware = 0;
  97
  98         data->registry_data.log_avfs_param = 0;
  99         data->registry_data.sclk_throttle_low_notification = 1;
 100         data->registry_data.force_dpm_high = 0;
 101         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
 102
 103         data->registry_data.didt_support = 0;
 104         if (data->registry_data.didt_support) {
 105                 data->registry_data.didt_mode = 6;
 106                 data->registry_data.sq_ramping_support = 1;
 107                 data->registry_data.db_ramping_support = 0;
 108                 data->registry_data.td_ramping_support = 0;
 109                 data->registry_data.tcp_ramping_support = 0;
 110                 data->registry_data.dbr_ramping_support = 0;
 111                 data->registry_data.edc_didt_support = 1;
 112                 data->registry_data.gc_didt_support = 0;
 113                 data->registry_data.psm_didt_support = 0;
 114         }
 115
 116         data->registry_data.pcie_lane_override = 0xff;
 117         data->registry_data.pcie_speed_override = 0xff;
 118         data->registry_data.pcie_clock_override = 0xffffffff;
 119         data->registry_data.regulator_hot_gpio_support = 1;
 120         data->registry_data.ac_dc_switch_gpio_support = 0;
 121         data->registry_data.quick_transition_support = 0;
 122         data->registry_data.zrpm_start_temp = 0xffff;
 123         data->registry_data.zrpm_stop_temp = 0xffff;
 124         data->registry_data.od8_feature_enable = 1;
 125         data->registry_data.disable_water_mark = 0;
 126         data->registry_data.disable_pp_tuning = 0;
 127         data->registry_data.disable_xlpp_tuning = 0;
 128         data->registry_data.disable_workload_policy = 0;
 129         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 130         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 131         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 132         data->registry_data.force_workload_policy_mask = 0;
 133         data->registry_data.disable_3d_fs_detection = 0;
 134         data->registry_data.fps_support = 1;
 135         data->registry_data.disable_auto_wattman = 1;
 136         data->registry_data.auto_wattman_debug = 0;
 137         data->registry_data.auto_wattman_sample_period = 100;
 138         data->registry_data.fclk_gfxclk_ratio = 0;
 139         data->registry_data.auto_wattman_threshold = 50;
 140         data->registry_data.gfxoff_controlled_by_driver = 1;
 141         data->gfxoff_allowed = false;
 142         data->counter_gfxoff = 0;
 143 }
 144
 145 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 146 {
 147         struct vega20_hwmgr *data =
 148                         (struct vega20_hwmgr *)(hwmgr->backend);
 149         struct amdgpu_device *adev = hwmgr->adev;
 150
 151         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 152                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 153                                 PHM_PlatformCaps_ControlVDDCI);
 154
 155         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 156                         PHM_PlatformCaps_TablelessHardwareInterface);
 157
 158         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 159                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 160
 161         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 162                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 163                                 PHM_PlatformCaps_UVDPowerGating);
 164
 165         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 166                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 167                                 PHM_PlatformCaps_VCEPowerGating);
 168
 169         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 170                         PHM_PlatformCaps_UnTabledHardwareInterface);
 171
 172         if (data->registry_data.od8_feature_enable)
 173                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 174                                 PHM_PlatformCaps_OD8inACSupport);
 175
 176         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 177                         PHM_PlatformCaps_ActivityReporting);
 178         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 179                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 180
 181         if (data->registry_data.od_state_in_dc_support) {
 182                 if (data->registry_data.od8_feature_enable)
 183                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 184                                         PHM_PlatformCaps_OD8inDCSupport);
 185         }
 186
 187         if (data->registry_data.thermal_support &&
 188             data->registry_data.fuzzy_fan_control_support &&
 189             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 190                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 191                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 192
 193         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 194                         PHM_PlatformCaps_DynamicPowerManagement);
 195         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                         PHM_PlatformCaps_SMC);
 197         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 198                         PHM_PlatformCaps_ThermalPolicyDelay);
 199
 200         if (data->registry_data.force_dpm_high)
 201                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 202                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 203
 204         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_DynamicUVDState);
 206
 207         if (data->registry_data.sclk_throttle_low_notification)
 208                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 209                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 210
 211         /* power tune caps */
 212         /* assume disabled */
 213         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 214                         PHM_PlatformCaps_PowerContainment);
 215         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 216                         PHM_PlatformCaps_DiDtSupport);
 217         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 218                         PHM_PlatformCaps_SQRamping);
 219         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 220                         PHM_PlatformCaps_DBRamping);
 221         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_TDRamping);
 223         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_TCPRamping);
 225         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_DBRRamping);
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_DiDtEDCEnable);
 229         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 230                         PHM_PlatformCaps_GCEDC);
 231         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_PSM);
 233
 234         if (data->registry_data.didt_support) {
 235                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 236                                 PHM_PlatformCaps_DiDtSupport);
 237                 if (data->registry_data.sq_ramping_support)
 238                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 239                                         PHM_PlatformCaps_SQRamping);
 240                 if (data->registry_data.db_ramping_support)
 241                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_DBRamping);
 243                 if (data->registry_data.td_ramping_support)
 244                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 245                                         PHM_PlatformCaps_TDRamping);
 246                 if (data->registry_data.tcp_ramping_support)
 247                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 248                                         PHM_PlatformCaps_TCPRamping);
 249                 if (data->registry_data.dbr_ramping_support)
 250                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 251                                         PHM_PlatformCaps_DBRRamping);
 252                 if (data->registry_data.edc_didt_support)
 253                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 254                                         PHM_PlatformCaps_DiDtEDCEnable);
 255                 if (data->registry_data.gc_didt_support)
 256                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 257                                         PHM_PlatformCaps_GCEDC);
 258                 if (data->registry_data.psm_didt_support)
 259                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 260                                         PHM_PlatformCaps_PSM);
 261         }
 262
 263         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 264                         PHM_PlatformCaps_RegulatorHot);
 265
 266         if (data->registry_data.ac_dc_switch_gpio_support) {
 267                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                 PHM_PlatformCaps_AutomaticDCTransition);
 269                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 270                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 271         }
 272
 273         if (data->registry_data.quick_transition_support) {
 274                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 275                                 PHM_PlatformCaps_AutomaticDCTransition);
 276                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 277                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 278                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 279                                 PHM_PlatformCaps_Falcon_QuickTransition);
 280         }
 281
 282         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 283                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 284                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 285                 if (data->lowest_uclk_reserved_for_ulv == 1)
 286                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 287                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 288         }
 289
 290         if (data->registry_data.custom_fan_support)
 291                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 292                                 PHM_PlatformCaps_CustomFanControlSupport);
 293
 294         return 0;
 295 }
 296
 297 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 298 {
 299         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 300         int i;
 301
 302         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 303                         FEATURE_DPM_PREFETCHER_BIT;
 304         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 305                         FEATURE_DPM_GFXCLK_BIT;
 306         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 307                         FEATURE_DPM_UCLK_BIT;
 308         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 309                         FEATURE_DPM_SOCCLK_BIT;
 310         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 311                         FEATURE_DPM_UVD_BIT;
 312         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 313                         FEATURE_DPM_VCE_BIT;
 314         data->smu_features[GNLD_ULV].smu_feature_id =
 315                         FEATURE_ULV_BIT;
 316         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 317                         FEATURE_DPM_MP0CLK_BIT;
 318         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 319                         FEATURE_DPM_LINK_BIT;
 320         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 321                         FEATURE_DPM_DCEFCLK_BIT;
 322         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 323                         FEATURE_DS_GFXCLK_BIT;
 324         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 325                         FEATURE_DS_SOCCLK_BIT;
 326         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 327                         FEATURE_DS_LCLK_BIT;
 328         data->smu_features[GNLD_PPT].smu_feature_id =
 329                         FEATURE_PPT_BIT;
 330         data->smu_features[GNLD_TDC].smu_feature_id =
 331                         FEATURE_TDC_BIT;
 332         data->smu_features[GNLD_THERMAL].smu_feature_id =
 333                         FEATURE_THERMAL_BIT;
 334         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 335                         FEATURE_GFX_PER_CU_CG_BIT;
 336         data->smu_features[GNLD_RM].smu_feature_id =
 337                         FEATURE_RM_BIT;
 338         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 339                         FEATURE_DS_DCEFCLK_BIT;
 340         data->smu_features[GNLD_ACDC].smu_feature_id =
 341                         FEATURE_ACDC_BIT;
 342         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 343                         FEATURE_VR0HOT_BIT;
 344         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 345                         FEATURE_VR1HOT_BIT;
 346         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 347                         FEATURE_FW_CTF_BIT;
 348         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 349                         FEATURE_LED_DISPLAY_BIT;
 350         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 351                         FEATURE_FAN_CONTROL_BIT;
 352         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 353         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 354         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 355         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 356         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 357         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 358         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 359         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 360
 361         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 362                 data->smu_features[i].smu_feature_bitmap =
 363                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 364                 data->smu_features[i].allowed =
 365                         ((data->registry_data.disallowed_features >> i) & 1) ?
 366                         false : true;
 367         }
 368 }
 369
 370 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 371 {
 372         return 0;
 373 }
 374
 375 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 376 {
 377         kfree(hwmgr->backend);
 378         hwmgr->backend = NULL;
 379
 380         return 0;
 381 }
 382
 383 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 384 {
 385         struct vega20_hwmgr *data;
 386         struct amdgpu_device *adev = hwmgr->adev;
 387
 388         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 389         if (data == NULL)
 390                 return -ENOMEM;
 391
 392         hwmgr->backend = data;
 393
 394         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 395         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 396         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 397
 398         vega20_set_default_registry_data(hwmgr);
 399
 400         data->disable_dpm_mask = 0xff;
 401
 402         /* need to set voltage control types before EVV patching */
 403         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 404         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 405         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 406
 407         data->water_marks_bitmap = 0;
 408         data->avfs_exist = false;
 409
 410         vega20_set_features_platform_caps(hwmgr);
 411
 412         vega20_init_dpm_defaults(hwmgr);
 413
 414         /* Parse pptable data read from VBIOS */
 415         vega20_set_private_data_based_on_pptable(hwmgr);
 416
 417         data->is_tlu_enabled = false;
 418
 419         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 420                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 421         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 422         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 423
 424         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 425         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 426         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 427         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 428
 429         data->total_active_cus = adev->gfx.cu_info.number;
 430
 431         return 0;
 432 }
 433
 434 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 435 {
 436         struct vega20_hwmgr *data =
 437                         (struct vega20_hwmgr *)(hwmgr->backend);
 438
 439         data->low_sclk_interrupt_threshold = 0;
 440
 441         return 0;
 442 }
 443
 444 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 445 {
 446         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 447         int ret = 0;
 448
 449         ret = vega20_init_sclk_threshold(hwmgr);
 450         PP_ASSERT_WITH_CODE(!ret,
 451                         "Failed to init sclk threshold!",
 452                         return ret);
 453
 454         if (adev->in_baco_reset) {
 455                 adev->in_baco_reset = 0;
 456
 457                 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
 458                 if (ret)
 459                         pr_err("Failed to apply vega20 baco workaround!\n");
 460         }
 461
 462         return ret;
 463 }
 464
 465 /*
 466  * @fn vega20_init_dpm_state
 467  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 468  *
 469  * @param    dpm_state - the address of the DPM Table to initiailize.
 470  * @return   None.
 471  */
 472 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 473 {
 474         dpm_state->soft_min_level = 0x0;
 475         dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
 476         dpm_state->hard_min_level = 0x0;
 477         dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
 478 }
 479
 480 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 481                 PPCLK_e clk_id, uint32_t *num_of_levels)
 482 {
 483         int ret = 0;
 484
 485         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 486                         PPSMC_MSG_GetDpmFreqByIndex,
 487                         (clk_id << 16 | 0xFF));
 488         PP_ASSERT_WITH_CODE(!ret,
 489                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 490                         return ret);
 491
 492         *num_of_levels = smum_get_argument(hwmgr);
 493         PP_ASSERT_WITH_CODE(*num_of_levels > 0,
 494                         "[GetNumOfDpmLevel] number of clk levels is invalid!",
 495                         return -EINVAL);
 496
 497         return ret;
 498 }
 499
 500 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 501                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 502 {
 503         int ret = 0;
 504
 505         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 506                         PPSMC_MSG_GetDpmFreqByIndex,
 507                         (clk_id << 16 | index));
 508         PP_ASSERT_WITH_CODE(!ret,
 509                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 510                         return ret);
 511
 512         *clk = smum_get_argument(hwmgr);
 513         PP_ASSERT_WITH_CODE(*clk,
 514                         "[GetDpmFreqByIndex] clk value is invalid!",
 515                         return -EINVAL);
 516
 517         return ret;
 518 }
 519
 520 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 521                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 522 {
 523         int ret = 0;
 524         uint32_t i, num_of_levels, clk;
 525
 526         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 527         PP_ASSERT_WITH_CODE(!ret,
 528                         "[SetupSingleDpmTable] failed to get clk levels!",
 529                         return ret);
 530
 531         dpm_table->count = num_of_levels;
 532
 533         for (i = 0; i < num_of_levels; i++) {
 534                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 535                 PP_ASSERT_WITH_CODE(!ret,
 536                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 537                         return ret);
 538                 dpm_table->dpm_levels[i].value = clk;
 539                 dpm_table->dpm_levels[i].enabled = true;
 540         }
 541
 542         return ret;
 543 }
 544
 545 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 546 {
 547         struct vega20_hwmgr *data =
 548                         (struct vega20_hwmgr *)(hwmgr->backend);
 549         struct vega20_single_dpm_table *dpm_table;
 550         int ret = 0;
 551
 552         dpm_table = &(data->dpm_table.gfx_table);
 553         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 554                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 555                 PP_ASSERT_WITH_CODE(!ret,
 556                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 557                                 return ret);
 558         } else {
 559                 dpm_table->count = 1;
 560                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 561         }
 562
 563         return ret;
 564 }
 565
 566 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 567 {
 568         struct vega20_hwmgr *data =
 569                         (struct vega20_hwmgr *)(hwmgr->backend);
 570         struct vega20_single_dpm_table *dpm_table;
 571         int ret = 0;
 572
 573         dpm_table = &(data->dpm_table.mem_table);
 574         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 575                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 576                 PP_ASSERT_WITH_CODE(!ret,
 577                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 578                                 return ret);
 579         } else {
 580                 dpm_table->count = 1;
 581                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 582         }
 583
 584         return ret;
 585 }
 586
 587 /*
 588  * This function is to initialize all DPM state tables
 589  * for SMU based on the dependency table.
 590  * Dynamic state patching function will then trim these
 591  * state tables to the allowed range based
 592  * on the power policy or external client requests,
 593  * such as UVD request, etc.
 594  */
 595 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 596 {
 597         struct vega20_hwmgr *data =
 598                         (struct vega20_hwmgr *)(hwmgr->backend);
 599         struct vega20_single_dpm_table *dpm_table;
 600         int ret = 0;
 601
 602         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 603
 604         /* socclk */
 605         dpm_table = &(data->dpm_table.soc_table);
 606         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 607                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 608                 PP_ASSERT_WITH_CODE(!ret,
 609                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 610                                 return ret);
 611         } else {
 612                 dpm_table->count = 1;
 613                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 614         }
 615         vega20_init_dpm_state(&(dpm_table->dpm_state));
 616
 617         /* gfxclk */
 618         dpm_table = &(data->dpm_table.gfx_table);
 619         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 620         if (ret)
 621                 return ret;
 622         vega20_init_dpm_state(&(dpm_table->dpm_state));
 623
 624         /* memclk */
 625         dpm_table = &(data->dpm_table.mem_table);
 626         ret = vega20_setup_memclk_dpm_table(hwmgr);
 627         if (ret)
 628                 return ret;
 629         vega20_init_dpm_state(&(dpm_table->dpm_state));
 630
 631         /* eclk */
 632         dpm_table = &(data->dpm_table.eclk_table);
 633         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 634                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 635                 PP_ASSERT_WITH_CODE(!ret,
 636                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 637                                 return ret);
 638         } else {
 639                 dpm_table->count = 1;
 640                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 641         }
 642         vega20_init_dpm_state(&(dpm_table->dpm_state));
 643
 644         /* vclk */
 645         dpm_table = &(data->dpm_table.vclk_table);
 646         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 647                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 648                 PP_ASSERT_WITH_CODE(!ret,
 649                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 650                                 return ret);
 651         } else {
 652                 dpm_table->count = 1;
 653                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 654         }
 655         vega20_init_dpm_state(&(dpm_table->dpm_state));
 656
 657         /* dclk */
 658         dpm_table = &(data->dpm_table.dclk_table);
 659         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 660                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 661                 PP_ASSERT_WITH_CODE(!ret,
 662                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 663                                 return ret);
 664         } else {
 665                 dpm_table->count = 1;
 666                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 667         }
 668         vega20_init_dpm_state(&(dpm_table->dpm_state));
 669
 670         /* dcefclk */
 671         dpm_table = &(data->dpm_table.dcef_table);
 672         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 673                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 674                 PP_ASSERT_WITH_CODE(!ret,
 675                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 676                                 return ret);
 677         } else {
 678                 dpm_table->count = 1;
 679                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 680         }
 681         vega20_init_dpm_state(&(dpm_table->dpm_state));
 682
 683         /* pixclk */
 684         dpm_table = &(data->dpm_table.pixel_table);
 685         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 686                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 687                 PP_ASSERT_WITH_CODE(!ret,
 688                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 689                                 return ret);
 690         } else
 691                 dpm_table->count = 0;
 692         vega20_init_dpm_state(&(dpm_table->dpm_state));
 693
 694         /* dispclk */
 695         dpm_table = &(data->dpm_table.display_table);
 696         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 697                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 698                 PP_ASSERT_WITH_CODE(!ret,
 699                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 700                                 return ret);
 701         } else
 702                 dpm_table->count = 0;
 703         vega20_init_dpm_state(&(dpm_table->dpm_state));
 704
 705         /* phyclk */
 706         dpm_table = &(data->dpm_table.phy_table);
 707         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 708                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 709                 PP_ASSERT_WITH_CODE(!ret,
 710                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 711                                 return ret);
 712         } else
 713                 dpm_table->count = 0;
 714         vega20_init_dpm_state(&(dpm_table->dpm_state));
 715
 716         /* fclk */
 717         dpm_table = &(data->dpm_table.fclk_table);
 718         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 719                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 720                 PP_ASSERT_WITH_CODE(!ret,
 721                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 722                                 return ret);
 723         } else {
 724                 dpm_table->count = 1;
 725                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
 726         }
 727         vega20_init_dpm_state(&(dpm_table->dpm_state));
 728
 729         /* save a copy of the default DPM table */
 730         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 731                         sizeof(struct vega20_dpm_table));
 732
 733         return 0;
 734 }
 735
 736 /**
 737 * Initializes the SMC table and uploads it
 738 *
 739 * @param    hwmgr  the address of the powerplay hardware manager.
 740 * @param    pInput  the pointer to input data (PowerState)
 741 * @return   always 0
 742 */
 743 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 744 {
 745         int result;
 746         struct vega20_hwmgr *data =
 747                         (struct vega20_hwmgr *)(hwmgr->backend);
 748         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 749         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 750         struct phm_ppt_v3_information *pptable_information =
 751                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 752
 753         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 754         PP_ASSERT_WITH_CODE(!result,
 755                         "[InitSMCTable] Failed to get vbios bootup values!",
 756                         return result);
 757
 758         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 759         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 760         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 761         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 762         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 763         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 764         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 765         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 766         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 767         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 768         data->vbios_boot_state.fclock = boot_up_values.ulFClk;
 769         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 770
 771         smum_send_msg_to_smc_with_parameter(hwmgr,
 772                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 773                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 774
 775         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 776
 777         result = smum_smc_table_manager(hwmgr,
 778                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 779         PP_ASSERT_WITH_CODE(!result,
 780                         "[InitSMCTable] Failed to upload PPtable!",
 781                         return result);
 782
 783         return 0;
 784 }
 785
 786 /*
 787  * Override PCIe link speed and link width for DPM Level 1. PPTable entries
 788  * reflect the ASIC capabilities and not the system capabilities. For e.g.
 789  * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
 790  * to DPM1, it fails as system doesn't support Gen4.
 791  */
 792 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 795         struct vega20_hwmgr *data =
 796                         (struct vega20_hwmgr *)(hwmgr->backend);
 797         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 798         int ret;
 799
 800         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 801                 pcie_gen = 3;
 802         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 803                 pcie_gen = 2;
 804         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 805                 pcie_gen = 1;
 806         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 807                 pcie_gen = 0;
 808
 809         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 810                 pcie_width = 6;
 811         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 812                 pcie_width = 5;
 813         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 814                 pcie_width = 4;
 815         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 816                 pcie_width = 3;
 817         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 818                 pcie_width = 2;
 819         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 820                 pcie_width = 1;
 821
 822         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 823          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 824          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 825          */
 826         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 827         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 828                         PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);
 829         PP_ASSERT_WITH_CODE(!ret,
 830                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 831                 return ret);
 832
 833         data->pcie_parameters_override = 1;
 834         data->pcie_gen_level1 = pcie_gen;
 835         data->pcie_width_level1 = pcie_width;
 836
 837         return 0;
 838 }
 839
 840 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 841 {
 842         struct vega20_hwmgr *data =
 843                         (struct vega20_hwmgr *)(hwmgr->backend);
 844         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 845         int i;
 846         int ret = 0;
 847
 848         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 849                 if (data->smu_features[i].allowed)
 850                         data->smu_features[i].smu_feature_id > 31 ?
 851                                 (allowed_features_high |=
 852                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 853                                   & 0xFFFFFFFF)) :
 854                                 (allowed_features_low |=
 855                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 856                                   & 0xFFFFFFFF));
 857
 858         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 859                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
 860         PP_ASSERT_WITH_CODE(!ret,
 861                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 862                 return ret);
 863
 864         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 865                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
 866         PP_ASSERT_WITH_CODE(!ret,
 867                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 868                 return ret);
 869
 870         return 0;
 871 }
 872
 873 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
 874 {
 875         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
 876 }
 877
 878 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 879 {
 880         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
 881 }
 882
 883 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 884 {
 885         struct vega20_hwmgr *data =
 886                         (struct vega20_hwmgr *)(hwmgr->backend);
 887         uint64_t features_enabled;
 888         int i;
 889         bool enabled;
 890         int ret = 0;
 891
 892         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 893                         PPSMC_MSG_EnableAllSmuFeatures)) == 0,
 894                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 895                         return ret);
 896
 897         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 898         PP_ASSERT_WITH_CODE(!ret,
 899                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 900                         return ret);
 901
 902         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 903                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 904                         true : false;
 905                 data->smu_features[i].enabled = enabled;
 906                 data->smu_features[i].supported = enabled;
 907
 908 #if 0
 909                 if (data->smu_features[i].allowed && !enabled)
 910                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 911                 else if (!data->smu_features[i].allowed && enabled)
 912                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 913 #endif
 914         }
 915
 916         return 0;
 917 }
 918
 919 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
 920 {
 921         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 922
 923         if (data->smu_features[GNLD_DPM_UCLK].enabled)
 924                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 925                         PPSMC_MSG_SetUclkFastSwitch,
 926                         1);
 927
 928         return 0;
 929 }
 930
 931 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 932 {
 933         struct vega20_hwmgr *data =
 934                         (struct vega20_hwmgr *)(hwmgr->backend);
 935
 936         return smum_send_msg_to_smc_with_parameter(hwmgr,
 937                         PPSMC_MSG_SetFclkGfxClkRatio,
 938                         data->registry_data.fclk_gfxclk_ratio);
 939 }
 940
 941 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 942 {
 943         struct vega20_hwmgr *data =
 944                         (struct vega20_hwmgr *)(hwmgr->backend);
 945         uint64_t features_enabled;
 946         int i;
 947         bool enabled;
 948         int ret = 0;
 949
 950         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 951                         PPSMC_MSG_DisableAllSmuFeatures)) == 0,
 952                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 953                         return ret);
 954
 955         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 956         PP_ASSERT_WITH_CODE(!ret,
 957                         "[DisableAllSMUFeatures] Failed to get enabled smc features!",
 958                         return ret);
 959
 960         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 961                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 962                         true : false;
 963                 data->smu_features[i].enabled = enabled;
 964                 data->smu_features[i].supported = enabled;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int vega20_od8_set_feature_capabilities(
 971                 struct pp_hwmgr *hwmgr)
 972 {
 973         struct phm_ppt_v3_information *pptable_information =
 974                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 975         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 976         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 977         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 978
 979         od_settings->overdrive8_capabilities = 0;
 980
 981         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 982                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
 983                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
 984                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
 985                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
 986                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
 987                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
 988
 989                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
 990                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
 991                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
 992                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
 993                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
 994                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
 995                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
 996                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
 997         }
 998
 999         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1000                 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1001                         data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1002                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1003                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1004                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1005                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1006                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1007                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1008         }
1009
1010         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1011             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1012             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1013             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1014             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1015                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1016
1017         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1018                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1019                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1020                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1021                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1022                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1023                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1024
1025                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1026                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1027                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1028                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1029                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1030                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1031                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1032         }
1033
1034         if (data->smu_features[GNLD_THERMAL].enabled) {
1035                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1036                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1037                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1038                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1039                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1040                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1041
1042                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1043                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1044                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1045                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1046                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1047                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1048         }
1049
1050         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1051                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1052
1053         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1054             pp_table->FanZeroRpmEnable)
1055                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1056
1057         if (!od_settings->overdrive8_capabilities)
1058                 hwmgr->od_enabled = false;
1059
1060         return 0;
1061 }
1062
1063 static int vega20_od8_set_feature_id(
1064                 struct pp_hwmgr *hwmgr)
1065 {
1066         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1067         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1068
1069         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1070                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1071                         OD8_GFXCLK_LIMITS;
1072                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1073                         OD8_GFXCLK_LIMITS;
1074         } else {
1075                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1076                         0;
1077                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1078                         0;
1079         }
1080
1081         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1082                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1083                         OD8_GFXCLK_CURVE;
1084                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1085                         OD8_GFXCLK_CURVE;
1086                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1087                         OD8_GFXCLK_CURVE;
1088                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1089                         OD8_GFXCLK_CURVE;
1090                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1091                         OD8_GFXCLK_CURVE;
1092                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1093                         OD8_GFXCLK_CURVE;
1094         } else {
1095                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1096                         0;
1097                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1098                         0;
1099                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1100                         0;
1101                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1102                         0;
1103                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1104                         0;
1105                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1106                         0;
1107         }
1108
1109         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1110                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1111         else
1112                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1113
1114         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1115                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1116         else
1117                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1118
1119         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1120                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1121                         OD8_ACOUSTIC_LIMIT_SCLK;
1122         else
1123                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1124                         0;
1125
1126         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1127                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1128                         OD8_FAN_SPEED_MIN;
1129         else
1130                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1131                         0;
1132
1133         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1134                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1135                         OD8_TEMPERATURE_FAN;
1136         else
1137                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1138                         0;
1139
1140         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1141                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1142                         OD8_TEMPERATURE_SYSTEM;
1143         else
1144                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1145                         0;
1146
1147         return 0;
1148 }
1149
1150 static int vega20_od8_get_gfx_clock_base_voltage(
1151                 struct pp_hwmgr *hwmgr,
1152                 uint32_t *voltage,
1153                 uint32_t freq)
1154 {
1155         int ret = 0;
1156
1157         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1158                         PPSMC_MSG_GetAVFSVoltageByDpm,
1159                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1160         PP_ASSERT_WITH_CODE(!ret,
1161                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1162                         return ret);
1163
1164         *voltage = smum_get_argument(hwmgr);
1165         *voltage = *voltage / VOLTAGE_SCALE;
1166
1167         return 0;
1168 }
1169
1170 static int vega20_od8_initialize_default_settings(
1171                 struct pp_hwmgr *hwmgr)
1172 {
1173         struct phm_ppt_v3_information *pptable_information =
1174                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1175         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1176         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1177         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1178         int i, ret = 0;
1179
1180         /* Set Feature Capabilities */
1181         vega20_od8_set_feature_capabilities(hwmgr);
1182
1183         /* Map FeatureID to individual settings */
1184         vega20_od8_set_feature_id(hwmgr);
1185
1186         /* Set default values */
1187         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1188         PP_ASSERT_WITH_CODE(!ret,
1189                         "Failed to export over drive table!",
1190                         return ret);
1191
1192         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1193                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1194                         od_table->GfxclkFmin;
1195                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1196                         od_table->GfxclkFmax;
1197         } else {
1198                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1199                         0;
1200                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1201                         0;
1202         }
1203
1204         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1205                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1206                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1207                         od_table->GfxclkFreq1;
1208
1209                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1210                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1211                         od_table->GfxclkFreq3;
1212
1213                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1214                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1215                         od_table->GfxclkFreq2;
1216
1217                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1218                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1219                                      od_table->GfxclkFreq1),
1220                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1221                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1222                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1223                         * VOLTAGE_SCALE;
1224
1225                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1226                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1227                                      od_table->GfxclkFreq2),
1228                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1229                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1230                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1231                         * VOLTAGE_SCALE;
1232
1233                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1234                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1235                                      od_table->GfxclkFreq3),
1236                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1237                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1238                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1239                         * VOLTAGE_SCALE;
1240         } else {
1241                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1242                         0;
1243                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1244                         0;
1245                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1246                         0;
1247                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1248                         0;
1249                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1250                         0;
1251                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1252                         0;
1253         }
1254
1255         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1256                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1257                         od_table->UclkFmax;
1258         else
1259                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1260                         0;
1261
1262         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1263                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1264                         od_table->OverDrivePct;
1265         else
1266                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1267                         0;
1268
1269         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1270                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1271                         od_table->FanMaximumRpm;
1272         else
1273                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1274                         0;
1275
1276         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1277                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1278                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1279         else
1280                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1281                         0;
1282
1283         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1284                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1285                         od_table->FanTargetTemperature;
1286         else
1287                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1288                         0;
1289
1290         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1291                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1292                         od_table->MaxOpTemp;
1293         else
1294                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1295                         0;
1296
1297         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1298                 if (od8_settings->od8_settings_array[i].feature_id) {
1299                         od8_settings->od8_settings_array[i].min_value =
1300                                 pptable_information->od_settings_min[i];
1301                         od8_settings->od8_settings_array[i].max_value =
1302                                 pptable_information->od_settings_max[i];
1303                         od8_settings->od8_settings_array[i].current_value =
1304                                 od8_settings->od8_settings_array[i].default_value;
1305                 } else {
1306                         od8_settings->od8_settings_array[i].min_value =
1307                                 0;
1308                         od8_settings->od8_settings_array[i].max_value =
1309                                 0;
1310                         od8_settings->od8_settings_array[i].current_value =
1311                                 0;
1312                 }
1313         }
1314
1315         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1316         PP_ASSERT_WITH_CODE(!ret,
1317                         "Failed to import over drive table!",
1318                         return ret);
1319
1320         return 0;
1321 }
1322
1323 static int vega20_od8_set_settings(
1324                 struct pp_hwmgr *hwmgr,
1325                 uint32_t index,
1326                 uint32_t value)
1327 {
1328         OverDriveTable_t od_table;
1329         int ret = 0;
1330         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1331         struct vega20_od8_single_setting *od8_settings =
1332                         data->od8_settings.od8_settings_array;
1333
1334         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1335         PP_ASSERT_WITH_CODE(!ret,
1336                         "Failed to export over drive table!",
1337                         return ret);
1338
1339         switch(index) {
1340         case OD8_SETTING_GFXCLK_FMIN:
1341                 od_table.GfxclkFmin = (uint16_t)value;
1342                 break;
1343         case OD8_SETTING_GFXCLK_FMAX:
1344                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1345                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1346                         return -EINVAL;
1347
1348                 od_table.GfxclkFmax = (uint16_t)value;
1349                 break;
1350         case OD8_SETTING_GFXCLK_FREQ1:
1351                 od_table.GfxclkFreq1 = (uint16_t)value;
1352                 break;
1353         case OD8_SETTING_GFXCLK_VOLTAGE1:
1354                 od_table.GfxclkVolt1 = (uint16_t)value;
1355                 break;
1356         case OD8_SETTING_GFXCLK_FREQ2:
1357                 od_table.GfxclkFreq2 = (uint16_t)value;
1358                 break;
1359         case OD8_SETTING_GFXCLK_VOLTAGE2:
1360                 od_table.GfxclkVolt2 = (uint16_t)value;
1361                 break;
1362         case OD8_SETTING_GFXCLK_FREQ3:
1363                 od_table.GfxclkFreq3 = (uint16_t)value;
1364                 break;
1365         case OD8_SETTING_GFXCLK_VOLTAGE3:
1366                 od_table.GfxclkVolt3 = (uint16_t)value;
1367                 break;
1368         case OD8_SETTING_UCLK_FMAX:
1369                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1370                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1371                         return -EINVAL;
1372                 od_table.UclkFmax = (uint16_t)value;
1373                 break;
1374         case OD8_SETTING_POWER_PERCENTAGE:
1375                 od_table.OverDrivePct = (int16_t)value;
1376                 break;
1377         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1378                 od_table.FanMaximumRpm = (uint16_t)value;
1379                 break;
1380         case OD8_SETTING_FAN_MIN_SPEED:
1381                 od_table.FanMinimumPwm = (uint16_t)value;
1382                 break;
1383         case OD8_SETTING_FAN_TARGET_TEMP:
1384                 od_table.FanTargetTemperature = (uint16_t)value;
1385                 break;
1386         case OD8_SETTING_OPERATING_TEMP_MAX:
1387                 od_table.MaxOpTemp = (uint16_t)value;
1388                 break;
1389         }
1390
1391         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1392         PP_ASSERT_WITH_CODE(!ret,
1393                         "Failed to import over drive table!",
1394                         return ret);
1395
1396         return 0;
1397 }
1398
1399 static int vega20_get_sclk_od(
1400                 struct pp_hwmgr *hwmgr)
1401 {
1402         struct vega20_hwmgr *data = hwmgr->backend;
1403         struct vega20_single_dpm_table *sclk_table =
1404                         &(data->dpm_table.gfx_table);
1405         struct vega20_single_dpm_table *golden_sclk_table =
1406                         &(data->golden_dpm_table.gfx_table);
1407         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1408         int golden_value = golden_sclk_table->dpm_levels
1409                         [golden_sclk_table->count - 1].value;
1410
1411         /* od percentage */
1412         value -= golden_value;
1413         value = DIV_ROUND_UP(value * 100, golden_value);
1414
1415         return value;
1416 }
1417
1418 static int vega20_set_sclk_od(
1419                 struct pp_hwmgr *hwmgr, uint32_t value)
1420 {
1421         struct vega20_hwmgr *data = hwmgr->backend;
1422         struct vega20_single_dpm_table *golden_sclk_table =
1423                         &(data->golden_dpm_table.gfx_table);
1424         uint32_t od_sclk;
1425         int ret = 0;
1426
1427         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1428         od_sclk /= 100;
1429         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1430
1431         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1432         PP_ASSERT_WITH_CODE(!ret,
1433                         "[SetSclkOD] failed to set od gfxclk!",
1434                         return ret);
1435
1436         /* retrieve updated gfxclk table */
1437         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1438         PP_ASSERT_WITH_CODE(!ret,
1439                         "[SetSclkOD] failed to refresh gfxclk table!",
1440                         return ret);
1441
1442         return 0;
1443 }
1444
1445 static int vega20_get_mclk_od(
1446                 struct pp_hwmgr *hwmgr)
1447 {
1448         struct vega20_hwmgr *data = hwmgr->backend;
1449         struct vega20_single_dpm_table *mclk_table =
1450                         &(data->dpm_table.mem_table);
1451         struct vega20_single_dpm_table *golden_mclk_table =
1452                         &(data->golden_dpm_table.mem_table);
1453         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1454         int golden_value = golden_mclk_table->dpm_levels
1455                         [golden_mclk_table->count - 1].value;
1456
1457         /* od percentage */
1458         value -= golden_value;
1459         value = DIV_ROUND_UP(value * 100, golden_value);
1460
1461         return value;
1462 }
1463
1464 static int vega20_set_mclk_od(
1465                 struct pp_hwmgr *hwmgr, uint32_t value)
1466 {
1467         struct vega20_hwmgr *data = hwmgr->backend;
1468         struct vega20_single_dpm_table *golden_mclk_table =
1469                         &(data->golden_dpm_table.mem_table);
1470         uint32_t od_mclk;
1471         int ret = 0;
1472
1473         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1474         od_mclk /= 100;
1475         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1476
1477         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1478         PP_ASSERT_WITH_CODE(!ret,
1479                         "[SetMclkOD] failed to set od memclk!",
1480                         return ret);
1481
1482         /* retrieve updated memclk table */
1483         ret = vega20_setup_memclk_dpm_table(hwmgr);
1484         PP_ASSERT_WITH_CODE(!ret,
1485                         "[SetMclkOD] failed to refresh memclk table!",
1486                         return ret);
1487
1488         return 0;
1489 }
1490
1491 static int vega20_populate_umdpstate_clocks(
1492                 struct pp_hwmgr *hwmgr)
1493 {
1494         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1495         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1496         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1497
1498         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1499         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1500
1501         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1502             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1503                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1504                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1505         }
1506
1507         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1508         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1509
1510         return 0;
1511 }
1512
1513 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1514                 PP_Clock *clock, PPCLK_e clock_select)
1515 {
1516         int ret = 0;
1517
1518         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1519                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1520                         (clock_select << 16))) == 0,
1521                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1522                         return ret);
1523         *clock = smum_get_argument(hwmgr);
1524
1525         /* if DC limit is zero, return AC limit */
1526         if (*clock == 0) {
1527                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1528                         PPSMC_MSG_GetMaxDpmFreq,
1529                         (clock_select << 16))) == 0,
1530                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1531                         return ret);
1532                 *clock = smum_get_argument(hwmgr);
1533         }
1534
1535         return 0;
1536 }
1537
1538 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1539 {
1540         struct vega20_hwmgr *data =
1541                 (struct vega20_hwmgr *)(hwmgr->backend);
1542         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1543                 &(data->max_sustainable_clocks);
1544         int ret = 0;
1545
1546         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1547         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1548         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1549         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1550         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1551         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1552
1553         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1554                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1555                                 &(max_sustainable_clocks->uclock),
1556                                 PPCLK_UCLK)) == 0,
1557                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1558                                 return ret);
1559
1560         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1561                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1562                                 &(max_sustainable_clocks->soc_clock),
1563                                 PPCLK_SOCCLK)) == 0,
1564                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1565                                 return ret);
1566
1567         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1568                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1569                                 &(max_sustainable_clocks->dcef_clock),
1570                                 PPCLK_DCEFCLK)) == 0,
1571                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1572                                 return ret);
1573                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1574                                 &(max_sustainable_clocks->display_clock),
1575                                 PPCLK_DISPCLK)) == 0,
1576                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1577                                 return ret);
1578                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1579                                 &(max_sustainable_clocks->phy_clock),
1580                                 PPCLK_PHYCLK)) == 0,
1581                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1582                                 return ret);
1583                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1584                                 &(max_sustainable_clocks->pixel_clock),
1585                                 PPCLK_PIXCLK)) == 0,
1586                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1587                                 return ret);
1588         }
1589
1590         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1591                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1592
1593         return 0;
1594 }
1595
1596 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1597 {
1598         int result;
1599
1600         result = smum_send_msg_to_smc(hwmgr,
1601                 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1602         PP_ASSERT_WITH_CODE(!result,
1603                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1604                         return result);
1605
1606         return 0;
1607 }
1608
1609 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1610 {
1611         struct vega20_hwmgr *data =
1612                 (struct vega20_hwmgr *)(hwmgr->backend);
1613
1614         data->uvd_power_gated = true;
1615         data->vce_power_gated = true;
1616
1617         if (data->smu_features[GNLD_DPM_UVD].enabled)
1618                 data->uvd_power_gated = false;
1619
1620         if (data->smu_features[GNLD_DPM_VCE].enabled)
1621                 data->vce_power_gated = false;
1622 }
1623
1624 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1625 {
1626         int result = 0;
1627
1628         smum_send_msg_to_smc_with_parameter(hwmgr,
1629                         PPSMC_MSG_NumOfDisplays, 0);
1630
1631         result = vega20_set_allowed_featuresmask(hwmgr);
1632         PP_ASSERT_WITH_CODE(!result,
1633                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1634                         return result);
1635
1636         result = vega20_init_smc_table(hwmgr);
1637         PP_ASSERT_WITH_CODE(!result,
1638                         "[EnableDPMTasks] Failed to initialize SMC table!",
1639                         return result);
1640
1641         result = vega20_run_btc(hwmgr);
1642         PP_ASSERT_WITH_CODE(!result,
1643                         "[EnableDPMTasks] Failed to run btc!",
1644                         return result);
1645
1646         result = vega20_run_btc_afll(hwmgr);
1647         PP_ASSERT_WITH_CODE(!result,
1648                         "[EnableDPMTasks] Failed to run btc afll!",
1649                         return result);
1650
1651         result = vega20_enable_all_smu_features(hwmgr);
1652         PP_ASSERT_WITH_CODE(!result,
1653                         "[EnableDPMTasks] Failed to enable all smu features!",
1654                         return result);
1655
1656         result = vega20_override_pcie_parameters(hwmgr);
1657         PP_ASSERT_WITH_CODE(!result,
1658                         "[EnableDPMTasks] Failed to override pcie parameters!",
1659                         return result);
1660
1661         result = vega20_notify_smc_display_change(hwmgr);
1662         PP_ASSERT_WITH_CODE(!result,
1663                         "[EnableDPMTasks] Failed to notify smc display change!",
1664                         return result);
1665
1666         result = vega20_send_clock_ratio(hwmgr);
1667         PP_ASSERT_WITH_CODE(!result,
1668                         "[EnableDPMTasks] Failed to send clock ratio!",
1669                         return result);
1670
1671         /* Initialize UVD/VCE powergating state */
1672         vega20_init_powergate_state(hwmgr);
1673
1674         result = vega20_setup_default_dpm_tables(hwmgr);
1675         PP_ASSERT_WITH_CODE(!result,
1676                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1677                         return result);
1678
1679         result = vega20_init_max_sustainable_clocks(hwmgr);
1680         PP_ASSERT_WITH_CODE(!result,
1681                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1682                         return result);
1683
1684         result = vega20_power_control_set_level(hwmgr);
1685         PP_ASSERT_WITH_CODE(!result,
1686                         "[EnableDPMTasks] Failed to power control set level!",
1687                         return result);
1688
1689         result = vega20_od8_initialize_default_settings(hwmgr);
1690         PP_ASSERT_WITH_CODE(!result,
1691                         "[EnableDPMTasks] Failed to initialize odn settings!",
1692                         return result);
1693
1694         result = vega20_populate_umdpstate_clocks(hwmgr);
1695         PP_ASSERT_WITH_CODE(!result,
1696                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1697                         return result);
1698
1699         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1700                         POWER_SOURCE_AC << 16);
1701         PP_ASSERT_WITH_CODE(!result,
1702                         "[GetPptLimit] get default PPT limit failed!",
1703                         return result);
1704         hwmgr->power_limit =
1705                 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1706
1707         return 0;
1708 }
1709
1710 static uint32_t vega20_find_lowest_dpm_level(
1711                 struct vega20_single_dpm_table *table)
1712 {
1713         uint32_t i;
1714
1715         for (i = 0; i < table->count; i++) {
1716                 if (table->dpm_levels[i].enabled)
1717                         break;
1718         }
1719         if (i >= table->count) {
1720                 i = 0;
1721                 table->dpm_levels[i].enabled = true;
1722         }
1723
1724         return i;
1725 }
1726
1727 static uint32_t vega20_find_highest_dpm_level(
1728                 struct vega20_single_dpm_table *table)
1729 {
1730         int i = 0;
1731
1732         PP_ASSERT_WITH_CODE(table != NULL,
1733                         "[FindHighestDPMLevel] DPM Table does not exist!",
1734                         return 0);
1735         PP_ASSERT_WITH_CODE(table->count > 0,
1736                         "[FindHighestDPMLevel] DPM Table has no entry!",
1737                         return 0);
1738         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1739                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1740                         return MAX_REGULAR_DPM_NUMBER - 1);
1741
1742         for (i = table->count - 1; i >= 0; i--) {
1743                 if (table->dpm_levels[i].enabled)
1744                         break;
1745         }
1746         if (i < 0) {
1747                 i = 0;
1748                 table->dpm_levels[i].enabled = true;
1749         }
1750
1751         return i;
1752 }
1753
1754 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1755 {
1756         struct vega20_hwmgr *data =
1757                         (struct vega20_hwmgr *)(hwmgr->backend);
1758         uint32_t min_freq;
1759         int ret = 0;
1760
1761         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1762            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1763                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1764                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1765                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1766                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1767                                         "Failed to set soft min gfxclk !",
1768                                         return ret);
1769         }
1770
1771         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1772            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1773                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1774                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1775                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1776                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1777                                         "Failed to set soft min memclk !",
1778                                         return ret);
1779         }
1780
1781         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1782            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1783                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1784
1785                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1786                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1787                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1788                                         "Failed to set soft min vclk!",
1789                                         return ret);
1790
1791                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1792
1793                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1794                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1795                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1796                                         "Failed to set soft min dclk!",
1797                                         return ret);
1798         }
1799
1800         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1801            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1802                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1803
1804                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1805                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1806                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1807                                         "Failed to set soft min eclk!",
1808                                         return ret);
1809         }
1810
1811         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1812            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1813                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1814
1815                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1816                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1817                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1818                                         "Failed to set soft min socclk!",
1819                                         return ret);
1820         }
1821
1822         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1823            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1824                 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1825
1826                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1827                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1828                                         (PPCLK_FCLK << 16) | (min_freq & 0xffff))),
1829                                         "Failed to set soft min fclk!",
1830                                         return ret);
1831         }
1832
1833         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1834            (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1835                 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1836
1837                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1838                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1839                                         (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
1840                                         "Failed to set hard min dcefclk!",
1841                                         return ret);
1842         }
1843
1844         return ret;
1845 }
1846
1847 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1848 {
1849         struct vega20_hwmgr *data =
1850                         (struct vega20_hwmgr *)(hwmgr->backend);
1851         uint32_t max_freq;
1852         int ret = 0;
1853
1854         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1855            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1856                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1857
1858                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1859                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1860                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1861                                         "Failed to set soft max gfxclk!",
1862                                         return ret);
1863         }
1864
1865         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1866            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1867                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1868
1869                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1870                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1871                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1872                                         "Failed to set soft max memclk!",
1873                                         return ret);
1874         }
1875
1876         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1877            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1878                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1879
1880                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1881                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1882                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1883                                         "Failed to set soft max vclk!",
1884                                         return ret);
1885
1886                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1887                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1888                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1889                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1890                                         "Failed to set soft max dclk!",
1891                                         return ret);
1892         }
1893
1894         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1895            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1896                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1897
1898                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1899                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1900                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1901                                         "Failed to set soft max eclk!",
1902                                         return ret);
1903         }
1904
1905         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1906            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1907                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1908
1909                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1910                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1911                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1912                                         "Failed to set soft max socclk!",
1913                                         return ret);
1914         }
1915
1916         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1917            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1918                 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1919
1920                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1921                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1922                                         (PPCLK_FCLK << 16) | (max_freq & 0xffff))),
1923                                         "Failed to set soft max fclk!",
1924                                         return ret);
1925         }
1926
1927         return ret;
1928 }
1929
1930 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1931 {
1932         struct vega20_hwmgr *data =
1933                         (struct vega20_hwmgr *)(hwmgr->backend);
1934         int ret = 0;
1935
1936         if (data->smu_features[GNLD_DPM_VCE].supported) {
1937                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1938                         if (enable)
1939                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1940                         else
1941                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1942                 }
1943
1944                 ret = vega20_enable_smc_features(hwmgr,
1945                                 enable,
1946                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1947                 PP_ASSERT_WITH_CODE(!ret,
1948                                 "Attempt to Enable/Disable DPM VCE Failed!",
1949                                 return ret);
1950                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1951         }
1952
1953         return 0;
1954 }
1955
1956 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1957                 uint32_t *clock,
1958                 PPCLK_e clock_select,
1959                 bool max)
1960 {
1961         int ret;
1962         *clock = 0;
1963
1964         if (max) {
1965                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1966                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1967                                 "[GetClockRanges] Failed to get max clock from SMC!",
1968                                 return ret);
1969                 *clock = smum_get_argument(hwmgr);
1970         } else {
1971                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1972                                 PPSMC_MSG_GetMinDpmFreq,
1973                                 (clock_select << 16))) == 0,
1974                                 "[GetClockRanges] Failed to get min clock from SMC!",
1975                                 return ret);
1976                 *clock = smum_get_argument(hwmgr);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1983 {
1984         struct vega20_hwmgr *data =
1985                         (struct vega20_hwmgr *)(hwmgr->backend);
1986         uint32_t gfx_clk;
1987         int ret = 0;
1988
1989         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1990                         "[GetSclks]: gfxclk dpm not enabled!\n",
1991                         return -EPERM);
1992
1993         if (low) {
1994                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1995                 PP_ASSERT_WITH_CODE(!ret,
1996                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1997                         return ret);
1998         } else {
1999                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2000                 PP_ASSERT_WITH_CODE(!ret,
2001                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2002                         return ret);
2003         }
2004
2005         return (gfx_clk * 100);
2006 }
2007
2008 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2009 {
2010         struct vega20_hwmgr *data =
2011                         (struct vega20_hwmgr *)(hwmgr->backend);
2012         uint32_t mem_clk;
2013         int ret = 0;
2014
2015         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2016                         "[MemMclks]: memclk dpm not enabled!\n",
2017                         return -EPERM);
2018
2019         if (low) {
2020                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2021                 PP_ASSERT_WITH_CODE(!ret,
2022                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
2023                         return ret);
2024         } else {
2025                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2026                 PP_ASSERT_WITH_CODE(!ret,
2027                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
2028                         return ret);
2029         }
2030
2031         return (mem_clk * 100);
2032 }
2033
2034 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
2035 {
2036         struct vega20_hwmgr *data =
2037                         (struct vega20_hwmgr *)(hwmgr->backend);
2038         int ret = 0;
2039
2040         if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
2041                 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
2042                                 TABLE_SMU_METRICS, true);
2043                 if (ret) {
2044                         pr_info("Failed to export SMU metrics table!\n");
2045                         return ret;
2046                 }
2047                 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
2048                 data->metrics_time = jiffies;
2049         } else
2050                 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2051
2052         return ret;
2053 }
2054
2055 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
2056                 uint32_t *query)
2057 {
2058         int ret = 0;
2059         SmuMetrics_t metrics_table;
2060
2061         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2062         if (ret)
2063                 return ret;
2064
2065         *query = metrics_table.CurrSocketPower << 8;
2066
2067         return ret;
2068 }
2069
2070 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2071                 PPCLK_e clk_id, uint32_t *clk_freq)
2072 {
2073         int ret = 0;
2074
2075         *clk_freq = 0;
2076
2077         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2078                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
2079                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2080                         return ret);
2081         *clk_freq = smum_get_argument(hwmgr);
2082
2083         *clk_freq = *clk_freq * 100;
2084
2085         return 0;
2086 }
2087
2088 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2089                 uint32_t *activity_percent)
2090 {
2091         int ret = 0;
2092         SmuMetrics_t metrics_table;
2093
2094         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2095         if (ret)
2096                 return ret;
2097
2098         *activity_percent = metrics_table.AverageGfxActivity;
2099
2100         return ret;
2101 }
2102
2103 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2104                               void *value, int *size)
2105 {
2106         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2107         struct amdgpu_device *adev = hwmgr->adev;
2108         SmuMetrics_t metrics_table;
2109         uint32_t val_vid;
2110         int ret = 0;
2111
2112         switch (idx) {
2113         case AMDGPU_PP_SENSOR_GFX_SCLK:
2114                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2115                 if (ret)
2116                         return ret;
2117
2118                 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2119                 *size = 4;
2120                 break;
2121         case AMDGPU_PP_SENSOR_GFX_MCLK:
2122                 ret = vega20_get_current_clk_freq(hwmgr,
2123                                 PPCLK_UCLK,
2124                                 (uint32_t *)value);
2125                 if (!ret)
2126                         *size = 4;
2127                 break;
2128         case AMDGPU_PP_SENSOR_GPU_LOAD:
2129                 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
2130                 if (!ret)
2131                         *size = 4;
2132                 break;
2133         case AMDGPU_PP_SENSOR_GPU_TEMP:
2134                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2135                 *size = 4;
2136                 break;
2137         case AMDGPU_PP_SENSOR_UVD_POWER:
2138                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2139                 *size = 4;
2140                 break;
2141         case AMDGPU_PP_SENSOR_VCE_POWER:
2142                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2143                 *size = 4;
2144                 break;
2145         case AMDGPU_PP_SENSOR_GPU_POWER:
2146                 *size = 16;
2147                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2148                 break;
2149         case AMDGPU_PP_SENSOR_VDDGFX:
2150                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2151                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2152                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2153                 *((uint32_t *)value) =
2154                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
2155                 break;
2156         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2157                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2158                 if (!ret)
2159                         *size = 8;
2160                 break;
2161         default:
2162                 ret = -EINVAL;
2163                 break;
2164         }
2165         return ret;
2166 }
2167
2168 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2169                 struct pp_display_clock_request *clock_req)
2170 {
2171         int result = 0;
2172         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2173         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2174         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2175         PPCLK_e clk_select = 0;
2176         uint32_t clk_request = 0;
2177
2178         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2179                 switch (clk_type) {
2180                 case amd_pp_dcef_clock:
2181                         clk_select = PPCLK_DCEFCLK;
2182                         break;
2183                 case amd_pp_disp_clock:
2184                         clk_select = PPCLK_DISPCLK;
2185                         break;
2186                 case amd_pp_pixel_clock:
2187                         clk_select = PPCLK_PIXCLK;
2188                         break;
2189                 case amd_pp_phy_clock:
2190                         clk_select = PPCLK_PHYCLK;
2191                         break;
2192                 default:
2193                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2194                         result = -EINVAL;
2195                         break;
2196                 }
2197
2198                 if (!result) {
2199                         clk_request = (clk_select << 16) | clk_freq;
2200                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2201                                         PPSMC_MSG_SetHardMinByFreq,
2202                                         clk_request);
2203                 }
2204         }
2205
2206         return result;
2207 }
2208
2209 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2210                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2211                                 PHM_PerformanceLevel *level)
2212 {
2213         return 0;
2214 }
2215
2216 static int vega20_notify_smc_display_config_after_ps_adjustment(
2217                 struct pp_hwmgr *hwmgr)
2218 {
2219         struct vega20_hwmgr *data =
2220                         (struct vega20_hwmgr *)(hwmgr->backend);
2221         struct vega20_single_dpm_table *dpm_table =
2222                         &data->dpm_table.mem_table;
2223         struct PP_Clocks min_clocks = {0};
2224         struct pp_display_clock_request clock_req;
2225         int ret = 0;
2226
2227         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2228         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2229         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2230
2231         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2232                 clock_req.clock_type = amd_pp_dcef_clock;
2233                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2234                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2235                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2236                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2237                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2238                                         min_clocks.dcefClockInSR / 100)) == 0,
2239                                         "Attempt to set divider for DCEFCLK Failed!",
2240                                         return ret);
2241                 } else {
2242                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2243                 }
2244         }
2245
2246         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2247                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2248                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2249                                 PPSMC_MSG_SetHardMinByFreq,
2250                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2251                                 "[SetHardMinFreq] Set hard min uclk failed!",
2252                                 return ret);
2253         }
2254
2255         return 0;
2256 }
2257
2258 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2259 {
2260         struct vega20_hwmgr *data =
2261                         (struct vega20_hwmgr *)(hwmgr->backend);
2262         uint32_t soft_level;
2263         int ret = 0;
2264
2265         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2266
2267         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2268                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2269                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2270
2271         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2272
2273         data->dpm_table.mem_table.dpm_state.soft_min_level =
2274                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2275                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2276
2277         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2278
2279         data->dpm_table.soc_table.dpm_state.soft_min_level =
2280                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2281                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2282
2283         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2284         PP_ASSERT_WITH_CODE(!ret,
2285                         "Failed to upload boot level to highest!",
2286                         return ret);
2287
2288         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2289         PP_ASSERT_WITH_CODE(!ret,
2290                         "Failed to upload dpm max level to highest!",
2291                         return ret);
2292
2293         return 0;
2294 }
2295
2296 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2297 {
2298         struct vega20_hwmgr *data =
2299                         (struct vega20_hwmgr *)(hwmgr->backend);
2300         uint32_t soft_level;
2301         int ret = 0;
2302
2303         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2304
2305         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2306                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2307                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2308
2309         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2310
2311         data->dpm_table.mem_table.dpm_state.soft_min_level =
2312                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2313                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2314
2315         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2316
2317         data->dpm_table.soc_table.dpm_state.soft_min_level =
2318                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2319                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2320
2321         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2322         PP_ASSERT_WITH_CODE(!ret,
2323                         "Failed to upload boot level to highest!",
2324                         return ret);
2325
2326         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2327         PP_ASSERT_WITH_CODE(!ret,
2328                         "Failed to upload dpm max level to highest!",
2329                         return ret);
2330
2331         return 0;
2332
2333 }
2334
2335 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2336 {
2337         int ret = 0;
2338
2339         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2340         PP_ASSERT_WITH_CODE(!ret,
2341                         "Failed to upload DPM Bootup Levels!",
2342                         return ret);
2343
2344         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2345         PP_ASSERT_WITH_CODE(!ret,
2346                         "Failed to upload DPM Max Levels!",
2347                         return ret);
2348
2349         return 0;
2350 }
2351
2352 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2353                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2354 {
2355         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2356         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2357         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2358         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2359
2360         *sclk_mask = 0;
2361         *mclk_mask = 0;
2362         *soc_mask  = 0;
2363
2364         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2365             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2366             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2367                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2368                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2369                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2370         }
2371
2372         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2373                 *sclk_mask = 0;
2374         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2375                 *mclk_mask = 0;
2376         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2377                 *sclk_mask = gfx_dpm_table->count - 1;
2378                 *mclk_mask = mem_dpm_table->count - 1;
2379                 *soc_mask  = soc_dpm_table->count - 1;
2380         }
2381
2382         return 0;
2383 }
2384
2385 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2386                 enum pp_clock_type type, uint32_t mask)
2387 {
2388         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2389         uint32_t soft_min_level, soft_max_level, hard_min_level;
2390         int ret = 0;
2391
2392         switch (type) {
2393         case PP_SCLK:
2394                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2395                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2396
2397                 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2398                         pr_err("Clock level specified %d is over max allowed %d\n",
2399                                         soft_max_level,
2400                                         data->dpm_table.gfx_table.count - 1);
2401                         return -EINVAL;
2402                 }
2403
2404                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2405                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2406                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2407                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2408
2409                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2410                 PP_ASSERT_WITH_CODE(!ret,
2411                         "Failed to upload boot level to lowest!",
2412                         return ret);
2413
2414                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2415                 PP_ASSERT_WITH_CODE(!ret,
2416                         "Failed to upload dpm max level to highest!",
2417                         return ret);
2418                 break;
2419
2420         case PP_MCLK:
2421                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2422                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2423
2424                 if (soft_max_level >= data->dpm_table.mem_table.count) {
2425                         pr_err("Clock level specified %d is over max allowed %d\n",
2426                                         soft_max_level,
2427                                         data->dpm_table.mem_table.count - 1);
2428                         return -EINVAL;
2429                 }
2430
2431                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2432                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2433                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2434                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2435
2436                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2437                 PP_ASSERT_WITH_CODE(!ret,
2438                         "Failed to upload boot level to lowest!",
2439                         return ret);
2440
2441                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2442                 PP_ASSERT_WITH_CODE(!ret,
2443                         "Failed to upload dpm max level to highest!",
2444                         return ret);
2445
2446                 break;
2447
2448         case PP_SOCCLK:
2449                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2450                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2451
2452                 if (soft_max_level >= data->dpm_table.soc_table.count) {
2453                         pr_err("Clock level specified %d is over max allowed %d\n",
2454                                         soft_max_level,
2455                                         data->dpm_table.soc_table.count - 1);
2456                         return -EINVAL;
2457                 }
2458
2459                 data->dpm_table.soc_table.dpm_state.soft_min_level =
2460                         data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2461                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2462                         data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2463
2464                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2465                 PP_ASSERT_WITH_CODE(!ret,
2466                         "Failed to upload boot level to lowest!",
2467                         return ret);
2468
2469                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2470                 PP_ASSERT_WITH_CODE(!ret,
2471                         "Failed to upload dpm max level to highest!",
2472                         return ret);
2473
2474                 break;
2475
2476         case PP_FCLK:
2477                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2478                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2479
2480                 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2481                         pr_err("Clock level specified %d is over max allowed %d\n",
2482                                         soft_max_level,
2483                                         data->dpm_table.fclk_table.count - 1);
2484                         return -EINVAL;
2485                 }
2486
2487                 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2488                         data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2489                 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2490                         data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2491
2492                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2493                 PP_ASSERT_WITH_CODE(!ret,
2494                         "Failed to upload boot level to lowest!",
2495                         return ret);
2496
2497                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2498                 PP_ASSERT_WITH_CODE(!ret,
2499                         "Failed to upload dpm max level to highest!",
2500                         return ret);
2501
2502                 break;
2503
2504         case PP_DCEFCLK:
2505                 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2506
2507                 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2508                         pr_err("Clock level specified %d is over max allowed %d\n",
2509                                         hard_min_level,
2510                                         data->dpm_table.dcef_table.count - 1);
2511                         return -EINVAL;
2512                 }
2513
2514                 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2515                         data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2516
2517                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2518                 PP_ASSERT_WITH_CODE(!ret,
2519                         "Failed to upload boot level to lowest!",
2520                         return ret);
2521
2522                 //TODO: Setting DCEFCLK max dpm level is not supported
2523
2524                 break;
2525
2526         case PP_PCIE:
2527                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2528                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2529                 if (soft_min_level >= NUM_LINK_LEVELS ||
2530                     soft_max_level >= NUM_LINK_LEVELS)
2531                         return -EINVAL;
2532
2533                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2534                         PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2535                 PP_ASSERT_WITH_CODE(!ret,
2536                         "Failed to set min link dpm level!",
2537                         return ret);
2538
2539                 break;
2540
2541         default:
2542                 break;
2543         }
2544
2545         return 0;
2546 }
2547
2548 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2549                                 enum amd_dpm_forced_level level)
2550 {
2551         int ret = 0;
2552         uint32_t sclk_mask, mclk_mask, soc_mask;
2553
2554         switch (level) {
2555         case AMD_DPM_FORCED_LEVEL_HIGH:
2556                 ret = vega20_force_dpm_highest(hwmgr);
2557                 break;
2558
2559         case AMD_DPM_FORCED_LEVEL_LOW:
2560                 ret = vega20_force_dpm_lowest(hwmgr);
2561                 break;
2562
2563         case AMD_DPM_FORCED_LEVEL_AUTO:
2564                 ret = vega20_unforce_dpm_levels(hwmgr);
2565                 break;
2566
2567         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2568         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2569         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2570         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2571                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2572                 if (ret)
2573                         return ret;
2574                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2575                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2576                 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2577                 break;
2578
2579         case AMD_DPM_FORCED_LEVEL_MANUAL:
2580         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2581         default:
2582                 break;
2583         }
2584
2585         return ret;
2586 }
2587
2588 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2589 {
2590         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2591
2592         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2593                 return AMD_FAN_CTRL_MANUAL;
2594         else
2595                 return AMD_FAN_CTRL_AUTO;
2596 }
2597
2598 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2599 {
2600         switch (mode) {
2601         case AMD_FAN_CTRL_NONE:
2602                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2603                 break;
2604         case AMD_FAN_CTRL_MANUAL:
2605                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2606                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2607                 break;
2608         case AMD_FAN_CTRL_AUTO:
2609                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2610                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2611                 break;
2612         default:
2613                 break;
2614         }
2615 }
2616
2617 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2618                 struct amd_pp_simple_clock_info *info)
2619 {
2620 #if 0
2621         struct phm_ppt_v2_information *table_info =
2622                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2623         struct phm_clock_and_voltage_limits *max_limits =
2624                         &table_info->max_clock_voltage_on_ac;
2625
2626         info->engine_max_clock = max_limits->sclk;
2627         info->memory_max_clock = max_limits->mclk;
2628 #endif
2629         return 0;
2630 }
2631
2632
2633 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2634                 struct pp_clock_levels_with_latency *clocks)
2635 {
2636         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2637         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2638         int i, count;
2639
2640         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2641                 return -1;
2642
2643         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2644         clocks->num_levels = count;
2645
2646         for (i = 0; i < count; i++) {
2647                 clocks->data[i].clocks_in_khz =
2648                         dpm_table->dpm_levels[i].value * 1000;
2649                 clocks->data[i].latency_in_us = 0;
2650         }
2651
2652         return 0;
2653 }
2654
2655 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2656                 uint32_t clock)
2657 {
2658         return 25;
2659 }
2660
2661 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2662                 struct pp_clock_levels_with_latency *clocks)
2663 {
2664         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2665         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2666         int i, count;
2667
2668         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2669                 return -1;
2670
2671         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2672         clocks->num_levels = data->mclk_latency_table.count = count;
2673
2674         for (i = 0; i < count; i++) {
2675                 clocks->data[i].clocks_in_khz =
2676                         data->mclk_latency_table.entries[i].frequency =
2677                         dpm_table->dpm_levels[i].value * 1000;
2678                 clocks->data[i].latency_in_us =
2679                         data->mclk_latency_table.entries[i].latency =
2680                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2687                 struct pp_clock_levels_with_latency *clocks)
2688 {
2689         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2690         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2691         int i, count;
2692
2693         if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2694                 return -1;
2695
2696         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2697         clocks->num_levels = count;
2698
2699         for (i = 0; i < count; i++) {
2700                 clocks->data[i].clocks_in_khz =
2701                         dpm_table->dpm_levels[i].value * 1000;
2702                 clocks->data[i].latency_in_us = 0;
2703         }
2704
2705         return 0;
2706 }
2707
2708 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2709                 struct pp_clock_levels_with_latency *clocks)
2710 {
2711         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2712         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2713         int i, count;
2714
2715         if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2716                 return -1;
2717
2718         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2719         clocks->num_levels = count;
2720
2721         for (i = 0; i < count; i++) {
2722                 clocks->data[i].clocks_in_khz =
2723                         dpm_table->dpm_levels[i].value * 1000;
2724                 clocks->data[i].latency_in_us = 0;
2725         }
2726
2727         return 0;
2728
2729 }
2730
2731 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2732                 enum amd_pp_clock_type type,
2733                 struct pp_clock_levels_with_latency *clocks)
2734 {
2735         int ret;
2736
2737         switch (type) {
2738         case amd_pp_sys_clock:
2739                 ret = vega20_get_sclks(hwmgr, clocks);
2740                 break;
2741         case amd_pp_mem_clock:
2742                 ret = vega20_get_memclocks(hwmgr, clocks);
2743                 break;
2744         case amd_pp_dcef_clock:
2745                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2746                 break;
2747         case amd_pp_soc_clock:
2748                 ret = vega20_get_socclocks(hwmgr, clocks);
2749                 break;
2750         default:
2751                 return -EINVAL;
2752         }
2753
2754         return ret;
2755 }
2756
2757 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2758                 enum amd_pp_clock_type type,
2759                 struct pp_clock_levels_with_voltage *clocks)
2760 {
2761         clocks->num_levels = 0;
2762
2763         return 0;
2764 }
2765
2766 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2767                                                    void *clock_ranges)
2768 {
2769         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2770         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2771         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2772
2773         if (!data->registry_data.disable_water_mark &&
2774             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2775             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2776                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2777                 data->water_marks_bitmap |= WaterMarksExist;
2778                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2779         }
2780
2781         return 0;
2782 }
2783
2784 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2785                                         enum PP_OD_DPM_TABLE_COMMAND type,
2786                                         long *input, uint32_t size)
2787 {
2788         struct vega20_hwmgr *data =
2789                         (struct vega20_hwmgr *)(hwmgr->backend);
2790         struct vega20_od8_single_setting *od8_settings =
2791                         data->od8_settings.od8_settings_array;
2792         OverDriveTable_t *od_table =
2793                         &(data->smc_state_table.overdrive_table);
2794         int32_t input_index, input_clk, input_vol, i;
2795         int od8_id;
2796         int ret;
2797
2798         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2799                                 return -EINVAL);
2800
2801         switch (type) {
2802         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2803                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2804                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2805                         pr_info("Sclk min/max frequency overdrive not supported\n");
2806                         return -EOPNOTSUPP;
2807                 }
2808
2809                 for (i = 0; i < size; i += 2) {
2810                         if (i + 2 > size) {
2811                                 pr_info("invalid number of input parameters %d\n",
2812                                         size);
2813                                 return -EINVAL;
2814                         }
2815
2816                         input_index = input[i];
2817                         input_clk = input[i + 1];
2818
2819                         if (input_index != 0 && input_index != 1) {
2820                                 pr_info("Invalid index %d\n", input_index);
2821                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2822                                 return -EINVAL;
2823                         }
2824
2825                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2826                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2827                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2828                                         input_clk,
2829                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2830                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2831                                 return -EINVAL;
2832                         }
2833
2834                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2835                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2836                                 data->gfxclk_overdrive = true;
2837
2838                         if (input_index == 0)
2839                                 od_table->GfxclkFmin = input_clk;
2840                         else
2841                                 od_table->GfxclkFmax = input_clk;
2842                 }
2843
2844                 break;
2845
2846         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2847                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2848                         pr_info("Mclk max frequency overdrive not supported\n");
2849                         return -EOPNOTSUPP;
2850                 }
2851
2852                 for (i = 0; i < size; i += 2) {
2853                         if (i + 2 > size) {
2854                                 pr_info("invalid number of input parameters %d\n",
2855                                         size);
2856                                 return -EINVAL;
2857                         }
2858
2859                         input_index = input[i];
2860                         input_clk = input[i + 1];
2861
2862                         if (input_index != 1) {
2863                                 pr_info("Invalid index %d\n", input_index);
2864                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2865                                 return -EINVAL;
2866                         }
2867
2868                         if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
2869                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2870                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2871                                         input_clk,
2872                                         od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
2873                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2874                                 return -EINVAL;
2875                         }
2876
2877                         if (input_index == 1 && od_table->UclkFmax != input_clk)
2878                                 data->memclk_overdrive = true;
2879
2880                         od_table->UclkFmax = input_clk;
2881                 }
2882
2883                 break;
2884
2885         case PP_OD_EDIT_VDDC_CURVE:
2886                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2887                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2888                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2889                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2890                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2891                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2892                         pr_info("Voltage curve calibrate not supported\n");
2893                         return -EOPNOTSUPP;
2894                 }
2895
2896                 for (i = 0; i < size; i += 3) {
2897                         if (i + 3 > size) {
2898                                 pr_info("invalid number of input parameters %d\n",
2899                                         size);
2900                                 return -EINVAL;
2901                         }
2902
2903                         input_index = input[i];
2904                         input_clk = input[i + 1];
2905                         input_vol = input[i + 2];
2906
2907                         if (input_index > 2) {
2908                                 pr_info("Setting for point %d is not supported\n",
2909                                                 input_index + 1);
2910                                 pr_info("Three supported points index by 0, 1, 2\n");
2911                                 return -EINVAL;
2912                         }
2913
2914                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2915                         if (input_clk < od8_settings[od8_id].min_value ||
2916                             input_clk > od8_settings[od8_id].max_value) {
2917                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2918                                         input_clk,
2919                                         od8_settings[od8_id].min_value,
2920                                         od8_settings[od8_id].max_value);
2921                                 return -EINVAL;
2922                         }
2923
2924                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2925                         if (input_vol < od8_settings[od8_id].min_value ||
2926                             input_vol > od8_settings[od8_id].max_value) {
2927                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2928                                         input_vol,
2929                                         od8_settings[od8_id].min_value,
2930                                         od8_settings[od8_id].max_value);
2931                                 return -EINVAL;
2932                         }
2933
2934                         switch (input_index) {
2935                         case 0:
2936                                 od_table->GfxclkFreq1 = input_clk;
2937                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2938                                 break;
2939                         case 1:
2940                                 od_table->GfxclkFreq2 = input_clk;
2941                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2942                                 break;
2943                         case 2:
2944                                 od_table->GfxclkFreq3 = input_clk;
2945                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2946                                 break;
2947                         }
2948                 }
2949                 break;
2950
2951         case PP_OD_RESTORE_DEFAULT_TABLE:
2952                 data->gfxclk_overdrive = false;
2953                 data->memclk_overdrive = false;
2954
2955                 ret = smum_smc_table_manager(hwmgr,
2956                                              (uint8_t *)od_table,
2957                                              TABLE_OVERDRIVE, true);
2958                 PP_ASSERT_WITH_CODE(!ret,
2959                                 "Failed to export overdrive table!",
2960                                 return ret);
2961                 break;
2962
2963         case PP_OD_COMMIT_DPM_TABLE:
2964                 ret = smum_smc_table_manager(hwmgr,
2965                                              (uint8_t *)od_table,
2966                                              TABLE_OVERDRIVE, false);
2967                 PP_ASSERT_WITH_CODE(!ret,
2968                                 "Failed to import overdrive table!",
2969                                 return ret);
2970
2971                 /* retrieve updated gfxclk table */
2972                 if (data->gfxclk_overdrive) {
2973                         data->gfxclk_overdrive = false;
2974
2975                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2976                         if (ret)
2977                                 return ret;
2978                 }
2979
2980                 /* retrieve updated memclk table */
2981                 if (data->memclk_overdrive) {
2982                         data->memclk_overdrive = false;
2983
2984                         ret = vega20_setup_memclk_dpm_table(hwmgr);
2985                         if (ret)
2986                                 return ret;
2987                 }
2988                 break;
2989
2990         default:
2991                 return -EINVAL;
2992         }
2993
2994         return 0;
2995 }
2996
2997 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2998 {
2999         static const char *ppfeature_name[] = {
3000                                 "DPM_PREFETCHER",
3001                                 "GFXCLK_DPM",
3002                                 "UCLK_DPM",
3003                                 "SOCCLK_DPM",
3004                                 "UVD_DPM",
3005                                 "VCE_DPM",
3006                                 "ULV",
3007                                 "MP0CLK_DPM",
3008                                 "LINK_DPM",
3009                                 "DCEFCLK_DPM",
3010                                 "GFXCLK_DS",
3011                                 "SOCCLK_DS",
3012                                 "LCLK_DS",
3013                                 "PPT",
3014                                 "TDC",
3015                                 "THERMAL",
3016                                 "GFX_PER_CU_CG",
3017                                 "RM",
3018                                 "DCEFCLK_DS",
3019                                 "ACDC",
3020                                 "VR0HOT",
3021                                 "VR1HOT",
3022                                 "FW_CTF",
3023                                 "LED_DISPLAY",
3024                                 "FAN_CONTROL",
3025                                 "GFX_EDC",
3026                                 "GFXOFF",
3027                                 "CG",
3028                                 "FCLK_DPM",
3029                                 "FCLK_DS",
3030                                 "MP1CLK_DS",
3031                                 "MP0CLK_DS",
3032                                 "XGMI"};
3033         static const char *output_title[] = {
3034                                 "FEATURES",
3035                                 "BITMASK",
3036                                 "ENABLEMENT"};
3037         uint64_t features_enabled;
3038         int i;
3039         int ret = 0;
3040         int size = 0;
3041
3042         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3043         PP_ASSERT_WITH_CODE(!ret,
3044                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3045                         return ret);
3046
3047         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3048         size += sprintf(buf + size, "%-19s %-22s %s\n",
3049                                 output_title[0],
3050                                 output_title[1],
3051                                 output_title[2]);
3052         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3053                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
3054                                         ppfeature_name[i],
3055                                         1ULL << i,
3056                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
3057         }
3058
3059         return size;
3060 }
3061
3062 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3063 {
3064         uint64_t features_enabled;
3065         uint64_t features_to_enable;
3066         uint64_t features_to_disable;
3067         int ret = 0;
3068
3069         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3070                 return -EINVAL;
3071
3072         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3073         if (ret)
3074                 return ret;
3075
3076         features_to_disable =
3077                 features_enabled & ~new_ppfeature_masks;
3078         features_to_enable =
3079                 ~features_enabled & new_ppfeature_masks;
3080
3081         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3082         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3083
3084         if (features_to_disable) {
3085                 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3086                 if (ret)
3087                         return ret;
3088         }
3089
3090         if (features_to_enable) {
3091                 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3092                 if (ret)
3093                         return ret;
3094         }
3095
3096         return 0;
3097 }
3098
3099 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3100                 enum pp_clock_type type, char *buf)
3101 {
3102         struct vega20_hwmgr *data =
3103                         (struct vega20_hwmgr *)(hwmgr->backend);
3104         struct vega20_od8_single_setting *od8_settings =
3105                         data->od8_settings.od8_settings_array;
3106         OverDriveTable_t *od_table =
3107                         &(data->smc_state_table.overdrive_table);
3108         struct phm_ppt_v3_information *pptable_information =
3109                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3110         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
3111         struct amdgpu_device *adev = hwmgr->adev;
3112         struct pp_clock_levels_with_latency clocks;
3113         struct vega20_single_dpm_table *fclk_dpm_table =
3114                         &(data->dpm_table.fclk_table);
3115         int i, now, size = 0;
3116         int ret = 0;
3117         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3118
3119         switch (type) {
3120         case PP_SCLK:
3121                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3122                 PP_ASSERT_WITH_CODE(!ret,
3123                                 "Attempt to get current gfx clk Failed!",
3124                                 return ret);
3125
3126                 if (vega20_get_sclks(hwmgr, &clocks)) {
3127                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3128                                 now / 100);
3129                         break;
3130                 }
3131
3132                 for (i = 0; i < clocks.num_levels; i++)
3133                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3134                                 i, clocks.data[i].clocks_in_khz / 1000,
3135                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3136                 break;
3137
3138         case PP_MCLK:
3139                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3140                 PP_ASSERT_WITH_CODE(!ret,
3141                                 "Attempt to get current mclk freq Failed!",
3142                                 return ret);
3143
3144                 if (vega20_get_memclocks(hwmgr, &clocks)) {
3145                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3146                                 now / 100);
3147                         break;
3148                 }
3149
3150                 for (i = 0; i < clocks.num_levels; i++)
3151                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3152                                 i, clocks.data[i].clocks_in_khz / 1000,
3153                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3154                 break;
3155
3156         case PP_SOCCLK:
3157                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3158                 PP_ASSERT_WITH_CODE(!ret,
3159                                 "Attempt to get current socclk freq Failed!",
3160                                 return ret);
3161
3162                 if (vega20_get_socclocks(hwmgr, &clocks)) {
3163                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3164                                 now / 100);
3165                         break;
3166                 }
3167
3168                 for (i = 0; i < clocks.num_levels; i++)
3169                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3170                                 i, clocks.data[i].clocks_in_khz / 1000,
3171                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3172                 break;
3173
3174         case PP_FCLK:
3175                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3176                 PP_ASSERT_WITH_CODE(!ret,
3177                                 "Attempt to get current fclk freq Failed!",
3178                                 return ret);
3179
3180                 for (i = 0; i < fclk_dpm_table->count; i++)
3181                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3182                                 i, fclk_dpm_table->dpm_levels[i].value,
3183                                 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3184                 break;
3185
3186         case PP_DCEFCLK:
3187                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3188                 PP_ASSERT_WITH_CODE(!ret,
3189                                 "Attempt to get current dcefclk freq Failed!",
3190                                 return ret);
3191
3192                 if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3193                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3194                                 now / 100);
3195                         break;
3196                 }
3197
3198                 for (i = 0; i < clocks.num_levels; i++)
3199                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3200                                 i, clocks.data[i].clocks_in_khz / 1000,
3201                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3202                 break;
3203
3204         case PP_PCIE:
3205                 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3206                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3207                             >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3208                 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3209                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3210                             >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3211                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3212                         if (i == 1 && data->pcie_parameters_override) {
3213                                 gen_speed = data->pcie_gen_level1;
3214                                 lane_width = data->pcie_width_level1;
3215                         } else {
3216                                 gen_speed = pptable->PcieGenSpeed[i];
3217                                 lane_width = pptable->PcieLaneCount[i];
3218                         }
3219                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3220                                         (gen_speed == 0) ? "2.5GT/s," :
3221                                         (gen_speed == 1) ? "5.0GT/s," :
3222                                         (gen_speed == 2) ? "8.0GT/s," :
3223                                         (gen_speed == 3) ? "16.0GT/s," : "",
3224                                         (lane_width == 1) ? "x1" :
3225                                         (lane_width == 2) ? "x2" :
3226                                         (lane_width == 3) ? "x4" :
3227                                         (lane_width == 4) ? "x8" :
3228                                         (lane_width == 5) ? "x12" :
3229                                         (lane_width == 6) ? "x16" : "",
3230                                         pptable->LclkFreq[i],
3231                                         (current_gen_speed == gen_speed) &&
3232                                         (current_lane_width == lane_width) ?
3233                                         "*" : "");
3234                 }
3235                 break;
3236
3237         case OD_SCLK:
3238                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3239                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3240                         size = sprintf(buf, "%s:\n", "OD_SCLK");
3241                         size += sprintf(buf + size, "0: %10uMhz\n",
3242                                 od_table->GfxclkFmin);
3243                         size += sprintf(buf + size, "1: %10uMhz\n",
3244                                 od_table->GfxclkFmax);
3245                 }
3246                 break;
3247
3248         case OD_MCLK:
3249                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3250                         size = sprintf(buf, "%s:\n", "OD_MCLK");
3251                         size += sprintf(buf + size, "1: %10uMhz\n",
3252                                 od_table->UclkFmax);
3253                 }
3254
3255                 break;
3256
3257         case OD_VDDC_CURVE:
3258                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3259                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3260                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3261                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3262                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3263                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3264                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
3265                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3266                                 od_table->GfxclkFreq1,
3267                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3268                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3269                                 od_table->GfxclkFreq2,
3270                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3271                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3272                                 od_table->GfxclkFreq3,
3273                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3274                 }
3275
3276                 break;
3277
3278         case OD_RANGE:
3279                 size = sprintf(buf, "%s:\n", "OD_RANGE");
3280
3281                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3282                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3283                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3284                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3285                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3286                 }
3287
3288                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3289                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3290                                 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3291                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3292                 }
3293
3294                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3295                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3296                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3297                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3298                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3299                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3300                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3301                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3302                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3303                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3304                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3305                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3306                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3307                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3308                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3309                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3310                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3311                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3312                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3313                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3314                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3315                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3316                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3317                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3318                 }
3319
3320                 break;
3321         default:
3322                 break;
3323         }
3324         return size;
3325 }
3326
3327 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3328                 struct vega20_single_dpm_table *dpm_table)
3329 {
3330         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3331         int ret = 0;
3332
3333         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3334                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3335                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3336                                 return -EINVAL);
3337                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3338                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3339                                 return -EINVAL);
3340
3341                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3342                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3343                                 PPSMC_MSG_SetHardMinByFreq,
3344                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
3345                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3346                                 return ret);
3347         }
3348
3349         return ret;
3350 }
3351
3352 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3353 {
3354         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3355         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3356         int ret = 0;
3357
3358         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3359                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3360                                 "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3361                                 return -EINVAL);
3362                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3363                                 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3364                                 return -EINVAL);
3365
3366                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3367                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3368                                 PPSMC_MSG_SetSoftMinByFreq,
3369                                 (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level)),
3370                                 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3371                                 return ret);
3372         }
3373
3374         return ret;
3375 }
3376
3377 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3378 {
3379         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3380         int ret = 0;
3381
3382         smum_send_msg_to_smc_with_parameter(hwmgr,
3383                         PPSMC_MSG_NumOfDisplays, 0);
3384
3385         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3386                         &data->dpm_table.mem_table);
3387         if (ret)
3388                 return ret;
3389
3390         return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3391 }
3392
3393 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3394 {
3395         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3396         int result = 0;
3397         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3398
3399         if ((data->water_marks_bitmap & WaterMarksExist) &&
3400             !(data->water_marks_bitmap & WaterMarksLoaded)) {
3401                 result = smum_smc_table_manager(hwmgr,
3402                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3403                 PP_ASSERT_WITH_CODE(!result,
3404                                 "Failed to update WMTABLE!",
3405                                 return result);
3406                 data->water_marks_bitmap |= WaterMarksLoaded;
3407         }
3408
3409         if ((data->water_marks_bitmap & WaterMarksExist) &&
3410             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3411             data->smu_features[GNLD_DPM_SOCCLK].supported) {
3412                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3413                         PPSMC_MSG_NumOfDisplays,
3414                         hwmgr->display_config->num_display);
3415         }
3416
3417         return result;
3418 }
3419
3420 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3421 {
3422         struct vega20_hwmgr *data =
3423                         (struct vega20_hwmgr *)(hwmgr->backend);
3424         int ret = 0;
3425
3426         if (data->smu_features[GNLD_DPM_UVD].supported) {
3427                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3428                         if (enable)
3429                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3430                         else
3431                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3432                 }
3433
3434                 ret = vega20_enable_smc_features(hwmgr,
3435                                 enable,
3436                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3437                 PP_ASSERT_WITH_CODE(!ret,
3438                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3439                                 return ret);
3440                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3441         }
3442
3443         return 0;
3444 }
3445
3446 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3447 {
3448         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3449
3450         if (data->vce_power_gated == bgate)
3451                 return ;
3452
3453         data->vce_power_gated = bgate;
3454         vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3455 }
3456
3457 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3458 {
3459         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3460
3461         if (data->uvd_power_gated == bgate)
3462                 return ;
3463
3464         data->uvd_power_gated = bgate;
3465         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3466 }
3467
3468 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3469 {
3470         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3471         struct vega20_single_dpm_table *dpm_table;
3472         bool vblank_too_short = false;
3473         bool disable_mclk_switching;
3474         uint32_t i, latency;
3475
3476         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3477                            !hwmgr->display_config->multi_monitor_in_sync) ||
3478                             vblank_too_short;
3479         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3480
3481         /* gfxclk */
3482         dpm_table = &(data->dpm_table.gfx_table);
3483         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3484         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3485         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3486         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3487
3488         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3489                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3490                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3491                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3492                 }
3493
3494                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3495                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3496                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3497                 }
3498
3499                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3500                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3501                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3502                 }
3503         }
3504
3505         /* memclk */
3506         dpm_table = &(data->dpm_table.mem_table);
3507         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3508         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3509         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3510         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3511
3512         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3513                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3514                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3515                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3516                 }
3517
3518                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3519                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3520                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3521                 }
3522
3523                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3524                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3525                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3526                 }
3527         }
3528
3529         /* honour DAL's UCLK Hardmin */
3530         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3531                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3532
3533         /* Hardmin is dependent on displayconfig */
3534         if (disable_mclk_switching) {
3535                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3536                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3537                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3538                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3539                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3540                                         break;
3541                                 }
3542                         }
3543                 }
3544         }
3545
3546         if (hwmgr->display_config->nb_pstate_switch_disable)
3547                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3548
3549         /* fclk */
3550         dpm_table = &(data->dpm_table.fclk_table);
3551         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3552         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3553         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3554         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3555         if (hwmgr->display_config->nb_pstate_switch_disable)
3556                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3557
3558         /* vclk */
3559         dpm_table = &(data->dpm_table.vclk_table);
3560         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3561         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3562         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3563         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3564
3565         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3566                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3567                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3568                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3569                 }
3570
3571                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3572                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3573                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3574                 }
3575         }
3576
3577         /* dclk */
3578         dpm_table = &(data->dpm_table.dclk_table);
3579         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3580         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3581         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3582         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3583
3584         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3585                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3586                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3587                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3588                 }
3589
3590                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3591                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3592                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3593                 }
3594         }
3595
3596         /* socclk */
3597         dpm_table = &(data->dpm_table.soc_table);
3598         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3599         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3600         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3601         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3602
3603         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3604                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3605                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3606                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3607                 }
3608
3609                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3610                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3611                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3612                 }
3613         }
3614
3615         /* eclk */
3616         dpm_table = &(data->dpm_table.eclk_table);
3617         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3618         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3619         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3620         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3621
3622         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3623                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3624                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3625                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3626                 }
3627
3628                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3629                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3630                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3631                 }
3632         }
3633
3634         return 0;
3635 }
3636
3637 static bool
3638 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3639 {
3640         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3641         bool is_update_required = false;
3642
3643         if (data->display_timing.num_existing_displays !=
3644                         hwmgr->display_config->num_display)
3645                 is_update_required = true;
3646
3647         if (data->registry_data.gfx_clk_deep_sleep_support &&
3648            (data->display_timing.min_clock_in_sr !=
3649             hwmgr->display_config->min_core_set_clock_in_sr))
3650                 is_update_required = true;
3651
3652         return is_update_required;
3653 }
3654
3655 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3656 {
3657         int ret = 0;
3658
3659         ret = vega20_disable_all_smu_features(hwmgr);
3660         PP_ASSERT_WITH_CODE(!ret,
3661                         "[DisableDpmTasks] Failed to disable all smu features!",
3662                         return ret);
3663
3664         return 0;
3665 }
3666
3667 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3668 {
3669         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3670         int result;
3671
3672         result = vega20_disable_dpm_tasks(hwmgr);
3673         PP_ASSERT_WITH_CODE((0 == result),
3674                         "[PowerOffAsic] Failed to disable DPM!",
3675                         );
3676         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3677
3678         return result;
3679 }
3680
3681 static int conv_power_profile_to_pplib_workload(int power_profile)
3682 {
3683         int pplib_workload = 0;
3684
3685         switch (power_profile) {
3686         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3687                 pplib_workload = WORKLOAD_DEFAULT_BIT;
3688                 break;
3689         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3690                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3691                 break;
3692         case PP_SMC_POWER_PROFILE_POWERSAVING:
3693                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3694                 break;
3695         case PP_SMC_POWER_PROFILE_VIDEO:
3696                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3697                 break;
3698         case PP_SMC_POWER_PROFILE_VR:
3699                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3700                 break;
3701         case PP_SMC_POWER_PROFILE_COMPUTE:
3702                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3703                 break;
3704         case PP_SMC_POWER_PROFILE_CUSTOM:
3705                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3706                 break;
3707         }
3708
3709         return pplib_workload;
3710 }
3711
3712 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3713 {
3714         DpmActivityMonitorCoeffInt_t activity_monitor;
3715         uint32_t i, size = 0;
3716         uint16_t workload_type = 0;
3717         static const char *profile_name[] = {
3718                                         "BOOTUP_DEFAULT",
3719                                         "3D_FULL_SCREEN",
3720                                         "POWER_SAVING",
3721                                         "VIDEO",
3722                                         "VR",
3723                                         "COMPUTE",
3724                                         "CUSTOM"};
3725         static const char *title[] = {
3726                         "PROFILE_INDEX(NAME)",
3727                         "CLOCK_TYPE(NAME)",
3728                         "FPS",
3729                         "UseRlcBusy",
3730                         "MinActiveFreqType",
3731                         "MinActiveFreq",
3732                         "BoosterFreqType",
3733                         "BoosterFreq",
3734                         "PD_Data_limit_c",
3735                         "PD_Data_error_coeff",
3736                         "PD_Data_error_rate_coeff"};
3737         int result = 0;
3738
3739         if (!buf)
3740                 return -EINVAL;
3741
3742         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3743                         title[0], title[1], title[2], title[3], title[4], title[5],
3744                         title[6], title[7], title[8], title[9], title[10]);
3745
3746         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3747                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3748                 workload_type = conv_power_profile_to_pplib_workload(i);
3749                 result = vega20_get_activity_monitor_coeff(hwmgr,
3750                                 (uint8_t *)(&activity_monitor), workload_type);
3751                 PP_ASSERT_WITH_CODE(!result,
3752                                 "[GetPowerProfile] Failed to get activity monitor!",
3753                                 return result);
3754
3755                 size += sprintf(buf + size, "%2d %14s%s:\n",
3756                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3757
3758                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3759                         " ",
3760                         0,
3761                         "GFXCLK",
3762                         activity_monitor.Gfx_FPS,
3763                         activity_monitor.Gfx_UseRlcBusy,
3764                         activity_monitor.Gfx_MinActiveFreqType,
3765                         activity_monitor.Gfx_MinActiveFreq,
3766                         activity_monitor.Gfx_BoosterFreqType,
3767                         activity_monitor.Gfx_BoosterFreq,
3768                         activity_monitor.Gfx_PD_Data_limit_c,
3769                         activity_monitor.Gfx_PD_Data_error_coeff,
3770                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3771
3772                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3773                         " ",
3774                         1,
3775                         "SOCCLK",
3776                         activity_monitor.Soc_FPS,
3777                         activity_monitor.Soc_UseRlcBusy,
3778                         activity_monitor.Soc_MinActiveFreqType,
3779                         activity_monitor.Soc_MinActiveFreq,
3780                         activity_monitor.Soc_BoosterFreqType,
3781                         activity_monitor.Soc_BoosterFreq,
3782                         activity_monitor.Soc_PD_Data_limit_c,
3783                         activity_monitor.Soc_PD_Data_error_coeff,
3784                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3785
3786                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3787                         " ",
3788                         2,
3789                         "UCLK",
3790                         activity_monitor.Mem_FPS,
3791                         activity_monitor.Mem_UseRlcBusy,
3792                         activity_monitor.Mem_MinActiveFreqType,
3793                         activity_monitor.Mem_MinActiveFreq,
3794                         activity_monitor.Mem_BoosterFreqType,
3795                         activity_monitor.Mem_BoosterFreq,
3796                         activity_monitor.Mem_PD_Data_limit_c,
3797                         activity_monitor.Mem_PD_Data_error_coeff,
3798                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3799
3800                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3801                         " ",
3802                         3,
3803                         "FCLK",
3804                         activity_monitor.Fclk_FPS,
3805                         activity_monitor.Fclk_UseRlcBusy,
3806                         activity_monitor.Fclk_MinActiveFreqType,
3807                         activity_monitor.Fclk_MinActiveFreq,
3808                         activity_monitor.Fclk_BoosterFreqType,
3809                         activity_monitor.Fclk_BoosterFreq,
3810                         activity_monitor.Fclk_PD_Data_limit_c,
3811                         activity_monitor.Fclk_PD_Data_error_coeff,
3812                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
3813         }
3814
3815         return size;
3816 }
3817
3818 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3819 {
3820         DpmActivityMonitorCoeffInt_t activity_monitor;
3821         int workload_type, result = 0;
3822         uint32_t power_profile_mode = input[size];
3823
3824         if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3825                 pr_err("Invalid power profile mode %d\n", power_profile_mode);
3826                 return -EINVAL;
3827         }
3828
3829         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3830                 if (size < 10)
3831                         return -EINVAL;
3832
3833                 result = vega20_get_activity_monitor_coeff(hwmgr,
3834                                 (uint8_t *)(&activity_monitor),
3835                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3836                 PP_ASSERT_WITH_CODE(!result,
3837                                 "[SetPowerProfile] Failed to get activity monitor!",
3838                                 return result);
3839
3840                 switch (input[0]) {
3841                 case 0: /* Gfxclk */
3842                         activity_monitor.Gfx_FPS = input[1];
3843                         activity_monitor.Gfx_UseRlcBusy = input[2];
3844                         activity_monitor.Gfx_MinActiveFreqType = input[3];
3845                         activity_monitor.Gfx_MinActiveFreq = input[4];
3846                         activity_monitor.Gfx_BoosterFreqType = input[5];
3847                         activity_monitor.Gfx_BoosterFreq = input[6];
3848                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
3849                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3850                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3851                         break;
3852                 case 1: /* Socclk */
3853                         activity_monitor.Soc_FPS = input[1];
3854                         activity_monitor.Soc_UseRlcBusy = input[2];
3855                         activity_monitor.Soc_MinActiveFreqType = input[3];
3856                         activity_monitor.Soc_MinActiveFreq = input[4];
3857                         activity_monitor.Soc_BoosterFreqType = input[5];
3858                         activity_monitor.Soc_BoosterFreq = input[6];
3859                         activity_monitor.Soc_PD_Data_limit_c = input[7];
3860                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
3861                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3862                         break;
3863                 case 2: /* Uclk */
3864                         activity_monitor.Mem_FPS = input[1];
3865                         activity_monitor.Mem_UseRlcBusy = input[2];
3866                         activity_monitor.Mem_MinActiveFreqType = input[3];
3867                         activity_monitor.Mem_MinActiveFreq = input[4];
3868                         activity_monitor.Mem_BoosterFreqType = input[5];
3869                         activity_monitor.Mem_BoosterFreq = input[6];
3870                         activity_monitor.Mem_PD_Data_limit_c = input[7];
3871                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
3872                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3873                         break;
3874                 case 3: /* Fclk */
3875                         activity_monitor.Fclk_FPS = input[1];
3876                         activity_monitor.Fclk_UseRlcBusy = input[2];
3877                         activity_monitor.Fclk_MinActiveFreqType = input[3];
3878                         activity_monitor.Fclk_MinActiveFreq = input[4];
3879                         activity_monitor.Fclk_BoosterFreqType = input[5];
3880                         activity_monitor.Fclk_BoosterFreq = input[6];
3881                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
3882                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3883                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3884                         break;
3885                 }
3886
3887                 result = vega20_set_activity_monitor_coeff(hwmgr,
3888                                 (uint8_t *)(&activity_monitor),
3889                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3890                 PP_ASSERT_WITH_CODE(!result,
3891                                 "[SetPowerProfile] Failed to set activity monitor!",
3892                                 return result);
3893         }
3894
3895         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3896         workload_type =
3897                 conv_power_profile_to_pplib_workload(power_profile_mode);
3898         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3899                                                 1 << workload_type);
3900
3901         hwmgr->power_profile_mode = power_profile_mode;
3902
3903         return 0;
3904 }
3905
3906 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3907                                         uint32_t virtual_addr_low,
3908                                         uint32_t virtual_addr_hi,
3909                                         uint32_t mc_addr_low,
3910                                         uint32_t mc_addr_hi,
3911                                         uint32_t size)
3912 {
3913         smum_send_msg_to_smc_with_parameter(hwmgr,
3914                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3915                                         virtual_addr_hi);
3916         smum_send_msg_to_smc_with_parameter(hwmgr,
3917                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
3918                                         virtual_addr_low);
3919         smum_send_msg_to_smc_with_parameter(hwmgr,
3920                                         PPSMC_MSG_DramLogSetDramAddrHigh,
3921                                         mc_addr_hi);
3922
3923         smum_send_msg_to_smc_with_parameter(hwmgr,
3924                                         PPSMC_MSG_DramLogSetDramAddrLow,
3925                                         mc_addr_low);
3926
3927         smum_send_msg_to_smc_with_parameter(hwmgr,
3928                                         PPSMC_MSG_DramLogSetDramSize,
3929                                         size);
3930         return 0;
3931 }
3932
3933 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3934                 struct PP_TemperatureRange *thermal_data)
3935 {
3936         struct phm_ppt_v3_information *pptable_information =
3937                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3938
3939         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3940
3941         thermal_data->max = pptable_information->us_software_shutdown_temp *
3942                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3943
3944         return 0;
3945 }
3946
3947 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3948         /* init/fini related */
3949         .backend_init = vega20_hwmgr_backend_init,
3950         .backend_fini = vega20_hwmgr_backend_fini,
3951         .asic_setup = vega20_setup_asic_task,
3952         .power_off_asic = vega20_power_off_asic,
3953         .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3954         .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3955         /* power state related */
3956         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3957         .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3958         .display_config_changed = vega20_display_configuration_changed_task,
3959         .check_smc_update_required_for_display_configuration =
3960                 vega20_check_smc_update_required_for_display_configuration,
3961         .notify_smc_display_config_after_ps_adjustment =
3962                 vega20_notify_smc_display_config_after_ps_adjustment,
3963         /* export to DAL */
3964         .get_sclk = vega20_dpm_get_sclk,
3965         .get_mclk = vega20_dpm_get_mclk,
3966         .get_dal_power_level = vega20_get_dal_power_level,
3967         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3968         .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3969         .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3970         .display_clock_voltage_request = vega20_display_clock_voltage_request,
3971         .get_performance_level = vega20_get_performance_level,
3972         /* UMD pstate, profile related */
3973         .force_dpm_level = vega20_dpm_force_dpm_level,
3974         .get_power_profile_mode = vega20_get_power_profile_mode,
3975         .set_power_profile_mode = vega20_set_power_profile_mode,
3976         /* od related */
3977         .set_power_limit = vega20_set_power_limit,
3978         .get_sclk_od = vega20_get_sclk_od,
3979         .set_sclk_od = vega20_set_sclk_od,
3980         .get_mclk_od = vega20_get_mclk_od,
3981         .set_mclk_od = vega20_set_mclk_od,
3982         .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3983         /* for sysfs to retrive/set gfxclk/memclk */
3984         .force_clock_level = vega20_force_clock_level,
3985         .print_clock_levels = vega20_print_clock_levels,
3986         .read_sensor = vega20_read_sensor,
3987         .get_ppfeature_status = vega20_get_ppfeature_status,
3988         .set_ppfeature_status = vega20_set_ppfeature_status,
3989         /* powergate related */
3990         .powergate_uvd = vega20_power_gate_uvd,
3991         .powergate_vce = vega20_power_gate_vce,
3992         /* thermal related */
3993         .start_thermal_controller = vega20_start_thermal_controller,
3994         .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3995         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3996         .register_irq_handlers = smu9_register_irq_handlers,
3997         .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3998         /* fan control related */
3999         .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
4000         .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
4001         .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4002         .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4003         .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4004         .get_fan_control_mode = vega20_get_fan_control_mode,
4005         .set_fan_control_mode = vega20_set_fan_control_mode,
4006         /* smu memory related */
4007         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4008         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4009         /* BACO related */
4010         .get_asic_baco_capability = vega20_baco_get_capability,
4011         .get_asic_baco_state = vega20_baco_get_state,
4012         .set_asic_baco_state = vega20_baco_set_state,
4013 };
4014
4015 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4016 {
4017         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4018         hwmgr->pptable_func = &vega20_pptable_funcs;
4019
4020         return 0;
4021 }