2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "vega20_baco.h"
51 #include "smuio/smuio_9_0_offset.h"
52 #include "smuio/smuio_9_0_sh_mask.h"
53 #include "nbio/nbio_7_4_sh_mask.h"
55 #define smnPCIE_LC_SPEED_CNTL 0x11140290
56 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
58 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
60 struct vega20_hwmgr *data =
61 (struct vega20_hwmgr *)(hwmgr->backend);
63 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
64 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
65 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
66 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
67 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
69 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
70 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
81 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
84 * Disable the following features for now:
93 data->registry_data.disallowed_features = 0xE0041C00;
94 data->registry_data.od_state_in_dc_support = 0;
95 data->registry_data.thermal_support = 1;
96 data->registry_data.skip_baco_hardware = 0;
98 data->registry_data.log_avfs_param = 0;
99 data->registry_data.sclk_throttle_low_notification = 1;
100 data->registry_data.force_dpm_high = 0;
101 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
103 data->registry_data.didt_support = 0;
104 if (data->registry_data.didt_support) {
105 data->registry_data.didt_mode = 6;
106 data->registry_data.sq_ramping_support = 1;
107 data->registry_data.db_ramping_support = 0;
108 data->registry_data.td_ramping_support = 0;
109 data->registry_data.tcp_ramping_support = 0;
110 data->registry_data.dbr_ramping_support = 0;
111 data->registry_data.edc_didt_support = 1;
112 data->registry_data.gc_didt_support = 0;
113 data->registry_data.psm_didt_support = 0;
116 data->registry_data.pcie_lane_override = 0xff;
117 data->registry_data.pcie_speed_override = 0xff;
118 data->registry_data.pcie_clock_override = 0xffffffff;
119 data->registry_data.regulator_hot_gpio_support = 1;
120 data->registry_data.ac_dc_switch_gpio_support = 0;
121 data->registry_data.quick_transition_support = 0;
122 data->registry_data.zrpm_start_temp = 0xffff;
123 data->registry_data.zrpm_stop_temp = 0xffff;
124 data->registry_data.od8_feature_enable = 1;
125 data->registry_data.disable_water_mark = 0;
126 data->registry_data.disable_pp_tuning = 0;
127 data->registry_data.disable_xlpp_tuning = 0;
128 data->registry_data.disable_workload_policy = 0;
129 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
130 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
131 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
132 data->registry_data.force_workload_policy_mask = 0;
133 data->registry_data.disable_3d_fs_detection = 0;
134 data->registry_data.fps_support = 1;
135 data->registry_data.disable_auto_wattman = 1;
136 data->registry_data.auto_wattman_debug = 0;
137 data->registry_data.auto_wattman_sample_period = 100;
138 data->registry_data.fclk_gfxclk_ratio = 0;
139 data->registry_data.auto_wattman_threshold = 50;
140 data->registry_data.gfxoff_controlled_by_driver = 1;
141 data->gfxoff_allowed = false;
142 data->counter_gfxoff = 0;
145 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
147 struct vega20_hwmgr *data =
148 (struct vega20_hwmgr *)(hwmgr->backend);
149 struct amdgpu_device *adev = hwmgr->adev;
151 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
152 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
153 PHM_PlatformCaps_ControlVDDCI);
155 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
156 PHM_PlatformCaps_TablelessHardwareInterface);
158 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
159 PHM_PlatformCaps_EnableSMU7ThermalManagement);
161 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
162 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
163 PHM_PlatformCaps_UVDPowerGating);
165 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
166 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
167 PHM_PlatformCaps_VCEPowerGating);
169 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 PHM_PlatformCaps_UnTabledHardwareInterface);
172 if (data->registry_data.od8_feature_enable)
173 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
174 PHM_PlatformCaps_OD8inACSupport);
176 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
177 PHM_PlatformCaps_ActivityReporting);
178 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
179 PHM_PlatformCaps_FanSpeedInTableIsRPM);
181 if (data->registry_data.od_state_in_dc_support) {
182 if (data->registry_data.od8_feature_enable)
183 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
184 PHM_PlatformCaps_OD8inDCSupport);
187 if (data->registry_data.thermal_support &&
188 data->registry_data.fuzzy_fan_control_support &&
189 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_ODFuzzyFanControlSupport);
193 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
194 PHM_PlatformCaps_DynamicPowerManagement);
195 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
196 PHM_PlatformCaps_SMC);
197 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
198 PHM_PlatformCaps_ThermalPolicyDelay);
200 if (data->registry_data.force_dpm_high)
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
204 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
205 PHM_PlatformCaps_DynamicUVDState);
207 if (data->registry_data.sclk_throttle_low_notification)
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_SclkThrottleLowNotification);
211 /* power tune caps */
212 /* assume disabled */
213 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
214 PHM_PlatformCaps_PowerContainment);
215 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
216 PHM_PlatformCaps_DiDtSupport);
217 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
218 PHM_PlatformCaps_SQRamping);
219 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_DBRamping);
221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
222 PHM_PlatformCaps_TDRamping);
223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
224 PHM_PlatformCaps_TCPRamping);
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_DBRRamping);
227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
228 PHM_PlatformCaps_DiDtEDCEnable);
229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
230 PHM_PlatformCaps_GCEDC);
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_PSM);
234 if (data->registry_data.didt_support) {
235 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
236 PHM_PlatformCaps_DiDtSupport);
237 if (data->registry_data.sq_ramping_support)
238 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
239 PHM_PlatformCaps_SQRamping);
240 if (data->registry_data.db_ramping_support)
241 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
242 PHM_PlatformCaps_DBRamping);
243 if (data->registry_data.td_ramping_support)
244 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
245 PHM_PlatformCaps_TDRamping);
246 if (data->registry_data.tcp_ramping_support)
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_TCPRamping);
249 if (data->registry_data.dbr_ramping_support)
250 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
251 PHM_PlatformCaps_DBRRamping);
252 if (data->registry_data.edc_didt_support)
253 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
254 PHM_PlatformCaps_DiDtEDCEnable);
255 if (data->registry_data.gc_didt_support)
256 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
257 PHM_PlatformCaps_GCEDC);
258 if (data->registry_data.psm_didt_support)
259 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
260 PHM_PlatformCaps_PSM);
263 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
264 PHM_PlatformCaps_RegulatorHot);
266 if (data->registry_data.ac_dc_switch_gpio_support) {
267 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
268 PHM_PlatformCaps_AutomaticDCTransition);
269 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
273 if (data->registry_data.quick_transition_support) {
274 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
275 PHM_PlatformCaps_AutomaticDCTransition);
276 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
277 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
278 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_Falcon_QuickTransition);
282 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
283 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
284 PHM_PlatformCaps_LowestUclkReservedForUlv);
285 if (data->lowest_uclk_reserved_for_ulv == 1)
286 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
287 PHM_PlatformCaps_LowestUclkReservedForUlv);
290 if (data->registry_data.custom_fan_support)
291 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
292 PHM_PlatformCaps_CustomFanControlSupport);
297 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
299 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
302 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
303 FEATURE_DPM_PREFETCHER_BIT;
304 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
305 FEATURE_DPM_GFXCLK_BIT;
306 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
307 FEATURE_DPM_UCLK_BIT;
308 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
309 FEATURE_DPM_SOCCLK_BIT;
310 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
312 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
314 data->smu_features[GNLD_ULV].smu_feature_id =
316 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
317 FEATURE_DPM_MP0CLK_BIT;
318 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
319 FEATURE_DPM_LINK_BIT;
320 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
321 FEATURE_DPM_DCEFCLK_BIT;
322 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
323 FEATURE_DS_GFXCLK_BIT;
324 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
325 FEATURE_DS_SOCCLK_BIT;
326 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
328 data->smu_features[GNLD_PPT].smu_feature_id =
330 data->smu_features[GNLD_TDC].smu_feature_id =
332 data->smu_features[GNLD_THERMAL].smu_feature_id =
334 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
335 FEATURE_GFX_PER_CU_CG_BIT;
336 data->smu_features[GNLD_RM].smu_feature_id =
338 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
339 FEATURE_DS_DCEFCLK_BIT;
340 data->smu_features[GNLD_ACDC].smu_feature_id =
342 data->smu_features[GNLD_VR0HOT].smu_feature_id =
344 data->smu_features[GNLD_VR1HOT].smu_feature_id =
346 data->smu_features[GNLD_FW_CTF].smu_feature_id =
348 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
349 FEATURE_LED_DISPLAY_BIT;
350 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
351 FEATURE_FAN_CONTROL_BIT;
352 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
353 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
354 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
355 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
356 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
357 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
358 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
359 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
361 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
362 data->smu_features[i].smu_feature_bitmap =
363 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
364 data->smu_features[i].allowed =
365 ((data->registry_data.disallowed_features >> i) & 1) ?
370 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
375 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
377 kfree(hwmgr->backend);
378 hwmgr->backend = NULL;
383 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
385 struct vega20_hwmgr *data;
386 struct amdgpu_device *adev = hwmgr->adev;
388 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
392 hwmgr->backend = data;
394 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
395 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
396 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
398 vega20_set_default_registry_data(hwmgr);
400 data->disable_dpm_mask = 0xff;
402 /* need to set voltage control types before EVV patching */
403 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
404 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
405 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
407 data->water_marks_bitmap = 0;
408 data->avfs_exist = false;
410 vega20_set_features_platform_caps(hwmgr);
412 vega20_init_dpm_defaults(hwmgr);
414 /* Parse pptable data read from VBIOS */
415 vega20_set_private_data_based_on_pptable(hwmgr);
417 data->is_tlu_enabled = false;
419 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
420 VEGA20_MAX_HARDWARE_POWERLEVELS;
421 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
422 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
424 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
425 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
426 hwmgr->platform_descriptor.clockStep.engineClock = 500;
427 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
429 data->total_active_cus = adev->gfx.cu_info.number;
434 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
436 struct vega20_hwmgr *data =
437 (struct vega20_hwmgr *)(hwmgr->backend);
439 data->low_sclk_interrupt_threshold = 0;
444 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
446 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
449 ret = vega20_init_sclk_threshold(hwmgr);
450 PP_ASSERT_WITH_CODE(!ret,
451 "Failed to init sclk threshold!",
454 if (adev->in_baco_reset) {
455 adev->in_baco_reset = 0;
457 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
459 pr_err("Failed to apply vega20 baco workaround!\n");
466 * @fn vega20_init_dpm_state
467 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
469 * @param dpm_state - the address of the DPM Table to initiailize.
472 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
474 dpm_state->soft_min_level = 0x0;
475 dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
476 dpm_state->hard_min_level = 0x0;
477 dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
480 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
481 PPCLK_e clk_id, uint32_t *num_of_levels)
485 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
486 PPSMC_MSG_GetDpmFreqByIndex,
487 (clk_id << 16 | 0xFF));
488 PP_ASSERT_WITH_CODE(!ret,
489 "[GetNumOfDpmLevel] failed to get dpm levels!",
492 *num_of_levels = smum_get_argument(hwmgr);
493 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
494 "[GetNumOfDpmLevel] number of clk levels is invalid!",
500 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
501 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
505 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
506 PPSMC_MSG_GetDpmFreqByIndex,
507 (clk_id << 16 | index));
508 PP_ASSERT_WITH_CODE(!ret,
509 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
512 *clk = smum_get_argument(hwmgr);
513 PP_ASSERT_WITH_CODE(*clk,
514 "[GetDpmFreqByIndex] clk value is invalid!",
520 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
521 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
524 uint32_t i, num_of_levels, clk;
526 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
527 PP_ASSERT_WITH_CODE(!ret,
528 "[SetupSingleDpmTable] failed to get clk levels!",
531 dpm_table->count = num_of_levels;
533 for (i = 0; i < num_of_levels; i++) {
534 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
535 PP_ASSERT_WITH_CODE(!ret,
536 "[SetupSingleDpmTable] failed to get clk of specific level!",
538 dpm_table->dpm_levels[i].value = clk;
539 dpm_table->dpm_levels[i].enabled = true;
545 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
547 struct vega20_hwmgr *data =
548 (struct vega20_hwmgr *)(hwmgr->backend);
549 struct vega20_single_dpm_table *dpm_table;
552 dpm_table = &(data->dpm_table.gfx_table);
553 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
554 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
555 PP_ASSERT_WITH_CODE(!ret,
556 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
559 dpm_table->count = 1;
560 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
566 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
568 struct vega20_hwmgr *data =
569 (struct vega20_hwmgr *)(hwmgr->backend);
570 struct vega20_single_dpm_table *dpm_table;
573 dpm_table = &(data->dpm_table.mem_table);
574 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
575 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
576 PP_ASSERT_WITH_CODE(!ret,
577 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
580 dpm_table->count = 1;
581 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
588 * This function is to initialize all DPM state tables
589 * for SMU based on the dependency table.
590 * Dynamic state patching function will then trim these
591 * state tables to the allowed range based
592 * on the power policy or external client requests,
593 * such as UVD request, etc.
595 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
597 struct vega20_hwmgr *data =
598 (struct vega20_hwmgr *)(hwmgr->backend);
599 struct vega20_single_dpm_table *dpm_table;
602 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
605 dpm_table = &(data->dpm_table.soc_table);
606 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
607 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
608 PP_ASSERT_WITH_CODE(!ret,
609 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
612 dpm_table->count = 1;
613 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
615 vega20_init_dpm_state(&(dpm_table->dpm_state));
618 dpm_table = &(data->dpm_table.gfx_table);
619 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
622 vega20_init_dpm_state(&(dpm_table->dpm_state));
625 dpm_table = &(data->dpm_table.mem_table);
626 ret = vega20_setup_memclk_dpm_table(hwmgr);
629 vega20_init_dpm_state(&(dpm_table->dpm_state));
632 dpm_table = &(data->dpm_table.eclk_table);
633 if (data->smu_features[GNLD_DPM_VCE].enabled) {
634 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
635 PP_ASSERT_WITH_CODE(!ret,
636 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
639 dpm_table->count = 1;
640 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
642 vega20_init_dpm_state(&(dpm_table->dpm_state));
645 dpm_table = &(data->dpm_table.vclk_table);
646 if (data->smu_features[GNLD_DPM_UVD].enabled) {
647 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
648 PP_ASSERT_WITH_CODE(!ret,
649 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
652 dpm_table->count = 1;
653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
655 vega20_init_dpm_state(&(dpm_table->dpm_state));
658 dpm_table = &(data->dpm_table.dclk_table);
659 if (data->smu_features[GNLD_DPM_UVD].enabled) {
660 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
661 PP_ASSERT_WITH_CODE(!ret,
662 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
665 dpm_table->count = 1;
666 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
668 vega20_init_dpm_state(&(dpm_table->dpm_state));
671 dpm_table = &(data->dpm_table.dcef_table);
672 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
673 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
674 PP_ASSERT_WITH_CODE(!ret,
675 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
678 dpm_table->count = 1;
679 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
681 vega20_init_dpm_state(&(dpm_table->dpm_state));
684 dpm_table = &(data->dpm_table.pixel_table);
685 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
686 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
687 PP_ASSERT_WITH_CODE(!ret,
688 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
691 dpm_table->count = 0;
692 vega20_init_dpm_state(&(dpm_table->dpm_state));
695 dpm_table = &(data->dpm_table.display_table);
696 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
697 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
698 PP_ASSERT_WITH_CODE(!ret,
699 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
702 dpm_table->count = 0;
703 vega20_init_dpm_state(&(dpm_table->dpm_state));
706 dpm_table = &(data->dpm_table.phy_table);
707 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
708 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
709 PP_ASSERT_WITH_CODE(!ret,
710 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
713 dpm_table->count = 0;
714 vega20_init_dpm_state(&(dpm_table->dpm_state));
717 dpm_table = &(data->dpm_table.fclk_table);
718 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
719 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
720 PP_ASSERT_WITH_CODE(!ret,
721 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
724 dpm_table->count = 1;
725 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
727 vega20_init_dpm_state(&(dpm_table->dpm_state));
729 /* save a copy of the default DPM table */
730 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
731 sizeof(struct vega20_dpm_table));
737 * Initializes the SMC table and uploads it
739 * @param hwmgr the address of the powerplay hardware manager.
740 * @param pInput the pointer to input data (PowerState)
743 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
746 struct vega20_hwmgr *data =
747 (struct vega20_hwmgr *)(hwmgr->backend);
748 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
749 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
750 struct phm_ppt_v3_information *pptable_information =
751 (struct phm_ppt_v3_information *)hwmgr->pptable;
753 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
754 PP_ASSERT_WITH_CODE(!result,
755 "[InitSMCTable] Failed to get vbios bootup values!",
758 data->vbios_boot_state.vddc = boot_up_values.usVddc;
759 data->vbios_boot_state.vddci = boot_up_values.usVddci;
760 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
761 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
762 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
763 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
764 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
765 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
766 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
767 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
768 data->vbios_boot_state.fclock = boot_up_values.ulFClk;
769 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
771 smum_send_msg_to_smc_with_parameter(hwmgr,
772 PPSMC_MSG_SetMinDeepSleepDcefclk,
773 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
775 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
777 result = smum_smc_table_manager(hwmgr,
778 (uint8_t *)pp_table, TABLE_PPTABLE, false);
779 PP_ASSERT_WITH_CODE(!result,
780 "[InitSMCTable] Failed to upload PPtable!",
787 * Override PCIe link speed and link width for DPM Level 1. PPTable entries
788 * reflect the ASIC capabilities and not the system capabilities. For e.g.
789 * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
790 * to DPM1, it fails as system doesn't support Gen4.
792 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
794 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
795 struct vega20_hwmgr *data =
796 (struct vega20_hwmgr *)(hwmgr->backend);
797 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
800 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
802 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
804 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
806 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
809 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
811 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
813 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
815 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
817 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
819 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
822 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
823 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
824 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
826 smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
827 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
828 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);
829 PP_ASSERT_WITH_CODE(!ret,
830 "[OverridePcieParameters] Attempt to override pcie params failed!",
833 data->pcie_parameters_override = 1;
834 data->pcie_gen_level1 = pcie_gen;
835 data->pcie_width_level1 = pcie_width;
840 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
842 struct vega20_hwmgr *data =
843 (struct vega20_hwmgr *)(hwmgr->backend);
844 uint32_t allowed_features_low = 0, allowed_features_high = 0;
848 for (i = 0; i < GNLD_FEATURES_MAX; i++)
849 if (data->smu_features[i].allowed)
850 data->smu_features[i].smu_feature_id > 31 ?
851 (allowed_features_high |=
852 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
854 (allowed_features_low |=
855 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
858 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
859 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
860 PP_ASSERT_WITH_CODE(!ret,
861 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
864 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
865 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
866 PP_ASSERT_WITH_CODE(!ret,
867 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
873 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
875 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
878 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
880 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
883 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
885 struct vega20_hwmgr *data =
886 (struct vega20_hwmgr *)(hwmgr->backend);
887 uint64_t features_enabled;
892 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
893 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
894 "[EnableAllSMUFeatures] Failed to enable all smu features!",
897 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
898 PP_ASSERT_WITH_CODE(!ret,
899 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
902 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
903 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
905 data->smu_features[i].enabled = enabled;
906 data->smu_features[i].supported = enabled;
909 if (data->smu_features[i].allowed && !enabled)
910 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
911 else if (!data->smu_features[i].allowed && enabled)
912 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
919 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
921 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
923 if (data->smu_features[GNLD_DPM_UCLK].enabled)
924 return smum_send_msg_to_smc_with_parameter(hwmgr,
925 PPSMC_MSG_SetUclkFastSwitch,
931 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
933 struct vega20_hwmgr *data =
934 (struct vega20_hwmgr *)(hwmgr->backend);
936 return smum_send_msg_to_smc_with_parameter(hwmgr,
937 PPSMC_MSG_SetFclkGfxClkRatio,
938 data->registry_data.fclk_gfxclk_ratio);
941 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
943 struct vega20_hwmgr *data =
944 (struct vega20_hwmgr *)(hwmgr->backend);
945 uint64_t features_enabled;
950 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
951 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
952 "[DisableAllSMUFeatures] Failed to disable all smu features!",
955 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
956 PP_ASSERT_WITH_CODE(!ret,
957 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
960 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
961 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
963 data->smu_features[i].enabled = enabled;
964 data->smu_features[i].supported = enabled;
970 static int vega20_od8_set_feature_capabilities(
971 struct pp_hwmgr *hwmgr)
973 struct phm_ppt_v3_information *pptable_information =
974 (struct phm_ppt_v3_information *)hwmgr->pptable;
975 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
976 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
977 struct vega20_od8_settings *od_settings = &(data->od8_settings);
979 od_settings->overdrive8_capabilities = 0;
981 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
982 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
983 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
984 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
985 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
986 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
987 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
989 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
990 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
991 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
992 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
993 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
994 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
995 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
996 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
999 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1000 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1001 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1002 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1003 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1004 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1005 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1006 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1007 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1010 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1011 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1012 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1013 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1014 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1015 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1017 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1018 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1019 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1020 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1021 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1022 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1023 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1025 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1026 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1027 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1028 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1029 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1030 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1031 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1034 if (data->smu_features[GNLD_THERMAL].enabled) {
1035 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1036 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1037 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1038 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1039 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1040 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1042 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1043 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1044 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1045 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1046 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1047 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1050 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1051 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1053 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1054 pp_table->FanZeroRpmEnable)
1055 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1057 if (!od_settings->overdrive8_capabilities)
1058 hwmgr->od_enabled = false;
1063 static int vega20_od8_set_feature_id(
1064 struct pp_hwmgr *hwmgr)
1066 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1067 struct vega20_od8_settings *od_settings = &(data->od8_settings);
1069 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1070 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1072 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1075 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1077 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1081 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1082 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1084 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1086 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1088 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1090 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1092 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1095 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1097 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1099 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1101 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1103 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1105 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1109 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1110 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1112 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1114 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1115 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1117 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1119 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1120 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1121 OD8_ACOUSTIC_LIMIT_SCLK;
1123 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1126 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1127 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1130 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1133 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1134 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1135 OD8_TEMPERATURE_FAN;
1137 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1140 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1141 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1142 OD8_TEMPERATURE_SYSTEM;
1144 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1150 static int vega20_od8_get_gfx_clock_base_voltage(
1151 struct pp_hwmgr *hwmgr,
1157 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1158 PPSMC_MSG_GetAVFSVoltageByDpm,
1159 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1160 PP_ASSERT_WITH_CODE(!ret,
1161 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1164 *voltage = smum_get_argument(hwmgr);
1165 *voltage = *voltage / VOLTAGE_SCALE;
1170 static int vega20_od8_initialize_default_settings(
1171 struct pp_hwmgr *hwmgr)
1173 struct phm_ppt_v3_information *pptable_information =
1174 (struct phm_ppt_v3_information *)hwmgr->pptable;
1175 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1176 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1177 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1180 /* Set Feature Capabilities */
1181 vega20_od8_set_feature_capabilities(hwmgr);
1183 /* Map FeatureID to individual settings */
1184 vega20_od8_set_feature_id(hwmgr);
1186 /* Set default values */
1187 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1188 PP_ASSERT_WITH_CODE(!ret,
1189 "Failed to export over drive table!",
1192 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1193 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1194 od_table->GfxclkFmin;
1195 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1196 od_table->GfxclkFmax;
1198 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1200 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1204 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1205 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1206 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1207 od_table->GfxclkFreq1;
1209 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1210 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1211 od_table->GfxclkFreq3;
1213 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1214 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1215 od_table->GfxclkFreq2;
1217 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1218 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1219 od_table->GfxclkFreq1),
1220 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1221 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1222 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1225 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1226 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1227 od_table->GfxclkFreq2),
1228 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1229 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1230 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1233 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1234 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1235 od_table->GfxclkFreq3),
1236 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1237 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1238 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1241 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1243 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1245 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1247 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1249 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1251 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1255 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1256 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1259 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1262 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1263 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1264 od_table->OverDrivePct;
1266 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1269 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1270 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1271 od_table->FanMaximumRpm;
1273 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1276 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1277 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1278 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1280 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1283 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1284 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1285 od_table->FanTargetTemperature;
1287 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1290 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1291 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1292 od_table->MaxOpTemp;
1294 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1297 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1298 if (od8_settings->od8_settings_array[i].feature_id) {
1299 od8_settings->od8_settings_array[i].min_value =
1300 pptable_information->od_settings_min[i];
1301 od8_settings->od8_settings_array[i].max_value =
1302 pptable_information->od_settings_max[i];
1303 od8_settings->od8_settings_array[i].current_value =
1304 od8_settings->od8_settings_array[i].default_value;
1306 od8_settings->od8_settings_array[i].min_value =
1308 od8_settings->od8_settings_array[i].max_value =
1310 od8_settings->od8_settings_array[i].current_value =
1315 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1316 PP_ASSERT_WITH_CODE(!ret,
1317 "Failed to import over drive table!",
1323 static int vega20_od8_set_settings(
1324 struct pp_hwmgr *hwmgr,
1328 OverDriveTable_t od_table;
1330 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1331 struct vega20_od8_single_setting *od8_settings =
1332 data->od8_settings.od8_settings_array;
1334 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1335 PP_ASSERT_WITH_CODE(!ret,
1336 "Failed to export over drive table!",
1340 case OD8_SETTING_GFXCLK_FMIN:
1341 od_table.GfxclkFmin = (uint16_t)value;
1343 case OD8_SETTING_GFXCLK_FMAX:
1344 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1345 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1348 od_table.GfxclkFmax = (uint16_t)value;
1350 case OD8_SETTING_GFXCLK_FREQ1:
1351 od_table.GfxclkFreq1 = (uint16_t)value;
1353 case OD8_SETTING_GFXCLK_VOLTAGE1:
1354 od_table.GfxclkVolt1 = (uint16_t)value;
1356 case OD8_SETTING_GFXCLK_FREQ2:
1357 od_table.GfxclkFreq2 = (uint16_t)value;
1359 case OD8_SETTING_GFXCLK_VOLTAGE2:
1360 od_table.GfxclkVolt2 = (uint16_t)value;
1362 case OD8_SETTING_GFXCLK_FREQ3:
1363 od_table.GfxclkFreq3 = (uint16_t)value;
1365 case OD8_SETTING_GFXCLK_VOLTAGE3:
1366 od_table.GfxclkVolt3 = (uint16_t)value;
1368 case OD8_SETTING_UCLK_FMAX:
1369 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1370 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1372 od_table.UclkFmax = (uint16_t)value;
1374 case OD8_SETTING_POWER_PERCENTAGE:
1375 od_table.OverDrivePct = (int16_t)value;
1377 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1378 od_table.FanMaximumRpm = (uint16_t)value;
1380 case OD8_SETTING_FAN_MIN_SPEED:
1381 od_table.FanMinimumPwm = (uint16_t)value;
1383 case OD8_SETTING_FAN_TARGET_TEMP:
1384 od_table.FanTargetTemperature = (uint16_t)value;
1386 case OD8_SETTING_OPERATING_TEMP_MAX:
1387 od_table.MaxOpTemp = (uint16_t)value;
1391 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1392 PP_ASSERT_WITH_CODE(!ret,
1393 "Failed to import over drive table!",
1399 static int vega20_get_sclk_od(
1400 struct pp_hwmgr *hwmgr)
1402 struct vega20_hwmgr *data = hwmgr->backend;
1403 struct vega20_single_dpm_table *sclk_table =
1404 &(data->dpm_table.gfx_table);
1405 struct vega20_single_dpm_table *golden_sclk_table =
1406 &(data->golden_dpm_table.gfx_table);
1407 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1408 int golden_value = golden_sclk_table->dpm_levels
1409 [golden_sclk_table->count - 1].value;
1412 value -= golden_value;
1413 value = DIV_ROUND_UP(value * 100, golden_value);
1418 static int vega20_set_sclk_od(
1419 struct pp_hwmgr *hwmgr, uint32_t value)
1421 struct vega20_hwmgr *data = hwmgr->backend;
1422 struct vega20_single_dpm_table *golden_sclk_table =
1423 &(data->golden_dpm_table.gfx_table);
1427 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1429 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1431 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1432 PP_ASSERT_WITH_CODE(!ret,
1433 "[SetSclkOD] failed to set od gfxclk!",
1436 /* retrieve updated gfxclk table */
1437 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1438 PP_ASSERT_WITH_CODE(!ret,
1439 "[SetSclkOD] failed to refresh gfxclk table!",
1445 static int vega20_get_mclk_od(
1446 struct pp_hwmgr *hwmgr)
1448 struct vega20_hwmgr *data = hwmgr->backend;
1449 struct vega20_single_dpm_table *mclk_table =
1450 &(data->dpm_table.mem_table);
1451 struct vega20_single_dpm_table *golden_mclk_table =
1452 &(data->golden_dpm_table.mem_table);
1453 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1454 int golden_value = golden_mclk_table->dpm_levels
1455 [golden_mclk_table->count - 1].value;
1458 value -= golden_value;
1459 value = DIV_ROUND_UP(value * 100, golden_value);
1464 static int vega20_set_mclk_od(
1465 struct pp_hwmgr *hwmgr, uint32_t value)
1467 struct vega20_hwmgr *data = hwmgr->backend;
1468 struct vega20_single_dpm_table *golden_mclk_table =
1469 &(data->golden_dpm_table.mem_table);
1473 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1475 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1477 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1478 PP_ASSERT_WITH_CODE(!ret,
1479 "[SetMclkOD] failed to set od memclk!",
1482 /* retrieve updated memclk table */
1483 ret = vega20_setup_memclk_dpm_table(hwmgr);
1484 PP_ASSERT_WITH_CODE(!ret,
1485 "[SetMclkOD] failed to refresh memclk table!",
1491 static int vega20_populate_umdpstate_clocks(
1492 struct pp_hwmgr *hwmgr)
1494 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1495 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1496 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1498 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1499 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1501 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1502 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1503 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1504 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1507 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1508 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1513 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1514 PP_Clock *clock, PPCLK_e clock_select)
1518 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1519 PPSMC_MSG_GetDcModeMaxDpmFreq,
1520 (clock_select << 16))) == 0,
1521 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1523 *clock = smum_get_argument(hwmgr);
1525 /* if DC limit is zero, return AC limit */
1527 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1528 PPSMC_MSG_GetMaxDpmFreq,
1529 (clock_select << 16))) == 0,
1530 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1532 *clock = smum_get_argument(hwmgr);
1538 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1540 struct vega20_hwmgr *data =
1541 (struct vega20_hwmgr *)(hwmgr->backend);
1542 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1543 &(data->max_sustainable_clocks);
1546 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1547 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1548 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1549 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1550 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1551 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1553 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1554 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1555 &(max_sustainable_clocks->uclock),
1557 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1560 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1561 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1562 &(max_sustainable_clocks->soc_clock),
1563 PPCLK_SOCCLK)) == 0,
1564 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1567 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1568 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1569 &(max_sustainable_clocks->dcef_clock),
1570 PPCLK_DCEFCLK)) == 0,
1571 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1573 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1574 &(max_sustainable_clocks->display_clock),
1575 PPCLK_DISPCLK)) == 0,
1576 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1578 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1579 &(max_sustainable_clocks->phy_clock),
1580 PPCLK_PHYCLK)) == 0,
1581 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1583 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1584 &(max_sustainable_clocks->pixel_clock),
1585 PPCLK_PIXCLK)) == 0,
1586 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1590 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1591 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1596 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1600 result = smum_send_msg_to_smc(hwmgr,
1601 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1602 PP_ASSERT_WITH_CODE(!result,
1603 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1609 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1611 struct vega20_hwmgr *data =
1612 (struct vega20_hwmgr *)(hwmgr->backend);
1614 data->uvd_power_gated = true;
1615 data->vce_power_gated = true;
1617 if (data->smu_features[GNLD_DPM_UVD].enabled)
1618 data->uvd_power_gated = false;
1620 if (data->smu_features[GNLD_DPM_VCE].enabled)
1621 data->vce_power_gated = false;
1624 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1628 smum_send_msg_to_smc_with_parameter(hwmgr,
1629 PPSMC_MSG_NumOfDisplays, 0);
1631 result = vega20_set_allowed_featuresmask(hwmgr);
1632 PP_ASSERT_WITH_CODE(!result,
1633 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1636 result = vega20_init_smc_table(hwmgr);
1637 PP_ASSERT_WITH_CODE(!result,
1638 "[EnableDPMTasks] Failed to initialize SMC table!",
1641 result = vega20_run_btc(hwmgr);
1642 PP_ASSERT_WITH_CODE(!result,
1643 "[EnableDPMTasks] Failed to run btc!",
1646 result = vega20_run_btc_afll(hwmgr);
1647 PP_ASSERT_WITH_CODE(!result,
1648 "[EnableDPMTasks] Failed to run btc afll!",
1651 result = vega20_enable_all_smu_features(hwmgr);
1652 PP_ASSERT_WITH_CODE(!result,
1653 "[EnableDPMTasks] Failed to enable all smu features!",
1656 result = vega20_override_pcie_parameters(hwmgr);
1657 PP_ASSERT_WITH_CODE(!result,
1658 "[EnableDPMTasks] Failed to override pcie parameters!",
1661 result = vega20_notify_smc_display_change(hwmgr);
1662 PP_ASSERT_WITH_CODE(!result,
1663 "[EnableDPMTasks] Failed to notify smc display change!",
1666 result = vega20_send_clock_ratio(hwmgr);
1667 PP_ASSERT_WITH_CODE(!result,
1668 "[EnableDPMTasks] Failed to send clock ratio!",
1671 /* Initialize UVD/VCE powergating state */
1672 vega20_init_powergate_state(hwmgr);
1674 result = vega20_setup_default_dpm_tables(hwmgr);
1675 PP_ASSERT_WITH_CODE(!result,
1676 "[EnableDPMTasks] Failed to setup default DPM tables!",
1679 result = vega20_init_max_sustainable_clocks(hwmgr);
1680 PP_ASSERT_WITH_CODE(!result,
1681 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1684 result = vega20_power_control_set_level(hwmgr);
1685 PP_ASSERT_WITH_CODE(!result,
1686 "[EnableDPMTasks] Failed to power control set level!",
1689 result = vega20_od8_initialize_default_settings(hwmgr);
1690 PP_ASSERT_WITH_CODE(!result,
1691 "[EnableDPMTasks] Failed to initialize odn settings!",
1694 result = vega20_populate_umdpstate_clocks(hwmgr);
1695 PP_ASSERT_WITH_CODE(!result,
1696 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1699 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1700 POWER_SOURCE_AC << 16);
1701 PP_ASSERT_WITH_CODE(!result,
1702 "[GetPptLimit] get default PPT limit failed!",
1704 hwmgr->power_limit =
1705 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1710 static uint32_t vega20_find_lowest_dpm_level(
1711 struct vega20_single_dpm_table *table)
1715 for (i = 0; i < table->count; i++) {
1716 if (table->dpm_levels[i].enabled)
1719 if (i >= table->count) {
1721 table->dpm_levels[i].enabled = true;
1727 static uint32_t vega20_find_highest_dpm_level(
1728 struct vega20_single_dpm_table *table)
1732 PP_ASSERT_WITH_CODE(table != NULL,
1733 "[FindHighestDPMLevel] DPM Table does not exist!",
1735 PP_ASSERT_WITH_CODE(table->count > 0,
1736 "[FindHighestDPMLevel] DPM Table has no entry!",
1738 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1739 "[FindHighestDPMLevel] DPM Table has too many entries!",
1740 return MAX_REGULAR_DPM_NUMBER - 1);
1742 for (i = table->count - 1; i >= 0; i--) {
1743 if (table->dpm_levels[i].enabled)
1748 table->dpm_levels[i].enabled = true;
1754 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1756 struct vega20_hwmgr *data =
1757 (struct vega20_hwmgr *)(hwmgr->backend);
1761 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1762 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1763 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1764 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1765 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1766 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1767 "Failed to set soft min gfxclk !",
1771 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1772 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1773 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1774 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1775 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1776 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1777 "Failed to set soft min memclk !",
1781 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1782 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1783 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1785 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1786 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1787 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1788 "Failed to set soft min vclk!",
1791 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1793 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1794 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1795 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1796 "Failed to set soft min dclk!",
1800 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1801 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1802 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1804 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1805 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1806 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1807 "Failed to set soft min eclk!",
1811 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1812 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1813 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1815 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1816 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1817 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1818 "Failed to set soft min socclk!",
1822 if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1823 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1824 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1826 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1827 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1828 (PPCLK_FCLK << 16) | (min_freq & 0xffff))),
1829 "Failed to set soft min fclk!",
1833 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1834 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1835 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1837 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1838 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1839 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
1840 "Failed to set hard min dcefclk!",
1847 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1849 struct vega20_hwmgr *data =
1850 (struct vega20_hwmgr *)(hwmgr->backend);
1854 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1855 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1856 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1858 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1859 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1860 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1861 "Failed to set soft max gfxclk!",
1865 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1866 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1867 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1869 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1870 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1871 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1872 "Failed to set soft max memclk!",
1876 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1877 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1878 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1880 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1881 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1882 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1883 "Failed to set soft max vclk!",
1886 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1887 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1888 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1889 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1890 "Failed to set soft max dclk!",
1894 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1895 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1896 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1898 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1899 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1900 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1901 "Failed to set soft max eclk!",
1905 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1906 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1907 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1909 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1910 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1911 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1912 "Failed to set soft max socclk!",
1916 if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1917 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1918 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1920 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1921 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1922 (PPCLK_FCLK << 16) | (max_freq & 0xffff))),
1923 "Failed to set soft max fclk!",
1930 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1932 struct vega20_hwmgr *data =
1933 (struct vega20_hwmgr *)(hwmgr->backend);
1936 if (data->smu_features[GNLD_DPM_VCE].supported) {
1937 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1939 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1941 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1944 ret = vega20_enable_smc_features(hwmgr,
1946 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1947 PP_ASSERT_WITH_CODE(!ret,
1948 "Attempt to Enable/Disable DPM VCE Failed!",
1950 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1956 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1958 PPCLK_e clock_select,
1965 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1966 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1967 "[GetClockRanges] Failed to get max clock from SMC!",
1969 *clock = smum_get_argument(hwmgr);
1971 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1972 PPSMC_MSG_GetMinDpmFreq,
1973 (clock_select << 16))) == 0,
1974 "[GetClockRanges] Failed to get min clock from SMC!",
1976 *clock = smum_get_argument(hwmgr);
1982 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1984 struct vega20_hwmgr *data =
1985 (struct vega20_hwmgr *)(hwmgr->backend);
1989 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1990 "[GetSclks]: gfxclk dpm not enabled!\n",
1994 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1995 PP_ASSERT_WITH_CODE(!ret,
1996 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1999 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2000 PP_ASSERT_WITH_CODE(!ret,
2001 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2005 return (gfx_clk * 100);
2008 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2010 struct vega20_hwmgr *data =
2011 (struct vega20_hwmgr *)(hwmgr->backend);
2015 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2016 "[MemMclks]: memclk dpm not enabled!\n",
2020 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2021 PP_ASSERT_WITH_CODE(!ret,
2022 "[GetMclks]: fail to get min PPCLK_UCLK\n",
2025 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2026 PP_ASSERT_WITH_CODE(!ret,
2027 "[GetMclks]: fail to get max PPCLK_UCLK\n",
2031 return (mem_clk * 100);
2034 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
2036 struct vega20_hwmgr *data =
2037 (struct vega20_hwmgr *)(hwmgr->backend);
2040 if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
2041 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
2042 TABLE_SMU_METRICS, true);
2044 pr_info("Failed to export SMU metrics table!\n");
2047 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
2048 data->metrics_time = jiffies;
2050 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2055 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
2059 SmuMetrics_t metrics_table;
2061 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2065 *query = metrics_table.CurrSocketPower << 8;
2070 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2071 PPCLK_e clk_id, uint32_t *clk_freq)
2077 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2078 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
2079 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2081 *clk_freq = smum_get_argument(hwmgr);
2083 *clk_freq = *clk_freq * 100;
2088 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2089 uint32_t *activity_percent)
2092 SmuMetrics_t metrics_table;
2094 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2098 *activity_percent = metrics_table.AverageGfxActivity;
2103 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2104 void *value, int *size)
2106 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2107 struct amdgpu_device *adev = hwmgr->adev;
2108 SmuMetrics_t metrics_table;
2113 case AMDGPU_PP_SENSOR_GFX_SCLK:
2114 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2118 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2121 case AMDGPU_PP_SENSOR_GFX_MCLK:
2122 ret = vega20_get_current_clk_freq(hwmgr,
2128 case AMDGPU_PP_SENSOR_GPU_LOAD:
2129 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
2133 case AMDGPU_PP_SENSOR_GPU_TEMP:
2134 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2137 case AMDGPU_PP_SENSOR_UVD_POWER:
2138 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2141 case AMDGPU_PP_SENSOR_VCE_POWER:
2142 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2145 case AMDGPU_PP_SENSOR_GPU_POWER:
2147 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2149 case AMDGPU_PP_SENSOR_VDDGFX:
2150 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2151 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2152 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2153 *((uint32_t *)value) =
2154 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2156 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2157 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2168 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2169 struct pp_display_clock_request *clock_req)
2172 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2173 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2174 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2175 PPCLK_e clk_select = 0;
2176 uint32_t clk_request = 0;
2178 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2180 case amd_pp_dcef_clock:
2181 clk_select = PPCLK_DCEFCLK;
2183 case amd_pp_disp_clock:
2184 clk_select = PPCLK_DISPCLK;
2186 case amd_pp_pixel_clock:
2187 clk_select = PPCLK_PIXCLK;
2189 case amd_pp_phy_clock:
2190 clk_select = PPCLK_PHYCLK;
2193 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2199 clk_request = (clk_select << 16) | clk_freq;
2200 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2201 PPSMC_MSG_SetHardMinByFreq,
2209 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2210 PHM_PerformanceLevelDesignation designation, uint32_t index,
2211 PHM_PerformanceLevel *level)
2216 static int vega20_notify_smc_display_config_after_ps_adjustment(
2217 struct pp_hwmgr *hwmgr)
2219 struct vega20_hwmgr *data =
2220 (struct vega20_hwmgr *)(hwmgr->backend);
2221 struct vega20_single_dpm_table *dpm_table =
2222 &data->dpm_table.mem_table;
2223 struct PP_Clocks min_clocks = {0};
2224 struct pp_display_clock_request clock_req;
2227 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2228 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2229 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2231 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2232 clock_req.clock_type = amd_pp_dcef_clock;
2233 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2234 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2235 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2236 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2237 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2238 min_clocks.dcefClockInSR / 100)) == 0,
2239 "Attempt to set divider for DCEFCLK Failed!",
2242 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2246 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2247 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2248 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2249 PPSMC_MSG_SetHardMinByFreq,
2250 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2251 "[SetHardMinFreq] Set hard min uclk failed!",
2258 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2260 struct vega20_hwmgr *data =
2261 (struct vega20_hwmgr *)(hwmgr->backend);
2262 uint32_t soft_level;
2265 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2267 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2268 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2269 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2271 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2273 data->dpm_table.mem_table.dpm_state.soft_min_level =
2274 data->dpm_table.mem_table.dpm_state.soft_max_level =
2275 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2277 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2279 data->dpm_table.soc_table.dpm_state.soft_min_level =
2280 data->dpm_table.soc_table.dpm_state.soft_max_level =
2281 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2283 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2284 PP_ASSERT_WITH_CODE(!ret,
2285 "Failed to upload boot level to highest!",
2288 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2289 PP_ASSERT_WITH_CODE(!ret,
2290 "Failed to upload dpm max level to highest!",
2296 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2298 struct vega20_hwmgr *data =
2299 (struct vega20_hwmgr *)(hwmgr->backend);
2300 uint32_t soft_level;
2303 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2305 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2306 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2307 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2309 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2311 data->dpm_table.mem_table.dpm_state.soft_min_level =
2312 data->dpm_table.mem_table.dpm_state.soft_max_level =
2313 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2315 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2317 data->dpm_table.soc_table.dpm_state.soft_min_level =
2318 data->dpm_table.soc_table.dpm_state.soft_max_level =
2319 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2321 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2322 PP_ASSERT_WITH_CODE(!ret,
2323 "Failed to upload boot level to highest!",
2326 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2327 PP_ASSERT_WITH_CODE(!ret,
2328 "Failed to upload dpm max level to highest!",
2335 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2339 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2340 PP_ASSERT_WITH_CODE(!ret,
2341 "Failed to upload DPM Bootup Levels!",
2344 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2345 PP_ASSERT_WITH_CODE(!ret,
2346 "Failed to upload DPM Max Levels!",
2352 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2353 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2355 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2356 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2357 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2358 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2364 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2365 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2366 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2367 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2368 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2369 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2372 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2374 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2376 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2377 *sclk_mask = gfx_dpm_table->count - 1;
2378 *mclk_mask = mem_dpm_table->count - 1;
2379 *soc_mask = soc_dpm_table->count - 1;
2385 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2386 enum pp_clock_type type, uint32_t mask)
2388 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2389 uint32_t soft_min_level, soft_max_level, hard_min_level;
2394 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2395 soft_max_level = mask ? (fls(mask) - 1) : 0;
2397 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2398 pr_err("Clock level specified %d is over max allowed %d\n",
2400 data->dpm_table.gfx_table.count - 1);
2404 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2405 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2406 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2407 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2409 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2410 PP_ASSERT_WITH_CODE(!ret,
2411 "Failed to upload boot level to lowest!",
2414 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2415 PP_ASSERT_WITH_CODE(!ret,
2416 "Failed to upload dpm max level to highest!",
2421 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2422 soft_max_level = mask ? (fls(mask) - 1) : 0;
2424 if (soft_max_level >= data->dpm_table.mem_table.count) {
2425 pr_err("Clock level specified %d is over max allowed %d\n",
2427 data->dpm_table.mem_table.count - 1);
2431 data->dpm_table.mem_table.dpm_state.soft_min_level =
2432 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2433 data->dpm_table.mem_table.dpm_state.soft_max_level =
2434 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2436 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2437 PP_ASSERT_WITH_CODE(!ret,
2438 "Failed to upload boot level to lowest!",
2441 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2442 PP_ASSERT_WITH_CODE(!ret,
2443 "Failed to upload dpm max level to highest!",
2449 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2450 soft_max_level = mask ? (fls(mask) - 1) : 0;
2452 if (soft_max_level >= data->dpm_table.soc_table.count) {
2453 pr_err("Clock level specified %d is over max allowed %d\n",
2455 data->dpm_table.soc_table.count - 1);
2459 data->dpm_table.soc_table.dpm_state.soft_min_level =
2460 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2461 data->dpm_table.soc_table.dpm_state.soft_max_level =
2462 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2464 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2465 PP_ASSERT_WITH_CODE(!ret,
2466 "Failed to upload boot level to lowest!",
2469 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2470 PP_ASSERT_WITH_CODE(!ret,
2471 "Failed to upload dpm max level to highest!",
2477 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2478 soft_max_level = mask ? (fls(mask) - 1) : 0;
2480 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2481 pr_err("Clock level specified %d is over max allowed %d\n",
2483 data->dpm_table.fclk_table.count - 1);
2487 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2488 data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2489 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2490 data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2492 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2493 PP_ASSERT_WITH_CODE(!ret,
2494 "Failed to upload boot level to lowest!",
2497 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2498 PP_ASSERT_WITH_CODE(!ret,
2499 "Failed to upload dpm max level to highest!",
2505 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2507 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2508 pr_err("Clock level specified %d is over max allowed %d\n",
2510 data->dpm_table.dcef_table.count - 1);
2514 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2515 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2517 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2518 PP_ASSERT_WITH_CODE(!ret,
2519 "Failed to upload boot level to lowest!",
2522 //TODO: Setting DCEFCLK max dpm level is not supported
2527 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2528 soft_max_level = mask ? (fls(mask) - 1) : 0;
2529 if (soft_min_level >= NUM_LINK_LEVELS ||
2530 soft_max_level >= NUM_LINK_LEVELS)
2533 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2534 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2535 PP_ASSERT_WITH_CODE(!ret,
2536 "Failed to set min link dpm level!",
2548 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2549 enum amd_dpm_forced_level level)
2552 uint32_t sclk_mask, mclk_mask, soc_mask;
2555 case AMD_DPM_FORCED_LEVEL_HIGH:
2556 ret = vega20_force_dpm_highest(hwmgr);
2559 case AMD_DPM_FORCED_LEVEL_LOW:
2560 ret = vega20_force_dpm_lowest(hwmgr);
2563 case AMD_DPM_FORCED_LEVEL_AUTO:
2564 ret = vega20_unforce_dpm_levels(hwmgr);
2567 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2568 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2569 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2570 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2571 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2574 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2575 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2576 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2579 case AMD_DPM_FORCED_LEVEL_MANUAL:
2580 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2588 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2590 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2592 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2593 return AMD_FAN_CTRL_MANUAL;
2595 return AMD_FAN_CTRL_AUTO;
2598 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2601 case AMD_FAN_CTRL_NONE:
2602 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2604 case AMD_FAN_CTRL_MANUAL:
2605 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2606 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2608 case AMD_FAN_CTRL_AUTO:
2609 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2610 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2617 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2618 struct amd_pp_simple_clock_info *info)
2621 struct phm_ppt_v2_information *table_info =
2622 (struct phm_ppt_v2_information *)hwmgr->pptable;
2623 struct phm_clock_and_voltage_limits *max_limits =
2624 &table_info->max_clock_voltage_on_ac;
2626 info->engine_max_clock = max_limits->sclk;
2627 info->memory_max_clock = max_limits->mclk;
2633 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2634 struct pp_clock_levels_with_latency *clocks)
2636 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2637 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2640 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2643 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2644 clocks->num_levels = count;
2646 for (i = 0; i < count; i++) {
2647 clocks->data[i].clocks_in_khz =
2648 dpm_table->dpm_levels[i].value * 1000;
2649 clocks->data[i].latency_in_us = 0;
2655 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2661 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2662 struct pp_clock_levels_with_latency *clocks)
2664 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2665 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2668 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2671 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2672 clocks->num_levels = data->mclk_latency_table.count = count;
2674 for (i = 0; i < count; i++) {
2675 clocks->data[i].clocks_in_khz =
2676 data->mclk_latency_table.entries[i].frequency =
2677 dpm_table->dpm_levels[i].value * 1000;
2678 clocks->data[i].latency_in_us =
2679 data->mclk_latency_table.entries[i].latency =
2680 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2686 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2687 struct pp_clock_levels_with_latency *clocks)
2689 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2690 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2693 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2696 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2697 clocks->num_levels = count;
2699 for (i = 0; i < count; i++) {
2700 clocks->data[i].clocks_in_khz =
2701 dpm_table->dpm_levels[i].value * 1000;
2702 clocks->data[i].latency_in_us = 0;
2708 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2709 struct pp_clock_levels_with_latency *clocks)
2711 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2712 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2715 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2718 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2719 clocks->num_levels = count;
2721 for (i = 0; i < count; i++) {
2722 clocks->data[i].clocks_in_khz =
2723 dpm_table->dpm_levels[i].value * 1000;
2724 clocks->data[i].latency_in_us = 0;
2731 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2732 enum amd_pp_clock_type type,
2733 struct pp_clock_levels_with_latency *clocks)
2738 case amd_pp_sys_clock:
2739 ret = vega20_get_sclks(hwmgr, clocks);
2741 case amd_pp_mem_clock:
2742 ret = vega20_get_memclocks(hwmgr, clocks);
2744 case amd_pp_dcef_clock:
2745 ret = vega20_get_dcefclocks(hwmgr, clocks);
2747 case amd_pp_soc_clock:
2748 ret = vega20_get_socclocks(hwmgr, clocks);
2757 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2758 enum amd_pp_clock_type type,
2759 struct pp_clock_levels_with_voltage *clocks)
2761 clocks->num_levels = 0;
2766 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2769 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2770 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2771 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2773 if (!data->registry_data.disable_water_mark &&
2774 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2775 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2776 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2777 data->water_marks_bitmap |= WaterMarksExist;
2778 data->water_marks_bitmap &= ~WaterMarksLoaded;
2784 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2785 enum PP_OD_DPM_TABLE_COMMAND type,
2786 long *input, uint32_t size)
2788 struct vega20_hwmgr *data =
2789 (struct vega20_hwmgr *)(hwmgr->backend);
2790 struct vega20_od8_single_setting *od8_settings =
2791 data->od8_settings.od8_settings_array;
2792 OverDriveTable_t *od_table =
2793 &(data->smc_state_table.overdrive_table);
2794 int32_t input_index, input_clk, input_vol, i;
2798 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2802 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2803 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2804 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2805 pr_info("Sclk min/max frequency overdrive not supported\n");
2809 for (i = 0; i < size; i += 2) {
2811 pr_info("invalid number of input parameters %d\n",
2816 input_index = input[i];
2817 input_clk = input[i + 1];
2819 if (input_index != 0 && input_index != 1) {
2820 pr_info("Invalid index %d\n", input_index);
2821 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2825 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2826 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2827 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2829 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2830 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2834 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2835 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2836 data->gfxclk_overdrive = true;
2838 if (input_index == 0)
2839 od_table->GfxclkFmin = input_clk;
2841 od_table->GfxclkFmax = input_clk;
2846 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2847 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2848 pr_info("Mclk max frequency overdrive not supported\n");
2852 for (i = 0; i < size; i += 2) {
2854 pr_info("invalid number of input parameters %d\n",
2859 input_index = input[i];
2860 input_clk = input[i + 1];
2862 if (input_index != 1) {
2863 pr_info("Invalid index %d\n", input_index);
2864 pr_info("Support max Mclk frequency setting only which index by 1\n");
2868 if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
2869 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2870 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2872 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
2873 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2877 if (input_index == 1 && od_table->UclkFmax != input_clk)
2878 data->memclk_overdrive = true;
2880 od_table->UclkFmax = input_clk;
2885 case PP_OD_EDIT_VDDC_CURVE:
2886 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2887 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2888 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2889 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2890 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2891 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2892 pr_info("Voltage curve calibrate not supported\n");
2896 for (i = 0; i < size; i += 3) {
2898 pr_info("invalid number of input parameters %d\n",
2903 input_index = input[i];
2904 input_clk = input[i + 1];
2905 input_vol = input[i + 2];
2907 if (input_index > 2) {
2908 pr_info("Setting for point %d is not supported\n",
2910 pr_info("Three supported points index by 0, 1, 2\n");
2914 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2915 if (input_clk < od8_settings[od8_id].min_value ||
2916 input_clk > od8_settings[od8_id].max_value) {
2917 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2919 od8_settings[od8_id].min_value,
2920 od8_settings[od8_id].max_value);
2924 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2925 if (input_vol < od8_settings[od8_id].min_value ||
2926 input_vol > od8_settings[od8_id].max_value) {
2927 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2929 od8_settings[od8_id].min_value,
2930 od8_settings[od8_id].max_value);
2934 switch (input_index) {
2936 od_table->GfxclkFreq1 = input_clk;
2937 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2940 od_table->GfxclkFreq2 = input_clk;
2941 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2944 od_table->GfxclkFreq3 = input_clk;
2945 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2951 case PP_OD_RESTORE_DEFAULT_TABLE:
2952 data->gfxclk_overdrive = false;
2953 data->memclk_overdrive = false;
2955 ret = smum_smc_table_manager(hwmgr,
2956 (uint8_t *)od_table,
2957 TABLE_OVERDRIVE, true);
2958 PP_ASSERT_WITH_CODE(!ret,
2959 "Failed to export overdrive table!",
2963 case PP_OD_COMMIT_DPM_TABLE:
2964 ret = smum_smc_table_manager(hwmgr,
2965 (uint8_t *)od_table,
2966 TABLE_OVERDRIVE, false);
2967 PP_ASSERT_WITH_CODE(!ret,
2968 "Failed to import overdrive table!",
2971 /* retrieve updated gfxclk table */
2972 if (data->gfxclk_overdrive) {
2973 data->gfxclk_overdrive = false;
2975 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2980 /* retrieve updated memclk table */
2981 if (data->memclk_overdrive) {
2982 data->memclk_overdrive = false;
2984 ret = vega20_setup_memclk_dpm_table(hwmgr);
2997 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2999 static const char *ppfeature_name[] = {
3033 static const char *output_title[] = {
3037 uint64_t features_enabled;
3042 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3043 PP_ASSERT_WITH_CODE(!ret,
3044 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3047 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3048 size += sprintf(buf + size, "%-19s %-22s %s\n",
3052 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3053 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
3056 (features_enabled & (1ULL << i)) ? "Y" : "N");
3062 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3064 uint64_t features_enabled;
3065 uint64_t features_to_enable;
3066 uint64_t features_to_disable;
3069 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3072 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3076 features_to_disable =
3077 features_enabled & ~new_ppfeature_masks;
3078 features_to_enable =
3079 ~features_enabled & new_ppfeature_masks;
3081 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3082 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3084 if (features_to_disable) {
3085 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3090 if (features_to_enable) {
3091 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3099 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3100 enum pp_clock_type type, char *buf)
3102 struct vega20_hwmgr *data =
3103 (struct vega20_hwmgr *)(hwmgr->backend);
3104 struct vega20_od8_single_setting *od8_settings =
3105 data->od8_settings.od8_settings_array;
3106 OverDriveTable_t *od_table =
3107 &(data->smc_state_table.overdrive_table);
3108 struct phm_ppt_v3_information *pptable_information =
3109 (struct phm_ppt_v3_information *)hwmgr->pptable;
3110 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
3111 struct amdgpu_device *adev = hwmgr->adev;
3112 struct pp_clock_levels_with_latency clocks;
3113 struct vega20_single_dpm_table *fclk_dpm_table =
3114 &(data->dpm_table.fclk_table);
3115 int i, now, size = 0;
3117 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3121 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3122 PP_ASSERT_WITH_CODE(!ret,
3123 "Attempt to get current gfx clk Failed!",
3126 if (vega20_get_sclks(hwmgr, &clocks)) {
3127 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3132 for (i = 0; i < clocks.num_levels; i++)
3133 size += sprintf(buf + size, "%d: %uMhz %s\n",
3134 i, clocks.data[i].clocks_in_khz / 1000,
3135 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3139 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3140 PP_ASSERT_WITH_CODE(!ret,
3141 "Attempt to get current mclk freq Failed!",
3144 if (vega20_get_memclocks(hwmgr, &clocks)) {
3145 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3150 for (i = 0; i < clocks.num_levels; i++)
3151 size += sprintf(buf + size, "%d: %uMhz %s\n",
3152 i, clocks.data[i].clocks_in_khz / 1000,
3153 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3157 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3158 PP_ASSERT_WITH_CODE(!ret,
3159 "Attempt to get current socclk freq Failed!",
3162 if (vega20_get_socclocks(hwmgr, &clocks)) {
3163 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3168 for (i = 0; i < clocks.num_levels; i++)
3169 size += sprintf(buf + size, "%d: %uMhz %s\n",
3170 i, clocks.data[i].clocks_in_khz / 1000,
3171 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3175 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3176 PP_ASSERT_WITH_CODE(!ret,
3177 "Attempt to get current fclk freq Failed!",
3180 for (i = 0; i < fclk_dpm_table->count; i++)
3181 size += sprintf(buf + size, "%d: %uMhz %s\n",
3182 i, fclk_dpm_table->dpm_levels[i].value,
3183 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3187 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3188 PP_ASSERT_WITH_CODE(!ret,
3189 "Attempt to get current dcefclk freq Failed!",
3192 if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3193 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3198 for (i = 0; i < clocks.num_levels; i++)
3199 size += sprintf(buf + size, "%d: %uMhz %s\n",
3200 i, clocks.data[i].clocks_in_khz / 1000,
3201 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3205 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3206 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3207 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3208 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3209 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3210 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3211 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3212 if (i == 1 && data->pcie_parameters_override) {
3213 gen_speed = data->pcie_gen_level1;
3214 lane_width = data->pcie_width_level1;
3216 gen_speed = pptable->PcieGenSpeed[i];
3217 lane_width = pptable->PcieLaneCount[i];
3219 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3220 (gen_speed == 0) ? "2.5GT/s," :
3221 (gen_speed == 1) ? "5.0GT/s," :
3222 (gen_speed == 2) ? "8.0GT/s," :
3223 (gen_speed == 3) ? "16.0GT/s," : "",
3224 (lane_width == 1) ? "x1" :
3225 (lane_width == 2) ? "x2" :
3226 (lane_width == 3) ? "x4" :
3227 (lane_width == 4) ? "x8" :
3228 (lane_width == 5) ? "x12" :
3229 (lane_width == 6) ? "x16" : "",
3230 pptable->LclkFreq[i],
3231 (current_gen_speed == gen_speed) &&
3232 (current_lane_width == lane_width) ?
3238 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3239 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3240 size = sprintf(buf, "%s:\n", "OD_SCLK");
3241 size += sprintf(buf + size, "0: %10uMhz\n",
3242 od_table->GfxclkFmin);
3243 size += sprintf(buf + size, "1: %10uMhz\n",
3244 od_table->GfxclkFmax);
3249 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3250 size = sprintf(buf, "%s:\n", "OD_MCLK");
3251 size += sprintf(buf + size, "1: %10uMhz\n",
3252 od_table->UclkFmax);
3258 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3259 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3260 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3261 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3262 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3263 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3264 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
3265 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3266 od_table->GfxclkFreq1,
3267 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3268 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3269 od_table->GfxclkFreq2,
3270 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3271 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3272 od_table->GfxclkFreq3,
3273 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3279 size = sprintf(buf, "%s:\n", "OD_RANGE");
3281 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3282 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3283 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3284 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3285 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3288 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3289 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3290 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3291 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3294 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3295 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3296 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3297 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3298 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3299 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3300 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3301 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3302 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3303 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3304 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3305 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3306 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3307 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3308 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3309 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3310 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3311 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3312 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3313 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3314 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3315 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3316 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3317 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3327 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3328 struct vega20_single_dpm_table *dpm_table)
3330 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3333 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3334 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3335 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3337 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3338 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3341 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3342 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3343 PPSMC_MSG_SetHardMinByFreq,
3344 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
3345 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3352 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3354 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3355 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3358 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3359 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3360 "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3362 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3363 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3366 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3367 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3368 PPSMC_MSG_SetSoftMinByFreq,
3369 (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level)),
3370 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3377 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3379 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3382 smum_send_msg_to_smc_with_parameter(hwmgr,
3383 PPSMC_MSG_NumOfDisplays, 0);
3385 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3386 &data->dpm_table.mem_table);
3390 return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3393 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3395 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3397 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3399 if ((data->water_marks_bitmap & WaterMarksExist) &&
3400 !(data->water_marks_bitmap & WaterMarksLoaded)) {
3401 result = smum_smc_table_manager(hwmgr,
3402 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3403 PP_ASSERT_WITH_CODE(!result,
3404 "Failed to update WMTABLE!",
3406 data->water_marks_bitmap |= WaterMarksLoaded;
3409 if ((data->water_marks_bitmap & WaterMarksExist) &&
3410 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3411 data->smu_features[GNLD_DPM_SOCCLK].supported) {
3412 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3413 PPSMC_MSG_NumOfDisplays,
3414 hwmgr->display_config->num_display);
3420 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3422 struct vega20_hwmgr *data =
3423 (struct vega20_hwmgr *)(hwmgr->backend);
3426 if (data->smu_features[GNLD_DPM_UVD].supported) {
3427 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3429 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3431 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3434 ret = vega20_enable_smc_features(hwmgr,
3436 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3437 PP_ASSERT_WITH_CODE(!ret,
3438 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3440 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3446 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3448 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3450 if (data->vce_power_gated == bgate)
3453 data->vce_power_gated = bgate;
3454 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3457 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3459 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3461 if (data->uvd_power_gated == bgate)
3464 data->uvd_power_gated = bgate;
3465 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3468 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3470 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3471 struct vega20_single_dpm_table *dpm_table;
3472 bool vblank_too_short = false;
3473 bool disable_mclk_switching;
3474 uint32_t i, latency;
3476 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3477 !hwmgr->display_config->multi_monitor_in_sync) ||
3479 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3482 dpm_table = &(data->dpm_table.gfx_table);
3483 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3484 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3485 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3486 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3488 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3489 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3490 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3491 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3494 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3495 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3496 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3499 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3500 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3501 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3506 dpm_table = &(data->dpm_table.mem_table);
3507 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3508 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3509 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3510 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3512 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3513 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3514 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3515 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3518 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3519 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3520 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3523 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3524 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3525 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3529 /* honour DAL's UCLK Hardmin */
3530 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3531 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3533 /* Hardmin is dependent on displayconfig */
3534 if (disable_mclk_switching) {
3535 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3536 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3537 if (data->mclk_latency_table.entries[i].latency <= latency) {
3538 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3539 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3546 if (hwmgr->display_config->nb_pstate_switch_disable)
3547 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3550 dpm_table = &(data->dpm_table.fclk_table);
3551 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3552 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3553 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3554 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3555 if (hwmgr->display_config->nb_pstate_switch_disable)
3556 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3559 dpm_table = &(data->dpm_table.vclk_table);
3560 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3561 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3562 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3563 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3565 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3566 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3567 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3568 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3571 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3572 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3573 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3578 dpm_table = &(data->dpm_table.dclk_table);
3579 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3580 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3581 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3582 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3584 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3585 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3586 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3587 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3590 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3591 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3592 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3597 dpm_table = &(data->dpm_table.soc_table);
3598 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3599 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3600 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3601 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3603 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3604 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3605 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3606 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3609 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3610 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3611 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3616 dpm_table = &(data->dpm_table.eclk_table);
3617 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3618 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3619 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3620 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3622 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3623 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3624 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3625 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3628 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3629 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3630 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3638 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3640 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3641 bool is_update_required = false;
3643 if (data->display_timing.num_existing_displays !=
3644 hwmgr->display_config->num_display)
3645 is_update_required = true;
3647 if (data->registry_data.gfx_clk_deep_sleep_support &&
3648 (data->display_timing.min_clock_in_sr !=
3649 hwmgr->display_config->min_core_set_clock_in_sr))
3650 is_update_required = true;
3652 return is_update_required;
3655 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3659 ret = vega20_disable_all_smu_features(hwmgr);
3660 PP_ASSERT_WITH_CODE(!ret,
3661 "[DisableDpmTasks] Failed to disable all smu features!",
3667 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3669 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3672 result = vega20_disable_dpm_tasks(hwmgr);
3673 PP_ASSERT_WITH_CODE((0 == result),
3674 "[PowerOffAsic] Failed to disable DPM!",
3676 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3681 static int conv_power_profile_to_pplib_workload(int power_profile)
3683 int pplib_workload = 0;
3685 switch (power_profile) {
3686 case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3687 pplib_workload = WORKLOAD_DEFAULT_BIT;
3689 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3690 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3692 case PP_SMC_POWER_PROFILE_POWERSAVING:
3693 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3695 case PP_SMC_POWER_PROFILE_VIDEO:
3696 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3698 case PP_SMC_POWER_PROFILE_VR:
3699 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3701 case PP_SMC_POWER_PROFILE_COMPUTE:
3702 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3704 case PP_SMC_POWER_PROFILE_CUSTOM:
3705 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3709 return pplib_workload;
3712 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3714 DpmActivityMonitorCoeffInt_t activity_monitor;
3715 uint32_t i, size = 0;
3716 uint16_t workload_type = 0;
3717 static const char *profile_name[] = {
3725 static const char *title[] = {
3726 "PROFILE_INDEX(NAME)",
3730 "MinActiveFreqType",
3735 "PD_Data_error_coeff",
3736 "PD_Data_error_rate_coeff"};
3742 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3743 title[0], title[1], title[2], title[3], title[4], title[5],
3744 title[6], title[7], title[8], title[9], title[10]);
3746 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3747 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3748 workload_type = conv_power_profile_to_pplib_workload(i);
3749 result = vega20_get_activity_monitor_coeff(hwmgr,
3750 (uint8_t *)(&activity_monitor), workload_type);
3751 PP_ASSERT_WITH_CODE(!result,
3752 "[GetPowerProfile] Failed to get activity monitor!",
3755 size += sprintf(buf + size, "%2d %14s%s:\n",
3756 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3758 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3762 activity_monitor.Gfx_FPS,
3763 activity_monitor.Gfx_UseRlcBusy,
3764 activity_monitor.Gfx_MinActiveFreqType,
3765 activity_monitor.Gfx_MinActiveFreq,
3766 activity_monitor.Gfx_BoosterFreqType,
3767 activity_monitor.Gfx_BoosterFreq,
3768 activity_monitor.Gfx_PD_Data_limit_c,
3769 activity_monitor.Gfx_PD_Data_error_coeff,
3770 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3772 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3776 activity_monitor.Soc_FPS,
3777 activity_monitor.Soc_UseRlcBusy,
3778 activity_monitor.Soc_MinActiveFreqType,
3779 activity_monitor.Soc_MinActiveFreq,
3780 activity_monitor.Soc_BoosterFreqType,
3781 activity_monitor.Soc_BoosterFreq,
3782 activity_monitor.Soc_PD_Data_limit_c,
3783 activity_monitor.Soc_PD_Data_error_coeff,
3784 activity_monitor.Soc_PD_Data_error_rate_coeff);
3786 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3790 activity_monitor.Mem_FPS,
3791 activity_monitor.Mem_UseRlcBusy,
3792 activity_monitor.Mem_MinActiveFreqType,
3793 activity_monitor.Mem_MinActiveFreq,
3794 activity_monitor.Mem_BoosterFreqType,
3795 activity_monitor.Mem_BoosterFreq,
3796 activity_monitor.Mem_PD_Data_limit_c,
3797 activity_monitor.Mem_PD_Data_error_coeff,
3798 activity_monitor.Mem_PD_Data_error_rate_coeff);
3800 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3804 activity_monitor.Fclk_FPS,
3805 activity_monitor.Fclk_UseRlcBusy,
3806 activity_monitor.Fclk_MinActiveFreqType,
3807 activity_monitor.Fclk_MinActiveFreq,
3808 activity_monitor.Fclk_BoosterFreqType,
3809 activity_monitor.Fclk_BoosterFreq,
3810 activity_monitor.Fclk_PD_Data_limit_c,
3811 activity_monitor.Fclk_PD_Data_error_coeff,
3812 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3818 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3820 DpmActivityMonitorCoeffInt_t activity_monitor;
3821 int workload_type, result = 0;
3823 hwmgr->power_profile_mode = input[size];
3825 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3826 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3830 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3834 result = vega20_get_activity_monitor_coeff(hwmgr,
3835 (uint8_t *)(&activity_monitor),
3836 WORKLOAD_PPLIB_CUSTOM_BIT);
3837 PP_ASSERT_WITH_CODE(!result,
3838 "[SetPowerProfile] Failed to get activity monitor!",
3842 case 0: /* Gfxclk */
3843 activity_monitor.Gfx_FPS = input[1];
3844 activity_monitor.Gfx_UseRlcBusy = input[2];
3845 activity_monitor.Gfx_MinActiveFreqType = input[3];
3846 activity_monitor.Gfx_MinActiveFreq = input[4];
3847 activity_monitor.Gfx_BoosterFreqType = input[5];
3848 activity_monitor.Gfx_BoosterFreq = input[6];
3849 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3850 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3851 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3853 case 1: /* Socclk */
3854 activity_monitor.Soc_FPS = input[1];
3855 activity_monitor.Soc_UseRlcBusy = input[2];
3856 activity_monitor.Soc_MinActiveFreqType = input[3];
3857 activity_monitor.Soc_MinActiveFreq = input[4];
3858 activity_monitor.Soc_BoosterFreqType = input[5];
3859 activity_monitor.Soc_BoosterFreq = input[6];
3860 activity_monitor.Soc_PD_Data_limit_c = input[7];
3861 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3862 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3865 activity_monitor.Mem_FPS = input[1];
3866 activity_monitor.Mem_UseRlcBusy = input[2];
3867 activity_monitor.Mem_MinActiveFreqType = input[3];
3868 activity_monitor.Mem_MinActiveFreq = input[4];
3869 activity_monitor.Mem_BoosterFreqType = input[5];
3870 activity_monitor.Mem_BoosterFreq = input[6];
3871 activity_monitor.Mem_PD_Data_limit_c = input[7];
3872 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3873 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3876 activity_monitor.Fclk_FPS = input[1];
3877 activity_monitor.Fclk_UseRlcBusy = input[2];
3878 activity_monitor.Fclk_MinActiveFreqType = input[3];
3879 activity_monitor.Fclk_MinActiveFreq = input[4];
3880 activity_monitor.Fclk_BoosterFreqType = input[5];
3881 activity_monitor.Fclk_BoosterFreq = input[6];
3882 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3883 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3884 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3888 result = vega20_set_activity_monitor_coeff(hwmgr,
3889 (uint8_t *)(&activity_monitor),
3890 WORKLOAD_PPLIB_CUSTOM_BIT);
3891 PP_ASSERT_WITH_CODE(!result,
3892 "[SetPowerProfile] Failed to set activity monitor!",
3896 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3898 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3899 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3900 1 << workload_type);
3905 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3906 uint32_t virtual_addr_low,
3907 uint32_t virtual_addr_hi,
3908 uint32_t mc_addr_low,
3909 uint32_t mc_addr_hi,
3912 smum_send_msg_to_smc_with_parameter(hwmgr,
3913 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3915 smum_send_msg_to_smc_with_parameter(hwmgr,
3916 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3918 smum_send_msg_to_smc_with_parameter(hwmgr,
3919 PPSMC_MSG_DramLogSetDramAddrHigh,
3922 smum_send_msg_to_smc_with_parameter(hwmgr,
3923 PPSMC_MSG_DramLogSetDramAddrLow,
3926 smum_send_msg_to_smc_with_parameter(hwmgr,
3927 PPSMC_MSG_DramLogSetDramSize,
3932 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3933 struct PP_TemperatureRange *thermal_data)
3935 struct phm_ppt_v3_information *pptable_information =
3936 (struct phm_ppt_v3_information *)hwmgr->pptable;
3938 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3940 thermal_data->max = pptable_information->us_software_shutdown_temp *
3941 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3946 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3947 /* init/fini related */
3948 .backend_init = vega20_hwmgr_backend_init,
3949 .backend_fini = vega20_hwmgr_backend_fini,
3950 .asic_setup = vega20_setup_asic_task,
3951 .power_off_asic = vega20_power_off_asic,
3952 .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3953 .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3954 /* power state related */
3955 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3956 .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3957 .display_config_changed = vega20_display_configuration_changed_task,
3958 .check_smc_update_required_for_display_configuration =
3959 vega20_check_smc_update_required_for_display_configuration,
3960 .notify_smc_display_config_after_ps_adjustment =
3961 vega20_notify_smc_display_config_after_ps_adjustment,
3963 .get_sclk = vega20_dpm_get_sclk,
3964 .get_mclk = vega20_dpm_get_mclk,
3965 .get_dal_power_level = vega20_get_dal_power_level,
3966 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3967 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3968 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3969 .display_clock_voltage_request = vega20_display_clock_voltage_request,
3970 .get_performance_level = vega20_get_performance_level,
3971 /* UMD pstate, profile related */
3972 .force_dpm_level = vega20_dpm_force_dpm_level,
3973 .get_power_profile_mode = vega20_get_power_profile_mode,
3974 .set_power_profile_mode = vega20_set_power_profile_mode,
3976 .set_power_limit = vega20_set_power_limit,
3977 .get_sclk_od = vega20_get_sclk_od,
3978 .set_sclk_od = vega20_set_sclk_od,
3979 .get_mclk_od = vega20_get_mclk_od,
3980 .set_mclk_od = vega20_set_mclk_od,
3981 .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3982 /* for sysfs to retrive/set gfxclk/memclk */
3983 .force_clock_level = vega20_force_clock_level,
3984 .print_clock_levels = vega20_print_clock_levels,
3985 .read_sensor = vega20_read_sensor,
3986 .get_ppfeature_status = vega20_get_ppfeature_status,
3987 .set_ppfeature_status = vega20_set_ppfeature_status,
3988 /* powergate related */
3989 .powergate_uvd = vega20_power_gate_uvd,
3990 .powergate_vce = vega20_power_gate_vce,
3991 /* thermal related */
3992 .start_thermal_controller = vega20_start_thermal_controller,
3993 .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3994 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3995 .register_irq_handlers = smu9_register_irq_handlers,
3996 .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3997 /* fan control related */
3998 .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3999 .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
4000 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4001 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4002 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4003 .get_fan_control_mode = vega20_get_fan_control_mode,
4004 .set_fan_control_mode = vega20_set_fan_control_mode,
4005 /* smu memory related */
4006 .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4007 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4009 .get_asic_baco_capability = vega20_baco_get_capability,
4010 .get_asic_baco_state = vega20_baco_get_state,
4011 .set_asic_baco_state = vega20_baco_set_state,
4014 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4016 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4017 hwmgr->pptable_func = &vega20_pptable_funcs;