2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
52 #include "nbio/nbio_7_4_sh_mask.h"
54 #define smnPCIE_LC_SPEED_CNTL 0x11140290
55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
57 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
59 struct vega20_hwmgr *data =
60 (struct vega20_hwmgr *)(hwmgr->backend);
62 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
63 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
64 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
65 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
66 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
68 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
69 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
83 * Disable the following features for now:
92 data->registry_data.disallowed_features = 0xE0041C00;
93 data->registry_data.od_state_in_dc_support = 0;
94 data->registry_data.thermal_support = 1;
95 data->registry_data.skip_baco_hardware = 0;
97 data->registry_data.log_avfs_param = 0;
98 data->registry_data.sclk_throttle_low_notification = 1;
99 data->registry_data.force_dpm_high = 0;
100 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
102 data->registry_data.didt_support = 0;
103 if (data->registry_data.didt_support) {
104 data->registry_data.didt_mode = 6;
105 data->registry_data.sq_ramping_support = 1;
106 data->registry_data.db_ramping_support = 0;
107 data->registry_data.td_ramping_support = 0;
108 data->registry_data.tcp_ramping_support = 0;
109 data->registry_data.dbr_ramping_support = 0;
110 data->registry_data.edc_didt_support = 1;
111 data->registry_data.gc_didt_support = 0;
112 data->registry_data.psm_didt_support = 0;
115 data->registry_data.pcie_lane_override = 0xff;
116 data->registry_data.pcie_speed_override = 0xff;
117 data->registry_data.pcie_clock_override = 0xffffffff;
118 data->registry_data.regulator_hot_gpio_support = 1;
119 data->registry_data.ac_dc_switch_gpio_support = 0;
120 data->registry_data.quick_transition_support = 0;
121 data->registry_data.zrpm_start_temp = 0xffff;
122 data->registry_data.zrpm_stop_temp = 0xffff;
123 data->registry_data.od8_feature_enable = 1;
124 data->registry_data.disable_water_mark = 0;
125 data->registry_data.disable_pp_tuning = 0;
126 data->registry_data.disable_xlpp_tuning = 0;
127 data->registry_data.disable_workload_policy = 0;
128 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
129 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
130 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
131 data->registry_data.force_workload_policy_mask = 0;
132 data->registry_data.disable_3d_fs_detection = 0;
133 data->registry_data.fps_support = 1;
134 data->registry_data.disable_auto_wattman = 1;
135 data->registry_data.auto_wattman_debug = 0;
136 data->registry_data.auto_wattman_sample_period = 100;
137 data->registry_data.fclk_gfxclk_ratio = 0;
138 data->registry_data.auto_wattman_threshold = 50;
139 data->registry_data.gfxoff_controlled_by_driver = 1;
140 data->gfxoff_allowed = false;
141 data->counter_gfxoff = 0;
144 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
146 struct vega20_hwmgr *data =
147 (struct vega20_hwmgr *)(hwmgr->backend);
148 struct amdgpu_device *adev = hwmgr->adev;
150 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
151 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
152 PHM_PlatformCaps_ControlVDDCI);
154 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
155 PHM_PlatformCaps_TablelessHardwareInterface);
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_EnableSMU7ThermalManagement);
160 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_UVDPowerGating);
164 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
165 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
166 PHM_PlatformCaps_VCEPowerGating);
168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
169 PHM_PlatformCaps_UnTabledHardwareInterface);
171 if (data->registry_data.od8_feature_enable)
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_OD8inACSupport);
175 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 PHM_PlatformCaps_ActivityReporting);
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_FanSpeedInTableIsRPM);
180 if (data->registry_data.od_state_in_dc_support) {
181 if (data->registry_data.od8_feature_enable)
182 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
183 PHM_PlatformCaps_OD8inDCSupport);
186 if (data->registry_data.thermal_support &&
187 data->registry_data.fuzzy_fan_control_support &&
188 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 PHM_PlatformCaps_ODFuzzyFanControlSupport);
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_DynamicPowerManagement);
194 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
195 PHM_PlatformCaps_SMC);
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_ThermalPolicyDelay);
199 if (data->registry_data.force_dpm_high)
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_DynamicUVDState);
206 if (data->registry_data.sclk_throttle_low_notification)
207 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_SclkThrottleLowNotification);
210 /* power tune caps */
211 /* assume disabled */
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_PowerContainment);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_DiDtSupport);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_SQRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_DBRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_TDRamping);
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_TCPRamping);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_DBRRamping);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_DiDtEDCEnable);
228 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_GCEDC);
230 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_PSM);
233 if (data->registry_data.didt_support) {
234 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_DiDtSupport);
236 if (data->registry_data.sq_ramping_support)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_SQRamping);
239 if (data->registry_data.db_ramping_support)
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_DBRamping);
242 if (data->registry_data.td_ramping_support)
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_TDRamping);
245 if (data->registry_data.tcp_ramping_support)
246 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_TCPRamping);
248 if (data->registry_data.dbr_ramping_support)
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
250 PHM_PlatformCaps_DBRRamping);
251 if (data->registry_data.edc_didt_support)
252 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
253 PHM_PlatformCaps_DiDtEDCEnable);
254 if (data->registry_data.gc_didt_support)
255 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
256 PHM_PlatformCaps_GCEDC);
257 if (data->registry_data.psm_didt_support)
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_PSM);
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_RegulatorHot);
265 if (data->registry_data.ac_dc_switch_gpio_support) {
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
267 PHM_PlatformCaps_AutomaticDCTransition);
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
272 if (data->registry_data.quick_transition_support) {
273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_AutomaticDCTransition);
275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 PHM_PlatformCaps_Falcon_QuickTransition);
281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
283 PHM_PlatformCaps_LowestUclkReservedForUlv);
284 if (data->lowest_uclk_reserved_for_ulv == 1)
285 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 PHM_PlatformCaps_LowestUclkReservedForUlv);
289 if (data->registry_data.custom_fan_support)
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_CustomFanControlSupport);
296 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
301 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
302 FEATURE_DPM_PREFETCHER_BIT;
303 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
304 FEATURE_DPM_GFXCLK_BIT;
305 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
306 FEATURE_DPM_UCLK_BIT;
307 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
308 FEATURE_DPM_SOCCLK_BIT;
309 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
311 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
313 data->smu_features[GNLD_ULV].smu_feature_id =
315 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
316 FEATURE_DPM_MP0CLK_BIT;
317 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
318 FEATURE_DPM_LINK_BIT;
319 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
320 FEATURE_DPM_DCEFCLK_BIT;
321 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
322 FEATURE_DS_GFXCLK_BIT;
323 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
324 FEATURE_DS_SOCCLK_BIT;
325 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
327 data->smu_features[GNLD_PPT].smu_feature_id =
329 data->smu_features[GNLD_TDC].smu_feature_id =
331 data->smu_features[GNLD_THERMAL].smu_feature_id =
333 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
334 FEATURE_GFX_PER_CU_CG_BIT;
335 data->smu_features[GNLD_RM].smu_feature_id =
337 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
338 FEATURE_DS_DCEFCLK_BIT;
339 data->smu_features[GNLD_ACDC].smu_feature_id =
341 data->smu_features[GNLD_VR0HOT].smu_feature_id =
343 data->smu_features[GNLD_VR1HOT].smu_feature_id =
345 data->smu_features[GNLD_FW_CTF].smu_feature_id =
347 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
348 FEATURE_LED_DISPLAY_BIT;
349 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
350 FEATURE_FAN_CONTROL_BIT;
351 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
352 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
353 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
354 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
355 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
356 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
357 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
358 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
360 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
361 data->smu_features[i].smu_feature_bitmap =
362 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
363 data->smu_features[i].allowed =
364 ((data->registry_data.disallowed_features >> i) & 1) ?
369 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
374 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
376 kfree(hwmgr->backend);
377 hwmgr->backend = NULL;
382 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
384 struct vega20_hwmgr *data;
385 struct amdgpu_device *adev = hwmgr->adev;
387 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
391 hwmgr->backend = data;
393 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
394 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
395 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
397 vega20_set_default_registry_data(hwmgr);
399 data->disable_dpm_mask = 0xff;
401 /* need to set voltage control types before EVV patching */
402 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
403 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
404 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
406 data->water_marks_bitmap = 0;
407 data->avfs_exist = false;
409 vega20_set_features_platform_caps(hwmgr);
411 vega20_init_dpm_defaults(hwmgr);
413 /* Parse pptable data read from VBIOS */
414 vega20_set_private_data_based_on_pptable(hwmgr);
416 data->is_tlu_enabled = false;
418 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
419 VEGA20_MAX_HARDWARE_POWERLEVELS;
420 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
421 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
423 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
424 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
425 hwmgr->platform_descriptor.clockStep.engineClock = 500;
426 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
428 data->total_active_cus = adev->gfx.cu_info.number;
433 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
435 struct vega20_hwmgr *data =
436 (struct vega20_hwmgr *)(hwmgr->backend);
438 data->low_sclk_interrupt_threshold = 0;
443 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
447 ret = vega20_init_sclk_threshold(hwmgr);
448 PP_ASSERT_WITH_CODE(!ret,
449 "Failed to init sclk threshold!",
456 * @fn vega20_init_dpm_state
457 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
459 * @param dpm_state - the address of the DPM Table to initiailize.
462 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
464 dpm_state->soft_min_level = 0x0;
465 dpm_state->soft_max_level = 0xffff;
466 dpm_state->hard_min_level = 0x0;
467 dpm_state->hard_max_level = 0xffff;
470 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
471 PPCLK_e clk_id, uint32_t *num_of_levels)
475 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
476 PPSMC_MSG_GetDpmFreqByIndex,
477 (clk_id << 16 | 0xFF));
478 PP_ASSERT_WITH_CODE(!ret,
479 "[GetNumOfDpmLevel] failed to get dpm levels!",
482 *num_of_levels = smum_get_argument(hwmgr);
483 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
484 "[GetNumOfDpmLevel] number of clk levels is invalid!",
490 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
491 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
495 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
496 PPSMC_MSG_GetDpmFreqByIndex,
497 (clk_id << 16 | index));
498 PP_ASSERT_WITH_CODE(!ret,
499 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
502 *clk = smum_get_argument(hwmgr);
503 PP_ASSERT_WITH_CODE(*clk,
504 "[GetDpmFreqByIndex] clk value is invalid!",
510 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
511 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
514 uint32_t i, num_of_levels, clk;
516 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
517 PP_ASSERT_WITH_CODE(!ret,
518 "[SetupSingleDpmTable] failed to get clk levels!",
521 dpm_table->count = num_of_levels;
523 for (i = 0; i < num_of_levels; i++) {
524 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
525 PP_ASSERT_WITH_CODE(!ret,
526 "[SetupSingleDpmTable] failed to get clk of specific level!",
528 dpm_table->dpm_levels[i].value = clk;
529 dpm_table->dpm_levels[i].enabled = true;
535 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
537 struct vega20_hwmgr *data =
538 (struct vega20_hwmgr *)(hwmgr->backend);
539 struct vega20_single_dpm_table *dpm_table;
542 dpm_table = &(data->dpm_table.gfx_table);
543 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
544 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
545 PP_ASSERT_WITH_CODE(!ret,
546 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
549 dpm_table->count = 1;
550 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
556 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
558 struct vega20_hwmgr *data =
559 (struct vega20_hwmgr *)(hwmgr->backend);
560 struct vega20_single_dpm_table *dpm_table;
563 dpm_table = &(data->dpm_table.mem_table);
564 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
565 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
566 PP_ASSERT_WITH_CODE(!ret,
567 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
570 dpm_table->count = 1;
571 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
578 * This function is to initialize all DPM state tables
579 * for SMU based on the dependency table.
580 * Dynamic state patching function will then trim these
581 * state tables to the allowed range based
582 * on the power policy or external client requests,
583 * such as UVD request, etc.
585 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
587 struct vega20_hwmgr *data =
588 (struct vega20_hwmgr *)(hwmgr->backend);
589 struct vega20_single_dpm_table *dpm_table;
592 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
595 dpm_table = &(data->dpm_table.soc_table);
596 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
597 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
598 PP_ASSERT_WITH_CODE(!ret,
599 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
602 dpm_table->count = 1;
603 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
605 vega20_init_dpm_state(&(dpm_table->dpm_state));
608 dpm_table = &(data->dpm_table.gfx_table);
609 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
612 vega20_init_dpm_state(&(dpm_table->dpm_state));
615 dpm_table = &(data->dpm_table.mem_table);
616 ret = vega20_setup_memclk_dpm_table(hwmgr);
619 vega20_init_dpm_state(&(dpm_table->dpm_state));
622 dpm_table = &(data->dpm_table.eclk_table);
623 if (data->smu_features[GNLD_DPM_VCE].enabled) {
624 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
625 PP_ASSERT_WITH_CODE(!ret,
626 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
629 dpm_table->count = 1;
630 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
632 vega20_init_dpm_state(&(dpm_table->dpm_state));
635 dpm_table = &(data->dpm_table.vclk_table);
636 if (data->smu_features[GNLD_DPM_UVD].enabled) {
637 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
638 PP_ASSERT_WITH_CODE(!ret,
639 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
642 dpm_table->count = 1;
643 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
645 vega20_init_dpm_state(&(dpm_table->dpm_state));
648 dpm_table = &(data->dpm_table.dclk_table);
649 if (data->smu_features[GNLD_DPM_UVD].enabled) {
650 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
651 PP_ASSERT_WITH_CODE(!ret,
652 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
655 dpm_table->count = 1;
656 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
658 vega20_init_dpm_state(&(dpm_table->dpm_state));
661 dpm_table = &(data->dpm_table.dcef_table);
662 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
663 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
664 PP_ASSERT_WITH_CODE(!ret,
665 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
668 dpm_table->count = 1;
669 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
671 vega20_init_dpm_state(&(dpm_table->dpm_state));
674 dpm_table = &(data->dpm_table.pixel_table);
675 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
676 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
677 PP_ASSERT_WITH_CODE(!ret,
678 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
681 dpm_table->count = 0;
682 vega20_init_dpm_state(&(dpm_table->dpm_state));
685 dpm_table = &(data->dpm_table.display_table);
686 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
687 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
688 PP_ASSERT_WITH_CODE(!ret,
689 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
692 dpm_table->count = 0;
693 vega20_init_dpm_state(&(dpm_table->dpm_state));
696 dpm_table = &(data->dpm_table.phy_table);
697 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
698 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
699 PP_ASSERT_WITH_CODE(!ret,
700 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
703 dpm_table->count = 0;
704 vega20_init_dpm_state(&(dpm_table->dpm_state));
707 dpm_table = &(data->dpm_table.fclk_table);
708 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
709 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
710 PP_ASSERT_WITH_CODE(!ret,
711 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
714 dpm_table->count = 0;
715 vega20_init_dpm_state(&(dpm_table->dpm_state));
717 /* save a copy of the default DPM table */
718 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
719 sizeof(struct vega20_dpm_table));
725 * Initializes the SMC table and uploads it
727 * @param hwmgr the address of the powerplay hardware manager.
728 * @param pInput the pointer to input data (PowerState)
731 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
734 struct vega20_hwmgr *data =
735 (struct vega20_hwmgr *)(hwmgr->backend);
736 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
737 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
738 struct phm_ppt_v3_information *pptable_information =
739 (struct phm_ppt_v3_information *)hwmgr->pptable;
741 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
742 PP_ASSERT_WITH_CODE(!result,
743 "[InitSMCTable] Failed to get vbios bootup values!",
746 data->vbios_boot_state.vddc = boot_up_values.usVddc;
747 data->vbios_boot_state.vddci = boot_up_values.usVddci;
748 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
749 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
750 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
751 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
752 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
753 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
754 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
755 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
756 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
758 smum_send_msg_to_smc_with_parameter(hwmgr,
759 PPSMC_MSG_SetMinDeepSleepDcefclk,
760 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
762 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
764 result = smum_smc_table_manager(hwmgr,
765 (uint8_t *)pp_table, TABLE_PPTABLE, false);
766 PP_ASSERT_WITH_CODE(!result,
767 "[InitSMCTable] Failed to upload PPtable!",
773 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
775 struct vega20_hwmgr *data =
776 (struct vega20_hwmgr *)(hwmgr->backend);
777 uint32_t allowed_features_low = 0, allowed_features_high = 0;
781 for (i = 0; i < GNLD_FEATURES_MAX; i++)
782 if (data->smu_features[i].allowed)
783 data->smu_features[i].smu_feature_id > 31 ?
784 (allowed_features_high |=
785 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
787 (allowed_features_low |=
788 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
791 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
792 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
793 PP_ASSERT_WITH_CODE(!ret,
794 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
797 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
799 PP_ASSERT_WITH_CODE(!ret,
800 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
806 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
808 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
811 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
813 struct vega20_hwmgr *data =
814 (struct vega20_hwmgr *)(hwmgr->backend);
815 uint64_t features_enabled;
820 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
821 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
822 "[EnableAllSMUFeatures] Failed to enable all smu features!",
825 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
826 PP_ASSERT_WITH_CODE(!ret,
827 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
830 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
831 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
833 data->smu_features[i].enabled = enabled;
834 data->smu_features[i].supported = enabled;
837 if (data->smu_features[i].allowed && !enabled)
838 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
839 else if (!data->smu_features[i].allowed && enabled)
840 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
847 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
849 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
851 if (data->smu_features[GNLD_DPM_UCLK].enabled)
852 return smum_send_msg_to_smc_with_parameter(hwmgr,
853 PPSMC_MSG_SetUclkFastSwitch,
859 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
861 struct vega20_hwmgr *data =
862 (struct vega20_hwmgr *)(hwmgr->backend);
864 return smum_send_msg_to_smc_with_parameter(hwmgr,
865 PPSMC_MSG_SetFclkGfxClkRatio,
866 data->registry_data.fclk_gfxclk_ratio);
869 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
871 struct vega20_hwmgr *data =
872 (struct vega20_hwmgr *)(hwmgr->backend);
873 uint64_t features_enabled;
878 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
879 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
880 "[DisableAllSMUFeatures] Failed to disable all smu features!",
883 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
884 PP_ASSERT_WITH_CODE(!ret,
885 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
888 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
889 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
891 data->smu_features[i].enabled = enabled;
892 data->smu_features[i].supported = enabled;
898 static int vega20_od8_set_feature_capabilities(
899 struct pp_hwmgr *hwmgr)
901 struct phm_ppt_v3_information *pptable_information =
902 (struct phm_ppt_v3_information *)hwmgr->pptable;
903 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
904 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
905 struct vega20_od8_settings *od_settings = &(data->od8_settings);
907 od_settings->overdrive8_capabilities = 0;
909 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
910 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
911 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
912 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
913 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
914 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
915 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
917 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
918 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
919 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
920 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
921 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
922 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
923 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
924 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
927 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
928 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
929 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
930 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
931 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
932 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
933 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
936 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
937 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
938 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
939 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
940 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
941 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
943 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
944 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
945 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
946 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
947 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
948 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
949 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
951 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
952 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
953 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
954 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
955 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
956 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
957 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
960 if (data->smu_features[GNLD_THERMAL].enabled) {
961 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
962 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
963 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
964 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
965 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
966 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
968 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
969 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
970 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
971 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
972 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
973 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
976 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
977 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
979 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
980 pp_table->FanZeroRpmEnable)
981 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
983 if (!od_settings->overdrive8_capabilities)
984 hwmgr->od_enabled = false;
989 static int vega20_od8_set_feature_id(
990 struct pp_hwmgr *hwmgr)
992 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
993 struct vega20_od8_settings *od_settings = &(data->od8_settings);
995 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
996 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
998 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1001 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1003 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1007 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1008 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1010 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1012 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1014 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1016 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1018 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1021 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1023 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1025 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1027 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1029 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1031 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1035 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1036 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1038 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1040 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1041 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1043 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1045 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1046 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1047 OD8_ACOUSTIC_LIMIT_SCLK;
1049 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1052 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1053 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1056 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1059 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1060 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1061 OD8_TEMPERATURE_FAN;
1063 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1066 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1067 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1068 OD8_TEMPERATURE_SYSTEM;
1070 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1076 static int vega20_od8_get_gfx_clock_base_voltage(
1077 struct pp_hwmgr *hwmgr,
1083 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1084 PPSMC_MSG_GetAVFSVoltageByDpm,
1085 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1086 PP_ASSERT_WITH_CODE(!ret,
1087 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1090 *voltage = smum_get_argument(hwmgr);
1091 *voltage = *voltage / VOLTAGE_SCALE;
1096 static int vega20_od8_initialize_default_settings(
1097 struct pp_hwmgr *hwmgr)
1099 struct phm_ppt_v3_information *pptable_information =
1100 (struct phm_ppt_v3_information *)hwmgr->pptable;
1101 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1102 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1103 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1106 /* Set Feature Capabilities */
1107 vega20_od8_set_feature_capabilities(hwmgr);
1109 /* Map FeatureID to individual settings */
1110 vega20_od8_set_feature_id(hwmgr);
1112 /* Set default values */
1113 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1114 PP_ASSERT_WITH_CODE(!ret,
1115 "Failed to export over drive table!",
1118 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1119 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1120 od_table->GfxclkFmin;
1121 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1122 od_table->GfxclkFmax;
1124 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1126 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1130 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1131 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1132 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1133 od_table->GfxclkFreq1;
1135 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1136 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1137 od_table->GfxclkFreq3;
1139 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1141 od_table->GfxclkFreq2;
1143 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1144 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1145 od_table->GfxclkFreq1),
1146 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1147 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1148 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1151 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1152 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1153 od_table->GfxclkFreq2),
1154 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1156 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1159 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1160 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1161 od_table->GfxclkFreq3),
1162 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1163 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1164 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1167 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1169 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1171 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1173 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1175 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1177 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1181 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1182 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1185 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1188 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1189 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1190 od_table->OverDrivePct;
1192 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1195 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1196 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1197 od_table->FanMaximumRpm;
1199 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1202 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1203 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1204 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1206 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1209 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1210 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1211 od_table->FanTargetTemperature;
1213 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1216 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1217 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1218 od_table->MaxOpTemp;
1220 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1223 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1224 if (od8_settings->od8_settings_array[i].feature_id) {
1225 od8_settings->od8_settings_array[i].min_value =
1226 pptable_information->od_settings_min[i];
1227 od8_settings->od8_settings_array[i].max_value =
1228 pptable_information->od_settings_max[i];
1229 od8_settings->od8_settings_array[i].current_value =
1230 od8_settings->od8_settings_array[i].default_value;
1232 od8_settings->od8_settings_array[i].min_value =
1234 od8_settings->od8_settings_array[i].max_value =
1236 od8_settings->od8_settings_array[i].current_value =
1241 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1242 PP_ASSERT_WITH_CODE(!ret,
1243 "Failed to import over drive table!",
1249 static int vega20_od8_set_settings(
1250 struct pp_hwmgr *hwmgr,
1254 OverDriveTable_t od_table;
1256 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1257 struct vega20_od8_single_setting *od8_settings =
1258 data->od8_settings.od8_settings_array;
1260 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1261 PP_ASSERT_WITH_CODE(!ret,
1262 "Failed to export over drive table!",
1266 case OD8_SETTING_GFXCLK_FMIN:
1267 od_table.GfxclkFmin = (uint16_t)value;
1269 case OD8_SETTING_GFXCLK_FMAX:
1270 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1271 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1274 od_table.GfxclkFmax = (uint16_t)value;
1276 case OD8_SETTING_GFXCLK_FREQ1:
1277 od_table.GfxclkFreq1 = (uint16_t)value;
1279 case OD8_SETTING_GFXCLK_VOLTAGE1:
1280 od_table.GfxclkVolt1 = (uint16_t)value;
1282 case OD8_SETTING_GFXCLK_FREQ2:
1283 od_table.GfxclkFreq2 = (uint16_t)value;
1285 case OD8_SETTING_GFXCLK_VOLTAGE2:
1286 od_table.GfxclkVolt2 = (uint16_t)value;
1288 case OD8_SETTING_GFXCLK_FREQ3:
1289 od_table.GfxclkFreq3 = (uint16_t)value;
1291 case OD8_SETTING_GFXCLK_VOLTAGE3:
1292 od_table.GfxclkVolt3 = (uint16_t)value;
1294 case OD8_SETTING_UCLK_FMAX:
1295 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1296 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1298 od_table.UclkFmax = (uint16_t)value;
1300 case OD8_SETTING_POWER_PERCENTAGE:
1301 od_table.OverDrivePct = (int16_t)value;
1303 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1304 od_table.FanMaximumRpm = (uint16_t)value;
1306 case OD8_SETTING_FAN_MIN_SPEED:
1307 od_table.FanMinimumPwm = (uint16_t)value;
1309 case OD8_SETTING_FAN_TARGET_TEMP:
1310 od_table.FanTargetTemperature = (uint16_t)value;
1312 case OD8_SETTING_OPERATING_TEMP_MAX:
1313 od_table.MaxOpTemp = (uint16_t)value;
1317 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1318 PP_ASSERT_WITH_CODE(!ret,
1319 "Failed to import over drive table!",
1325 static int vega20_get_sclk_od(
1326 struct pp_hwmgr *hwmgr)
1328 struct vega20_hwmgr *data = hwmgr->backend;
1329 struct vega20_single_dpm_table *sclk_table =
1330 &(data->dpm_table.gfx_table);
1331 struct vega20_single_dpm_table *golden_sclk_table =
1332 &(data->golden_dpm_table.gfx_table);
1333 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1334 int golden_value = golden_sclk_table->dpm_levels
1335 [golden_sclk_table->count - 1].value;
1338 value -= golden_value;
1339 value = DIV_ROUND_UP(value * 100, golden_value);
1344 static int vega20_set_sclk_od(
1345 struct pp_hwmgr *hwmgr, uint32_t value)
1347 struct vega20_hwmgr *data = hwmgr->backend;
1348 struct vega20_single_dpm_table *golden_sclk_table =
1349 &(data->golden_dpm_table.gfx_table);
1353 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1355 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1357 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1358 PP_ASSERT_WITH_CODE(!ret,
1359 "[SetSclkOD] failed to set od gfxclk!",
1362 /* retrieve updated gfxclk table */
1363 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1364 PP_ASSERT_WITH_CODE(!ret,
1365 "[SetSclkOD] failed to refresh gfxclk table!",
1371 static int vega20_get_mclk_od(
1372 struct pp_hwmgr *hwmgr)
1374 struct vega20_hwmgr *data = hwmgr->backend;
1375 struct vega20_single_dpm_table *mclk_table =
1376 &(data->dpm_table.mem_table);
1377 struct vega20_single_dpm_table *golden_mclk_table =
1378 &(data->golden_dpm_table.mem_table);
1379 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1380 int golden_value = golden_mclk_table->dpm_levels
1381 [golden_mclk_table->count - 1].value;
1384 value -= golden_value;
1385 value = DIV_ROUND_UP(value * 100, golden_value);
1390 static int vega20_set_mclk_od(
1391 struct pp_hwmgr *hwmgr, uint32_t value)
1393 struct vega20_hwmgr *data = hwmgr->backend;
1394 struct vega20_single_dpm_table *golden_mclk_table =
1395 &(data->golden_dpm_table.mem_table);
1399 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1401 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1403 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1404 PP_ASSERT_WITH_CODE(!ret,
1405 "[SetMclkOD] failed to set od memclk!",
1408 /* retrieve updated memclk table */
1409 ret = vega20_setup_memclk_dpm_table(hwmgr);
1410 PP_ASSERT_WITH_CODE(!ret,
1411 "[SetMclkOD] failed to refresh memclk table!",
1417 static int vega20_populate_umdpstate_clocks(
1418 struct pp_hwmgr *hwmgr)
1420 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1421 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1422 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1424 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1425 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1427 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1428 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1429 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1430 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1433 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1434 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1439 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1440 PP_Clock *clock, PPCLK_e clock_select)
1444 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1445 PPSMC_MSG_GetDcModeMaxDpmFreq,
1446 (clock_select << 16))) == 0,
1447 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1449 *clock = smum_get_argument(hwmgr);
1451 /* if DC limit is zero, return AC limit */
1453 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1454 PPSMC_MSG_GetMaxDpmFreq,
1455 (clock_select << 16))) == 0,
1456 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1458 *clock = smum_get_argument(hwmgr);
1464 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1466 struct vega20_hwmgr *data =
1467 (struct vega20_hwmgr *)(hwmgr->backend);
1468 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1469 &(data->max_sustainable_clocks);
1472 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1473 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1474 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1475 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1476 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1477 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1479 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1480 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1481 &(max_sustainable_clocks->uclock),
1483 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1486 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1487 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1488 &(max_sustainable_clocks->soc_clock),
1489 PPCLK_SOCCLK)) == 0,
1490 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1493 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1494 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1495 &(max_sustainable_clocks->dcef_clock),
1496 PPCLK_DCEFCLK)) == 0,
1497 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1499 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1500 &(max_sustainable_clocks->display_clock),
1501 PPCLK_DISPCLK)) == 0,
1502 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1504 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1505 &(max_sustainable_clocks->phy_clock),
1506 PPCLK_PHYCLK)) == 0,
1507 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1509 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1510 &(max_sustainable_clocks->pixel_clock),
1511 PPCLK_PIXCLK)) == 0,
1512 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1516 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1517 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1522 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1526 result = smum_send_msg_to_smc(hwmgr,
1527 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1528 PP_ASSERT_WITH_CODE(!result,
1529 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1535 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1537 struct vega20_hwmgr *data =
1538 (struct vega20_hwmgr *)(hwmgr->backend);
1540 data->uvd_power_gated = true;
1541 data->vce_power_gated = true;
1543 if (data->smu_features[GNLD_DPM_UVD].enabled)
1544 data->uvd_power_gated = false;
1546 if (data->smu_features[GNLD_DPM_VCE].enabled)
1547 data->vce_power_gated = false;
1550 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1554 smum_send_msg_to_smc_with_parameter(hwmgr,
1555 PPSMC_MSG_NumOfDisplays, 0);
1557 result = vega20_set_allowed_featuresmask(hwmgr);
1558 PP_ASSERT_WITH_CODE(!result,
1559 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1562 result = vega20_init_smc_table(hwmgr);
1563 PP_ASSERT_WITH_CODE(!result,
1564 "[EnableDPMTasks] Failed to initialize SMC table!",
1567 result = vega20_run_btc_afll(hwmgr);
1568 PP_ASSERT_WITH_CODE(!result,
1569 "[EnableDPMTasks] Failed to run btc afll!",
1572 result = vega20_enable_all_smu_features(hwmgr);
1573 PP_ASSERT_WITH_CODE(!result,
1574 "[EnableDPMTasks] Failed to enable all smu features!",
1577 result = vega20_notify_smc_display_change(hwmgr);
1578 PP_ASSERT_WITH_CODE(!result,
1579 "[EnableDPMTasks] Failed to notify smc display change!",
1582 result = vega20_send_clock_ratio(hwmgr);
1583 PP_ASSERT_WITH_CODE(!result,
1584 "[EnableDPMTasks] Failed to send clock ratio!",
1587 /* Initialize UVD/VCE powergating state */
1588 vega20_init_powergate_state(hwmgr);
1590 result = vega20_setup_default_dpm_tables(hwmgr);
1591 PP_ASSERT_WITH_CODE(!result,
1592 "[EnableDPMTasks] Failed to setup default DPM tables!",
1595 result = vega20_init_max_sustainable_clocks(hwmgr);
1596 PP_ASSERT_WITH_CODE(!result,
1597 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1600 result = vega20_power_control_set_level(hwmgr);
1601 PP_ASSERT_WITH_CODE(!result,
1602 "[EnableDPMTasks] Failed to power control set level!",
1605 result = vega20_od8_initialize_default_settings(hwmgr);
1606 PP_ASSERT_WITH_CODE(!result,
1607 "[EnableDPMTasks] Failed to initialize odn settings!",
1610 result = vega20_populate_umdpstate_clocks(hwmgr);
1611 PP_ASSERT_WITH_CODE(!result,
1612 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1615 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1616 POWER_SOURCE_AC << 16);
1617 PP_ASSERT_WITH_CODE(!result,
1618 "[GetPptLimit] get default PPT limit failed!",
1620 hwmgr->power_limit =
1621 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1626 static uint32_t vega20_find_lowest_dpm_level(
1627 struct vega20_single_dpm_table *table)
1631 for (i = 0; i < table->count; i++) {
1632 if (table->dpm_levels[i].enabled)
1635 if (i >= table->count) {
1637 table->dpm_levels[i].enabled = true;
1643 static uint32_t vega20_find_highest_dpm_level(
1644 struct vega20_single_dpm_table *table)
1648 PP_ASSERT_WITH_CODE(table != NULL,
1649 "[FindHighestDPMLevel] DPM Table does not exist!",
1651 PP_ASSERT_WITH_CODE(table->count > 0,
1652 "[FindHighestDPMLevel] DPM Table has no entry!",
1654 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1655 "[FindHighestDPMLevel] DPM Table has too many entries!",
1656 return MAX_REGULAR_DPM_NUMBER - 1);
1658 for (i = table->count - 1; i >= 0; i--) {
1659 if (table->dpm_levels[i].enabled)
1664 table->dpm_levels[i].enabled = true;
1670 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1672 struct vega20_hwmgr *data =
1673 (struct vega20_hwmgr *)(hwmgr->backend);
1677 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1678 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1679 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1680 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1681 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1682 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1683 "Failed to set soft min gfxclk !",
1687 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1688 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1689 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1690 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1691 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1692 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1693 "Failed to set soft min memclk !",
1697 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1698 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1699 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1701 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1702 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1703 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1704 "Failed to set soft min vclk!",
1707 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1709 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1710 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1711 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1712 "Failed to set soft min dclk!",
1716 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1717 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1718 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1720 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1721 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1722 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1723 "Failed to set soft min eclk!",
1727 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1728 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1729 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1731 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1732 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1733 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1734 "Failed to set soft min socclk!",
1741 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1743 struct vega20_hwmgr *data =
1744 (struct vega20_hwmgr *)(hwmgr->backend);
1748 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1749 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1750 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1752 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1753 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1754 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1755 "Failed to set soft max gfxclk!",
1759 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1760 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1761 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1763 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1764 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1765 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1766 "Failed to set soft max memclk!",
1770 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1771 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1772 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1774 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1775 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1776 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1777 "Failed to set soft max vclk!",
1780 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1781 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1782 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1783 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1784 "Failed to set soft max dclk!",
1788 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1789 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1790 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1792 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1793 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1794 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1795 "Failed to set soft max eclk!",
1799 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1800 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1801 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1803 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1804 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1805 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1806 "Failed to set soft max socclk!",
1813 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1815 struct vega20_hwmgr *data =
1816 (struct vega20_hwmgr *)(hwmgr->backend);
1819 if (data->smu_features[GNLD_DPM_VCE].supported) {
1820 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1822 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1824 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1827 ret = vega20_enable_smc_features(hwmgr,
1829 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1830 PP_ASSERT_WITH_CODE(!ret,
1831 "Attempt to Enable/Disable DPM VCE Failed!",
1833 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1839 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1841 PPCLK_e clock_select,
1848 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1849 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1850 "[GetClockRanges] Failed to get max clock from SMC!",
1852 *clock = smum_get_argument(hwmgr);
1854 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1855 PPSMC_MSG_GetMinDpmFreq,
1856 (clock_select << 16))) == 0,
1857 "[GetClockRanges] Failed to get min clock from SMC!",
1859 *clock = smum_get_argument(hwmgr);
1865 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1867 struct vega20_hwmgr *data =
1868 (struct vega20_hwmgr *)(hwmgr->backend);
1872 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1873 "[GetSclks]: gfxclk dpm not enabled!\n",
1877 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1878 PP_ASSERT_WITH_CODE(!ret,
1879 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1882 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1883 PP_ASSERT_WITH_CODE(!ret,
1884 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1888 return (gfx_clk * 100);
1891 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1893 struct vega20_hwmgr *data =
1894 (struct vega20_hwmgr *)(hwmgr->backend);
1898 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1899 "[MemMclks]: memclk dpm not enabled!\n",
1903 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1904 PP_ASSERT_WITH_CODE(!ret,
1905 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1908 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1909 PP_ASSERT_WITH_CODE(!ret,
1910 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1914 return (mem_clk * 100);
1917 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1921 SmuMetrics_t metrics_table;
1923 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1924 PP_ASSERT_WITH_CODE(!ret,
1925 "Failed to export SMU METRICS table!",
1928 *query = metrics_table.CurrSocketPower << 8;
1933 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1934 PPCLK_e clk_id, uint32_t *clk_freq)
1940 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1941 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1942 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1944 *clk_freq = smum_get_argument(hwmgr);
1946 *clk_freq = *clk_freq * 100;
1951 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1952 uint32_t *activity_percent)
1955 SmuMetrics_t metrics_table;
1957 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1958 PP_ASSERT_WITH_CODE(!ret,
1959 "Failed to export SMU METRICS table!",
1962 *activity_percent = metrics_table.AverageGfxActivity;
1967 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1968 void *value, int *size)
1970 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1971 struct amdgpu_device *adev = hwmgr->adev;
1976 case AMDGPU_PP_SENSOR_GFX_SCLK:
1977 ret = vega20_get_current_clk_freq(hwmgr,
1983 case AMDGPU_PP_SENSOR_GFX_MCLK:
1984 ret = vega20_get_current_clk_freq(hwmgr,
1990 case AMDGPU_PP_SENSOR_GPU_LOAD:
1991 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1995 case AMDGPU_PP_SENSOR_GPU_TEMP:
1996 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1999 case AMDGPU_PP_SENSOR_UVD_POWER:
2000 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2003 case AMDGPU_PP_SENSOR_VCE_POWER:
2004 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2007 case AMDGPU_PP_SENSOR_GPU_POWER:
2009 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2011 case AMDGPU_PP_SENSOR_VDDGFX:
2012 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2013 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2014 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2015 *((uint32_t *)value) =
2016 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2018 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2019 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2030 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2031 struct pp_display_clock_request *clock_req)
2034 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2035 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2036 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2037 PPCLK_e clk_select = 0;
2038 uint32_t clk_request = 0;
2040 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2042 case amd_pp_dcef_clock:
2043 clk_select = PPCLK_DCEFCLK;
2045 case amd_pp_disp_clock:
2046 clk_select = PPCLK_DISPCLK;
2048 case amd_pp_pixel_clock:
2049 clk_select = PPCLK_PIXCLK;
2051 case amd_pp_phy_clock:
2052 clk_select = PPCLK_PHYCLK;
2055 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2061 clk_request = (clk_select << 16) | clk_freq;
2062 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2063 PPSMC_MSG_SetHardMinByFreq,
2071 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2072 PHM_PerformanceLevelDesignation designation, uint32_t index,
2073 PHM_PerformanceLevel *level)
2078 static int vega20_notify_smc_display_config_after_ps_adjustment(
2079 struct pp_hwmgr *hwmgr)
2081 struct vega20_hwmgr *data =
2082 (struct vega20_hwmgr *)(hwmgr->backend);
2083 struct vega20_single_dpm_table *dpm_table =
2084 &data->dpm_table.mem_table;
2085 struct PP_Clocks min_clocks = {0};
2086 struct pp_display_clock_request clock_req;
2089 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2090 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2091 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2093 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2094 clock_req.clock_type = amd_pp_dcef_clock;
2095 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2096 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2097 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2098 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2099 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2100 min_clocks.dcefClockInSR / 100)) == 0,
2101 "Attempt to set divider for DCEFCLK Failed!",
2104 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2108 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2109 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2110 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2111 PPSMC_MSG_SetHardMinByFreq,
2112 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2113 "[SetHardMinFreq] Set hard min uclk failed!",
2120 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2122 struct vega20_hwmgr *data =
2123 (struct vega20_hwmgr *)(hwmgr->backend);
2124 uint32_t soft_level;
2127 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2129 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2130 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2131 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2133 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2135 data->dpm_table.mem_table.dpm_state.soft_min_level =
2136 data->dpm_table.mem_table.dpm_state.soft_max_level =
2137 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2139 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2140 PP_ASSERT_WITH_CODE(!ret,
2141 "Failed to upload boot level to highest!",
2144 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2145 PP_ASSERT_WITH_CODE(!ret,
2146 "Failed to upload dpm max level to highest!",
2152 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2154 struct vega20_hwmgr *data =
2155 (struct vega20_hwmgr *)(hwmgr->backend);
2156 uint32_t soft_level;
2159 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2161 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2162 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2163 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2165 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2167 data->dpm_table.mem_table.dpm_state.soft_min_level =
2168 data->dpm_table.mem_table.dpm_state.soft_max_level =
2169 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2171 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2172 PP_ASSERT_WITH_CODE(!ret,
2173 "Failed to upload boot level to highest!",
2176 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2177 PP_ASSERT_WITH_CODE(!ret,
2178 "Failed to upload dpm max level to highest!",
2185 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2189 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2190 PP_ASSERT_WITH_CODE(!ret,
2191 "Failed to upload DPM Bootup Levels!",
2194 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2195 PP_ASSERT_WITH_CODE(!ret,
2196 "Failed to upload DPM Max Levels!",
2202 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2203 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2205 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2206 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2207 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2208 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2214 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2215 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2216 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2217 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2218 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2219 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2222 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2224 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2226 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2227 *sclk_mask = gfx_dpm_table->count - 1;
2228 *mclk_mask = mem_dpm_table->count - 1;
2229 *soc_mask = soc_dpm_table->count - 1;
2235 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2236 enum pp_clock_type type, uint32_t mask)
2238 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2239 uint32_t soft_min_level, soft_max_level;
2244 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2245 soft_max_level = mask ? (fls(mask) - 1) : 0;
2247 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2248 pr_err("Clock level specified %d is over max allowed %d\n",
2250 data->dpm_table.gfx_table.count - 1);
2254 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2255 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2256 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2257 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2259 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2260 PP_ASSERT_WITH_CODE(!ret,
2261 "Failed to upload boot level to lowest!",
2264 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2265 PP_ASSERT_WITH_CODE(!ret,
2266 "Failed to upload dpm max level to highest!",
2271 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2272 soft_max_level = mask ? (fls(mask) - 1) : 0;
2274 if (soft_max_level >= data->dpm_table.mem_table.count) {
2275 pr_err("Clock level specified %d is over max allowed %d\n",
2277 data->dpm_table.mem_table.count - 1);
2281 data->dpm_table.mem_table.dpm_state.soft_min_level =
2282 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2283 data->dpm_table.mem_table.dpm_state.soft_max_level =
2284 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2286 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2287 PP_ASSERT_WITH_CODE(!ret,
2288 "Failed to upload boot level to lowest!",
2291 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2292 PP_ASSERT_WITH_CODE(!ret,
2293 "Failed to upload dpm max level to highest!",
2299 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2300 soft_max_level = mask ? (fls(mask) - 1) : 0;
2301 if (soft_min_level >= NUM_LINK_LEVELS ||
2302 soft_max_level >= NUM_LINK_LEVELS)
2305 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2306 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2307 PP_ASSERT_WITH_CODE(!ret,
2308 "Failed to set min link dpm level!",
2320 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2321 enum amd_dpm_forced_level level)
2324 uint32_t sclk_mask, mclk_mask, soc_mask;
2327 case AMD_DPM_FORCED_LEVEL_HIGH:
2328 ret = vega20_force_dpm_highest(hwmgr);
2331 case AMD_DPM_FORCED_LEVEL_LOW:
2332 ret = vega20_force_dpm_lowest(hwmgr);
2335 case AMD_DPM_FORCED_LEVEL_AUTO:
2336 ret = vega20_unforce_dpm_levels(hwmgr);
2339 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2340 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2341 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2342 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2343 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2346 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2347 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2350 case AMD_DPM_FORCED_LEVEL_MANUAL:
2351 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2359 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2361 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2363 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2364 return AMD_FAN_CTRL_MANUAL;
2366 return AMD_FAN_CTRL_AUTO;
2369 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2372 case AMD_FAN_CTRL_NONE:
2373 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2375 case AMD_FAN_CTRL_MANUAL:
2376 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2377 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2379 case AMD_FAN_CTRL_AUTO:
2380 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2381 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2388 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2389 struct amd_pp_simple_clock_info *info)
2392 struct phm_ppt_v2_information *table_info =
2393 (struct phm_ppt_v2_information *)hwmgr->pptable;
2394 struct phm_clock_and_voltage_limits *max_limits =
2395 &table_info->max_clock_voltage_on_ac;
2397 info->engine_max_clock = max_limits->sclk;
2398 info->memory_max_clock = max_limits->mclk;
2404 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2405 struct pp_clock_levels_with_latency *clocks)
2407 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2408 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2411 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2412 "[GetSclks]: gfxclk dpm not enabled!\n",
2415 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2416 clocks->num_levels = count;
2418 for (i = 0; i < count; i++) {
2419 clocks->data[i].clocks_in_khz =
2420 dpm_table->dpm_levels[i].value * 1000;
2421 clocks->data[i].latency_in_us = 0;
2427 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2433 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2434 struct pp_clock_levels_with_latency *clocks)
2436 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2437 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2440 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2441 "[GetMclks]: uclk dpm not enabled!\n",
2444 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2445 clocks->num_levels = data->mclk_latency_table.count = count;
2447 for (i = 0; i < count; i++) {
2448 clocks->data[i].clocks_in_khz =
2449 data->mclk_latency_table.entries[i].frequency =
2450 dpm_table->dpm_levels[i].value * 1000;
2451 clocks->data[i].latency_in_us =
2452 data->mclk_latency_table.entries[i].latency =
2453 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2459 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2460 struct pp_clock_levels_with_latency *clocks)
2462 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2463 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2466 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2467 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2470 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2471 clocks->num_levels = count;
2473 for (i = 0; i < count; i++) {
2474 clocks->data[i].clocks_in_khz =
2475 dpm_table->dpm_levels[i].value * 1000;
2476 clocks->data[i].latency_in_us = 0;
2482 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2483 struct pp_clock_levels_with_latency *clocks)
2485 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2486 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2489 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2490 "[GetSocclks]: socclk dpm not enabled!\n",
2493 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2494 clocks->num_levels = count;
2496 for (i = 0; i < count; i++) {
2497 clocks->data[i].clocks_in_khz =
2498 dpm_table->dpm_levels[i].value * 1000;
2499 clocks->data[i].latency_in_us = 0;
2506 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2507 enum amd_pp_clock_type type,
2508 struct pp_clock_levels_with_latency *clocks)
2513 case amd_pp_sys_clock:
2514 ret = vega20_get_sclks(hwmgr, clocks);
2516 case amd_pp_mem_clock:
2517 ret = vega20_get_memclocks(hwmgr, clocks);
2519 case amd_pp_dcef_clock:
2520 ret = vega20_get_dcefclocks(hwmgr, clocks);
2522 case amd_pp_soc_clock:
2523 ret = vega20_get_socclocks(hwmgr, clocks);
2532 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2533 enum amd_pp_clock_type type,
2534 struct pp_clock_levels_with_voltage *clocks)
2536 clocks->num_levels = 0;
2541 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2544 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2545 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2546 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2548 if (!data->registry_data.disable_water_mark &&
2549 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2550 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2551 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2552 data->water_marks_bitmap |= WaterMarksExist;
2553 data->water_marks_bitmap &= ~WaterMarksLoaded;
2559 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2560 enum PP_OD_DPM_TABLE_COMMAND type,
2561 long *input, uint32_t size)
2563 struct vega20_hwmgr *data =
2564 (struct vega20_hwmgr *)(hwmgr->backend);
2565 struct vega20_od8_single_setting *od8_settings =
2566 data->od8_settings.od8_settings_array;
2567 OverDriveTable_t *od_table =
2568 &(data->smc_state_table.overdrive_table);
2569 struct pp_clock_levels_with_latency clocks;
2570 int32_t input_index, input_clk, input_vol, i;
2574 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2578 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2579 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2580 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2581 pr_info("Sclk min/max frequency overdrive not supported\n");
2585 for (i = 0; i < size; i += 2) {
2587 pr_info("invalid number of input parameters %d\n",
2592 input_index = input[i];
2593 input_clk = input[i + 1];
2595 if (input_index != 0 && input_index != 1) {
2596 pr_info("Invalid index %d\n", input_index);
2597 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2601 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2602 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2603 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2605 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2606 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2610 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2611 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2612 data->gfxclk_overdrive = true;
2614 if (input_index == 0)
2615 od_table->GfxclkFmin = input_clk;
2617 od_table->GfxclkFmax = input_clk;
2622 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2623 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2624 pr_info("Mclk max frequency overdrive not supported\n");
2628 ret = vega20_get_memclocks(hwmgr, &clocks);
2629 PP_ASSERT_WITH_CODE(!ret,
2630 "Attempt to get memory clk levels failed!",
2633 for (i = 0; i < size; i += 2) {
2635 pr_info("invalid number of input parameters %d\n",
2640 input_index = input[i];
2641 input_clk = input[i + 1];
2643 if (input_index != 1) {
2644 pr_info("Invalid index %d\n", input_index);
2645 pr_info("Support max Mclk frequency setting only which index by 1\n");
2649 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2650 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2651 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2653 clocks.data[0].clocks_in_khz / 1000,
2654 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2658 if (input_index == 1 && od_table->UclkFmax != input_clk)
2659 data->memclk_overdrive = true;
2661 od_table->UclkFmax = input_clk;
2666 case PP_OD_EDIT_VDDC_CURVE:
2667 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2668 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2669 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2670 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2671 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2672 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2673 pr_info("Voltage curve calibrate not supported\n");
2677 for (i = 0; i < size; i += 3) {
2679 pr_info("invalid number of input parameters %d\n",
2684 input_index = input[i];
2685 input_clk = input[i + 1];
2686 input_vol = input[i + 2];
2688 if (input_index > 2) {
2689 pr_info("Setting for point %d is not supported\n",
2691 pr_info("Three supported points index by 0, 1, 2\n");
2695 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2696 if (input_clk < od8_settings[od8_id].min_value ||
2697 input_clk > od8_settings[od8_id].max_value) {
2698 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2700 od8_settings[od8_id].min_value,
2701 od8_settings[od8_id].max_value);
2705 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2706 if (input_vol < od8_settings[od8_id].min_value ||
2707 input_vol > od8_settings[od8_id].max_value) {
2708 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2710 od8_settings[od8_id].min_value,
2711 od8_settings[od8_id].max_value);
2715 switch (input_index) {
2717 od_table->GfxclkFreq1 = input_clk;
2718 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2721 od_table->GfxclkFreq2 = input_clk;
2722 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2725 od_table->GfxclkFreq3 = input_clk;
2726 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2732 case PP_OD_RESTORE_DEFAULT_TABLE:
2733 data->gfxclk_overdrive = false;
2734 data->memclk_overdrive = false;
2736 ret = smum_smc_table_manager(hwmgr,
2737 (uint8_t *)od_table,
2738 TABLE_OVERDRIVE, true);
2739 PP_ASSERT_WITH_CODE(!ret,
2740 "Failed to export overdrive table!",
2744 case PP_OD_COMMIT_DPM_TABLE:
2745 ret = smum_smc_table_manager(hwmgr,
2746 (uint8_t *)od_table,
2747 TABLE_OVERDRIVE, false);
2748 PP_ASSERT_WITH_CODE(!ret,
2749 "Failed to import overdrive table!",
2752 /* retrieve updated gfxclk table */
2753 if (data->gfxclk_overdrive) {
2754 data->gfxclk_overdrive = false;
2756 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2761 /* retrieve updated memclk table */
2762 if (data->memclk_overdrive) {
2763 data->memclk_overdrive = false;
2765 ret = vega20_setup_memclk_dpm_table(hwmgr);
2778 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2779 enum pp_clock_type type, char *buf)
2781 struct vega20_hwmgr *data =
2782 (struct vega20_hwmgr *)(hwmgr->backend);
2783 struct vega20_od8_single_setting *od8_settings =
2784 data->od8_settings.od8_settings_array;
2785 OverDriveTable_t *od_table =
2786 &(data->smc_state_table.overdrive_table);
2787 struct phm_ppt_v3_information *pptable_information =
2788 (struct phm_ppt_v3_information *)hwmgr->pptable;
2789 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
2790 struct amdgpu_device *adev = hwmgr->adev;
2791 struct pp_clock_levels_with_latency clocks;
2792 int i, now, size = 0;
2794 uint32_t gen_speed, lane_width;
2798 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2799 PP_ASSERT_WITH_CODE(!ret,
2800 "Attempt to get current gfx clk Failed!",
2803 ret = vega20_get_sclks(hwmgr, &clocks);
2804 PP_ASSERT_WITH_CODE(!ret,
2805 "Attempt to get gfx clk levels Failed!",
2808 for (i = 0; i < clocks.num_levels; i++)
2809 size += sprintf(buf + size, "%d: %uMhz %s\n",
2810 i, clocks.data[i].clocks_in_khz / 1000,
2811 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2815 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2816 PP_ASSERT_WITH_CODE(!ret,
2817 "Attempt to get current mclk freq Failed!",
2820 ret = vega20_get_memclocks(hwmgr, &clocks);
2821 PP_ASSERT_WITH_CODE(!ret,
2822 "Attempt to get memory clk levels Failed!",
2825 for (i = 0; i < clocks.num_levels; i++)
2826 size += sprintf(buf + size, "%d: %uMhz %s\n",
2827 i, clocks.data[i].clocks_in_khz / 1000,
2828 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2832 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2833 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2834 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2835 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2836 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2837 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2838 for (i = 0; i < NUM_LINK_LEVELS; i++)
2839 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
2840 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
2841 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
2842 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
2843 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
2844 (pptable->PcieLaneCount[i] == 1) ? "x1" :
2845 (pptable->PcieLaneCount[i] == 2) ? "x2" :
2846 (pptable->PcieLaneCount[i] == 3) ? "x4" :
2847 (pptable->PcieLaneCount[i] == 4) ? "x8" :
2848 (pptable->PcieLaneCount[i] == 5) ? "x12" :
2849 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
2850 pptable->LclkFreq[i],
2851 (gen_speed == pptable->PcieGenSpeed[i]) &&
2852 (lane_width == pptable->PcieLaneCount[i]) ?
2857 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2858 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2859 size = sprintf(buf, "%s:\n", "OD_SCLK");
2860 size += sprintf(buf + size, "0: %10uMhz\n",
2861 od_table->GfxclkFmin);
2862 size += sprintf(buf + size, "1: %10uMhz\n",
2863 od_table->GfxclkFmax);
2868 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2869 size = sprintf(buf, "%s:\n", "OD_MCLK");
2870 size += sprintf(buf + size, "1: %10uMhz\n",
2871 od_table->UclkFmax);
2877 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2878 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2879 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2880 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2881 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2882 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2883 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2884 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2885 od_table->GfxclkFreq1,
2886 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2887 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2888 od_table->GfxclkFreq2,
2889 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2890 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2891 od_table->GfxclkFreq3,
2892 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2898 size = sprintf(buf, "%s:\n", "OD_RANGE");
2900 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2901 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2902 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2903 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2904 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2907 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2908 ret = vega20_get_memclocks(hwmgr, &clocks);
2909 PP_ASSERT_WITH_CODE(!ret,
2910 "Fail to get memory clk levels!",
2913 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2914 clocks.data[0].clocks_in_khz / 1000,
2915 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2918 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2919 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2920 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2921 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2922 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2923 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2924 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2925 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2926 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2927 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2928 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2929 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2930 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2931 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2932 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2933 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2934 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2935 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2936 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2937 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2938 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2939 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2940 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2941 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2951 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2952 struct vega20_single_dpm_table *dpm_table)
2954 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2957 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2958 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2959 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2961 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2962 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2965 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2966 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2967 PPSMC_MSG_SetHardMinByFreq,
2968 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2969 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2976 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2978 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2981 smum_send_msg_to_smc_with_parameter(hwmgr,
2982 PPSMC_MSG_NumOfDisplays, 0);
2984 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2985 &data->dpm_table.mem_table);
2990 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2992 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2994 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2996 if ((data->water_marks_bitmap & WaterMarksExist) &&
2997 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2998 result = smum_smc_table_manager(hwmgr,
2999 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3000 PP_ASSERT_WITH_CODE(!result,
3001 "Failed to update WMTABLE!",
3003 data->water_marks_bitmap |= WaterMarksLoaded;
3006 if ((data->water_marks_bitmap & WaterMarksExist) &&
3007 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3008 data->smu_features[GNLD_DPM_SOCCLK].supported) {
3009 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3010 PPSMC_MSG_NumOfDisplays,
3011 hwmgr->display_config->num_display);
3017 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3019 struct vega20_hwmgr *data =
3020 (struct vega20_hwmgr *)(hwmgr->backend);
3023 if (data->smu_features[GNLD_DPM_UVD].supported) {
3024 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3026 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3028 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3031 ret = vega20_enable_smc_features(hwmgr,
3033 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3034 PP_ASSERT_WITH_CODE(!ret,
3035 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3037 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3043 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3045 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3047 if (data->vce_power_gated == bgate)
3050 data->vce_power_gated = bgate;
3051 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3054 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3056 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3058 if (data->uvd_power_gated == bgate)
3061 data->uvd_power_gated = bgate;
3062 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3065 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3067 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3068 struct vega20_single_dpm_table *dpm_table;
3069 bool vblank_too_short = false;
3070 bool disable_mclk_switching;
3071 uint32_t i, latency;
3073 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3074 !hwmgr->display_config->multi_monitor_in_sync) ||
3076 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3079 dpm_table = &(data->dpm_table.gfx_table);
3080 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3081 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3082 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3083 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3085 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3086 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3087 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3088 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3091 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3092 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3093 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3096 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3097 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3098 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3103 dpm_table = &(data->dpm_table.mem_table);
3104 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3105 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3106 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3107 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3109 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3110 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3111 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3112 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3115 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3116 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3117 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3120 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3121 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3122 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3126 /* honour DAL's UCLK Hardmin */
3127 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3128 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3130 /* Hardmin is dependent on displayconfig */
3131 if (disable_mclk_switching) {
3132 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3133 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3134 if (data->mclk_latency_table.entries[i].latency <= latency) {
3135 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3136 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3143 if (hwmgr->display_config->nb_pstate_switch_disable)
3144 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3147 dpm_table = &(data->dpm_table.vclk_table);
3148 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3149 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3150 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3151 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3153 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3154 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3155 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3156 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3159 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3160 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3161 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3166 dpm_table = &(data->dpm_table.dclk_table);
3167 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3168 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3169 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3170 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3172 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3173 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3174 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3175 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3178 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3179 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3180 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3185 dpm_table = &(data->dpm_table.soc_table);
3186 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3187 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3188 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3189 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3191 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3192 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3193 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3194 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3197 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3198 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3199 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3204 dpm_table = &(data->dpm_table.eclk_table);
3205 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3206 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3207 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3208 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3210 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3211 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3212 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3213 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3216 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3217 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3218 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3226 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3228 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3229 bool is_update_required = false;
3231 if (data->display_timing.num_existing_displays !=
3232 hwmgr->display_config->num_display)
3233 is_update_required = true;
3235 if (data->registry_data.gfx_clk_deep_sleep_support &&
3236 (data->display_timing.min_clock_in_sr !=
3237 hwmgr->display_config->min_core_set_clock_in_sr))
3238 is_update_required = true;
3240 return is_update_required;
3243 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3247 ret = vega20_disable_all_smu_features(hwmgr);
3248 PP_ASSERT_WITH_CODE(!ret,
3249 "[DisableDpmTasks] Failed to disable all smu features!",
3255 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3257 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3260 result = vega20_disable_dpm_tasks(hwmgr);
3261 PP_ASSERT_WITH_CODE((0 == result),
3262 "[PowerOffAsic] Failed to disable DPM!",
3264 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3269 static int conv_power_profile_to_pplib_workload(int power_profile)
3271 int pplib_workload = 0;
3273 switch (power_profile) {
3274 case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3275 pplib_workload = WORKLOAD_DEFAULT_BIT;
3277 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3278 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3280 case PP_SMC_POWER_PROFILE_POWERSAVING:
3281 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3283 case PP_SMC_POWER_PROFILE_VIDEO:
3284 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3286 case PP_SMC_POWER_PROFILE_VR:
3287 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3289 case PP_SMC_POWER_PROFILE_COMPUTE:
3290 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3292 case PP_SMC_POWER_PROFILE_CUSTOM:
3293 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3297 return pplib_workload;
3300 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3302 DpmActivityMonitorCoeffInt_t activity_monitor;
3303 uint32_t i, size = 0;
3304 uint16_t workload_type = 0;
3305 static const char *profile_name[] = {
3313 static const char *title[] = {
3314 "PROFILE_INDEX(NAME)",
3318 "MinActiveFreqType",
3323 "PD_Data_error_coeff",
3324 "PD_Data_error_rate_coeff"};
3330 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3331 title[0], title[1], title[2], title[3], title[4], title[5],
3332 title[6], title[7], title[8], title[9], title[10]);
3334 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3335 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3336 workload_type = conv_power_profile_to_pplib_workload(i);
3337 result = vega20_get_activity_monitor_coeff(hwmgr,
3338 (uint8_t *)(&activity_monitor), workload_type);
3339 PP_ASSERT_WITH_CODE(!result,
3340 "[GetPowerProfile] Failed to get activity monitor!",
3343 size += sprintf(buf + size, "%2d %14s%s:\n",
3344 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3346 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3350 activity_monitor.Gfx_FPS,
3351 activity_monitor.Gfx_UseRlcBusy,
3352 activity_monitor.Gfx_MinActiveFreqType,
3353 activity_monitor.Gfx_MinActiveFreq,
3354 activity_monitor.Gfx_BoosterFreqType,
3355 activity_monitor.Gfx_BoosterFreq,
3356 activity_monitor.Gfx_PD_Data_limit_c,
3357 activity_monitor.Gfx_PD_Data_error_coeff,
3358 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3360 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3364 activity_monitor.Soc_FPS,
3365 activity_monitor.Soc_UseRlcBusy,
3366 activity_monitor.Soc_MinActiveFreqType,
3367 activity_monitor.Soc_MinActiveFreq,
3368 activity_monitor.Soc_BoosterFreqType,
3369 activity_monitor.Soc_BoosterFreq,
3370 activity_monitor.Soc_PD_Data_limit_c,
3371 activity_monitor.Soc_PD_Data_error_coeff,
3372 activity_monitor.Soc_PD_Data_error_rate_coeff);
3374 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3378 activity_monitor.Mem_FPS,
3379 activity_monitor.Mem_UseRlcBusy,
3380 activity_monitor.Mem_MinActiveFreqType,
3381 activity_monitor.Mem_MinActiveFreq,
3382 activity_monitor.Mem_BoosterFreqType,
3383 activity_monitor.Mem_BoosterFreq,
3384 activity_monitor.Mem_PD_Data_limit_c,
3385 activity_monitor.Mem_PD_Data_error_coeff,
3386 activity_monitor.Mem_PD_Data_error_rate_coeff);
3388 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3392 activity_monitor.Fclk_FPS,
3393 activity_monitor.Fclk_UseRlcBusy,
3394 activity_monitor.Fclk_MinActiveFreqType,
3395 activity_monitor.Fclk_MinActiveFreq,
3396 activity_monitor.Fclk_BoosterFreqType,
3397 activity_monitor.Fclk_BoosterFreq,
3398 activity_monitor.Fclk_PD_Data_limit_c,
3399 activity_monitor.Fclk_PD_Data_error_coeff,
3400 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3406 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3408 DpmActivityMonitorCoeffInt_t activity_monitor;
3409 int workload_type, result = 0;
3411 hwmgr->power_profile_mode = input[size];
3413 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3414 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3418 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3422 result = vega20_get_activity_monitor_coeff(hwmgr,
3423 (uint8_t *)(&activity_monitor),
3424 WORKLOAD_PPLIB_CUSTOM_BIT);
3425 PP_ASSERT_WITH_CODE(!result,
3426 "[SetPowerProfile] Failed to get activity monitor!",
3430 case 0: /* Gfxclk */
3431 activity_monitor.Gfx_FPS = input[1];
3432 activity_monitor.Gfx_UseRlcBusy = input[2];
3433 activity_monitor.Gfx_MinActiveFreqType = input[3];
3434 activity_monitor.Gfx_MinActiveFreq = input[4];
3435 activity_monitor.Gfx_BoosterFreqType = input[5];
3436 activity_monitor.Gfx_BoosterFreq = input[6];
3437 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3438 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3439 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3441 case 1: /* Socclk */
3442 activity_monitor.Soc_FPS = input[1];
3443 activity_monitor.Soc_UseRlcBusy = input[2];
3444 activity_monitor.Soc_MinActiveFreqType = input[3];
3445 activity_monitor.Soc_MinActiveFreq = input[4];
3446 activity_monitor.Soc_BoosterFreqType = input[5];
3447 activity_monitor.Soc_BoosterFreq = input[6];
3448 activity_monitor.Soc_PD_Data_limit_c = input[7];
3449 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3450 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3453 activity_monitor.Mem_FPS = input[1];
3454 activity_monitor.Mem_UseRlcBusy = input[2];
3455 activity_monitor.Mem_MinActiveFreqType = input[3];
3456 activity_monitor.Mem_MinActiveFreq = input[4];
3457 activity_monitor.Mem_BoosterFreqType = input[5];
3458 activity_monitor.Mem_BoosterFreq = input[6];
3459 activity_monitor.Mem_PD_Data_limit_c = input[7];
3460 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3461 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3464 activity_monitor.Fclk_FPS = input[1];
3465 activity_monitor.Fclk_UseRlcBusy = input[2];
3466 activity_monitor.Fclk_MinActiveFreqType = input[3];
3467 activity_monitor.Fclk_MinActiveFreq = input[4];
3468 activity_monitor.Fclk_BoosterFreqType = input[5];
3469 activity_monitor.Fclk_BoosterFreq = input[6];
3470 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3471 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3472 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3476 result = vega20_set_activity_monitor_coeff(hwmgr,
3477 (uint8_t *)(&activity_monitor),
3478 WORKLOAD_PPLIB_CUSTOM_BIT);
3479 PP_ASSERT_WITH_CODE(!result,
3480 "[SetPowerProfile] Failed to set activity monitor!",
3484 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3486 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3487 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3488 1 << workload_type);
3493 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3494 uint32_t virtual_addr_low,
3495 uint32_t virtual_addr_hi,
3496 uint32_t mc_addr_low,
3497 uint32_t mc_addr_hi,
3500 smum_send_msg_to_smc_with_parameter(hwmgr,
3501 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3503 smum_send_msg_to_smc_with_parameter(hwmgr,
3504 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3506 smum_send_msg_to_smc_with_parameter(hwmgr,
3507 PPSMC_MSG_DramLogSetDramAddrHigh,
3510 smum_send_msg_to_smc_with_parameter(hwmgr,
3511 PPSMC_MSG_DramLogSetDramAddrLow,
3514 smum_send_msg_to_smc_with_parameter(hwmgr,
3515 PPSMC_MSG_DramLogSetDramSize,
3520 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3521 struct PP_TemperatureRange *thermal_data)
3523 struct phm_ppt_v3_information *pptable_information =
3524 (struct phm_ppt_v3_information *)hwmgr->pptable;
3526 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3528 thermal_data->max = pptable_information->us_software_shutdown_temp *
3529 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3534 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3535 /* init/fini related */
3536 .backend_init = vega20_hwmgr_backend_init,
3537 .backend_fini = vega20_hwmgr_backend_fini,
3538 .asic_setup = vega20_setup_asic_task,
3539 .power_off_asic = vega20_power_off_asic,
3540 .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3541 .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3542 /* power state related */
3543 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3544 .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3545 .display_config_changed = vega20_display_configuration_changed_task,
3546 .check_smc_update_required_for_display_configuration =
3547 vega20_check_smc_update_required_for_display_configuration,
3548 .notify_smc_display_config_after_ps_adjustment =
3549 vega20_notify_smc_display_config_after_ps_adjustment,
3551 .get_sclk = vega20_dpm_get_sclk,
3552 .get_mclk = vega20_dpm_get_mclk,
3553 .get_dal_power_level = vega20_get_dal_power_level,
3554 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3555 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3556 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3557 .display_clock_voltage_request = vega20_display_clock_voltage_request,
3558 .get_performance_level = vega20_get_performance_level,
3559 /* UMD pstate, profile related */
3560 .force_dpm_level = vega20_dpm_force_dpm_level,
3561 .get_power_profile_mode = vega20_get_power_profile_mode,
3562 .set_power_profile_mode = vega20_set_power_profile_mode,
3564 .set_power_limit = vega20_set_power_limit,
3565 .get_sclk_od = vega20_get_sclk_od,
3566 .set_sclk_od = vega20_set_sclk_od,
3567 .get_mclk_od = vega20_get_mclk_od,
3568 .set_mclk_od = vega20_set_mclk_od,
3569 .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3570 /* for sysfs to retrive/set gfxclk/memclk */
3571 .force_clock_level = vega20_force_clock_level,
3572 .print_clock_levels = vega20_print_clock_levels,
3573 .read_sensor = vega20_read_sensor,
3574 /* powergate related */
3575 .powergate_uvd = vega20_power_gate_uvd,
3576 .powergate_vce = vega20_power_gate_vce,
3577 /* thermal related */
3578 .start_thermal_controller = vega20_start_thermal_controller,
3579 .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3580 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3581 .register_irq_handlers = smu9_register_irq_handlers,
3582 .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3583 /* fan control related */
3584 .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3585 .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
3586 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
3587 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
3588 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
3589 .get_fan_control_mode = vega20_get_fan_control_mode,
3590 .set_fan_control_mode = vega20_set_fan_control_mode,
3591 /* smu memory related */
3592 .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
3593 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
3596 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3598 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3599 hwmgr->pptable_func = &vega20_pptable_funcs;