drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "vega20_baco.h"
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53 #include "nbio/nbio_7_4_sh_mask.h"
  54
  55 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  56 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  57
  58 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  59 {
  60         struct vega20_hwmgr *data =
  61                         (struct vega20_hwmgr *)(hwmgr->backend);
  62
  63         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  64         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  65         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  66         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  67         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  68
  69         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  70         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  78         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  81         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  82
  83         /*
  84          * Disable the following features for now:
  85          *   GFXCLK DS
  86          *   SOCLK DS
  87          *   LCLK DS
  88          *   DCEFCLK DS
  89          *   FCLK DS
  90          *   MP1CLK DS
  91          *   MP0CLK DS
  92          */
  93         data->registry_data.disallowed_features = 0xE0041C00;
  94         data->registry_data.od_state_in_dc_support = 0;
  95         data->registry_data.thermal_support = 1;
  96         data->registry_data.skip_baco_hardware = 0;
  97
  98         data->registry_data.log_avfs_param = 0;
  99         data->registry_data.sclk_throttle_low_notification = 1;
 100         data->registry_data.force_dpm_high = 0;
 101         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
 102
 103         data->registry_data.didt_support = 0;
 104         if (data->registry_data.didt_support) {
 105                 data->registry_data.didt_mode = 6;
 106                 data->registry_data.sq_ramping_support = 1;
 107                 data->registry_data.db_ramping_support = 0;
 108                 data->registry_data.td_ramping_support = 0;
 109                 data->registry_data.tcp_ramping_support = 0;
 110                 data->registry_data.dbr_ramping_support = 0;
 111                 data->registry_data.edc_didt_support = 1;
 112                 data->registry_data.gc_didt_support = 0;
 113                 data->registry_data.psm_didt_support = 0;
 114         }
 115
 116         data->registry_data.pcie_lane_override = 0xff;
 117         data->registry_data.pcie_speed_override = 0xff;
 118         data->registry_data.pcie_clock_override = 0xffffffff;
 119         data->registry_data.regulator_hot_gpio_support = 1;
 120         data->registry_data.ac_dc_switch_gpio_support = 0;
 121         data->registry_data.quick_transition_support = 0;
 122         data->registry_data.zrpm_start_temp = 0xffff;
 123         data->registry_data.zrpm_stop_temp = 0xffff;
 124         data->registry_data.od8_feature_enable = 1;
 125         data->registry_data.disable_water_mark = 0;
 126         data->registry_data.disable_pp_tuning = 0;
 127         data->registry_data.disable_xlpp_tuning = 0;
 128         data->registry_data.disable_workload_policy = 0;
 129         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 130         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 131         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 132         data->registry_data.force_workload_policy_mask = 0;
 133         data->registry_data.disable_3d_fs_detection = 0;
 134         data->registry_data.fps_support = 1;
 135         data->registry_data.disable_auto_wattman = 1;
 136         data->registry_data.auto_wattman_debug = 0;
 137         data->registry_data.auto_wattman_sample_period = 100;
 138         data->registry_data.fclk_gfxclk_ratio = 0;
 139         data->registry_data.auto_wattman_threshold = 50;
 140         data->registry_data.gfxoff_controlled_by_driver = 1;
 141         data->gfxoff_allowed = false;
 142         data->counter_gfxoff = 0;
 143 }
 144
 145 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 146 {
 147         struct vega20_hwmgr *data =
 148                         (struct vega20_hwmgr *)(hwmgr->backend);
 149         struct amdgpu_device *adev = hwmgr->adev;
 150
 151         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 152                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 153                                 PHM_PlatformCaps_ControlVDDCI);
 154
 155         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 156                         PHM_PlatformCaps_TablelessHardwareInterface);
 157
 158         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 159                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 160
 161         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 162                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 163                                 PHM_PlatformCaps_UVDPowerGating);
 164
 165         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 166                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 167                                 PHM_PlatformCaps_VCEPowerGating);
 168
 169         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 170                         PHM_PlatformCaps_UnTabledHardwareInterface);
 171
 172         if (data->registry_data.od8_feature_enable)
 173                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 174                                 PHM_PlatformCaps_OD8inACSupport);
 175
 176         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 177                         PHM_PlatformCaps_ActivityReporting);
 178         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 179                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 180
 181         if (data->registry_data.od_state_in_dc_support) {
 182                 if (data->registry_data.od8_feature_enable)
 183                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 184                                         PHM_PlatformCaps_OD8inDCSupport);
 185         }
 186
 187         if (data->registry_data.thermal_support &&
 188             data->registry_data.fuzzy_fan_control_support &&
 189             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 190                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 191                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 192
 193         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 194                         PHM_PlatformCaps_DynamicPowerManagement);
 195         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                         PHM_PlatformCaps_SMC);
 197         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 198                         PHM_PlatformCaps_ThermalPolicyDelay);
 199
 200         if (data->registry_data.force_dpm_high)
 201                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 202                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 203
 204         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_DynamicUVDState);
 206
 207         if (data->registry_data.sclk_throttle_low_notification)
 208                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 209                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 210
 211         /* power tune caps */
 212         /* assume disabled */
 213         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 214                         PHM_PlatformCaps_PowerContainment);
 215         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 216                         PHM_PlatformCaps_DiDtSupport);
 217         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 218                         PHM_PlatformCaps_SQRamping);
 219         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 220                         PHM_PlatformCaps_DBRamping);
 221         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 222                         PHM_PlatformCaps_TDRamping);
 223         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 224                         PHM_PlatformCaps_TCPRamping);
 225         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 226                         PHM_PlatformCaps_DBRRamping);
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                         PHM_PlatformCaps_DiDtEDCEnable);
 229         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 230                         PHM_PlatformCaps_GCEDC);
 231         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 232                         PHM_PlatformCaps_PSM);
 233
 234         if (data->registry_data.didt_support) {
 235                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 236                                 PHM_PlatformCaps_DiDtSupport);
 237                 if (data->registry_data.sq_ramping_support)
 238                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 239                                         PHM_PlatformCaps_SQRamping);
 240                 if (data->registry_data.db_ramping_support)
 241                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_DBRamping);
 243                 if (data->registry_data.td_ramping_support)
 244                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 245                                         PHM_PlatformCaps_TDRamping);
 246                 if (data->registry_data.tcp_ramping_support)
 247                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 248                                         PHM_PlatformCaps_TCPRamping);
 249                 if (data->registry_data.dbr_ramping_support)
 250                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 251                                         PHM_PlatformCaps_DBRRamping);
 252                 if (data->registry_data.edc_didt_support)
 253                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 254                                         PHM_PlatformCaps_DiDtEDCEnable);
 255                 if (data->registry_data.gc_didt_support)
 256                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 257                                         PHM_PlatformCaps_GCEDC);
 258                 if (data->registry_data.psm_didt_support)
 259                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 260                                         PHM_PlatformCaps_PSM);
 261         }
 262
 263         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 264                         PHM_PlatformCaps_RegulatorHot);
 265
 266         if (data->registry_data.ac_dc_switch_gpio_support) {
 267                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                 PHM_PlatformCaps_AutomaticDCTransition);
 269                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 270                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 271         }
 272
 273         if (data->registry_data.quick_transition_support) {
 274                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 275                                 PHM_PlatformCaps_AutomaticDCTransition);
 276                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 277                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 278                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 279                                 PHM_PlatformCaps_Falcon_QuickTransition);
 280         }
 281
 282         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 283                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 284                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 285                 if (data->lowest_uclk_reserved_for_ulv == 1)
 286                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 287                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 288         }
 289
 290         if (data->registry_data.custom_fan_support)
 291                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 292                                 PHM_PlatformCaps_CustomFanControlSupport);
 293
 294         return 0;
 295 }
 296
 297 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 298 {
 299         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 300         int i;
 301
 302         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 303                         FEATURE_DPM_PREFETCHER_BIT;
 304         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 305                         FEATURE_DPM_GFXCLK_BIT;
 306         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 307                         FEATURE_DPM_UCLK_BIT;
 308         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 309                         FEATURE_DPM_SOCCLK_BIT;
 310         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 311                         FEATURE_DPM_UVD_BIT;
 312         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 313                         FEATURE_DPM_VCE_BIT;
 314         data->smu_features[GNLD_ULV].smu_feature_id =
 315                         FEATURE_ULV_BIT;
 316         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 317                         FEATURE_DPM_MP0CLK_BIT;
 318         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 319                         FEATURE_DPM_LINK_BIT;
 320         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 321                         FEATURE_DPM_DCEFCLK_BIT;
 322         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 323                         FEATURE_DS_GFXCLK_BIT;
 324         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 325                         FEATURE_DS_SOCCLK_BIT;
 326         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 327                         FEATURE_DS_LCLK_BIT;
 328         data->smu_features[GNLD_PPT].smu_feature_id =
 329                         FEATURE_PPT_BIT;
 330         data->smu_features[GNLD_TDC].smu_feature_id =
 331                         FEATURE_TDC_BIT;
 332         data->smu_features[GNLD_THERMAL].smu_feature_id =
 333                         FEATURE_THERMAL_BIT;
 334         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 335                         FEATURE_GFX_PER_CU_CG_BIT;
 336         data->smu_features[GNLD_RM].smu_feature_id =
 337                         FEATURE_RM_BIT;
 338         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 339                         FEATURE_DS_DCEFCLK_BIT;
 340         data->smu_features[GNLD_ACDC].smu_feature_id =
 341                         FEATURE_ACDC_BIT;
 342         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 343                         FEATURE_VR0HOT_BIT;
 344         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 345                         FEATURE_VR1HOT_BIT;
 346         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 347                         FEATURE_FW_CTF_BIT;
 348         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 349                         FEATURE_LED_DISPLAY_BIT;
 350         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 351                         FEATURE_FAN_CONTROL_BIT;
 352         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 353         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 354         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 355         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 356         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 357         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 358         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 359         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 360
 361         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 362                 data->smu_features[i].smu_feature_bitmap =
 363                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 364                 data->smu_features[i].allowed =
 365                         ((data->registry_data.disallowed_features >> i) & 1) ?
 366                         false : true;
 367         }
 368 }
 369
 370 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 371 {
 372         return 0;
 373 }
 374
 375 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 376 {
 377         kfree(hwmgr->backend);
 378         hwmgr->backend = NULL;
 379
 380         return 0;
 381 }
 382
 383 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 384 {
 385         struct vega20_hwmgr *data;
 386         struct amdgpu_device *adev = hwmgr->adev;
 387
 388         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 389         if (data == NULL)
 390                 return -ENOMEM;
 391
 392         hwmgr->backend = data;
 393
 394         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 395         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 396         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 397
 398         vega20_set_default_registry_data(hwmgr);
 399
 400         data->disable_dpm_mask = 0xff;
 401
 402         /* need to set voltage control types before EVV patching */
 403         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 404         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 405         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 406
 407         data->water_marks_bitmap = 0;
 408         data->avfs_exist = false;
 409
 410         vega20_set_features_platform_caps(hwmgr);
 411
 412         vega20_init_dpm_defaults(hwmgr);
 413
 414         /* Parse pptable data read from VBIOS */
 415         vega20_set_private_data_based_on_pptable(hwmgr);
 416
 417         data->is_tlu_enabled = false;
 418
 419         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 420                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 421         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 422         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 423
 424         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 425         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 426         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 427         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 428
 429         data->total_active_cus = adev->gfx.cu_info.number;
 430
 431         return 0;
 432 }
 433
 434 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 435 {
 436         struct vega20_hwmgr *data =
 437                         (struct vega20_hwmgr *)(hwmgr->backend);
 438
 439         data->low_sclk_interrupt_threshold = 0;
 440
 441         return 0;
 442 }
 443
 444 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 445 {
 446         int ret = 0;
 447
 448         ret = vega20_init_sclk_threshold(hwmgr);
 449         PP_ASSERT_WITH_CODE(!ret,
 450                         "Failed to init sclk threshold!",
 451                         return ret);
 452
 453         return 0;
 454 }
 455
 456 /*
 457  * @fn vega20_init_dpm_state
 458  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 459  *
 460  * @param    dpm_state - the address of the DPM Table to initiailize.
 461  * @return   None.
 462  */
 463 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 464 {
 465         dpm_state->soft_min_level = 0x0;
 466         dpm_state->soft_max_level = 0xffff;
 467         dpm_state->hard_min_level = 0x0;
 468         dpm_state->hard_max_level = 0xffff;
 469 }
 470
 471 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 472                 PPCLK_e clk_id, uint32_t *num_of_levels)
 473 {
 474         int ret = 0;
 475
 476         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 477                         PPSMC_MSG_GetDpmFreqByIndex,
 478                         (clk_id << 16 | 0xFF));
 479         PP_ASSERT_WITH_CODE(!ret,
 480                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 481                         return ret);
 482
 483         *num_of_levels = smum_get_argument(hwmgr);
 484         PP_ASSERT_WITH_CODE(*num_of_levels > 0,
 485                         "[GetNumOfDpmLevel] number of clk levels is invalid!",
 486                         return -EINVAL);
 487
 488         return ret;
 489 }
 490
 491 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 492                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 493 {
 494         int ret = 0;
 495
 496         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 497                         PPSMC_MSG_GetDpmFreqByIndex,
 498                         (clk_id << 16 | index));
 499         PP_ASSERT_WITH_CODE(!ret,
 500                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 501                         return ret);
 502
 503         *clk = smum_get_argument(hwmgr);
 504         PP_ASSERT_WITH_CODE(*clk,
 505                         "[GetDpmFreqByIndex] clk value is invalid!",
 506                         return -EINVAL);
 507
 508         return ret;
 509 }
 510
 511 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 512                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 513 {
 514         int ret = 0;
 515         uint32_t i, num_of_levels, clk;
 516
 517         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 518         PP_ASSERT_WITH_CODE(!ret,
 519                         "[SetupSingleDpmTable] failed to get clk levels!",
 520                         return ret);
 521
 522         dpm_table->count = num_of_levels;
 523
 524         for (i = 0; i < num_of_levels; i++) {
 525                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 526                 PP_ASSERT_WITH_CODE(!ret,
 527                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 528                         return ret);
 529                 dpm_table->dpm_levels[i].value = clk;
 530                 dpm_table->dpm_levels[i].enabled = true;
 531         }
 532
 533         return ret;
 534 }
 535
 536 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 537 {
 538         struct vega20_hwmgr *data =
 539                         (struct vega20_hwmgr *)(hwmgr->backend);
 540         struct vega20_single_dpm_table *dpm_table;
 541         int ret = 0;
 542
 543         dpm_table = &(data->dpm_table.gfx_table);
 544         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 545                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 546                 PP_ASSERT_WITH_CODE(!ret,
 547                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 548                                 return ret);
 549         } else {
 550                 dpm_table->count = 1;
 551                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 552         }
 553
 554         return ret;
 555 }
 556
 557 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 558 {
 559         struct vega20_hwmgr *data =
 560                         (struct vega20_hwmgr *)(hwmgr->backend);
 561         struct vega20_single_dpm_table *dpm_table;
 562         int ret = 0;
 563
 564         dpm_table = &(data->dpm_table.mem_table);
 565         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 566                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 567                 PP_ASSERT_WITH_CODE(!ret,
 568                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 569                                 return ret);
 570         } else {
 571                 dpm_table->count = 1;
 572                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 573         }
 574
 575         return ret;
 576 }
 577
 578 /*
 579  * This function is to initialize all DPM state tables
 580  * for SMU based on the dependency table.
 581  * Dynamic state patching function will then trim these
 582  * state tables to the allowed range based
 583  * on the power policy or external client requests,
 584  * such as UVD request, etc.
 585  */
 586 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 587 {
 588         struct vega20_hwmgr *data =
 589                         (struct vega20_hwmgr *)(hwmgr->backend);
 590         struct vega20_single_dpm_table *dpm_table;
 591         int ret = 0;
 592
 593         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 594
 595         /* socclk */
 596         dpm_table = &(data->dpm_table.soc_table);
 597         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 598                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 599                 PP_ASSERT_WITH_CODE(!ret,
 600                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 601                                 return ret);
 602         } else {
 603                 dpm_table->count = 1;
 604                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 605         }
 606         vega20_init_dpm_state(&(dpm_table->dpm_state));
 607
 608         /* gfxclk */
 609         dpm_table = &(data->dpm_table.gfx_table);
 610         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 611         if (ret)
 612                 return ret;
 613         vega20_init_dpm_state(&(dpm_table->dpm_state));
 614
 615         /* memclk */
 616         dpm_table = &(data->dpm_table.mem_table);
 617         ret = vega20_setup_memclk_dpm_table(hwmgr);
 618         if (ret)
 619                 return ret;
 620         vega20_init_dpm_state(&(dpm_table->dpm_state));
 621
 622         /* eclk */
 623         dpm_table = &(data->dpm_table.eclk_table);
 624         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 625                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 626                 PP_ASSERT_WITH_CODE(!ret,
 627                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 628                                 return ret);
 629         } else {
 630                 dpm_table->count = 1;
 631                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 632         }
 633         vega20_init_dpm_state(&(dpm_table->dpm_state));
 634
 635         /* vclk */
 636         dpm_table = &(data->dpm_table.vclk_table);
 637         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 638                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 639                 PP_ASSERT_WITH_CODE(!ret,
 640                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 641                                 return ret);
 642         } else {
 643                 dpm_table->count = 1;
 644                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 645         }
 646         vega20_init_dpm_state(&(dpm_table->dpm_state));
 647
 648         /* dclk */
 649         dpm_table = &(data->dpm_table.dclk_table);
 650         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 651                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 652                 PP_ASSERT_WITH_CODE(!ret,
 653                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 654                                 return ret);
 655         } else {
 656                 dpm_table->count = 1;
 657                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 658         }
 659         vega20_init_dpm_state(&(dpm_table->dpm_state));
 660
 661         /* dcefclk */
 662         dpm_table = &(data->dpm_table.dcef_table);
 663         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 664                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 665                 PP_ASSERT_WITH_CODE(!ret,
 666                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 667                                 return ret);
 668         } else {
 669                 dpm_table->count = 1;
 670                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 671         }
 672         vega20_init_dpm_state(&(dpm_table->dpm_state));
 673
 674         /* pixclk */
 675         dpm_table = &(data->dpm_table.pixel_table);
 676         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 677                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 678                 PP_ASSERT_WITH_CODE(!ret,
 679                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 680                                 return ret);
 681         } else
 682                 dpm_table->count = 0;
 683         vega20_init_dpm_state(&(dpm_table->dpm_state));
 684
 685         /* dispclk */
 686         dpm_table = &(data->dpm_table.display_table);
 687         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 688                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 689                 PP_ASSERT_WITH_CODE(!ret,
 690                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 691                                 return ret);
 692         } else
 693                 dpm_table->count = 0;
 694         vega20_init_dpm_state(&(dpm_table->dpm_state));
 695
 696         /* phyclk */
 697         dpm_table = &(data->dpm_table.phy_table);
 698         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 699                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 700                 PP_ASSERT_WITH_CODE(!ret,
 701                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 702                                 return ret);
 703         } else
 704                 dpm_table->count = 0;
 705         vega20_init_dpm_state(&(dpm_table->dpm_state));
 706
 707         /* fclk */
 708         dpm_table = &(data->dpm_table.fclk_table);
 709         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 710                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 711                 PP_ASSERT_WITH_CODE(!ret,
 712                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 713                                 return ret);
 714         } else
 715                 dpm_table->count = 0;
 716         vega20_init_dpm_state(&(dpm_table->dpm_state));
 717
 718         /* save a copy of the default DPM table */
 719         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 720                         sizeof(struct vega20_dpm_table));
 721
 722         return 0;
 723 }
 724
 725 /**
 726 * Initializes the SMC table and uploads it
 727 *
 728 * @param    hwmgr  the address of the powerplay hardware manager.
 729 * @param    pInput  the pointer to input data (PowerState)
 730 * @return   always 0
 731 */
 732 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 733 {
 734         int result;
 735         struct vega20_hwmgr *data =
 736                         (struct vega20_hwmgr *)(hwmgr->backend);
 737         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 738         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 739         struct phm_ppt_v3_information *pptable_information =
 740                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 741
 742         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 743         PP_ASSERT_WITH_CODE(!result,
 744                         "[InitSMCTable] Failed to get vbios bootup values!",
 745                         return result);
 746
 747         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 748         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 749         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 750         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 751         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 752         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 753         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 754         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 755         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 756         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 757         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 758
 759         smum_send_msg_to_smc_with_parameter(hwmgr,
 760                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 761                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 762
 763         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 764
 765         result = smum_smc_table_manager(hwmgr,
 766                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 767         PP_ASSERT_WITH_CODE(!result,
 768                         "[InitSMCTable] Failed to upload PPtable!",
 769                         return result);
 770
 771         return 0;
 772 }
 773
 774 /*
 775  * Override PCIe link speed and link width for DPM Level 1. PPTable entries
 776  * reflect the ASIC capabilities and not the system capabilities. For e.g.
 777  * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
 778  * to DPM1, it fails as system doesn't support Gen4.
 779  */
 780 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 781 {
 782         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 783         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 784         int ret;
 785
 786         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 787                 pcie_gen = 3;
 788         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 789                 pcie_gen = 2;
 790         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 791                 pcie_gen = 1;
 792         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 793                 pcie_gen = 0;
 794
 795         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 796                 pcie_width = 6;
 797         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 798                 pcie_width = 5;
 799         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 800                 pcie_width = 4;
 801         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 802                 pcie_width = 3;
 803         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 804                 pcie_width = 2;
 805         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 806                 pcie_width = 1;
 807
 808         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 809          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 810          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 811          */
 812         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 813         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 814                         PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);
 815         PP_ASSERT_WITH_CODE(!ret,
 816                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 817                 return ret);
 818
 819         return 0;
 820 }
 821
 822 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 823 {
 824         struct vega20_hwmgr *data =
 825                         (struct vega20_hwmgr *)(hwmgr->backend);
 826         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 827         int i;
 828         int ret = 0;
 829
 830         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 831                 if (data->smu_features[i].allowed)
 832                         data->smu_features[i].smu_feature_id > 31 ?
 833                                 (allowed_features_high |=
 834                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 835                                   & 0xFFFFFFFF)) :
 836                                 (allowed_features_low |=
 837                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 838                                   & 0xFFFFFFFF));
 839
 840         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 841                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
 842         PP_ASSERT_WITH_CODE(!ret,
 843                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 844                 return ret);
 845
 846         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 847                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
 848         PP_ASSERT_WITH_CODE(!ret,
 849                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 850                 return ret);
 851
 852         return 0;
 853 }
 854
 855 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
 856 {
 857         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
 858 }
 859
 860 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 861 {
 862         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
 863 }
 864
 865 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 866 {
 867         struct vega20_hwmgr *data =
 868                         (struct vega20_hwmgr *)(hwmgr->backend);
 869         uint64_t features_enabled;
 870         int i;
 871         bool enabled;
 872         int ret = 0;
 873
 874         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 875                         PPSMC_MSG_EnableAllSmuFeatures)) == 0,
 876                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 877                         return ret);
 878
 879         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 880         PP_ASSERT_WITH_CODE(!ret,
 881                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 882                         return ret);
 883
 884         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 885                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 886                         true : false;
 887                 data->smu_features[i].enabled = enabled;
 888                 data->smu_features[i].supported = enabled;
 889
 890 #if 0
 891                 if (data->smu_features[i].allowed && !enabled)
 892                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 893                 else if (!data->smu_features[i].allowed && enabled)
 894                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 895 #endif
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
 902 {
 903         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 904
 905         if (data->smu_features[GNLD_DPM_UCLK].enabled)
 906                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 907                         PPSMC_MSG_SetUclkFastSwitch,
 908                         1);
 909
 910         return 0;
 911 }
 912
 913 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 914 {
 915         struct vega20_hwmgr *data =
 916                         (struct vega20_hwmgr *)(hwmgr->backend);
 917
 918         return smum_send_msg_to_smc_with_parameter(hwmgr,
 919                         PPSMC_MSG_SetFclkGfxClkRatio,
 920                         data->registry_data.fclk_gfxclk_ratio);
 921 }
 922
 923 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 924 {
 925         struct vega20_hwmgr *data =
 926                         (struct vega20_hwmgr *)(hwmgr->backend);
 927         uint64_t features_enabled;
 928         int i;
 929         bool enabled;
 930         int ret = 0;
 931
 932         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 933                         PPSMC_MSG_DisableAllSmuFeatures)) == 0,
 934                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 935                         return ret);
 936
 937         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 938         PP_ASSERT_WITH_CODE(!ret,
 939                         "[DisableAllSMUFeatures] Failed to get enabled smc features!",
 940                         return ret);
 941
 942         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 943                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 944                         true : false;
 945                 data->smu_features[i].enabled = enabled;
 946                 data->smu_features[i].supported = enabled;
 947         }
 948
 949         return 0;
 950 }
 951
 952 static int vega20_od8_set_feature_capabilities(
 953                 struct pp_hwmgr *hwmgr)
 954 {
 955         struct phm_ppt_v3_information *pptable_information =
 956                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 957         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 958         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 959         struct vega20_od8_settings *od_settings = &(data->od8_settings);
 960
 961         od_settings->overdrive8_capabilities = 0;
 962
 963         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 964                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
 965                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
 966                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
 967                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
 968                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
 969                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
 970
 971                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
 972                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
 973                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
 974                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
 975                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
 976                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
 977                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
 978                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
 979         }
 980
 981         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 982                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
 983                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
 984                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
 985                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
 986                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
 987                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
 988         }
 989
 990         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
 991             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 992             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
 993             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
 994             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
 995                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
 996
 997         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
 998                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
 999                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1000                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1001                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1002                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1003                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1004
1005                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1006                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1007                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1008                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1009                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1010                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1011                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1012         }
1013
1014         if (data->smu_features[GNLD_THERMAL].enabled) {
1015                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1016                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1017                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1018                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1019                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1020                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1021
1022                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1023                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1024                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1025                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1026                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1027                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1028         }
1029
1030         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1031                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1032
1033         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1034             pp_table->FanZeroRpmEnable)
1035                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1036
1037         if (!od_settings->overdrive8_capabilities)
1038                 hwmgr->od_enabled = false;
1039
1040         return 0;
1041 }
1042
1043 static int vega20_od8_set_feature_id(
1044                 struct pp_hwmgr *hwmgr)
1045 {
1046         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1047         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1048
1049         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1050                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1051                         OD8_GFXCLK_LIMITS;
1052                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1053                         OD8_GFXCLK_LIMITS;
1054         } else {
1055                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1056                         0;
1057                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1058                         0;
1059         }
1060
1061         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1062                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1063                         OD8_GFXCLK_CURVE;
1064                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1065                         OD8_GFXCLK_CURVE;
1066                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1067                         OD8_GFXCLK_CURVE;
1068                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1069                         OD8_GFXCLK_CURVE;
1070                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1071                         OD8_GFXCLK_CURVE;
1072                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1073                         OD8_GFXCLK_CURVE;
1074         } else {
1075                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1076                         0;
1077                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1078                         0;
1079                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1080                         0;
1081                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1082                         0;
1083                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1084                         0;
1085                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1086                         0;
1087         }
1088
1089         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1090                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1091         else
1092                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1093
1094         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1095                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1096         else
1097                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1098
1099         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1100                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1101                         OD8_ACOUSTIC_LIMIT_SCLK;
1102         else
1103                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1104                         0;
1105
1106         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1107                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1108                         OD8_FAN_SPEED_MIN;
1109         else
1110                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1111                         0;
1112
1113         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1114                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1115                         OD8_TEMPERATURE_FAN;
1116         else
1117                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1118                         0;
1119
1120         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1121                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1122                         OD8_TEMPERATURE_SYSTEM;
1123         else
1124                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1125                         0;
1126
1127         return 0;
1128 }
1129
1130 static int vega20_od8_get_gfx_clock_base_voltage(
1131                 struct pp_hwmgr *hwmgr,
1132                 uint32_t *voltage,
1133                 uint32_t freq)
1134 {
1135         int ret = 0;
1136
1137         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1138                         PPSMC_MSG_GetAVFSVoltageByDpm,
1139                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1140         PP_ASSERT_WITH_CODE(!ret,
1141                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1142                         return ret);
1143
1144         *voltage = smum_get_argument(hwmgr);
1145         *voltage = *voltage / VOLTAGE_SCALE;
1146
1147         return 0;
1148 }
1149
1150 static int vega20_od8_initialize_default_settings(
1151                 struct pp_hwmgr *hwmgr)
1152 {
1153         struct phm_ppt_v3_information *pptable_information =
1154                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1155         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1156         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1157         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1158         int i, ret = 0;
1159
1160         /* Set Feature Capabilities */
1161         vega20_od8_set_feature_capabilities(hwmgr);
1162
1163         /* Map FeatureID to individual settings */
1164         vega20_od8_set_feature_id(hwmgr);
1165
1166         /* Set default values */
1167         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1168         PP_ASSERT_WITH_CODE(!ret,
1169                         "Failed to export over drive table!",
1170                         return ret);
1171
1172         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1173                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1174                         od_table->GfxclkFmin;
1175                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1176                         od_table->GfxclkFmax;
1177         } else {
1178                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1179                         0;
1180                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1181                         0;
1182         }
1183
1184         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1185                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1186                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1187                         od_table->GfxclkFreq1;
1188
1189                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1190                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1191                         od_table->GfxclkFreq3;
1192
1193                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1194                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1195                         od_table->GfxclkFreq2;
1196
1197                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1198                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1199                                      od_table->GfxclkFreq1),
1200                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1201                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1202                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1203                         * VOLTAGE_SCALE;
1204
1205                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1206                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1207                                      od_table->GfxclkFreq2),
1208                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1209                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1210                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1211                         * VOLTAGE_SCALE;
1212
1213                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1214                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1215                                      od_table->GfxclkFreq3),
1216                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1217                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1218                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1219                         * VOLTAGE_SCALE;
1220         } else {
1221                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1222                         0;
1223                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1224                         0;
1225                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1226                         0;
1227                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1228                         0;
1229                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1230                         0;
1231                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1232                         0;
1233         }
1234
1235         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1236                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1237                         od_table->UclkFmax;
1238         else
1239                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1240                         0;
1241
1242         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1243                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1244                         od_table->OverDrivePct;
1245         else
1246                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1247                         0;
1248
1249         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1250                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1251                         od_table->FanMaximumRpm;
1252         else
1253                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1254                         0;
1255
1256         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1257                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1258                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1259         else
1260                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1261                         0;
1262
1263         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1264                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1265                         od_table->FanTargetTemperature;
1266         else
1267                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1268                         0;
1269
1270         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1271                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1272                         od_table->MaxOpTemp;
1273         else
1274                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1275                         0;
1276
1277         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1278                 if (od8_settings->od8_settings_array[i].feature_id) {
1279                         od8_settings->od8_settings_array[i].min_value =
1280                                 pptable_information->od_settings_min[i];
1281                         od8_settings->od8_settings_array[i].max_value =
1282                                 pptable_information->od_settings_max[i];
1283                         od8_settings->od8_settings_array[i].current_value =
1284                                 od8_settings->od8_settings_array[i].default_value;
1285                 } else {
1286                         od8_settings->od8_settings_array[i].min_value =
1287                                 0;
1288                         od8_settings->od8_settings_array[i].max_value =
1289                                 0;
1290                         od8_settings->od8_settings_array[i].current_value =
1291                                 0;
1292                 }
1293         }
1294
1295         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1296         PP_ASSERT_WITH_CODE(!ret,
1297                         "Failed to import over drive table!",
1298                         return ret);
1299
1300         return 0;
1301 }
1302
1303 static int vega20_od8_set_settings(
1304                 struct pp_hwmgr *hwmgr,
1305                 uint32_t index,
1306                 uint32_t value)
1307 {
1308         OverDriveTable_t od_table;
1309         int ret = 0;
1310         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1311         struct vega20_od8_single_setting *od8_settings =
1312                         data->od8_settings.od8_settings_array;
1313
1314         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1315         PP_ASSERT_WITH_CODE(!ret,
1316                         "Failed to export over drive table!",
1317                         return ret);
1318
1319         switch(index) {
1320         case OD8_SETTING_GFXCLK_FMIN:
1321                 od_table.GfxclkFmin = (uint16_t)value;
1322                 break;
1323         case OD8_SETTING_GFXCLK_FMAX:
1324                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1325                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1326                         return -EINVAL;
1327
1328                 od_table.GfxclkFmax = (uint16_t)value;
1329                 break;
1330         case OD8_SETTING_GFXCLK_FREQ1:
1331                 od_table.GfxclkFreq1 = (uint16_t)value;
1332                 break;
1333         case OD8_SETTING_GFXCLK_VOLTAGE1:
1334                 od_table.GfxclkVolt1 = (uint16_t)value;
1335                 break;
1336         case OD8_SETTING_GFXCLK_FREQ2:
1337                 od_table.GfxclkFreq2 = (uint16_t)value;
1338                 break;
1339         case OD8_SETTING_GFXCLK_VOLTAGE2:
1340                 od_table.GfxclkVolt2 = (uint16_t)value;
1341                 break;
1342         case OD8_SETTING_GFXCLK_FREQ3:
1343                 od_table.GfxclkFreq3 = (uint16_t)value;
1344                 break;
1345         case OD8_SETTING_GFXCLK_VOLTAGE3:
1346                 od_table.GfxclkVolt3 = (uint16_t)value;
1347                 break;
1348         case OD8_SETTING_UCLK_FMAX:
1349                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1350                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1351                         return -EINVAL;
1352                 od_table.UclkFmax = (uint16_t)value;
1353                 break;
1354         case OD8_SETTING_POWER_PERCENTAGE:
1355                 od_table.OverDrivePct = (int16_t)value;
1356                 break;
1357         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1358                 od_table.FanMaximumRpm = (uint16_t)value;
1359                 break;
1360         case OD8_SETTING_FAN_MIN_SPEED:
1361                 od_table.FanMinimumPwm = (uint16_t)value;
1362                 break;
1363         case OD8_SETTING_FAN_TARGET_TEMP:
1364                 od_table.FanTargetTemperature = (uint16_t)value;
1365                 break;
1366         case OD8_SETTING_OPERATING_TEMP_MAX:
1367                 od_table.MaxOpTemp = (uint16_t)value;
1368                 break;
1369         }
1370
1371         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1372         PP_ASSERT_WITH_CODE(!ret,
1373                         "Failed to import over drive table!",
1374                         return ret);
1375
1376         return 0;
1377 }
1378
1379 static int vega20_get_sclk_od(
1380                 struct pp_hwmgr *hwmgr)
1381 {
1382         struct vega20_hwmgr *data = hwmgr->backend;
1383         struct vega20_single_dpm_table *sclk_table =
1384                         &(data->dpm_table.gfx_table);
1385         struct vega20_single_dpm_table *golden_sclk_table =
1386                         &(data->golden_dpm_table.gfx_table);
1387         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1388         int golden_value = golden_sclk_table->dpm_levels
1389                         [golden_sclk_table->count - 1].value;
1390
1391         /* od percentage */
1392         value -= golden_value;
1393         value = DIV_ROUND_UP(value * 100, golden_value);
1394
1395         return value;
1396 }
1397
1398 static int vega20_set_sclk_od(
1399                 struct pp_hwmgr *hwmgr, uint32_t value)
1400 {
1401         struct vega20_hwmgr *data = hwmgr->backend;
1402         struct vega20_single_dpm_table *golden_sclk_table =
1403                         &(data->golden_dpm_table.gfx_table);
1404         uint32_t od_sclk;
1405         int ret = 0;
1406
1407         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1408         od_sclk /= 100;
1409         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1410
1411         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1412         PP_ASSERT_WITH_CODE(!ret,
1413                         "[SetSclkOD] failed to set od gfxclk!",
1414                         return ret);
1415
1416         /* retrieve updated gfxclk table */
1417         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1418         PP_ASSERT_WITH_CODE(!ret,
1419                         "[SetSclkOD] failed to refresh gfxclk table!",
1420                         return ret);
1421
1422         return 0;
1423 }
1424
1425 static int vega20_get_mclk_od(
1426                 struct pp_hwmgr *hwmgr)
1427 {
1428         struct vega20_hwmgr *data = hwmgr->backend;
1429         struct vega20_single_dpm_table *mclk_table =
1430                         &(data->dpm_table.mem_table);
1431         struct vega20_single_dpm_table *golden_mclk_table =
1432                         &(data->golden_dpm_table.mem_table);
1433         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1434         int golden_value = golden_mclk_table->dpm_levels
1435                         [golden_mclk_table->count - 1].value;
1436
1437         /* od percentage */
1438         value -= golden_value;
1439         value = DIV_ROUND_UP(value * 100, golden_value);
1440
1441         return value;
1442 }
1443
1444 static int vega20_set_mclk_od(
1445                 struct pp_hwmgr *hwmgr, uint32_t value)
1446 {
1447         struct vega20_hwmgr *data = hwmgr->backend;
1448         struct vega20_single_dpm_table *golden_mclk_table =
1449                         &(data->golden_dpm_table.mem_table);
1450         uint32_t od_mclk;
1451         int ret = 0;
1452
1453         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1454         od_mclk /= 100;
1455         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1456
1457         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1458         PP_ASSERT_WITH_CODE(!ret,
1459                         "[SetMclkOD] failed to set od memclk!",
1460                         return ret);
1461
1462         /* retrieve updated memclk table */
1463         ret = vega20_setup_memclk_dpm_table(hwmgr);
1464         PP_ASSERT_WITH_CODE(!ret,
1465                         "[SetMclkOD] failed to refresh memclk table!",
1466                         return ret);
1467
1468         return 0;
1469 }
1470
1471 static int vega20_populate_umdpstate_clocks(
1472                 struct pp_hwmgr *hwmgr)
1473 {
1474         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1475         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1476         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1477
1478         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1479         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1480
1481         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1482             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1483                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1484                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1485         }
1486
1487         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1488         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1489
1490         return 0;
1491 }
1492
1493 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1494                 PP_Clock *clock, PPCLK_e clock_select)
1495 {
1496         int ret = 0;
1497
1498         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1499                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1500                         (clock_select << 16))) == 0,
1501                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1502                         return ret);
1503         *clock = smum_get_argument(hwmgr);
1504
1505         /* if DC limit is zero, return AC limit */
1506         if (*clock == 0) {
1507                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1508                         PPSMC_MSG_GetMaxDpmFreq,
1509                         (clock_select << 16))) == 0,
1510                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1511                         return ret);
1512                 *clock = smum_get_argument(hwmgr);
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1519 {
1520         struct vega20_hwmgr *data =
1521                 (struct vega20_hwmgr *)(hwmgr->backend);
1522         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1523                 &(data->max_sustainable_clocks);
1524         int ret = 0;
1525
1526         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1527         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1528         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1529         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1530         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1531         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1532
1533         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1534                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1535                                 &(max_sustainable_clocks->uclock),
1536                                 PPCLK_UCLK)) == 0,
1537                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1538                                 return ret);
1539
1540         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1541                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1542                                 &(max_sustainable_clocks->soc_clock),
1543                                 PPCLK_SOCCLK)) == 0,
1544                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1545                                 return ret);
1546
1547         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1548                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1549                                 &(max_sustainable_clocks->dcef_clock),
1550                                 PPCLK_DCEFCLK)) == 0,
1551                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1552                                 return ret);
1553                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1554                                 &(max_sustainable_clocks->display_clock),
1555                                 PPCLK_DISPCLK)) == 0,
1556                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1557                                 return ret);
1558                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1559                                 &(max_sustainable_clocks->phy_clock),
1560                                 PPCLK_PHYCLK)) == 0,
1561                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1562                                 return ret);
1563                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1564                                 &(max_sustainable_clocks->pixel_clock),
1565                                 PPCLK_PIXCLK)) == 0,
1566                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1567                                 return ret);
1568         }
1569
1570         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1571                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1572
1573         return 0;
1574 }
1575
1576 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1577 {
1578         int result;
1579
1580         result = smum_send_msg_to_smc(hwmgr,
1581                 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1582         PP_ASSERT_WITH_CODE(!result,
1583                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1584                         return result);
1585
1586         return 0;
1587 }
1588
1589 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1590 {
1591         struct vega20_hwmgr *data =
1592                 (struct vega20_hwmgr *)(hwmgr->backend);
1593
1594         data->uvd_power_gated = true;
1595         data->vce_power_gated = true;
1596
1597         if (data->smu_features[GNLD_DPM_UVD].enabled)
1598                 data->uvd_power_gated = false;
1599
1600         if (data->smu_features[GNLD_DPM_VCE].enabled)
1601                 data->vce_power_gated = false;
1602 }
1603
1604 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1605 {
1606         int result = 0;
1607
1608         smum_send_msg_to_smc_with_parameter(hwmgr,
1609                         PPSMC_MSG_NumOfDisplays, 0);
1610
1611         result = vega20_set_allowed_featuresmask(hwmgr);
1612         PP_ASSERT_WITH_CODE(!result,
1613                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1614                         return result);
1615
1616         result = vega20_init_smc_table(hwmgr);
1617         PP_ASSERT_WITH_CODE(!result,
1618                         "[EnableDPMTasks] Failed to initialize SMC table!",
1619                         return result);
1620
1621         result = vega20_run_btc(hwmgr);
1622         PP_ASSERT_WITH_CODE(!result,
1623                         "[EnableDPMTasks] Failed to run btc!",
1624                         return result);
1625
1626         result = vega20_run_btc_afll(hwmgr);
1627         PP_ASSERT_WITH_CODE(!result,
1628                         "[EnableDPMTasks] Failed to run btc afll!",
1629                         return result);
1630
1631         result = vega20_enable_all_smu_features(hwmgr);
1632         PP_ASSERT_WITH_CODE(!result,
1633                         "[EnableDPMTasks] Failed to enable all smu features!",
1634                         return result);
1635
1636         result = vega20_override_pcie_parameters(hwmgr);
1637         PP_ASSERT_WITH_CODE(!result,
1638                         "[EnableDPMTasks] Failed to override pcie parameters!",
1639                         return result);
1640
1641         result = vega20_notify_smc_display_change(hwmgr);
1642         PP_ASSERT_WITH_CODE(!result,
1643                         "[EnableDPMTasks] Failed to notify smc display change!",
1644                         return result);
1645
1646         result = vega20_send_clock_ratio(hwmgr);
1647         PP_ASSERT_WITH_CODE(!result,
1648                         "[EnableDPMTasks] Failed to send clock ratio!",
1649                         return result);
1650
1651         /* Initialize UVD/VCE powergating state */
1652         vega20_init_powergate_state(hwmgr);
1653
1654         result = vega20_setup_default_dpm_tables(hwmgr);
1655         PP_ASSERT_WITH_CODE(!result,
1656                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1657                         return result);
1658
1659         result = vega20_init_max_sustainable_clocks(hwmgr);
1660         PP_ASSERT_WITH_CODE(!result,
1661                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1662                         return result);
1663
1664         result = vega20_power_control_set_level(hwmgr);
1665         PP_ASSERT_WITH_CODE(!result,
1666                         "[EnableDPMTasks] Failed to power control set level!",
1667                         return result);
1668
1669         result = vega20_od8_initialize_default_settings(hwmgr);
1670         PP_ASSERT_WITH_CODE(!result,
1671                         "[EnableDPMTasks] Failed to initialize odn settings!",
1672                         return result);
1673
1674         result = vega20_populate_umdpstate_clocks(hwmgr);
1675         PP_ASSERT_WITH_CODE(!result,
1676                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1677                         return result);
1678
1679         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1680                         POWER_SOURCE_AC << 16);
1681         PP_ASSERT_WITH_CODE(!result,
1682                         "[GetPptLimit] get default PPT limit failed!",
1683                         return result);
1684         hwmgr->power_limit =
1685                 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1686
1687         return 0;
1688 }
1689
1690 static uint32_t vega20_find_lowest_dpm_level(
1691                 struct vega20_single_dpm_table *table)
1692 {
1693         uint32_t i;
1694
1695         for (i = 0; i < table->count; i++) {
1696                 if (table->dpm_levels[i].enabled)
1697                         break;
1698         }
1699         if (i >= table->count) {
1700                 i = 0;
1701                 table->dpm_levels[i].enabled = true;
1702         }
1703
1704         return i;
1705 }
1706
1707 static uint32_t vega20_find_highest_dpm_level(
1708                 struct vega20_single_dpm_table *table)
1709 {
1710         int i = 0;
1711
1712         PP_ASSERT_WITH_CODE(table != NULL,
1713                         "[FindHighestDPMLevel] DPM Table does not exist!",
1714                         return 0);
1715         PP_ASSERT_WITH_CODE(table->count > 0,
1716                         "[FindHighestDPMLevel] DPM Table has no entry!",
1717                         return 0);
1718         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1719                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1720                         return MAX_REGULAR_DPM_NUMBER - 1);
1721
1722         for (i = table->count - 1; i >= 0; i--) {
1723                 if (table->dpm_levels[i].enabled)
1724                         break;
1725         }
1726         if (i < 0) {
1727                 i = 0;
1728                 table->dpm_levels[i].enabled = true;
1729         }
1730
1731         return i;
1732 }
1733
1734 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1735 {
1736         struct vega20_hwmgr *data =
1737                         (struct vega20_hwmgr *)(hwmgr->backend);
1738         uint32_t min_freq;
1739         int ret = 0;
1740
1741         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1742            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1743                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1744                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1745                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1746                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1747                                         "Failed to set soft min gfxclk !",
1748                                         return ret);
1749         }
1750
1751         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1752            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1753                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1754                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1755                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1756                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1757                                         "Failed to set soft min memclk !",
1758                                         return ret);
1759         }
1760
1761         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1762            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1763                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1764
1765                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1766                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1767                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1768                                         "Failed to set soft min vclk!",
1769                                         return ret);
1770
1771                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1772
1773                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1774                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1775                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1776                                         "Failed to set soft min dclk!",
1777                                         return ret);
1778         }
1779
1780         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1781            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1782                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1783
1784                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1785                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1786                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1787                                         "Failed to set soft min eclk!",
1788                                         return ret);
1789         }
1790
1791         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1792            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1793                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1794
1795                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1796                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1797                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1798                                         "Failed to set soft min socclk!",
1799                                         return ret);
1800         }
1801
1802         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1803            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1804                 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1805
1806                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1807                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1808                                         (PPCLK_FCLK << 16) | (min_freq & 0xffff))),
1809                                         "Failed to set soft min fclk!",
1810                                         return ret);
1811         }
1812
1813         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1814            (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1815                 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1816
1817                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1818                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1819                                         (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
1820                                         "Failed to set hard min dcefclk!",
1821                                         return ret);
1822         }
1823
1824         return ret;
1825 }
1826
1827 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1828 {
1829         struct vega20_hwmgr *data =
1830                         (struct vega20_hwmgr *)(hwmgr->backend);
1831         uint32_t max_freq;
1832         int ret = 0;
1833
1834         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1835            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1836                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1837
1838                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1839                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1840                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1841                                         "Failed to set soft max gfxclk!",
1842                                         return ret);
1843         }
1844
1845         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1846            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1847                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1848
1849                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1850                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1851                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1852                                         "Failed to set soft max memclk!",
1853                                         return ret);
1854         }
1855
1856         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1857            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1858                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1859
1860                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1861                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1862                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1863                                         "Failed to set soft max vclk!",
1864                                         return ret);
1865
1866                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1867                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1868                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1869                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1870                                         "Failed to set soft max dclk!",
1871                                         return ret);
1872         }
1873
1874         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1875            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1876                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1877
1878                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1879                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1880                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1881                                         "Failed to set soft max eclk!",
1882                                         return ret);
1883         }
1884
1885         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1886            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1887                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1888
1889                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1890                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1891                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1892                                         "Failed to set soft max socclk!",
1893                                         return ret);
1894         }
1895
1896         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1897            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1898                 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1899
1900                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1901                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1902                                         (PPCLK_FCLK << 16) | (max_freq & 0xffff))),
1903                                         "Failed to set soft max fclk!",
1904                                         return ret);
1905         }
1906
1907         return ret;
1908 }
1909
1910 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1911 {
1912         struct vega20_hwmgr *data =
1913                         (struct vega20_hwmgr *)(hwmgr->backend);
1914         int ret = 0;
1915
1916         if (data->smu_features[GNLD_DPM_VCE].supported) {
1917                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1918                         if (enable)
1919                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1920                         else
1921                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1922                 }
1923
1924                 ret = vega20_enable_smc_features(hwmgr,
1925                                 enable,
1926                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1927                 PP_ASSERT_WITH_CODE(!ret,
1928                                 "Attempt to Enable/Disable DPM VCE Failed!",
1929                                 return ret);
1930                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1931         }
1932
1933         return 0;
1934 }
1935
1936 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1937                 uint32_t *clock,
1938                 PPCLK_e clock_select,
1939                 bool max)
1940 {
1941         int ret;
1942         *clock = 0;
1943
1944         if (max) {
1945                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1946                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1947                                 "[GetClockRanges] Failed to get max clock from SMC!",
1948                                 return ret);
1949                 *clock = smum_get_argument(hwmgr);
1950         } else {
1951                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1952                                 PPSMC_MSG_GetMinDpmFreq,
1953                                 (clock_select << 16))) == 0,
1954                                 "[GetClockRanges] Failed to get min clock from SMC!",
1955                                 return ret);
1956                 *clock = smum_get_argument(hwmgr);
1957         }
1958
1959         return 0;
1960 }
1961
1962 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1963 {
1964         struct vega20_hwmgr *data =
1965                         (struct vega20_hwmgr *)(hwmgr->backend);
1966         uint32_t gfx_clk;
1967         int ret = 0;
1968
1969         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1970                         "[GetSclks]: gfxclk dpm not enabled!\n",
1971                         return -EPERM);
1972
1973         if (low) {
1974                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1975                 PP_ASSERT_WITH_CODE(!ret,
1976                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1977                         return ret);
1978         } else {
1979                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1980                 PP_ASSERT_WITH_CODE(!ret,
1981                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1982                         return ret);
1983         }
1984
1985         return (gfx_clk * 100);
1986 }
1987
1988 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1989 {
1990         struct vega20_hwmgr *data =
1991                         (struct vega20_hwmgr *)(hwmgr->backend);
1992         uint32_t mem_clk;
1993         int ret = 0;
1994
1995         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1996                         "[MemMclks]: memclk dpm not enabled!\n",
1997                         return -EPERM);
1998
1999         if (low) {
2000                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2001                 PP_ASSERT_WITH_CODE(!ret,
2002                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
2003                         return ret);
2004         } else {
2005                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2006                 PP_ASSERT_WITH_CODE(!ret,
2007                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
2008                         return ret);
2009         }
2010
2011         return (mem_clk * 100);
2012 }
2013
2014 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
2015 {
2016         struct vega20_hwmgr *data =
2017                         (struct vega20_hwmgr *)(hwmgr->backend);
2018         int ret = 0;
2019
2020         if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
2021                 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
2022                                 TABLE_SMU_METRICS, true);
2023                 if (ret) {
2024                         pr_info("Failed to export SMU metrics table!\n");
2025                         return ret;
2026                 }
2027                 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
2028                 data->metrics_time = jiffies;
2029         } else
2030                 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2031
2032         return ret;
2033 }
2034
2035 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
2036                 uint32_t *query)
2037 {
2038         int ret = 0;
2039         SmuMetrics_t metrics_table;
2040
2041         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2042         if (ret)
2043                 return ret;
2044
2045         *query = metrics_table.CurrSocketPower << 8;
2046
2047         return ret;
2048 }
2049
2050 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2051                 PPCLK_e clk_id, uint32_t *clk_freq)
2052 {
2053         int ret = 0;
2054
2055         *clk_freq = 0;
2056
2057         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2058                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
2059                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2060                         return ret);
2061         *clk_freq = smum_get_argument(hwmgr);
2062
2063         *clk_freq = *clk_freq * 100;
2064
2065         return 0;
2066 }
2067
2068 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2069                 uint32_t *activity_percent)
2070 {
2071         int ret = 0;
2072         SmuMetrics_t metrics_table;
2073
2074         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2075         if (ret)
2076                 return ret;
2077
2078         *activity_percent = metrics_table.AverageGfxActivity;
2079
2080         return ret;
2081 }
2082
2083 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2084                               void *value, int *size)
2085 {
2086         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2087         struct amdgpu_device *adev = hwmgr->adev;
2088         SmuMetrics_t metrics_table;
2089         uint32_t val_vid;
2090         int ret = 0;
2091
2092         switch (idx) {
2093         case AMDGPU_PP_SENSOR_GFX_SCLK:
2094                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2095                 if (ret)
2096                         return ret;
2097
2098                 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2099                 *size = 4;
2100                 break;
2101         case AMDGPU_PP_SENSOR_GFX_MCLK:
2102                 ret = vega20_get_current_clk_freq(hwmgr,
2103                                 PPCLK_UCLK,
2104                                 (uint32_t *)value);
2105                 if (!ret)
2106                         *size = 4;
2107                 break;
2108         case AMDGPU_PP_SENSOR_GPU_LOAD:
2109                 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
2110                 if (!ret)
2111                         *size = 4;
2112                 break;
2113         case AMDGPU_PP_SENSOR_GPU_TEMP:
2114                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2115                 *size = 4;
2116                 break;
2117         case AMDGPU_PP_SENSOR_UVD_POWER:
2118                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2119                 *size = 4;
2120                 break;
2121         case AMDGPU_PP_SENSOR_VCE_POWER:
2122                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2123                 *size = 4;
2124                 break;
2125         case AMDGPU_PP_SENSOR_GPU_POWER:
2126                 *size = 16;
2127                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2128                 break;
2129         case AMDGPU_PP_SENSOR_VDDGFX:
2130                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2131                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2132                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2133                 *((uint32_t *)value) =
2134                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
2135                 break;
2136         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2137                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2138                 if (!ret)
2139                         *size = 8;
2140                 break;
2141         default:
2142                 ret = -EINVAL;
2143                 break;
2144         }
2145         return ret;
2146 }
2147
2148 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2149                 struct pp_display_clock_request *clock_req)
2150 {
2151         int result = 0;
2152         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2153         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2154         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2155         PPCLK_e clk_select = 0;
2156         uint32_t clk_request = 0;
2157
2158         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2159                 switch (clk_type) {
2160                 case amd_pp_dcef_clock:
2161                         clk_select = PPCLK_DCEFCLK;
2162                         break;
2163                 case amd_pp_disp_clock:
2164                         clk_select = PPCLK_DISPCLK;
2165                         break;
2166                 case amd_pp_pixel_clock:
2167                         clk_select = PPCLK_PIXCLK;
2168                         break;
2169                 case amd_pp_phy_clock:
2170                         clk_select = PPCLK_PHYCLK;
2171                         break;
2172                 default:
2173                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2174                         result = -EINVAL;
2175                         break;
2176                 }
2177
2178                 if (!result) {
2179                         clk_request = (clk_select << 16) | clk_freq;
2180                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2181                                         PPSMC_MSG_SetHardMinByFreq,
2182                                         clk_request);
2183                 }
2184         }
2185
2186         return result;
2187 }
2188
2189 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2190                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2191                                 PHM_PerformanceLevel *level)
2192 {
2193         return 0;
2194 }
2195
2196 static int vega20_notify_smc_display_config_after_ps_adjustment(
2197                 struct pp_hwmgr *hwmgr)
2198 {
2199         struct vega20_hwmgr *data =
2200                         (struct vega20_hwmgr *)(hwmgr->backend);
2201         struct vega20_single_dpm_table *dpm_table =
2202                         &data->dpm_table.mem_table;
2203         struct PP_Clocks min_clocks = {0};
2204         struct pp_display_clock_request clock_req;
2205         int ret = 0;
2206
2207         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2208         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2209         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2210
2211         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2212                 clock_req.clock_type = amd_pp_dcef_clock;
2213                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2214                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2215                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2216                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2217                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2218                                         min_clocks.dcefClockInSR / 100)) == 0,
2219                                         "Attempt to set divider for DCEFCLK Failed!",
2220                                         return ret);
2221                 } else {
2222                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2223                 }
2224         }
2225
2226         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2227                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2228                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2229                                 PPSMC_MSG_SetHardMinByFreq,
2230                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2231                                 "[SetHardMinFreq] Set hard min uclk failed!",
2232                                 return ret);
2233         }
2234
2235         return 0;
2236 }
2237
2238 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2239 {
2240         struct vega20_hwmgr *data =
2241                         (struct vega20_hwmgr *)(hwmgr->backend);
2242         uint32_t soft_level;
2243         int ret = 0;
2244
2245         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2246
2247         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2248                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2249                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2250
2251         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2252
2253         data->dpm_table.mem_table.dpm_state.soft_min_level =
2254                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2255                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2256
2257         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2258
2259         data->dpm_table.soc_table.dpm_state.soft_min_level =
2260                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2261                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2262
2263         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2264         PP_ASSERT_WITH_CODE(!ret,
2265                         "Failed to upload boot level to highest!",
2266                         return ret);
2267
2268         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2269         PP_ASSERT_WITH_CODE(!ret,
2270                         "Failed to upload dpm max level to highest!",
2271                         return ret);
2272
2273         return 0;
2274 }
2275
2276 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2277 {
2278         struct vega20_hwmgr *data =
2279                         (struct vega20_hwmgr *)(hwmgr->backend);
2280         uint32_t soft_level;
2281         int ret = 0;
2282
2283         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2284
2285         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2286                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2287                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2288
2289         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2290
2291         data->dpm_table.mem_table.dpm_state.soft_min_level =
2292                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2293                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2294
2295         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2296
2297         data->dpm_table.soc_table.dpm_state.soft_min_level =
2298                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2299                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2300
2301         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2302         PP_ASSERT_WITH_CODE(!ret,
2303                         "Failed to upload boot level to highest!",
2304                         return ret);
2305
2306         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2307         PP_ASSERT_WITH_CODE(!ret,
2308                         "Failed to upload dpm max level to highest!",
2309                         return ret);
2310
2311         return 0;
2312
2313 }
2314
2315 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2316 {
2317         struct vega20_hwmgr *data =
2318                         (struct vega20_hwmgr *)(hwmgr->backend);
2319         uint32_t soft_min_level, soft_max_level;
2320         int ret = 0;
2321
2322         soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2323         soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2324         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2325                 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2326         data->dpm_table.gfx_table.dpm_state.soft_max_level =
2327                 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2328
2329         soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2330         soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2331         data->dpm_table.mem_table.dpm_state.soft_min_level =
2332                 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2333         data->dpm_table.mem_table.dpm_state.soft_max_level =
2334                 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2335
2336         soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2337         soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2338         data->dpm_table.soc_table.dpm_state.soft_min_level =
2339                 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2340         data->dpm_table.soc_table.dpm_state.soft_max_level =
2341                 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2342
2343         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2344         PP_ASSERT_WITH_CODE(!ret,
2345                         "Failed to upload DPM Bootup Levels!",
2346                         return ret);
2347
2348         ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2349         PP_ASSERT_WITH_CODE(!ret,
2350                         "Failed to upload DPM Max Levels!",
2351                         return ret);
2352
2353         return 0;
2354 }
2355
2356 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2357                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2358 {
2359         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2360         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2361         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2362         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2363
2364         *sclk_mask = 0;
2365         *mclk_mask = 0;
2366         *soc_mask  = 0;
2367
2368         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2369             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2370             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2371                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2372                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2373                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2374         }
2375
2376         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2377                 *sclk_mask = 0;
2378         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2379                 *mclk_mask = 0;
2380         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2381                 *sclk_mask = gfx_dpm_table->count - 1;
2382                 *mclk_mask = mem_dpm_table->count - 1;
2383                 *soc_mask  = soc_dpm_table->count - 1;
2384         }
2385
2386         return 0;
2387 }
2388
2389 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2390                 enum pp_clock_type type, uint32_t mask)
2391 {
2392         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2393         uint32_t soft_min_level, soft_max_level, hard_min_level;
2394         int ret = 0;
2395
2396         switch (type) {
2397         case PP_SCLK:
2398                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2399                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2400
2401                 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2402                         pr_err("Clock level specified %d is over max allowed %d\n",
2403                                         soft_max_level,
2404                                         data->dpm_table.gfx_table.count - 1);
2405                         return -EINVAL;
2406                 }
2407
2408                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2409                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2410                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2411                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2412
2413                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2414                 PP_ASSERT_WITH_CODE(!ret,
2415                         "Failed to upload boot level to lowest!",
2416                         return ret);
2417
2418                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2419                 PP_ASSERT_WITH_CODE(!ret,
2420                         "Failed to upload dpm max level to highest!",
2421                         return ret);
2422                 break;
2423
2424         case PP_MCLK:
2425                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2426                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2427
2428                 if (soft_max_level >= data->dpm_table.mem_table.count) {
2429                         pr_err("Clock level specified %d is over max allowed %d\n",
2430                                         soft_max_level,
2431                                         data->dpm_table.mem_table.count - 1);
2432                         return -EINVAL;
2433                 }
2434
2435                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2436                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2437                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2438                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2439
2440                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2441                 PP_ASSERT_WITH_CODE(!ret,
2442                         "Failed to upload boot level to lowest!",
2443                         return ret);
2444
2445                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2446                 PP_ASSERT_WITH_CODE(!ret,
2447                         "Failed to upload dpm max level to highest!",
2448                         return ret);
2449
2450                 break;
2451
2452         case PP_SOCCLK:
2453                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2454                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2455
2456                 if (soft_max_level >= data->dpm_table.soc_table.count) {
2457                         pr_err("Clock level specified %d is over max allowed %d\n",
2458                                         soft_max_level,
2459                                         data->dpm_table.soc_table.count - 1);
2460                         return -EINVAL;
2461                 }
2462
2463                 data->dpm_table.soc_table.dpm_state.soft_min_level =
2464                         data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2465                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2466                         data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2467
2468                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2469                 PP_ASSERT_WITH_CODE(!ret,
2470                         "Failed to upload boot level to lowest!",
2471                         return ret);
2472
2473                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2474                 PP_ASSERT_WITH_CODE(!ret,
2475                         "Failed to upload dpm max level to highest!",
2476                         return ret);
2477
2478                 break;
2479
2480         case PP_FCLK:
2481                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2482                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2483
2484                 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2485                         pr_err("Clock level specified %d is over max allowed %d\n",
2486                                         soft_max_level,
2487                                         data->dpm_table.fclk_table.count - 1);
2488                         return -EINVAL;
2489                 }
2490
2491                 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2492                         data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2493                 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2494                         data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2495
2496                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2497                 PP_ASSERT_WITH_CODE(!ret,
2498                         "Failed to upload boot level to lowest!",
2499                         return ret);
2500
2501                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2502                 PP_ASSERT_WITH_CODE(!ret,
2503                         "Failed to upload dpm max level to highest!",
2504                         return ret);
2505
2506                 break;
2507
2508         case PP_DCEFCLK:
2509                 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2510
2511                 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2512                         pr_err("Clock level specified %d is over max allowed %d\n",
2513                                         hard_min_level,
2514                                         data->dpm_table.dcef_table.count - 1);
2515                         return -EINVAL;
2516                 }
2517
2518                 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2519                         data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2520
2521                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2522                 PP_ASSERT_WITH_CODE(!ret,
2523                         "Failed to upload boot level to lowest!",
2524                         return ret);
2525
2526                 //TODO: Setting DCEFCLK max dpm level is not supported
2527
2528                 break;
2529
2530         case PP_PCIE:
2531                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2532                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2533                 if (soft_min_level >= NUM_LINK_LEVELS ||
2534                     soft_max_level >= NUM_LINK_LEVELS)
2535                         return -EINVAL;
2536
2537                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2538                         PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2539                 PP_ASSERT_WITH_CODE(!ret,
2540                         "Failed to set min link dpm level!",
2541                         return ret);
2542
2543                 break;
2544
2545         default:
2546                 break;
2547         }
2548
2549         return 0;
2550 }
2551
2552 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2553                                 enum amd_dpm_forced_level level)
2554 {
2555         int ret = 0;
2556         uint32_t sclk_mask, mclk_mask, soc_mask;
2557
2558         switch (level) {
2559         case AMD_DPM_FORCED_LEVEL_HIGH:
2560                 ret = vega20_force_dpm_highest(hwmgr);
2561                 break;
2562
2563         case AMD_DPM_FORCED_LEVEL_LOW:
2564                 ret = vega20_force_dpm_lowest(hwmgr);
2565                 break;
2566
2567         case AMD_DPM_FORCED_LEVEL_AUTO:
2568                 ret = vega20_unforce_dpm_levels(hwmgr);
2569                 break;
2570
2571         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2572         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2573         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2574         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2575                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2576                 if (ret)
2577                         return ret;
2578                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2579                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2580                 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2581                 break;
2582
2583         case AMD_DPM_FORCED_LEVEL_MANUAL:
2584         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2585         default:
2586                 break;
2587         }
2588
2589         return ret;
2590 }
2591
2592 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2593 {
2594         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2595
2596         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2597                 return AMD_FAN_CTRL_MANUAL;
2598         else
2599                 return AMD_FAN_CTRL_AUTO;
2600 }
2601
2602 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2603 {
2604         switch (mode) {
2605         case AMD_FAN_CTRL_NONE:
2606                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2607                 break;
2608         case AMD_FAN_CTRL_MANUAL:
2609                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2610                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2611                 break;
2612         case AMD_FAN_CTRL_AUTO:
2613                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2614                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2615                 break;
2616         default:
2617                 break;
2618         }
2619 }
2620
2621 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2622                 struct amd_pp_simple_clock_info *info)
2623 {
2624 #if 0
2625         struct phm_ppt_v2_information *table_info =
2626                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2627         struct phm_clock_and_voltage_limits *max_limits =
2628                         &table_info->max_clock_voltage_on_ac;
2629
2630         info->engine_max_clock = max_limits->sclk;
2631         info->memory_max_clock = max_limits->mclk;
2632 #endif
2633         return 0;
2634 }
2635
2636
2637 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2638                 struct pp_clock_levels_with_latency *clocks)
2639 {
2640         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2641         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2642         int i, count;
2643
2644         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2645                 "[GetSclks]: gfxclk dpm not enabled!\n",
2646                 return -EPERM);
2647
2648         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2649         clocks->num_levels = count;
2650
2651         for (i = 0; i < count; i++) {
2652                 clocks->data[i].clocks_in_khz =
2653                         dpm_table->dpm_levels[i].value * 1000;
2654                 clocks->data[i].latency_in_us = 0;
2655         }
2656
2657         return 0;
2658 }
2659
2660 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2661                 uint32_t clock)
2662 {
2663         return 25;
2664 }
2665
2666 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2667                 struct pp_clock_levels_with_latency *clocks)
2668 {
2669         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2670         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2671         int i, count;
2672
2673         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2674                 "[GetMclks]: uclk dpm not enabled!\n",
2675                 return -EPERM);
2676
2677         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2678         clocks->num_levels = data->mclk_latency_table.count = count;
2679
2680         for (i = 0; i < count; i++) {
2681                 clocks->data[i].clocks_in_khz =
2682                         data->mclk_latency_table.entries[i].frequency =
2683                         dpm_table->dpm_levels[i].value * 1000;
2684                 clocks->data[i].latency_in_us =
2685                         data->mclk_latency_table.entries[i].latency =
2686                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2687         }
2688
2689         return 0;
2690 }
2691
2692 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2693                 struct pp_clock_levels_with_latency *clocks)
2694 {
2695         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2696         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2697         int i, count;
2698
2699         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2700                 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2701                 return -EPERM);
2702
2703         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2704         clocks->num_levels = count;
2705
2706         for (i = 0; i < count; i++) {
2707                 clocks->data[i].clocks_in_khz =
2708                         dpm_table->dpm_levels[i].value * 1000;
2709                 clocks->data[i].latency_in_us = 0;
2710         }
2711
2712         return 0;
2713 }
2714
2715 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2716                 struct pp_clock_levels_with_latency *clocks)
2717 {
2718         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2719         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2720         int i, count;
2721
2722         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2723                 "[GetSocclks]: socclk dpm not enabled!\n",
2724                 return -EPERM);
2725
2726         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2727         clocks->num_levels = count;
2728
2729         for (i = 0; i < count; i++) {
2730                 clocks->data[i].clocks_in_khz =
2731                         dpm_table->dpm_levels[i].value * 1000;
2732                 clocks->data[i].latency_in_us = 0;
2733         }
2734
2735         return 0;
2736
2737 }
2738
2739 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2740                 enum amd_pp_clock_type type,
2741                 struct pp_clock_levels_with_latency *clocks)
2742 {
2743         int ret;
2744
2745         switch (type) {
2746         case amd_pp_sys_clock:
2747                 ret = vega20_get_sclks(hwmgr, clocks);
2748                 break;
2749         case amd_pp_mem_clock:
2750                 ret = vega20_get_memclocks(hwmgr, clocks);
2751                 break;
2752         case amd_pp_dcef_clock:
2753                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2754                 break;
2755         case amd_pp_soc_clock:
2756                 ret = vega20_get_socclocks(hwmgr, clocks);
2757                 break;
2758         default:
2759                 return -EINVAL;
2760         }
2761
2762         return ret;
2763 }
2764
2765 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2766                 enum amd_pp_clock_type type,
2767                 struct pp_clock_levels_with_voltage *clocks)
2768 {
2769         clocks->num_levels = 0;
2770
2771         return 0;
2772 }
2773
2774 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2775                                                    void *clock_ranges)
2776 {
2777         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2778         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2779         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2780
2781         if (!data->registry_data.disable_water_mark &&
2782             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2783             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2784                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2785                 data->water_marks_bitmap |= WaterMarksExist;
2786                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2787         }
2788
2789         return 0;
2790 }
2791
2792 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2793                                         enum PP_OD_DPM_TABLE_COMMAND type,
2794                                         long *input, uint32_t size)
2795 {
2796         struct vega20_hwmgr *data =
2797                         (struct vega20_hwmgr *)(hwmgr->backend);
2798         struct vega20_od8_single_setting *od8_settings =
2799                         data->od8_settings.od8_settings_array;
2800         OverDriveTable_t *od_table =
2801                         &(data->smc_state_table.overdrive_table);
2802         struct pp_clock_levels_with_latency clocks;
2803         int32_t input_index, input_clk, input_vol, i;
2804         int od8_id;
2805         int ret;
2806
2807         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2808                                 return -EINVAL);
2809
2810         switch (type) {
2811         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2812                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2813                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2814                         pr_info("Sclk min/max frequency overdrive not supported\n");
2815                         return -EOPNOTSUPP;
2816                 }
2817
2818                 for (i = 0; i < size; i += 2) {
2819                         if (i + 2 > size) {
2820                                 pr_info("invalid number of input parameters %d\n",
2821                                         size);
2822                                 return -EINVAL;
2823                         }
2824
2825                         input_index = input[i];
2826                         input_clk = input[i + 1];
2827
2828                         if (input_index != 0 && input_index != 1) {
2829                                 pr_info("Invalid index %d\n", input_index);
2830                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2831                                 return -EINVAL;
2832                         }
2833
2834                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2835                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2836                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2837                                         input_clk,
2838                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2839                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2840                                 return -EINVAL;
2841                         }
2842
2843                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2844                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2845                                 data->gfxclk_overdrive = true;
2846
2847                         if (input_index == 0)
2848                                 od_table->GfxclkFmin = input_clk;
2849                         else
2850                                 od_table->GfxclkFmax = input_clk;
2851                 }
2852
2853                 break;
2854
2855         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2856                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2857                         pr_info("Mclk max frequency overdrive not supported\n");
2858                         return -EOPNOTSUPP;
2859                 }
2860
2861                 ret = vega20_get_memclocks(hwmgr, &clocks);
2862                 PP_ASSERT_WITH_CODE(!ret,
2863                                 "Attempt to get memory clk levels failed!",
2864                                 return ret);
2865
2866                 for (i = 0; i < size; i += 2) {
2867                         if (i + 2 > size) {
2868                                 pr_info("invalid number of input parameters %d\n",
2869                                         size);
2870                                 return -EINVAL;
2871                         }
2872
2873                         input_index = input[i];
2874                         input_clk = input[i + 1];
2875
2876                         if (input_index != 1) {
2877                                 pr_info("Invalid index %d\n", input_index);
2878                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2879                                 return -EINVAL;
2880                         }
2881
2882                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2883                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2884                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2885                                         input_clk,
2886                                         clocks.data[0].clocks_in_khz / 1000,
2887                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2888                                 return -EINVAL;
2889                         }
2890
2891                         if (input_index == 1 && od_table->UclkFmax != input_clk)
2892                                 data->memclk_overdrive = true;
2893
2894                         od_table->UclkFmax = input_clk;
2895                 }
2896
2897                 break;
2898
2899         case PP_OD_EDIT_VDDC_CURVE:
2900                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2901                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2902                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2903                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2904                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2905                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2906                         pr_info("Voltage curve calibrate not supported\n");
2907                         return -EOPNOTSUPP;
2908                 }
2909
2910                 for (i = 0; i < size; i += 3) {
2911                         if (i + 3 > size) {
2912                                 pr_info("invalid number of input parameters %d\n",
2913                                         size);
2914                                 return -EINVAL;
2915                         }
2916
2917                         input_index = input[i];
2918                         input_clk = input[i + 1];
2919                         input_vol = input[i + 2];
2920
2921                         if (input_index > 2) {
2922                                 pr_info("Setting for point %d is not supported\n",
2923                                                 input_index + 1);
2924                                 pr_info("Three supported points index by 0, 1, 2\n");
2925                                 return -EINVAL;
2926                         }
2927
2928                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2929                         if (input_clk < od8_settings[od8_id].min_value ||
2930                             input_clk > od8_settings[od8_id].max_value) {
2931                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2932                                         input_clk,
2933                                         od8_settings[od8_id].min_value,
2934                                         od8_settings[od8_id].max_value);
2935                                 return -EINVAL;
2936                         }
2937
2938                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2939                         if (input_vol < od8_settings[od8_id].min_value ||
2940                             input_vol > od8_settings[od8_id].max_value) {
2941                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2942                                         input_vol,
2943                                         od8_settings[od8_id].min_value,
2944                                         od8_settings[od8_id].max_value);
2945                                 return -EINVAL;
2946                         }
2947
2948                         switch (input_index) {
2949                         case 0:
2950                                 od_table->GfxclkFreq1 = input_clk;
2951                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2952                                 break;
2953                         case 1:
2954                                 od_table->GfxclkFreq2 = input_clk;
2955                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2956                                 break;
2957                         case 2:
2958                                 od_table->GfxclkFreq3 = input_clk;
2959                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2960                                 break;
2961                         }
2962                 }
2963                 break;
2964
2965         case PP_OD_RESTORE_DEFAULT_TABLE:
2966                 data->gfxclk_overdrive = false;
2967                 data->memclk_overdrive = false;
2968
2969                 ret = smum_smc_table_manager(hwmgr,
2970                                              (uint8_t *)od_table,
2971                                              TABLE_OVERDRIVE, true);
2972                 PP_ASSERT_WITH_CODE(!ret,
2973                                 "Failed to export overdrive table!",
2974                                 return ret);
2975                 break;
2976
2977         case PP_OD_COMMIT_DPM_TABLE:
2978                 ret = smum_smc_table_manager(hwmgr,
2979                                              (uint8_t *)od_table,
2980                                              TABLE_OVERDRIVE, false);
2981                 PP_ASSERT_WITH_CODE(!ret,
2982                                 "Failed to import overdrive table!",
2983                                 return ret);
2984
2985                 /* retrieve updated gfxclk table */
2986                 if (data->gfxclk_overdrive) {
2987                         data->gfxclk_overdrive = false;
2988
2989                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2990                         if (ret)
2991                                 return ret;
2992                 }
2993
2994                 /* retrieve updated memclk table */
2995                 if (data->memclk_overdrive) {
2996                         data->memclk_overdrive = false;
2997
2998                         ret = vega20_setup_memclk_dpm_table(hwmgr);
2999                         if (ret)
3000                                 return ret;
3001                 }
3002                 break;
3003
3004         default:
3005                 return -EINVAL;
3006         }
3007
3008         return 0;
3009 }
3010
3011 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
3012 {
3013         static const char *ppfeature_name[] = {
3014                                 "DPM_PREFETCHER",
3015                                 "GFXCLK_DPM",
3016                                 "UCLK_DPM",
3017                                 "SOCCLK_DPM",
3018                                 "UVD_DPM",
3019                                 "VCE_DPM",
3020                                 "ULV",
3021                                 "MP0CLK_DPM",
3022                                 "LINK_DPM",
3023                                 "DCEFCLK_DPM",
3024                                 "GFXCLK_DS",
3025                                 "SOCCLK_DS",
3026                                 "LCLK_DS",
3027                                 "PPT",
3028                                 "TDC",
3029                                 "THERMAL",
3030                                 "GFX_PER_CU_CG",
3031                                 "RM",
3032                                 "DCEFCLK_DS",
3033                                 "ACDC",
3034                                 "VR0HOT",
3035                                 "VR1HOT",
3036                                 "FW_CTF",
3037                                 "LED_DISPLAY",
3038                                 "FAN_CONTROL",
3039                                 "GFX_EDC",
3040                                 "GFXOFF",
3041                                 "CG",
3042                                 "FCLK_DPM",
3043                                 "FCLK_DS",
3044                                 "MP1CLK_DS",
3045                                 "MP0CLK_DS",
3046                                 "XGMI"};
3047         static const char *output_title[] = {
3048                                 "FEATURES",
3049                                 "BITMASK",
3050                                 "ENABLEMENT"};
3051         uint64_t features_enabled;
3052         int i;
3053         int ret = 0;
3054         int size = 0;
3055
3056         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3057         PP_ASSERT_WITH_CODE(!ret,
3058                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3059                         return ret);
3060
3061         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3062         size += sprintf(buf + size, "%-19s %-22s %s\n",
3063                                 output_title[0],
3064                                 output_title[1],
3065                                 output_title[2]);
3066         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3067                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
3068                                         ppfeature_name[i],
3069                                         1ULL << i,
3070                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
3071         }
3072
3073         return size;
3074 }
3075
3076 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3077 {
3078         uint64_t features_enabled;
3079         uint64_t features_to_enable;
3080         uint64_t features_to_disable;
3081         int ret = 0;
3082
3083         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3084                 return -EINVAL;
3085
3086         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3087         if (ret)
3088                 return ret;
3089
3090         features_to_disable =
3091                 (features_enabled ^ new_ppfeature_masks) & features_enabled;
3092         features_to_enable =
3093                 (features_enabled ^ new_ppfeature_masks) ^ features_to_disable;
3094
3095         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3096         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3097
3098         if (features_to_disable) {
3099                 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3100                 if (ret)
3101                         return ret;
3102         }
3103
3104         if (features_to_enable) {
3105                 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3106                 if (ret)
3107                         return ret;
3108         }
3109
3110         return 0;
3111 }
3112
3113 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3114                 enum pp_clock_type type, char *buf)
3115 {
3116         struct vega20_hwmgr *data =
3117                         (struct vega20_hwmgr *)(hwmgr->backend);
3118         struct vega20_od8_single_setting *od8_settings =
3119                         data->od8_settings.od8_settings_array;
3120         OverDriveTable_t *od_table =
3121                         &(data->smc_state_table.overdrive_table);
3122         struct phm_ppt_v3_information *pptable_information =
3123                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3124         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
3125         struct amdgpu_device *adev = hwmgr->adev;
3126         struct pp_clock_levels_with_latency clocks;
3127         struct vega20_single_dpm_table *fclk_dpm_table =
3128                         &(data->dpm_table.fclk_table);
3129         int i, now, size = 0;
3130         int ret = 0;
3131         uint32_t gen_speed, lane_width;
3132
3133         switch (type) {
3134         case PP_SCLK:
3135                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3136                 PP_ASSERT_WITH_CODE(!ret,
3137                                 "Attempt to get current gfx clk Failed!",
3138                                 return ret);
3139
3140                 ret = vega20_get_sclks(hwmgr, &clocks);
3141                 PP_ASSERT_WITH_CODE(!ret,
3142                                 "Attempt to get gfx clk levels Failed!",
3143                                 return ret);
3144
3145                 for (i = 0; i < clocks.num_levels; i++)
3146                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3147                                 i, clocks.data[i].clocks_in_khz / 1000,
3148                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3149                 break;
3150
3151         case PP_MCLK:
3152                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3153                 PP_ASSERT_WITH_CODE(!ret,
3154                                 "Attempt to get current mclk freq Failed!",
3155                                 return ret);
3156
3157                 ret = vega20_get_memclocks(hwmgr, &clocks);
3158                 PP_ASSERT_WITH_CODE(!ret,
3159                                 "Attempt to get memory clk levels Failed!",
3160                                 return ret);
3161
3162                 for (i = 0; i < clocks.num_levels; i++)
3163                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3164                                 i, clocks.data[i].clocks_in_khz / 1000,
3165                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3166                 break;
3167
3168         case PP_SOCCLK:
3169                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3170                 PP_ASSERT_WITH_CODE(!ret,
3171                                 "Attempt to get current socclk freq Failed!",
3172                                 return ret);
3173
3174                 ret = vega20_get_socclocks(hwmgr, &clocks);
3175                 PP_ASSERT_WITH_CODE(!ret,
3176                                 "Attempt to get soc clk levels Failed!",
3177                                 return ret);
3178
3179                 for (i = 0; i < clocks.num_levels; i++)
3180                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3181                                 i, clocks.data[i].clocks_in_khz / 1000,
3182                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3183                 break;
3184
3185         case PP_FCLK:
3186                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3187                 PP_ASSERT_WITH_CODE(!ret,
3188                                 "Attempt to get current fclk freq Failed!",
3189                                 return ret);
3190
3191                 for (i = 0; i < fclk_dpm_table->count; i++)
3192                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3193                                 i, fclk_dpm_table->dpm_levels[i].value,
3194                                 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3195                 break;
3196
3197         case PP_DCEFCLK:
3198                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3199                 PP_ASSERT_WITH_CODE(!ret,
3200                                 "Attempt to get current dcefclk freq Failed!",
3201                                 return ret);
3202
3203                 ret = vega20_get_dcefclocks(hwmgr, &clocks);
3204                 PP_ASSERT_WITH_CODE(!ret,
3205                                 "Attempt to get dcefclk levels Failed!",
3206                                 return ret);
3207
3208                 for (i = 0; i < clocks.num_levels; i++)
3209                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3210                                 i, clocks.data[i].clocks_in_khz / 1000,
3211                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3212                 break;
3213
3214         case PP_PCIE:
3215                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3216                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3217                             >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3218                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3219                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3220                             >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3221                 for (i = 0; i < NUM_LINK_LEVELS; i++)
3222                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3223                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
3224                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
3225                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
3226                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
3227                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
3228                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
3229                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
3230                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
3231                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
3232                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
3233                                         pptable->LclkFreq[i],
3234                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
3235                                         (lane_width == pptable->PcieLaneCount[i]) ?
3236                                         "*" : "");
3237                 break;
3238
3239         case OD_SCLK:
3240                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3241                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3242                         size = sprintf(buf, "%s:\n", "OD_SCLK");
3243                         size += sprintf(buf + size, "0: %10uMhz\n",
3244                                 od_table->GfxclkFmin);
3245                         size += sprintf(buf + size, "1: %10uMhz\n",
3246                                 od_table->GfxclkFmax);
3247                 }
3248                 break;
3249
3250         case OD_MCLK:
3251                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3252                         size = sprintf(buf, "%s:\n", "OD_MCLK");
3253                         size += sprintf(buf + size, "1: %10uMhz\n",
3254                                 od_table->UclkFmax);
3255                 }
3256
3257                 break;
3258
3259         case OD_VDDC_CURVE:
3260                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3261                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3262                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3263                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3264                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3265                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3266                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
3267                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3268                                 od_table->GfxclkFreq1,
3269                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3270                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3271                                 od_table->GfxclkFreq2,
3272                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3273                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3274                                 od_table->GfxclkFreq3,
3275                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3276                 }
3277
3278                 break;
3279
3280         case OD_RANGE:
3281                 size = sprintf(buf, "%s:\n", "OD_RANGE");
3282
3283                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3284                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3285                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3286                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3287                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3288                 }
3289
3290                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3291                         ret = vega20_get_memclocks(hwmgr, &clocks);
3292                         PP_ASSERT_WITH_CODE(!ret,
3293                                         "Fail to get memory clk levels!",
3294                                         return ret);
3295
3296                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3297                                 clocks.data[0].clocks_in_khz / 1000,
3298                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3299                 }
3300
3301                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3302                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3303                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3304                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3305                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3306                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3307                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3308                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3309                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3310                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3311                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3312                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3313                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3314                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3315                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3316                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3317                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3318                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3319                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3320                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3321                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3322                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3323                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3324                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3325                 }
3326
3327                 break;
3328         default:
3329                 break;
3330         }
3331         return size;
3332 }
3333
3334 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3335                 struct vega20_single_dpm_table *dpm_table)
3336 {
3337         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3338         int ret = 0;
3339
3340         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3341                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3342                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3343                                 return -EINVAL);
3344                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3345                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3346                                 return -EINVAL);
3347
3348                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3349                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3350                                 PPSMC_MSG_SetHardMinByFreq,
3351                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
3352                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3353                                 return ret);
3354         }
3355
3356         return ret;
3357 }
3358
3359 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3360 {
3361         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3362         int ret = 0;
3363
3364         smum_send_msg_to_smc_with_parameter(hwmgr,
3365                         PPSMC_MSG_NumOfDisplays, 0);
3366
3367         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3368                         &data->dpm_table.mem_table);
3369
3370         return ret;
3371 }
3372
3373 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3374 {
3375         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3376         int result = 0;
3377         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3378
3379         if ((data->water_marks_bitmap & WaterMarksExist) &&
3380             !(data->water_marks_bitmap & WaterMarksLoaded)) {
3381                 result = smum_smc_table_manager(hwmgr,
3382                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3383                 PP_ASSERT_WITH_CODE(!result,
3384                                 "Failed to update WMTABLE!",
3385                                 return result);
3386                 data->water_marks_bitmap |= WaterMarksLoaded;
3387         }
3388
3389         if ((data->water_marks_bitmap & WaterMarksExist) &&
3390             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3391             data->smu_features[GNLD_DPM_SOCCLK].supported) {
3392                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3393                         PPSMC_MSG_NumOfDisplays,
3394                         hwmgr->display_config->num_display);
3395         }
3396
3397         return result;
3398 }
3399
3400 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3401 {
3402         struct vega20_hwmgr *data =
3403                         (struct vega20_hwmgr *)(hwmgr->backend);
3404         int ret = 0;
3405
3406         if (data->smu_features[GNLD_DPM_UVD].supported) {
3407                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3408                         if (enable)
3409                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3410                         else
3411                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3412                 }
3413
3414                 ret = vega20_enable_smc_features(hwmgr,
3415                                 enable,
3416                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3417                 PP_ASSERT_WITH_CODE(!ret,
3418                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3419                                 return ret);
3420                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3421         }
3422
3423         return 0;
3424 }
3425
3426 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3427 {
3428         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3429
3430         if (data->vce_power_gated == bgate)
3431                 return ;
3432
3433         data->vce_power_gated = bgate;
3434         vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3435 }
3436
3437 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3438 {
3439         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3440
3441         if (data->uvd_power_gated == bgate)
3442                 return ;
3443
3444         data->uvd_power_gated = bgate;
3445         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3446 }
3447
3448 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3449 {
3450         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3451         struct vega20_single_dpm_table *dpm_table;
3452         bool vblank_too_short = false;
3453         bool disable_mclk_switching;
3454         uint32_t i, latency;
3455
3456         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3457                            !hwmgr->display_config->multi_monitor_in_sync) ||
3458                             vblank_too_short;
3459         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3460
3461         /* gfxclk */
3462         dpm_table = &(data->dpm_table.gfx_table);
3463         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3464         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3465         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3466         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3467
3468         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3469                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3470                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3471                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3472                 }
3473
3474                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3475                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3476                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3477                 }
3478
3479                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3480                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3481                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3482                 }
3483         }
3484
3485         /* memclk */
3486         dpm_table = &(data->dpm_table.mem_table);
3487         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3488         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3489         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3490         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3491
3492         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3493                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3494                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3495                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3496                 }
3497
3498                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3499                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3500                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3501                 }
3502
3503                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3504                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3505                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3506                 }
3507         }
3508
3509         /* honour DAL's UCLK Hardmin */
3510         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3511                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3512
3513         /* Hardmin is dependent on displayconfig */
3514         if (disable_mclk_switching) {
3515                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3516                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3517                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3518                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3519                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3520                                         break;
3521                                 }
3522                         }
3523                 }
3524         }
3525
3526         if (hwmgr->display_config->nb_pstate_switch_disable)
3527                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3528
3529         /* vclk */
3530         dpm_table = &(data->dpm_table.vclk_table);
3531         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3532         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3533         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3534         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3535
3536         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3537                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3538                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3539                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3540                 }
3541
3542                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3543                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3544                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3545                 }
3546         }
3547
3548         /* dclk */
3549         dpm_table = &(data->dpm_table.dclk_table);
3550         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3551         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3552         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3553         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3554
3555         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3556                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3557                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3558                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3559                 }
3560
3561                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3562                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3563                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3564                 }
3565         }
3566
3567         /* socclk */
3568         dpm_table = &(data->dpm_table.soc_table);
3569         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3570         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3571         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3572         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3573
3574         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3575                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3576                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3577                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3578                 }
3579
3580                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3581                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3582                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3583                 }
3584         }
3585
3586         /* eclk */
3587         dpm_table = &(data->dpm_table.eclk_table);
3588         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3589         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3590         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3591         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3592
3593         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3594                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3595                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3596                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3597                 }
3598
3599                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3600                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3601                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3602                 }
3603         }
3604
3605         return 0;
3606 }
3607
3608 static bool
3609 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3610 {
3611         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3612         bool is_update_required = false;
3613
3614         if (data->display_timing.num_existing_displays !=
3615                         hwmgr->display_config->num_display)
3616                 is_update_required = true;
3617
3618         if (data->registry_data.gfx_clk_deep_sleep_support &&
3619            (data->display_timing.min_clock_in_sr !=
3620             hwmgr->display_config->min_core_set_clock_in_sr))
3621                 is_update_required = true;
3622
3623         return is_update_required;
3624 }
3625
3626 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3627 {
3628         int ret = 0;
3629
3630         ret = vega20_disable_all_smu_features(hwmgr);
3631         PP_ASSERT_WITH_CODE(!ret,
3632                         "[DisableDpmTasks] Failed to disable all smu features!",
3633                         return ret);
3634
3635         return 0;
3636 }
3637
3638 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3639 {
3640         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3641         int result;
3642
3643         result = vega20_disable_dpm_tasks(hwmgr);
3644         PP_ASSERT_WITH_CODE((0 == result),
3645                         "[PowerOffAsic] Failed to disable DPM!",
3646                         );
3647         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3648
3649         return result;
3650 }
3651
3652 static int conv_power_profile_to_pplib_workload(int power_profile)
3653 {
3654         int pplib_workload = 0;
3655
3656         switch (power_profile) {
3657         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3658                 pplib_workload = WORKLOAD_DEFAULT_BIT;
3659                 break;
3660         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3661                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3662                 break;
3663         case PP_SMC_POWER_PROFILE_POWERSAVING:
3664                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3665                 break;
3666         case PP_SMC_POWER_PROFILE_VIDEO:
3667                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3668                 break;
3669         case PP_SMC_POWER_PROFILE_VR:
3670                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3671                 break;
3672         case PP_SMC_POWER_PROFILE_COMPUTE:
3673                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3674                 break;
3675         case PP_SMC_POWER_PROFILE_CUSTOM:
3676                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3677                 break;
3678         }
3679
3680         return pplib_workload;
3681 }
3682
3683 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3684 {
3685         DpmActivityMonitorCoeffInt_t activity_monitor;
3686         uint32_t i, size = 0;
3687         uint16_t workload_type = 0;
3688         static const char *profile_name[] = {
3689                                         "BOOTUP_DEFAULT",
3690                                         "3D_FULL_SCREEN",
3691                                         "POWER_SAVING",
3692                                         "VIDEO",
3693                                         "VR",
3694                                         "COMPUTE",
3695                                         "CUSTOM"};
3696         static const char *title[] = {
3697                         "PROFILE_INDEX(NAME)",
3698                         "CLOCK_TYPE(NAME)",
3699                         "FPS",
3700                         "UseRlcBusy",
3701                         "MinActiveFreqType",
3702                         "MinActiveFreq",
3703                         "BoosterFreqType",
3704                         "BoosterFreq",
3705                         "PD_Data_limit_c",
3706                         "PD_Data_error_coeff",
3707                         "PD_Data_error_rate_coeff"};
3708         int result = 0;
3709
3710         if (!buf)
3711                 return -EINVAL;
3712
3713         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3714                         title[0], title[1], title[2], title[3], title[4], title[5],
3715                         title[6], title[7], title[8], title[9], title[10]);
3716
3717         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3718                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3719                 workload_type = conv_power_profile_to_pplib_workload(i);
3720                 result = vega20_get_activity_monitor_coeff(hwmgr,
3721                                 (uint8_t *)(&activity_monitor), workload_type);
3722                 PP_ASSERT_WITH_CODE(!result,
3723                                 "[GetPowerProfile] Failed to get activity monitor!",
3724                                 return result);
3725
3726                 size += sprintf(buf + size, "%2d %14s%s:\n",
3727                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3728
3729                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3730                         " ",
3731                         0,
3732                         "GFXCLK",
3733                         activity_monitor.Gfx_FPS,
3734                         activity_monitor.Gfx_UseRlcBusy,
3735                         activity_monitor.Gfx_MinActiveFreqType,
3736                         activity_monitor.Gfx_MinActiveFreq,
3737                         activity_monitor.Gfx_BoosterFreqType,
3738                         activity_monitor.Gfx_BoosterFreq,
3739                         activity_monitor.Gfx_PD_Data_limit_c,
3740                         activity_monitor.Gfx_PD_Data_error_coeff,
3741                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3742
3743                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3744                         " ",
3745                         1,
3746                         "SOCCLK",
3747                         activity_monitor.Soc_FPS,
3748                         activity_monitor.Soc_UseRlcBusy,
3749                         activity_monitor.Soc_MinActiveFreqType,
3750                         activity_monitor.Soc_MinActiveFreq,
3751                         activity_monitor.Soc_BoosterFreqType,
3752                         activity_monitor.Soc_BoosterFreq,
3753                         activity_monitor.Soc_PD_Data_limit_c,
3754                         activity_monitor.Soc_PD_Data_error_coeff,
3755                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3756
3757                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3758                         " ",
3759                         2,
3760                         "UCLK",
3761                         activity_monitor.Mem_FPS,
3762                         activity_monitor.Mem_UseRlcBusy,
3763                         activity_monitor.Mem_MinActiveFreqType,
3764                         activity_monitor.Mem_MinActiveFreq,
3765                         activity_monitor.Mem_BoosterFreqType,
3766                         activity_monitor.Mem_BoosterFreq,
3767                         activity_monitor.Mem_PD_Data_limit_c,
3768                         activity_monitor.Mem_PD_Data_error_coeff,
3769                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3770
3771                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3772                         " ",
3773                         3,
3774                         "FCLK",
3775                         activity_monitor.Fclk_FPS,
3776                         activity_monitor.Fclk_UseRlcBusy,
3777                         activity_monitor.Fclk_MinActiveFreqType,
3778                         activity_monitor.Fclk_MinActiveFreq,
3779                         activity_monitor.Fclk_BoosterFreqType,
3780                         activity_monitor.Fclk_BoosterFreq,
3781                         activity_monitor.Fclk_PD_Data_limit_c,
3782                         activity_monitor.Fclk_PD_Data_error_coeff,
3783                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
3784         }
3785
3786         return size;
3787 }
3788
3789 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3790 {
3791         DpmActivityMonitorCoeffInt_t activity_monitor;
3792         int workload_type, result = 0;
3793
3794         hwmgr->power_profile_mode = input[size];
3795
3796         if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3797                 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3798                 return -EINVAL;
3799         }
3800
3801         if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3802                 if (size < 10)
3803                         return -EINVAL;
3804
3805                 result = vega20_get_activity_monitor_coeff(hwmgr,
3806                                 (uint8_t *)(&activity_monitor),
3807                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3808                 PP_ASSERT_WITH_CODE(!result,
3809                                 "[SetPowerProfile] Failed to get activity monitor!",
3810                                 return result);
3811
3812                 switch (input[0]) {
3813                 case 0: /* Gfxclk */
3814                         activity_monitor.Gfx_FPS = input[1];
3815                         activity_monitor.Gfx_UseRlcBusy = input[2];
3816                         activity_monitor.Gfx_MinActiveFreqType = input[3];
3817                         activity_monitor.Gfx_MinActiveFreq = input[4];
3818                         activity_monitor.Gfx_BoosterFreqType = input[5];
3819                         activity_monitor.Gfx_BoosterFreq = input[6];
3820                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
3821                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3822                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3823                         break;
3824                 case 1: /* Socclk */
3825                         activity_monitor.Soc_FPS = input[1];
3826                         activity_monitor.Soc_UseRlcBusy = input[2];
3827                         activity_monitor.Soc_MinActiveFreqType = input[3];
3828                         activity_monitor.Soc_MinActiveFreq = input[4];
3829                         activity_monitor.Soc_BoosterFreqType = input[5];
3830                         activity_monitor.Soc_BoosterFreq = input[6];
3831                         activity_monitor.Soc_PD_Data_limit_c = input[7];
3832                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
3833                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3834                         break;
3835                 case 2: /* Uclk */
3836                         activity_monitor.Mem_FPS = input[1];
3837                         activity_monitor.Mem_UseRlcBusy = input[2];
3838                         activity_monitor.Mem_MinActiveFreqType = input[3];
3839                         activity_monitor.Mem_MinActiveFreq = input[4];
3840                         activity_monitor.Mem_BoosterFreqType = input[5];
3841                         activity_monitor.Mem_BoosterFreq = input[6];
3842                         activity_monitor.Mem_PD_Data_limit_c = input[7];
3843                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
3844                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3845                         break;
3846                 case 3: /* Fclk */
3847                         activity_monitor.Fclk_FPS = input[1];
3848                         activity_monitor.Fclk_UseRlcBusy = input[2];
3849                         activity_monitor.Fclk_MinActiveFreqType = input[3];
3850                         activity_monitor.Fclk_MinActiveFreq = input[4];
3851                         activity_monitor.Fclk_BoosterFreqType = input[5];
3852                         activity_monitor.Fclk_BoosterFreq = input[6];
3853                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
3854                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3855                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3856                         break;
3857                 }
3858
3859                 result = vega20_set_activity_monitor_coeff(hwmgr,
3860                                 (uint8_t *)(&activity_monitor),
3861                                 WORKLOAD_PPLIB_CUSTOM_BIT);
3862                 PP_ASSERT_WITH_CODE(!result,
3863                                 "[SetPowerProfile] Failed to set activity monitor!",
3864                                 return result);
3865         }
3866
3867         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3868         workload_type =
3869                 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3870         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3871                                                 1 << workload_type);
3872
3873         return 0;
3874 }
3875
3876 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3877                                         uint32_t virtual_addr_low,
3878                                         uint32_t virtual_addr_hi,
3879                                         uint32_t mc_addr_low,
3880                                         uint32_t mc_addr_hi,
3881                                         uint32_t size)
3882 {
3883         smum_send_msg_to_smc_with_parameter(hwmgr,
3884                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3885                                         virtual_addr_hi);
3886         smum_send_msg_to_smc_with_parameter(hwmgr,
3887                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
3888                                         virtual_addr_low);
3889         smum_send_msg_to_smc_with_parameter(hwmgr,
3890                                         PPSMC_MSG_DramLogSetDramAddrHigh,
3891                                         mc_addr_hi);
3892
3893         smum_send_msg_to_smc_with_parameter(hwmgr,
3894                                         PPSMC_MSG_DramLogSetDramAddrLow,
3895                                         mc_addr_low);
3896
3897         smum_send_msg_to_smc_with_parameter(hwmgr,
3898                                         PPSMC_MSG_DramLogSetDramSize,
3899                                         size);
3900         return 0;
3901 }
3902
3903 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3904                 struct PP_TemperatureRange *thermal_data)
3905 {
3906         struct phm_ppt_v3_information *pptable_information =
3907                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3908
3909         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3910
3911         thermal_data->max = pptable_information->us_software_shutdown_temp *
3912                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3913
3914         return 0;
3915 }
3916
3917 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3918         /* init/fini related */
3919         .backend_init = vega20_hwmgr_backend_init,
3920         .backend_fini = vega20_hwmgr_backend_fini,
3921         .asic_setup = vega20_setup_asic_task,
3922         .power_off_asic = vega20_power_off_asic,
3923         .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3924         .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3925         /* power state related */
3926         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3927         .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3928         .display_config_changed = vega20_display_configuration_changed_task,
3929         .check_smc_update_required_for_display_configuration =
3930                 vega20_check_smc_update_required_for_display_configuration,
3931         .notify_smc_display_config_after_ps_adjustment =
3932                 vega20_notify_smc_display_config_after_ps_adjustment,
3933         /* export to DAL */
3934         .get_sclk = vega20_dpm_get_sclk,
3935         .get_mclk = vega20_dpm_get_mclk,
3936         .get_dal_power_level = vega20_get_dal_power_level,
3937         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3938         .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3939         .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3940         .display_clock_voltage_request = vega20_display_clock_voltage_request,
3941         .get_performance_level = vega20_get_performance_level,
3942         /* UMD pstate, profile related */
3943         .force_dpm_level = vega20_dpm_force_dpm_level,
3944         .get_power_profile_mode = vega20_get_power_profile_mode,
3945         .set_power_profile_mode = vega20_set_power_profile_mode,
3946         /* od related */
3947         .set_power_limit = vega20_set_power_limit,
3948         .get_sclk_od = vega20_get_sclk_od,
3949         .set_sclk_od = vega20_set_sclk_od,
3950         .get_mclk_od = vega20_get_mclk_od,
3951         .set_mclk_od = vega20_set_mclk_od,
3952         .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3953         /* for sysfs to retrive/set gfxclk/memclk */
3954         .force_clock_level = vega20_force_clock_level,
3955         .print_clock_levels = vega20_print_clock_levels,
3956         .read_sensor = vega20_read_sensor,
3957         .get_ppfeature_status = vega20_get_ppfeature_status,
3958         .set_ppfeature_status = vega20_set_ppfeature_status,
3959         /* powergate related */
3960         .powergate_uvd = vega20_power_gate_uvd,
3961         .powergate_vce = vega20_power_gate_vce,
3962         /* thermal related */
3963         .start_thermal_controller = vega20_start_thermal_controller,
3964         .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3965         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3966         .register_irq_handlers = smu9_register_irq_handlers,
3967         .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3968         /* fan control related */
3969         .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3970         .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
3971         .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
3972         .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
3973         .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
3974         .get_fan_control_mode = vega20_get_fan_control_mode,
3975         .set_fan_control_mode = vega20_set_fan_control_mode,
3976         /* smu memory related */
3977         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
3978         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
3979         /* BACO related */
3980         .get_asic_baco_capability = vega20_baco_get_capability,
3981         .get_asic_baco_state = vega20_baco_get_state,
3982         .set_asic_baco_state = vega20_baco_set_state,
3983 };
3984
3985 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3986 {
3987         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3988         hwmgr->pptable_func = &vega20_pptable_funcs;
3989
3990         return 0;
3991 }