2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
53 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
55 struct vega20_hwmgr *data =
56 (struct vega20_hwmgr *)(hwmgr->backend);
58 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
59 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
60 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
61 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
62 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
64 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
65 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
66 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
67 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
68 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
69 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 * Disable the following features for now:
88 data->registry_data.disallowed_features = 0xE0041C00;
89 data->registry_data.od_state_in_dc_support = 0;
90 data->registry_data.thermal_support = 1;
91 data->registry_data.skip_baco_hardware = 0;
93 data->registry_data.log_avfs_param = 0;
94 data->registry_data.sclk_throttle_low_notification = 1;
95 data->registry_data.force_dpm_high = 0;
96 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
98 data->registry_data.didt_support = 0;
99 if (data->registry_data.didt_support) {
100 data->registry_data.didt_mode = 6;
101 data->registry_data.sq_ramping_support = 1;
102 data->registry_data.db_ramping_support = 0;
103 data->registry_data.td_ramping_support = 0;
104 data->registry_data.tcp_ramping_support = 0;
105 data->registry_data.dbr_ramping_support = 0;
106 data->registry_data.edc_didt_support = 1;
107 data->registry_data.gc_didt_support = 0;
108 data->registry_data.psm_didt_support = 0;
111 data->registry_data.pcie_lane_override = 0xff;
112 data->registry_data.pcie_speed_override = 0xff;
113 data->registry_data.pcie_clock_override = 0xffffffff;
114 data->registry_data.regulator_hot_gpio_support = 1;
115 data->registry_data.ac_dc_switch_gpio_support = 0;
116 data->registry_data.quick_transition_support = 0;
117 data->registry_data.zrpm_start_temp = 0xffff;
118 data->registry_data.zrpm_stop_temp = 0xffff;
119 data->registry_data.od8_feature_enable = 1;
120 data->registry_data.disable_water_mark = 0;
121 data->registry_data.disable_pp_tuning = 0;
122 data->registry_data.disable_xlpp_tuning = 0;
123 data->registry_data.disable_workload_policy = 0;
124 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
125 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
126 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
127 data->registry_data.force_workload_policy_mask = 0;
128 data->registry_data.disable_3d_fs_detection = 0;
129 data->registry_data.fps_support = 1;
130 data->registry_data.disable_auto_wattman = 1;
131 data->registry_data.auto_wattman_debug = 0;
132 data->registry_data.auto_wattman_sample_period = 100;
133 data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
134 data->registry_data.auto_wattman_threshold = 50;
135 data->registry_data.gfxoff_controlled_by_driver = 1;
136 data->gfxoff_allowed = false;
137 data->counter_gfxoff = 0;
140 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
142 struct vega20_hwmgr *data =
143 (struct vega20_hwmgr *)(hwmgr->backend);
144 struct amdgpu_device *adev = hwmgr->adev;
146 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
147 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
148 PHM_PlatformCaps_ControlVDDCI);
150 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
151 PHM_PlatformCaps_TablelessHardwareInterface);
153 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
154 PHM_PlatformCaps_EnableSMU7ThermalManagement);
156 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_UVDPowerGating);
160 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_VCEPowerGating);
164 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
165 PHM_PlatformCaps_UnTabledHardwareInterface);
167 if (data->registry_data.od8_feature_enable)
168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
169 PHM_PlatformCaps_OD8inACSupport);
171 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
172 PHM_PlatformCaps_ActivityReporting);
173 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
174 PHM_PlatformCaps_FanSpeedInTableIsRPM);
176 if (data->registry_data.od_state_in_dc_support) {
177 if (data->registry_data.od8_feature_enable)
178 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
179 PHM_PlatformCaps_OD8inDCSupport);
182 if (data->registry_data.thermal_support &&
183 data->registry_data.fuzzy_fan_control_support &&
184 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
185 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
186 PHM_PlatformCaps_ODFuzzyFanControlSupport);
188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 PHM_PlatformCaps_DynamicPowerManagement);
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_SMC);
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_ThermalPolicyDelay);
195 if (data->registry_data.force_dpm_high)
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
199 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
200 PHM_PlatformCaps_DynamicUVDState);
202 if (data->registry_data.sclk_throttle_low_notification)
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_SclkThrottleLowNotification);
206 /* power tune caps */
207 /* assume disabled */
208 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_PowerContainment);
210 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
211 PHM_PlatformCaps_DiDtSupport);
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_SQRamping);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_DBRamping);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_TDRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_TCPRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_DBRRamping);
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_DiDtEDCEnable);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_GCEDC);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_PSM);
229 if (data->registry_data.didt_support) {
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_DiDtSupport);
232 if (data->registry_data.sq_ramping_support)
233 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
234 PHM_PlatformCaps_SQRamping);
235 if (data->registry_data.db_ramping_support)
236 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_DBRamping);
238 if (data->registry_data.td_ramping_support)
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_TDRamping);
241 if (data->registry_data.tcp_ramping_support)
242 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
243 PHM_PlatformCaps_TCPRamping);
244 if (data->registry_data.dbr_ramping_support)
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
246 PHM_PlatformCaps_DBRRamping);
247 if (data->registry_data.edc_didt_support)
248 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
249 PHM_PlatformCaps_DiDtEDCEnable);
250 if (data->registry_data.gc_didt_support)
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
252 PHM_PlatformCaps_GCEDC);
253 if (data->registry_data.psm_didt_support)
254 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_PSM);
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_RegulatorHot);
261 if (data->registry_data.ac_dc_switch_gpio_support) {
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_AutomaticDCTransition);
264 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
265 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
268 if (data->registry_data.quick_transition_support) {
269 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_AutomaticDCTransition);
271 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
272 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
273 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_Falcon_QuickTransition);
277 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
278 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_LowestUclkReservedForUlv);
280 if (data->lowest_uclk_reserved_for_ulv == 1)
281 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
282 PHM_PlatformCaps_LowestUclkReservedForUlv);
285 if (data->registry_data.custom_fan_support)
286 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
287 PHM_PlatformCaps_CustomFanControlSupport);
292 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
294 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
297 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
298 FEATURE_DPM_PREFETCHER_BIT;
299 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
300 FEATURE_DPM_GFXCLK_BIT;
301 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
302 FEATURE_DPM_UCLK_BIT;
303 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
304 FEATURE_DPM_SOCCLK_BIT;
305 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
307 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
309 data->smu_features[GNLD_ULV].smu_feature_id =
311 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
312 FEATURE_DPM_MP0CLK_BIT;
313 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
314 FEATURE_DPM_LINK_BIT;
315 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
316 FEATURE_DPM_DCEFCLK_BIT;
317 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
318 FEATURE_DS_GFXCLK_BIT;
319 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
320 FEATURE_DS_SOCCLK_BIT;
321 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
323 data->smu_features[GNLD_PPT].smu_feature_id =
325 data->smu_features[GNLD_TDC].smu_feature_id =
327 data->smu_features[GNLD_THERMAL].smu_feature_id =
329 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
330 FEATURE_GFX_PER_CU_CG_BIT;
331 data->smu_features[GNLD_RM].smu_feature_id =
333 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
334 FEATURE_DS_DCEFCLK_BIT;
335 data->smu_features[GNLD_ACDC].smu_feature_id =
337 data->smu_features[GNLD_VR0HOT].smu_feature_id =
339 data->smu_features[GNLD_VR1HOT].smu_feature_id =
341 data->smu_features[GNLD_FW_CTF].smu_feature_id =
343 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
344 FEATURE_LED_DISPLAY_BIT;
345 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
346 FEATURE_FAN_CONTROL_BIT;
347 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
348 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
349 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
350 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
351 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
352 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
353 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
354 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
356 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
357 data->smu_features[i].smu_feature_bitmap =
358 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
359 data->smu_features[i].allowed =
360 ((data->registry_data.disallowed_features >> i) & 1) ?
365 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
370 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
372 kfree(hwmgr->backend);
373 hwmgr->backend = NULL;
378 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
380 struct vega20_hwmgr *data;
381 struct amdgpu_device *adev = hwmgr->adev;
383 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
387 hwmgr->backend = data;
389 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
390 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
391 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
393 vega20_set_default_registry_data(hwmgr);
395 data->disable_dpm_mask = 0xff;
397 /* need to set voltage control types before EVV patching */
398 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
399 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
400 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
402 data->water_marks_bitmap = 0;
403 data->avfs_exist = false;
405 vega20_set_features_platform_caps(hwmgr);
407 vega20_init_dpm_defaults(hwmgr);
409 /* Parse pptable data read from VBIOS */
410 vega20_set_private_data_based_on_pptable(hwmgr);
412 data->is_tlu_enabled = false;
414 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
415 VEGA20_MAX_HARDWARE_POWERLEVELS;
416 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
417 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
419 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
420 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
421 hwmgr->platform_descriptor.clockStep.engineClock = 500;
422 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
424 data->total_active_cus = adev->gfx.cu_info.number;
429 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
431 struct vega20_hwmgr *data =
432 (struct vega20_hwmgr *)(hwmgr->backend);
434 data->low_sclk_interrupt_threshold = 0;
439 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
443 ret = vega20_init_sclk_threshold(hwmgr);
444 PP_ASSERT_WITH_CODE(!ret,
445 "Failed to init sclk threshold!",
452 * @fn vega20_init_dpm_state
453 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
455 * @param dpm_state - the address of the DPM Table to initiailize.
458 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
460 dpm_state->soft_min_level = 0x0;
461 dpm_state->soft_max_level = 0xffff;
462 dpm_state->hard_min_level = 0x0;
463 dpm_state->hard_max_level = 0xffff;
466 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
467 PPCLK_e clk_id, uint32_t *num_of_levels)
471 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
472 PPSMC_MSG_GetDpmFreqByIndex,
473 (clk_id << 16 | 0xFF));
474 PP_ASSERT_WITH_CODE(!ret,
475 "[GetNumOfDpmLevel] failed to get dpm levels!",
478 *num_of_levels = smum_get_argument(hwmgr);
479 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
480 "[GetNumOfDpmLevel] number of clk levels is invalid!",
486 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
487 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
491 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
492 PPSMC_MSG_GetDpmFreqByIndex,
493 (clk_id << 16 | index));
494 PP_ASSERT_WITH_CODE(!ret,
495 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
498 *clk = smum_get_argument(hwmgr);
499 PP_ASSERT_WITH_CODE(*clk,
500 "[GetDpmFreqByIndex] clk value is invalid!",
506 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
507 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
510 uint32_t i, num_of_levels, clk;
512 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
513 PP_ASSERT_WITH_CODE(!ret,
514 "[SetupSingleDpmTable] failed to get clk levels!",
517 dpm_table->count = num_of_levels;
519 for (i = 0; i < num_of_levels; i++) {
520 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
521 PP_ASSERT_WITH_CODE(!ret,
522 "[SetupSingleDpmTable] failed to get clk of specific level!",
524 dpm_table->dpm_levels[i].value = clk;
525 dpm_table->dpm_levels[i].enabled = true;
531 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
533 struct vega20_hwmgr *data =
534 (struct vega20_hwmgr *)(hwmgr->backend);
535 struct vega20_single_dpm_table *dpm_table;
538 dpm_table = &(data->dpm_table.gfx_table);
539 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
540 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
541 PP_ASSERT_WITH_CODE(!ret,
542 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
545 dpm_table->count = 1;
546 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
552 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
554 struct vega20_hwmgr *data =
555 (struct vega20_hwmgr *)(hwmgr->backend);
556 struct vega20_single_dpm_table *dpm_table;
559 dpm_table = &(data->dpm_table.mem_table);
560 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
561 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
562 PP_ASSERT_WITH_CODE(!ret,
563 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
566 dpm_table->count = 1;
567 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
574 * This function is to initialize all DPM state tables
575 * for SMU based on the dependency table.
576 * Dynamic state patching function will then trim these
577 * state tables to the allowed range based
578 * on the power policy or external client requests,
579 * such as UVD request, etc.
581 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
583 struct vega20_hwmgr *data =
584 (struct vega20_hwmgr *)(hwmgr->backend);
585 struct vega20_single_dpm_table *dpm_table;
588 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
591 dpm_table = &(data->dpm_table.soc_table);
592 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
593 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
594 PP_ASSERT_WITH_CODE(!ret,
595 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
598 dpm_table->count = 1;
599 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
601 vega20_init_dpm_state(&(dpm_table->dpm_state));
604 dpm_table = &(data->dpm_table.gfx_table);
605 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
608 vega20_init_dpm_state(&(dpm_table->dpm_state));
611 dpm_table = &(data->dpm_table.mem_table);
612 ret = vega20_setup_memclk_dpm_table(hwmgr);
615 vega20_init_dpm_state(&(dpm_table->dpm_state));
618 dpm_table = &(data->dpm_table.eclk_table);
619 if (data->smu_features[GNLD_DPM_VCE].enabled) {
620 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
621 PP_ASSERT_WITH_CODE(!ret,
622 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
625 dpm_table->count = 1;
626 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
628 vega20_init_dpm_state(&(dpm_table->dpm_state));
631 dpm_table = &(data->dpm_table.vclk_table);
632 if (data->smu_features[GNLD_DPM_UVD].enabled) {
633 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
634 PP_ASSERT_WITH_CODE(!ret,
635 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
638 dpm_table->count = 1;
639 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
641 vega20_init_dpm_state(&(dpm_table->dpm_state));
644 dpm_table = &(data->dpm_table.dclk_table);
645 if (data->smu_features[GNLD_DPM_UVD].enabled) {
646 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
647 PP_ASSERT_WITH_CODE(!ret,
648 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
651 dpm_table->count = 1;
652 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
654 vega20_init_dpm_state(&(dpm_table->dpm_state));
657 dpm_table = &(data->dpm_table.dcef_table);
658 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
659 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
660 PP_ASSERT_WITH_CODE(!ret,
661 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
664 dpm_table->count = 1;
665 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
667 vega20_init_dpm_state(&(dpm_table->dpm_state));
670 dpm_table = &(data->dpm_table.pixel_table);
671 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
672 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
673 PP_ASSERT_WITH_CODE(!ret,
674 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
677 dpm_table->count = 0;
678 vega20_init_dpm_state(&(dpm_table->dpm_state));
681 dpm_table = &(data->dpm_table.display_table);
682 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
683 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
684 PP_ASSERT_WITH_CODE(!ret,
685 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
688 dpm_table->count = 0;
689 vega20_init_dpm_state(&(dpm_table->dpm_state));
692 dpm_table = &(data->dpm_table.phy_table);
693 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
694 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
695 PP_ASSERT_WITH_CODE(!ret,
696 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
699 dpm_table->count = 0;
700 vega20_init_dpm_state(&(dpm_table->dpm_state));
703 dpm_table = &(data->dpm_table.fclk_table);
704 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
705 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
706 PP_ASSERT_WITH_CODE(!ret,
707 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
710 dpm_table->count = 0;
711 vega20_init_dpm_state(&(dpm_table->dpm_state));
713 /* save a copy of the default DPM table */
714 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
715 sizeof(struct vega20_dpm_table));
721 * Initializes the SMC table and uploads it
723 * @param hwmgr the address of the powerplay hardware manager.
724 * @param pInput the pointer to input data (PowerState)
727 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
730 struct vega20_hwmgr *data =
731 (struct vega20_hwmgr *)(hwmgr->backend);
732 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
733 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
734 struct phm_ppt_v3_information *pptable_information =
735 (struct phm_ppt_v3_information *)hwmgr->pptable;
737 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
738 PP_ASSERT_WITH_CODE(!result,
739 "[InitSMCTable] Failed to get vbios bootup values!",
742 data->vbios_boot_state.vddc = boot_up_values.usVddc;
743 data->vbios_boot_state.vddci = boot_up_values.usVddci;
744 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
745 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
746 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
747 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
748 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
749 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
750 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
751 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
752 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
754 smum_send_msg_to_smc_with_parameter(hwmgr,
755 PPSMC_MSG_SetMinDeepSleepDcefclk,
756 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
758 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
760 result = smum_smc_table_manager(hwmgr,
761 (uint8_t *)pp_table, TABLE_PPTABLE, false);
762 PP_ASSERT_WITH_CODE(!result,
763 "[InitSMCTable] Failed to upload PPtable!",
769 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
771 struct vega20_hwmgr *data =
772 (struct vega20_hwmgr *)(hwmgr->backend);
773 uint32_t allowed_features_low = 0, allowed_features_high = 0;
777 for (i = 0; i < GNLD_FEATURES_MAX; i++)
778 if (data->smu_features[i].allowed)
779 data->smu_features[i].smu_feature_id > 31 ?
780 (allowed_features_high |=
781 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
783 (allowed_features_low |=
784 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
787 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
788 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
789 PP_ASSERT_WITH_CODE(!ret,
790 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
793 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
794 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
795 PP_ASSERT_WITH_CODE(!ret,
796 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
802 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
804 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
807 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
809 struct vega20_hwmgr *data =
810 (struct vega20_hwmgr *)(hwmgr->backend);
811 uint64_t features_enabled;
816 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
817 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
818 "[EnableAllSMUFeatures] Failed to enable all smu features!",
821 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
822 PP_ASSERT_WITH_CODE(!ret,
823 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
826 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
827 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
829 data->smu_features[i].enabled = enabled;
830 data->smu_features[i].supported = enabled;
833 if (data->smu_features[i].allowed && !enabled)
834 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
835 else if (!data->smu_features[i].allowed && enabled)
836 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
843 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
845 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
847 if (data->smu_features[GNLD_DPM_UCLK].enabled)
848 return smum_send_msg_to_smc_with_parameter(hwmgr,
849 PPSMC_MSG_SetUclkFastSwitch,
855 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
857 struct vega20_hwmgr *data =
858 (struct vega20_hwmgr *)(hwmgr->backend);
860 return smum_send_msg_to_smc_with_parameter(hwmgr,
861 PPSMC_MSG_SetFclkGfxClkRatio,
862 data->registry_data.fclk_gfxclk_ratio);
865 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
867 struct vega20_hwmgr *data =
868 (struct vega20_hwmgr *)(hwmgr->backend);
869 uint64_t features_enabled;
874 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
875 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
876 "[DisableAllSMUFeatures] Failed to disable all smu features!",
879 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
880 PP_ASSERT_WITH_CODE(!ret,
881 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
884 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
885 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
887 data->smu_features[i].enabled = enabled;
888 data->smu_features[i].supported = enabled;
894 static int vega20_od8_set_feature_capabilities(
895 struct pp_hwmgr *hwmgr)
897 struct phm_ppt_v3_information *pptable_information =
898 (struct phm_ppt_v3_information *)hwmgr->pptable;
899 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
900 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
901 struct vega20_od8_settings *od_settings = &(data->od8_settings);
903 od_settings->overdrive8_capabilities = 0;
905 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
906 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
907 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
908 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
909 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
910 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
911 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
913 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
914 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
915 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
916 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
917 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
918 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
919 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
920 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
923 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
924 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
925 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
926 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
927 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
928 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
929 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
932 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
933 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
934 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
935 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
936 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
937 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
939 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
940 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
941 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
942 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
943 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
944 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
945 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
947 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
948 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
949 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
950 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
951 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
952 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
953 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
956 if (data->smu_features[GNLD_THERMAL].enabled) {
957 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
958 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
959 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
960 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
961 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
962 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
964 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
965 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
966 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
967 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
968 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
969 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
972 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
973 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
975 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
976 pp_table->FanZeroRpmEnable)
977 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
982 static int vega20_od8_set_feature_id(
983 struct pp_hwmgr *hwmgr)
985 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
986 struct vega20_od8_settings *od_settings = &(data->od8_settings);
988 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
989 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
991 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
994 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
996 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1000 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1001 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1003 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1005 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1007 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1009 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1011 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1014 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1016 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1018 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1020 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1022 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1024 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1028 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1029 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1031 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1033 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1034 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1036 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1038 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1039 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1040 OD8_ACOUSTIC_LIMIT_SCLK;
1042 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1045 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1046 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1049 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1052 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1053 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1054 OD8_TEMPERATURE_FAN;
1056 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1059 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1060 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1061 OD8_TEMPERATURE_SYSTEM;
1063 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1069 static int vega20_od8_get_gfx_clock_base_voltage(
1070 struct pp_hwmgr *hwmgr,
1076 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1077 PPSMC_MSG_GetAVFSVoltageByDpm,
1078 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1079 PP_ASSERT_WITH_CODE(!ret,
1080 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1083 *voltage = smum_get_argument(hwmgr);
1084 *voltage = *voltage / VOLTAGE_SCALE;
1089 static int vega20_od8_initialize_default_settings(
1090 struct pp_hwmgr *hwmgr)
1092 struct phm_ppt_v3_information *pptable_information =
1093 (struct phm_ppt_v3_information *)hwmgr->pptable;
1094 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1095 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1096 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1099 /* Set Feature Capabilities */
1100 vega20_od8_set_feature_capabilities(hwmgr);
1102 /* Map FeatureID to individual settings */
1103 vega20_od8_set_feature_id(hwmgr);
1105 /* Set default values */
1106 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1107 PP_ASSERT_WITH_CODE(!ret,
1108 "Failed to export over drive table!",
1111 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1112 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1113 od_table->GfxclkFmin;
1114 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1115 od_table->GfxclkFmax;
1117 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1119 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1123 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1124 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1125 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1126 od_table->GfxclkFreq1;
1128 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1130 od_table->GfxclkFreq3;
1132 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1134 od_table->GfxclkFreq2;
1136 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1137 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1138 od_table->GfxclkFreq1),
1139 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1141 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1144 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1145 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1146 od_table->GfxclkFreq2),
1147 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1148 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1149 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1152 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1153 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1154 od_table->GfxclkFreq3),
1155 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1157 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1162 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1174 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1175 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1178 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1181 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1182 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1183 od_table->OverDrivePct;
1185 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1188 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1189 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1190 od_table->FanMaximumRpm;
1192 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1195 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1196 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1197 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1199 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1202 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1203 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1204 od_table->FanTargetTemperature;
1206 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1209 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1210 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1211 od_table->MaxOpTemp;
1213 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1216 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1217 if (od8_settings->od8_settings_array[i].feature_id) {
1218 od8_settings->od8_settings_array[i].min_value =
1219 pptable_information->od_settings_min[i];
1220 od8_settings->od8_settings_array[i].max_value =
1221 pptable_information->od_settings_max[i];
1222 od8_settings->od8_settings_array[i].current_value =
1223 od8_settings->od8_settings_array[i].default_value;
1225 od8_settings->od8_settings_array[i].min_value =
1227 od8_settings->od8_settings_array[i].max_value =
1229 od8_settings->od8_settings_array[i].current_value =
1234 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1235 PP_ASSERT_WITH_CODE(!ret,
1236 "Failed to import over drive table!",
1242 static int vega20_od8_set_settings(
1243 struct pp_hwmgr *hwmgr,
1247 OverDriveTable_t od_table;
1249 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1250 struct vega20_od8_single_setting *od8_settings =
1251 data->od8_settings.od8_settings_array;
1253 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1254 PP_ASSERT_WITH_CODE(!ret,
1255 "Failed to export over drive table!",
1259 case OD8_SETTING_GFXCLK_FMIN:
1260 od_table.GfxclkFmin = (uint16_t)value;
1262 case OD8_SETTING_GFXCLK_FMAX:
1263 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1264 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1267 od_table.GfxclkFmax = (uint16_t)value;
1269 case OD8_SETTING_GFXCLK_FREQ1:
1270 od_table.GfxclkFreq1 = (uint16_t)value;
1272 case OD8_SETTING_GFXCLK_VOLTAGE1:
1273 od_table.GfxclkVolt1 = (uint16_t)value;
1275 case OD8_SETTING_GFXCLK_FREQ2:
1276 od_table.GfxclkFreq2 = (uint16_t)value;
1278 case OD8_SETTING_GFXCLK_VOLTAGE2:
1279 od_table.GfxclkVolt2 = (uint16_t)value;
1281 case OD8_SETTING_GFXCLK_FREQ3:
1282 od_table.GfxclkFreq3 = (uint16_t)value;
1284 case OD8_SETTING_GFXCLK_VOLTAGE3:
1285 od_table.GfxclkVolt3 = (uint16_t)value;
1287 case OD8_SETTING_UCLK_FMAX:
1288 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1289 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1291 od_table.UclkFmax = (uint16_t)value;
1293 case OD8_SETTING_POWER_PERCENTAGE:
1294 od_table.OverDrivePct = (int16_t)value;
1296 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1297 od_table.FanMaximumRpm = (uint16_t)value;
1299 case OD8_SETTING_FAN_MIN_SPEED:
1300 od_table.FanMinimumPwm = (uint16_t)value;
1302 case OD8_SETTING_FAN_TARGET_TEMP:
1303 od_table.FanTargetTemperature = (uint16_t)value;
1305 case OD8_SETTING_OPERATING_TEMP_MAX:
1306 od_table.MaxOpTemp = (uint16_t)value;
1310 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1311 PP_ASSERT_WITH_CODE(!ret,
1312 "Failed to import over drive table!",
1318 static int vega20_get_sclk_od(
1319 struct pp_hwmgr *hwmgr)
1321 struct vega20_hwmgr *data = hwmgr->backend;
1322 struct vega20_single_dpm_table *sclk_table =
1323 &(data->dpm_table.gfx_table);
1324 struct vega20_single_dpm_table *golden_sclk_table =
1325 &(data->golden_dpm_table.gfx_table);
1326 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1327 int golden_value = golden_sclk_table->dpm_levels
1328 [golden_sclk_table->count - 1].value;
1331 value -= golden_value;
1332 value = DIV_ROUND_UP(value * 100, golden_value);
1337 static int vega20_set_sclk_od(
1338 struct pp_hwmgr *hwmgr, uint32_t value)
1340 struct vega20_hwmgr *data = hwmgr->backend;
1341 struct vega20_single_dpm_table *golden_sclk_table =
1342 &(data->golden_dpm_table.gfx_table);
1346 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1348 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1350 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1351 PP_ASSERT_WITH_CODE(!ret,
1352 "[SetSclkOD] failed to set od gfxclk!",
1355 /* retrieve updated gfxclk table */
1356 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1357 PP_ASSERT_WITH_CODE(!ret,
1358 "[SetSclkOD] failed to refresh gfxclk table!",
1364 static int vega20_get_mclk_od(
1365 struct pp_hwmgr *hwmgr)
1367 struct vega20_hwmgr *data = hwmgr->backend;
1368 struct vega20_single_dpm_table *mclk_table =
1369 &(data->dpm_table.mem_table);
1370 struct vega20_single_dpm_table *golden_mclk_table =
1371 &(data->golden_dpm_table.mem_table);
1372 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1373 int golden_value = golden_mclk_table->dpm_levels
1374 [golden_mclk_table->count - 1].value;
1377 value -= golden_value;
1378 value = DIV_ROUND_UP(value * 100, golden_value);
1383 static int vega20_set_mclk_od(
1384 struct pp_hwmgr *hwmgr, uint32_t value)
1386 struct vega20_hwmgr *data = hwmgr->backend;
1387 struct vega20_single_dpm_table *golden_mclk_table =
1388 &(data->golden_dpm_table.mem_table);
1392 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1394 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1396 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1397 PP_ASSERT_WITH_CODE(!ret,
1398 "[SetMclkOD] failed to set od memclk!",
1401 /* retrieve updated memclk table */
1402 ret = vega20_setup_memclk_dpm_table(hwmgr);
1403 PP_ASSERT_WITH_CODE(!ret,
1404 "[SetMclkOD] failed to refresh memclk table!",
1410 static int vega20_populate_umdpstate_clocks(
1411 struct pp_hwmgr *hwmgr)
1413 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1414 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1415 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1417 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1418 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1420 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1421 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1422 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1423 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1426 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1427 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1432 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1433 PP_Clock *clock, PPCLK_e clock_select)
1437 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1438 PPSMC_MSG_GetDcModeMaxDpmFreq,
1439 (clock_select << 16))) == 0,
1440 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1442 *clock = smum_get_argument(hwmgr);
1444 /* if DC limit is zero, return AC limit */
1446 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1447 PPSMC_MSG_GetMaxDpmFreq,
1448 (clock_select << 16))) == 0,
1449 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1451 *clock = smum_get_argument(hwmgr);
1457 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1459 struct vega20_hwmgr *data =
1460 (struct vega20_hwmgr *)(hwmgr->backend);
1461 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1462 &(data->max_sustainable_clocks);
1465 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1466 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1467 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1468 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1469 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1470 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1472 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1473 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1474 &(max_sustainable_clocks->uclock),
1476 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1479 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1480 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1481 &(max_sustainable_clocks->soc_clock),
1482 PPCLK_SOCCLK)) == 0,
1483 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1486 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1487 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1488 &(max_sustainable_clocks->dcef_clock),
1489 PPCLK_DCEFCLK)) == 0,
1490 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1492 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1493 &(max_sustainable_clocks->display_clock),
1494 PPCLK_DISPCLK)) == 0,
1495 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1497 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1498 &(max_sustainable_clocks->phy_clock),
1499 PPCLK_PHYCLK)) == 0,
1500 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1502 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1503 &(max_sustainable_clocks->pixel_clock),
1504 PPCLK_PIXCLK)) == 0,
1505 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1509 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1510 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1515 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1519 result = smum_send_msg_to_smc(hwmgr,
1520 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1521 PP_ASSERT_WITH_CODE(!result,
1522 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1528 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1530 struct vega20_hwmgr *data =
1531 (struct vega20_hwmgr *)(hwmgr->backend);
1533 data->uvd_power_gated = true;
1534 data->vce_power_gated = true;
1536 if (data->smu_features[GNLD_DPM_UVD].enabled)
1537 data->uvd_power_gated = false;
1539 if (data->smu_features[GNLD_DPM_VCE].enabled)
1540 data->vce_power_gated = false;
1543 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1547 smum_send_msg_to_smc_with_parameter(hwmgr,
1548 PPSMC_MSG_NumOfDisplays, 0);
1550 result = vega20_set_allowed_featuresmask(hwmgr);
1551 PP_ASSERT_WITH_CODE(!result,
1552 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1555 result = vega20_init_smc_table(hwmgr);
1556 PP_ASSERT_WITH_CODE(!result,
1557 "[EnableDPMTasks] Failed to initialize SMC table!",
1560 result = vega20_run_btc_afll(hwmgr);
1561 PP_ASSERT_WITH_CODE(!result,
1562 "[EnableDPMTasks] Failed to run btc afll!",
1565 result = vega20_enable_all_smu_features(hwmgr);
1566 PP_ASSERT_WITH_CODE(!result,
1567 "[EnableDPMTasks] Failed to enable all smu features!",
1570 result = vega20_notify_smc_display_change(hwmgr);
1571 PP_ASSERT_WITH_CODE(!result,
1572 "[EnableDPMTasks] Failed to notify smc display change!",
1575 result = vega20_send_clock_ratio(hwmgr);
1576 PP_ASSERT_WITH_CODE(!result,
1577 "[EnableDPMTasks] Failed to send clock ratio!",
1580 /* Initialize UVD/VCE powergating state */
1581 vega20_init_powergate_state(hwmgr);
1583 result = vega20_setup_default_dpm_tables(hwmgr);
1584 PP_ASSERT_WITH_CODE(!result,
1585 "[EnableDPMTasks] Failed to setup default DPM tables!",
1588 result = vega20_init_max_sustainable_clocks(hwmgr);
1589 PP_ASSERT_WITH_CODE(!result,
1590 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1593 result = vega20_power_control_set_level(hwmgr);
1594 PP_ASSERT_WITH_CODE(!result,
1595 "[EnableDPMTasks] Failed to power control set level!",
1598 result = vega20_od8_initialize_default_settings(hwmgr);
1599 PP_ASSERT_WITH_CODE(!result,
1600 "[EnableDPMTasks] Failed to initialize odn settings!",
1603 result = vega20_populate_umdpstate_clocks(hwmgr);
1604 PP_ASSERT_WITH_CODE(!result,
1605 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1608 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1609 POWER_SOURCE_AC << 16);
1610 PP_ASSERT_WITH_CODE(!result,
1611 "[GetPptLimit] get default PPT limit failed!",
1613 hwmgr->power_limit =
1614 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1619 static uint32_t vega20_find_lowest_dpm_level(
1620 struct vega20_single_dpm_table *table)
1624 for (i = 0; i < table->count; i++) {
1625 if (table->dpm_levels[i].enabled)
1628 if (i >= table->count) {
1630 table->dpm_levels[i].enabled = true;
1636 static uint32_t vega20_find_highest_dpm_level(
1637 struct vega20_single_dpm_table *table)
1641 PP_ASSERT_WITH_CODE(table != NULL,
1642 "[FindHighestDPMLevel] DPM Table does not exist!",
1644 PP_ASSERT_WITH_CODE(table->count > 0,
1645 "[FindHighestDPMLevel] DPM Table has no entry!",
1647 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1648 "[FindHighestDPMLevel] DPM Table has too many entries!",
1649 return MAX_REGULAR_DPM_NUMBER - 1);
1651 for (i = table->count - 1; i >= 0; i--) {
1652 if (table->dpm_levels[i].enabled)
1657 table->dpm_levels[i].enabled = true;
1663 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1665 struct vega20_hwmgr *data =
1666 (struct vega20_hwmgr *)(hwmgr->backend);
1670 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1671 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1672 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1673 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1674 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1675 "Failed to set soft min gfxclk !",
1679 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1680 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1681 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1682 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1683 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1684 "Failed to set soft min memclk !",
1687 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1688 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1689 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1690 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1691 "Failed to set hard min memclk !",
1695 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1696 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1698 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1699 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1700 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1701 "Failed to set soft min vclk!",
1704 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1706 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1707 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1708 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1709 "Failed to set soft min dclk!",
1713 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1714 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1716 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1717 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1718 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1719 "Failed to set soft min eclk!",
1723 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1724 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1726 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1727 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1728 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1729 "Failed to set soft min socclk!",
1736 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1738 struct vega20_hwmgr *data =
1739 (struct vega20_hwmgr *)(hwmgr->backend);
1743 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1744 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1746 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1747 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1748 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1749 "Failed to set soft max gfxclk!",
1753 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1754 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1756 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1757 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1758 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1759 "Failed to set soft max memclk!",
1763 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1764 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1766 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1767 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1768 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1769 "Failed to set soft max vclk!",
1772 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1773 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1774 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1775 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1776 "Failed to set soft max dclk!",
1780 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1781 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1783 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1784 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1785 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1786 "Failed to set soft max eclk!",
1790 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1791 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1793 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1794 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1795 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1796 "Failed to set soft max socclk!",
1803 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1805 struct vega20_hwmgr *data =
1806 (struct vega20_hwmgr *)(hwmgr->backend);
1809 if (data->smu_features[GNLD_DPM_VCE].supported) {
1810 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1812 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1814 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1817 ret = vega20_enable_smc_features(hwmgr,
1819 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1820 PP_ASSERT_WITH_CODE(!ret,
1821 "Attempt to Enable/Disable DPM VCE Failed!",
1823 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1829 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1831 PPCLK_e clock_select,
1838 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1839 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1840 "[GetClockRanges] Failed to get max clock from SMC!",
1842 *clock = smum_get_argument(hwmgr);
1844 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1845 PPSMC_MSG_GetMinDpmFreq,
1846 (clock_select << 16))) == 0,
1847 "[GetClockRanges] Failed to get min clock from SMC!",
1849 *clock = smum_get_argument(hwmgr);
1855 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1857 struct vega20_hwmgr *data =
1858 (struct vega20_hwmgr *)(hwmgr->backend);
1862 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1863 "[GetSclks]: gfxclk dpm not enabled!\n",
1867 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1868 PP_ASSERT_WITH_CODE(!ret,
1869 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1872 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1873 PP_ASSERT_WITH_CODE(!ret,
1874 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1878 return (gfx_clk * 100);
1881 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1883 struct vega20_hwmgr *data =
1884 (struct vega20_hwmgr *)(hwmgr->backend);
1888 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1889 "[MemMclks]: memclk dpm not enabled!\n",
1893 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1894 PP_ASSERT_WITH_CODE(!ret,
1895 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1898 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1899 PP_ASSERT_WITH_CODE(!ret,
1900 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1904 return (mem_clk * 100);
1907 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1911 SmuMetrics_t metrics_table;
1913 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1914 PP_ASSERT_WITH_CODE(!ret,
1915 "Failed to export SMU METRICS table!",
1918 *query = metrics_table.CurrSocketPower << 8;
1923 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1924 PPCLK_e clk_id, uint32_t *clk_freq)
1930 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1931 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1932 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1934 *clk_freq = smum_get_argument(hwmgr);
1936 *clk_freq = *clk_freq * 100;
1941 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1942 uint32_t *activity_percent)
1945 SmuMetrics_t metrics_table;
1947 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1948 PP_ASSERT_WITH_CODE(!ret,
1949 "Failed to export SMU METRICS table!",
1952 *activity_percent = metrics_table.AverageGfxActivity;
1957 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1958 void *value, int *size)
1960 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1961 struct amdgpu_device *adev = hwmgr->adev;
1966 case AMDGPU_PP_SENSOR_GFX_SCLK:
1967 ret = vega20_get_current_clk_freq(hwmgr,
1973 case AMDGPU_PP_SENSOR_GFX_MCLK:
1974 ret = vega20_get_current_clk_freq(hwmgr,
1980 case AMDGPU_PP_SENSOR_GPU_LOAD:
1981 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1985 case AMDGPU_PP_SENSOR_GPU_TEMP:
1986 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1989 case AMDGPU_PP_SENSOR_UVD_POWER:
1990 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1993 case AMDGPU_PP_SENSOR_VCE_POWER:
1994 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1997 case AMDGPU_PP_SENSOR_GPU_POWER:
1999 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2001 case AMDGPU_PP_SENSOR_VDDGFX:
2002 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2003 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2004 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2005 *((uint32_t *)value) =
2006 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2008 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2009 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2020 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2021 struct pp_display_clock_request *clock_req)
2024 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2025 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2026 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2027 PPCLK_e clk_select = 0;
2028 uint32_t clk_request = 0;
2030 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2032 case amd_pp_dcef_clock:
2033 clk_select = PPCLK_DCEFCLK;
2035 case amd_pp_disp_clock:
2036 clk_select = PPCLK_DISPCLK;
2038 case amd_pp_pixel_clock:
2039 clk_select = PPCLK_PIXCLK;
2041 case amd_pp_phy_clock:
2042 clk_select = PPCLK_PHYCLK;
2045 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2051 clk_request = (clk_select << 16) | clk_freq;
2052 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2053 PPSMC_MSG_SetHardMinByFreq,
2061 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2062 PHM_PerformanceLevelDesignation designation, uint32_t index,
2063 PHM_PerformanceLevel *level)
2068 static int vega20_notify_smc_display_config_after_ps_adjustment(
2069 struct pp_hwmgr *hwmgr)
2071 struct vega20_hwmgr *data =
2072 (struct vega20_hwmgr *)(hwmgr->backend);
2073 struct vega20_single_dpm_table *dpm_table =
2074 &data->dpm_table.mem_table;
2075 struct PP_Clocks min_clocks = {0};
2076 struct pp_display_clock_request clock_req;
2079 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2080 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2081 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2083 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2084 clock_req.clock_type = amd_pp_dcef_clock;
2085 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2086 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2087 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2088 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2089 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2090 min_clocks.dcefClockInSR / 100)) == 0,
2091 "Attempt to set divider for DCEFCLK Failed!",
2094 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2098 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2099 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2100 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2101 PPSMC_MSG_SetHardMinByFreq,
2102 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2103 "[SetHardMinFreq] Set hard min uclk failed!",
2110 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2112 struct vega20_hwmgr *data =
2113 (struct vega20_hwmgr *)(hwmgr->backend);
2114 uint32_t soft_level;
2117 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2119 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2120 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2121 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2123 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2125 data->dpm_table.mem_table.dpm_state.soft_min_level =
2126 data->dpm_table.mem_table.dpm_state.soft_max_level =
2127 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2129 ret = vega20_upload_dpm_min_level(hwmgr);
2130 PP_ASSERT_WITH_CODE(!ret,
2131 "Failed to upload boot level to highest!",
2134 ret = vega20_upload_dpm_max_level(hwmgr);
2135 PP_ASSERT_WITH_CODE(!ret,
2136 "Failed to upload dpm max level to highest!",
2142 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2144 struct vega20_hwmgr *data =
2145 (struct vega20_hwmgr *)(hwmgr->backend);
2146 uint32_t soft_level;
2149 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2151 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2152 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2153 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2155 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2157 data->dpm_table.mem_table.dpm_state.soft_min_level =
2158 data->dpm_table.mem_table.dpm_state.soft_max_level =
2159 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2161 ret = vega20_upload_dpm_min_level(hwmgr);
2162 PP_ASSERT_WITH_CODE(!ret,
2163 "Failed to upload boot level to highest!",
2166 ret = vega20_upload_dpm_max_level(hwmgr);
2167 PP_ASSERT_WITH_CODE(!ret,
2168 "Failed to upload dpm max level to highest!",
2175 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2179 ret = vega20_upload_dpm_min_level(hwmgr);
2180 PP_ASSERT_WITH_CODE(!ret,
2181 "Failed to upload DPM Bootup Levels!",
2184 ret = vega20_upload_dpm_max_level(hwmgr);
2185 PP_ASSERT_WITH_CODE(!ret,
2186 "Failed to upload DPM Max Levels!",
2192 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2193 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2195 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2196 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2197 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2198 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2204 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2205 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2206 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2207 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2208 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2209 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2212 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2214 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2216 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2217 *sclk_mask = gfx_dpm_table->count - 1;
2218 *mclk_mask = mem_dpm_table->count - 1;
2219 *soc_mask = soc_dpm_table->count - 1;
2225 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2226 enum pp_clock_type type, uint32_t mask)
2228 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2229 uint32_t soft_min_level, soft_max_level;
2234 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2235 soft_max_level = mask ? (fls(mask) - 1) : 0;
2237 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2238 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2239 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2240 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2242 ret = vega20_upload_dpm_min_level(hwmgr);
2243 PP_ASSERT_WITH_CODE(!ret,
2244 "Failed to upload boot level to lowest!",
2247 ret = vega20_upload_dpm_max_level(hwmgr);
2248 PP_ASSERT_WITH_CODE(!ret,
2249 "Failed to upload dpm max level to highest!",
2254 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2255 soft_max_level = mask ? (fls(mask) - 1) : 0;
2257 data->dpm_table.mem_table.dpm_state.soft_min_level =
2258 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2259 data->dpm_table.mem_table.dpm_state.soft_max_level =
2260 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2262 ret = vega20_upload_dpm_min_level(hwmgr);
2263 PP_ASSERT_WITH_CODE(!ret,
2264 "Failed to upload boot level to lowest!",
2267 ret = vega20_upload_dpm_max_level(hwmgr);
2268 PP_ASSERT_WITH_CODE(!ret,
2269 "Failed to upload dpm max level to highest!",
2284 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2285 enum amd_dpm_forced_level level)
2288 uint32_t sclk_mask, mclk_mask, soc_mask;
2291 case AMD_DPM_FORCED_LEVEL_HIGH:
2292 ret = vega20_force_dpm_highest(hwmgr);
2295 case AMD_DPM_FORCED_LEVEL_LOW:
2296 ret = vega20_force_dpm_lowest(hwmgr);
2299 case AMD_DPM_FORCED_LEVEL_AUTO:
2300 ret = vega20_unforce_dpm_levels(hwmgr);
2303 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2304 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2305 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2306 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2307 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2310 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2311 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2314 case AMD_DPM_FORCED_LEVEL_MANUAL:
2315 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2323 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2325 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2327 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2328 return AMD_FAN_CTRL_MANUAL;
2330 return AMD_FAN_CTRL_AUTO;
2333 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2336 case AMD_FAN_CTRL_NONE:
2337 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2339 case AMD_FAN_CTRL_MANUAL:
2340 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2341 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2343 case AMD_FAN_CTRL_AUTO:
2344 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2345 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2352 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2353 struct amd_pp_simple_clock_info *info)
2356 struct phm_ppt_v2_information *table_info =
2357 (struct phm_ppt_v2_information *)hwmgr->pptable;
2358 struct phm_clock_and_voltage_limits *max_limits =
2359 &table_info->max_clock_voltage_on_ac;
2361 info->engine_max_clock = max_limits->sclk;
2362 info->memory_max_clock = max_limits->mclk;
2368 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2369 struct pp_clock_levels_with_latency *clocks)
2371 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2372 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2375 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2376 "[GetSclks]: gfxclk dpm not enabled!\n",
2379 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2380 clocks->num_levels = count;
2382 for (i = 0; i < count; i++) {
2383 clocks->data[i].clocks_in_khz =
2384 dpm_table->dpm_levels[i].value * 1000;
2385 clocks->data[i].latency_in_us = 0;
2391 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2397 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2398 struct pp_clock_levels_with_latency *clocks)
2400 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2401 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2404 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2405 "[GetMclks]: uclk dpm not enabled!\n",
2408 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2409 clocks->num_levels = data->mclk_latency_table.count = count;
2411 for (i = 0; i < count; i++) {
2412 clocks->data[i].clocks_in_khz =
2413 data->mclk_latency_table.entries[i].frequency =
2414 dpm_table->dpm_levels[i].value * 1000;
2415 clocks->data[i].latency_in_us =
2416 data->mclk_latency_table.entries[i].latency =
2417 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2423 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2424 struct pp_clock_levels_with_latency *clocks)
2426 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2427 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2430 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2431 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2434 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2435 clocks->num_levels = count;
2437 for (i = 0; i < count; i++) {
2438 clocks->data[i].clocks_in_khz =
2439 dpm_table->dpm_levels[i].value * 1000;
2440 clocks->data[i].latency_in_us = 0;
2446 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2447 struct pp_clock_levels_with_latency *clocks)
2449 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2450 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2453 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2454 "[GetSocclks]: socclk dpm not enabled!\n",
2457 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2458 clocks->num_levels = count;
2460 for (i = 0; i < count; i++) {
2461 clocks->data[i].clocks_in_khz =
2462 dpm_table->dpm_levels[i].value * 1000;
2463 clocks->data[i].latency_in_us = 0;
2470 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2471 enum amd_pp_clock_type type,
2472 struct pp_clock_levels_with_latency *clocks)
2477 case amd_pp_sys_clock:
2478 ret = vega20_get_sclks(hwmgr, clocks);
2480 case amd_pp_mem_clock:
2481 ret = vega20_get_memclocks(hwmgr, clocks);
2483 case amd_pp_dcef_clock:
2484 ret = vega20_get_dcefclocks(hwmgr, clocks);
2486 case amd_pp_soc_clock:
2487 ret = vega20_get_socclocks(hwmgr, clocks);
2496 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2497 enum amd_pp_clock_type type,
2498 struct pp_clock_levels_with_voltage *clocks)
2500 clocks->num_levels = 0;
2505 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2508 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2509 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2510 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2512 if (!data->registry_data.disable_water_mark &&
2513 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2514 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2515 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2516 data->water_marks_bitmap |= WaterMarksExist;
2517 data->water_marks_bitmap &= ~WaterMarksLoaded;
2523 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2524 enum PP_OD_DPM_TABLE_COMMAND type,
2525 long *input, uint32_t size)
2527 struct vega20_hwmgr *data =
2528 (struct vega20_hwmgr *)(hwmgr->backend);
2529 struct vega20_od8_single_setting *od8_settings =
2530 data->od8_settings.od8_settings_array;
2531 OverDriveTable_t *od_table =
2532 &(data->smc_state_table.overdrive_table);
2533 struct pp_clock_levels_with_latency clocks;
2534 int32_t input_index, input_clk, input_vol, i;
2538 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2542 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2543 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2544 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2545 pr_info("Sclk min/max frequency overdrive not supported\n");
2549 for (i = 0; i < size; i += 2) {
2551 pr_info("invalid number of input parameters %d\n",
2556 input_index = input[i];
2557 input_clk = input[i + 1];
2559 if (input_index != 0 && input_index != 1) {
2560 pr_info("Invalid index %d\n", input_index);
2561 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2565 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2566 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2567 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2569 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2570 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2574 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2575 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2576 data->gfxclk_overdrive = true;
2578 if (input_index == 0)
2579 od_table->GfxclkFmin = input_clk;
2581 od_table->GfxclkFmax = input_clk;
2586 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2587 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2588 pr_info("Mclk max frequency overdrive not supported\n");
2592 ret = vega20_get_memclocks(hwmgr, &clocks);
2593 PP_ASSERT_WITH_CODE(!ret,
2594 "Attempt to get memory clk levels failed!",
2597 for (i = 0; i < size; i += 2) {
2599 pr_info("invalid number of input parameters %d\n",
2604 input_index = input[i];
2605 input_clk = input[i + 1];
2607 if (input_index != 1) {
2608 pr_info("Invalid index %d\n", input_index);
2609 pr_info("Support max Mclk frequency setting only which index by 1\n");
2613 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2614 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2615 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2617 clocks.data[0].clocks_in_khz / 1000,
2618 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2622 if (input_index == 1 && od_table->UclkFmax != input_clk)
2623 data->memclk_overdrive = true;
2625 od_table->UclkFmax = input_clk;
2630 case PP_OD_EDIT_VDDC_CURVE:
2631 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2632 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2633 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2634 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2635 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2636 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2637 pr_info("Voltage curve calibrate not supported\n");
2641 for (i = 0; i < size; i += 3) {
2643 pr_info("invalid number of input parameters %d\n",
2648 input_index = input[i];
2649 input_clk = input[i + 1];
2650 input_vol = input[i + 2];
2652 if (input_index > 2) {
2653 pr_info("Setting for point %d is not supported\n",
2655 pr_info("Three supported points index by 0, 1, 2\n");
2659 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2660 if (input_clk < od8_settings[od8_id].min_value ||
2661 input_clk > od8_settings[od8_id].max_value) {
2662 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2664 od8_settings[od8_id].min_value,
2665 od8_settings[od8_id].max_value);
2669 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2670 if (input_vol < od8_settings[od8_id].min_value ||
2671 input_vol > od8_settings[od8_id].max_value) {
2672 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2674 od8_settings[od8_id].min_value,
2675 od8_settings[od8_id].max_value);
2679 switch (input_index) {
2681 od_table->GfxclkFreq1 = input_clk;
2682 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2685 od_table->GfxclkFreq2 = input_clk;
2686 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2689 od_table->GfxclkFreq3 = input_clk;
2690 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2696 case PP_OD_RESTORE_DEFAULT_TABLE:
2697 data->gfxclk_overdrive = false;
2698 data->memclk_overdrive = false;
2700 ret = smum_smc_table_manager(hwmgr,
2701 (uint8_t *)od_table,
2702 TABLE_OVERDRIVE, true);
2703 PP_ASSERT_WITH_CODE(!ret,
2704 "Failed to export overdrive table!",
2708 case PP_OD_COMMIT_DPM_TABLE:
2709 ret = smum_smc_table_manager(hwmgr,
2710 (uint8_t *)od_table,
2711 TABLE_OVERDRIVE, false);
2712 PP_ASSERT_WITH_CODE(!ret,
2713 "Failed to import overdrive table!",
2716 /* retrieve updated gfxclk table */
2717 if (data->gfxclk_overdrive) {
2718 data->gfxclk_overdrive = false;
2720 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2725 /* retrieve updated memclk table */
2726 if (data->memclk_overdrive) {
2727 data->memclk_overdrive = false;
2729 ret = vega20_setup_memclk_dpm_table(hwmgr);
2742 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2743 enum pp_clock_type type, char *buf)
2745 struct vega20_hwmgr *data =
2746 (struct vega20_hwmgr *)(hwmgr->backend);
2747 struct vega20_od8_single_setting *od8_settings =
2748 data->od8_settings.od8_settings_array;
2749 OverDriveTable_t *od_table =
2750 &(data->smc_state_table.overdrive_table);
2751 struct pp_clock_levels_with_latency clocks;
2752 int i, now, size = 0;
2757 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2758 PP_ASSERT_WITH_CODE(!ret,
2759 "Attempt to get current gfx clk Failed!",
2762 ret = vega20_get_sclks(hwmgr, &clocks);
2763 PP_ASSERT_WITH_CODE(!ret,
2764 "Attempt to get gfx clk levels Failed!",
2767 for (i = 0; i < clocks.num_levels; i++)
2768 size += sprintf(buf + size, "%d: %uMhz %s\n",
2769 i, clocks.data[i].clocks_in_khz / 1000,
2770 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2774 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2775 PP_ASSERT_WITH_CODE(!ret,
2776 "Attempt to get current mclk freq Failed!",
2779 ret = vega20_get_memclocks(hwmgr, &clocks);
2780 PP_ASSERT_WITH_CODE(!ret,
2781 "Attempt to get memory clk levels Failed!",
2784 for (i = 0; i < clocks.num_levels; i++)
2785 size += sprintf(buf + size, "%d: %uMhz %s\n",
2786 i, clocks.data[i].clocks_in_khz / 1000,
2787 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2794 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2795 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2796 size = sprintf(buf, "%s:\n", "OD_SCLK");
2797 size += sprintf(buf + size, "0: %10uMhz\n",
2798 od_table->GfxclkFmin);
2799 size += sprintf(buf + size, "1: %10uMhz\n",
2800 od_table->GfxclkFmax);
2805 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2806 size = sprintf(buf, "%s:\n", "OD_MCLK");
2807 size += sprintf(buf + size, "1: %10uMhz\n",
2808 od_table->UclkFmax);
2814 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2815 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2816 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2817 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2818 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2819 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2820 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2821 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2822 od_table->GfxclkFreq1,
2823 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2824 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2825 od_table->GfxclkFreq2,
2826 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2827 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2828 od_table->GfxclkFreq3,
2829 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2835 size = sprintf(buf, "%s:\n", "OD_RANGE");
2837 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2838 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2839 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2840 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2841 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2844 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2845 ret = vega20_get_memclocks(hwmgr, &clocks);
2846 PP_ASSERT_WITH_CODE(!ret,
2847 "Fail to get memory clk levels!",
2850 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2851 clocks.data[0].clocks_in_khz / 1000,
2852 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2855 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2856 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2857 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2858 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2859 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2860 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2861 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2862 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2863 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2864 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2865 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2866 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2867 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2868 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2869 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2870 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2871 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2872 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2873 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2874 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2875 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2876 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2877 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2878 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2888 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2889 struct vega20_single_dpm_table *dpm_table)
2891 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2894 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2895 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2896 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2898 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2899 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2902 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2903 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2904 PPSMC_MSG_SetHardMinByFreq,
2905 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2906 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2913 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2915 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2918 smum_send_msg_to_smc_with_parameter(hwmgr,
2919 PPSMC_MSG_NumOfDisplays, 0);
2921 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2922 &data->dpm_table.mem_table);
2927 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2929 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2931 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2933 if ((data->water_marks_bitmap & WaterMarksExist) &&
2934 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2935 result = smum_smc_table_manager(hwmgr,
2936 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2937 PP_ASSERT_WITH_CODE(!result,
2938 "Failed to update WMTABLE!",
2940 data->water_marks_bitmap |= WaterMarksLoaded;
2943 if ((data->water_marks_bitmap & WaterMarksExist) &&
2944 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2945 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2946 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2947 PPSMC_MSG_NumOfDisplays,
2948 hwmgr->display_config->num_display);
2954 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2956 struct vega20_hwmgr *data =
2957 (struct vega20_hwmgr *)(hwmgr->backend);
2960 if (data->smu_features[GNLD_DPM_UVD].supported) {
2961 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
2963 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
2965 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
2968 ret = vega20_enable_smc_features(hwmgr,
2970 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
2971 PP_ASSERT_WITH_CODE(!ret,
2972 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
2974 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2980 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2982 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2984 if (data->vce_power_gated == bgate)
2987 data->vce_power_gated = bgate;
2988 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
2991 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2993 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2995 if (data->uvd_power_gated == bgate)
2998 data->uvd_power_gated = bgate;
2999 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3002 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3004 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3005 struct vega20_single_dpm_table *dpm_table;
3006 bool vblank_too_short = false;
3007 bool disable_mclk_switching;
3008 uint32_t i, latency;
3010 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3011 !hwmgr->display_config->multi_monitor_in_sync) ||
3013 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3016 dpm_table = &(data->dpm_table.gfx_table);
3017 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3018 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3019 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3020 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3022 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3023 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3024 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3025 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3028 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3029 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3030 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3033 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3034 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3035 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3040 dpm_table = &(data->dpm_table.mem_table);
3041 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3042 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3043 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3044 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3046 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3047 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3048 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3049 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3052 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3053 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3054 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3057 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3058 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3059 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3063 /* honour DAL's UCLK Hardmin */
3064 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3065 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3067 /* Hardmin is dependent on displayconfig */
3068 if (disable_mclk_switching) {
3069 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3070 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3071 if (data->mclk_latency_table.entries[i].latency <= latency) {
3072 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3073 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3080 if (hwmgr->display_config->nb_pstate_switch_disable)
3081 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3084 dpm_table = &(data->dpm_table.vclk_table);
3085 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3086 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3087 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3088 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3090 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3091 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3092 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3093 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3096 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3097 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3098 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3103 dpm_table = &(data->dpm_table.dclk_table);
3104 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3105 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3106 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3107 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3109 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3110 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3111 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3112 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3115 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3116 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3117 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3122 dpm_table = &(data->dpm_table.soc_table);
3123 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3124 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3125 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3126 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3128 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3129 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3130 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3131 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3134 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3135 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3136 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3141 dpm_table = &(data->dpm_table.eclk_table);
3142 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3143 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3144 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3145 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3147 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3148 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3149 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3150 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3153 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3154 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3155 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3163 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3165 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3166 bool is_update_required = false;
3168 if (data->display_timing.num_existing_displays !=
3169 hwmgr->display_config->num_display)
3170 is_update_required = true;
3172 if (data->registry_data.gfx_clk_deep_sleep_support &&
3173 (data->display_timing.min_clock_in_sr !=
3174 hwmgr->display_config->min_core_set_clock_in_sr))
3175 is_update_required = true;
3177 return is_update_required;
3180 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3184 ret = vega20_disable_all_smu_features(hwmgr);
3185 PP_ASSERT_WITH_CODE(!ret,
3186 "[DisableDpmTasks] Failed to disable all smu features!",
3192 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3194 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3197 result = vega20_disable_dpm_tasks(hwmgr);
3198 PP_ASSERT_WITH_CODE((0 == result),
3199 "[PowerOffAsic] Failed to disable DPM!",
3201 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3206 static int conv_power_profile_to_pplib_workload(int power_profile)
3208 int pplib_workload = 0;
3210 switch (power_profile) {
3211 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3212 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3214 case PP_SMC_POWER_PROFILE_POWERSAVING:
3215 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3217 case PP_SMC_POWER_PROFILE_VIDEO:
3218 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3220 case PP_SMC_POWER_PROFILE_VR:
3221 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3223 case PP_SMC_POWER_PROFILE_COMPUTE:
3224 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3226 case PP_SMC_POWER_PROFILE_CUSTOM:
3227 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3231 return pplib_workload;
3234 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3236 DpmActivityMonitorCoeffInt_t activity_monitor;
3237 uint32_t i, size = 0;
3238 uint16_t workload_type = 0;
3239 static const char *profile_name[] = {
3246 static const char *title[] = {
3247 "PROFILE_INDEX(NAME)",
3251 "MinActiveFreqType",
3256 "PD_Data_error_coeff",
3257 "PD_Data_error_rate_coeff"};
3263 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3264 title[0], title[1], title[2], title[3], title[4], title[5],
3265 title[6], title[7], title[8], title[9], title[10]);
3267 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3268 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3269 workload_type = conv_power_profile_to_pplib_workload(i);
3270 result = vega20_get_activity_monitor_coeff(hwmgr,
3271 (uint8_t *)(&activity_monitor), workload_type);
3272 PP_ASSERT_WITH_CODE(!result,
3273 "[GetPowerProfile] Failed to get activity monitor!",
3276 size += sprintf(buf + size, "%2d %14s%s:\n",
3277 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3279 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3283 activity_monitor.Gfx_FPS,
3284 activity_monitor.Gfx_UseRlcBusy,
3285 activity_monitor.Gfx_MinActiveFreqType,
3286 activity_monitor.Gfx_MinActiveFreq,
3287 activity_monitor.Gfx_BoosterFreqType,
3288 activity_monitor.Gfx_BoosterFreq,
3289 activity_monitor.Gfx_PD_Data_limit_c,
3290 activity_monitor.Gfx_PD_Data_error_coeff,
3291 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3293 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3297 activity_monitor.Soc_FPS,
3298 activity_monitor.Soc_UseRlcBusy,
3299 activity_monitor.Soc_MinActiveFreqType,
3300 activity_monitor.Soc_MinActiveFreq,
3301 activity_monitor.Soc_BoosterFreqType,
3302 activity_monitor.Soc_BoosterFreq,
3303 activity_monitor.Soc_PD_Data_limit_c,
3304 activity_monitor.Soc_PD_Data_error_coeff,
3305 activity_monitor.Soc_PD_Data_error_rate_coeff);
3307 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3311 activity_monitor.Mem_FPS,
3312 activity_monitor.Mem_UseRlcBusy,
3313 activity_monitor.Mem_MinActiveFreqType,
3314 activity_monitor.Mem_MinActiveFreq,
3315 activity_monitor.Mem_BoosterFreqType,
3316 activity_monitor.Mem_BoosterFreq,
3317 activity_monitor.Mem_PD_Data_limit_c,
3318 activity_monitor.Mem_PD_Data_error_coeff,
3319 activity_monitor.Mem_PD_Data_error_rate_coeff);
3321 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3325 activity_monitor.Fclk_FPS,
3326 activity_monitor.Fclk_UseRlcBusy,
3327 activity_monitor.Fclk_MinActiveFreqType,
3328 activity_monitor.Fclk_MinActiveFreq,
3329 activity_monitor.Fclk_BoosterFreqType,
3330 activity_monitor.Fclk_BoosterFreq,
3331 activity_monitor.Fclk_PD_Data_limit_c,
3332 activity_monitor.Fclk_PD_Data_error_coeff,
3333 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3339 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3341 DpmActivityMonitorCoeffInt_t activity_monitor;
3342 int workload_type, result = 0;
3344 hwmgr->power_profile_mode = input[size];
3346 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3347 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3351 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3355 result = vega20_get_activity_monitor_coeff(hwmgr,
3356 (uint8_t *)(&activity_monitor),
3357 WORKLOAD_PPLIB_CUSTOM_BIT);
3358 PP_ASSERT_WITH_CODE(!result,
3359 "[SetPowerProfile] Failed to get activity monitor!",
3363 case 0: /* Gfxclk */
3364 activity_monitor.Gfx_FPS = input[1];
3365 activity_monitor.Gfx_UseRlcBusy = input[2];
3366 activity_monitor.Gfx_MinActiveFreqType = input[3];
3367 activity_monitor.Gfx_MinActiveFreq = input[4];
3368 activity_monitor.Gfx_BoosterFreqType = input[5];
3369 activity_monitor.Gfx_BoosterFreq = input[6];
3370 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3371 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3372 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3374 case 1: /* Socclk */
3375 activity_monitor.Soc_FPS = input[1];
3376 activity_monitor.Soc_UseRlcBusy = input[2];
3377 activity_monitor.Soc_MinActiveFreqType = input[3];
3378 activity_monitor.Soc_MinActiveFreq = input[4];
3379 activity_monitor.Soc_BoosterFreqType = input[5];
3380 activity_monitor.Soc_BoosterFreq = input[6];
3381 activity_monitor.Soc_PD_Data_limit_c = input[7];
3382 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3383 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3386 activity_monitor.Mem_FPS = input[1];
3387 activity_monitor.Mem_UseRlcBusy = input[2];
3388 activity_monitor.Mem_MinActiveFreqType = input[3];
3389 activity_monitor.Mem_MinActiveFreq = input[4];
3390 activity_monitor.Mem_BoosterFreqType = input[5];
3391 activity_monitor.Mem_BoosterFreq = input[6];
3392 activity_monitor.Mem_PD_Data_limit_c = input[7];
3393 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3394 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3397 activity_monitor.Fclk_FPS = input[1];
3398 activity_monitor.Fclk_UseRlcBusy = input[2];
3399 activity_monitor.Fclk_MinActiveFreqType = input[3];
3400 activity_monitor.Fclk_MinActiveFreq = input[4];
3401 activity_monitor.Fclk_BoosterFreqType = input[5];
3402 activity_monitor.Fclk_BoosterFreq = input[6];
3403 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3404 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3405 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3409 result = vega20_set_activity_monitor_coeff(hwmgr,
3410 (uint8_t *)(&activity_monitor),
3411 WORKLOAD_PPLIB_CUSTOM_BIT);
3412 PP_ASSERT_WITH_CODE(!result,
3413 "[SetPowerProfile] Failed to set activity monitor!",
3417 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3419 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3420 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3421 1 << workload_type);
3426 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3427 uint32_t virtual_addr_low,
3428 uint32_t virtual_addr_hi,
3429 uint32_t mc_addr_low,
3430 uint32_t mc_addr_hi,
3433 smum_send_msg_to_smc_with_parameter(hwmgr,
3434 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3436 smum_send_msg_to_smc_with_parameter(hwmgr,
3437 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3439 smum_send_msg_to_smc_with_parameter(hwmgr,
3440 PPSMC_MSG_DramLogSetDramAddrHigh,
3443 smum_send_msg_to_smc_with_parameter(hwmgr,
3444 PPSMC_MSG_DramLogSetDramAddrLow,
3447 smum_send_msg_to_smc_with_parameter(hwmgr,
3448 PPSMC_MSG_DramLogSetDramSize,
3453 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3454 struct PP_TemperatureRange *thermal_data)
3456 struct phm_ppt_v3_information *pptable_information =
3457 (struct phm_ppt_v3_information *)hwmgr->pptable;
3459 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3461 thermal_data->max = pptable_information->us_software_shutdown_temp *
3462 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3467 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3468 /* init/fini related */
3470 vega20_hwmgr_backend_init,
3472 vega20_hwmgr_backend_fini,
3474 vega20_setup_asic_task,
3476 vega20_power_off_asic,
3477 .dynamic_state_management_enable =
3478 vega20_enable_dpm_tasks,
3479 .dynamic_state_management_disable =
3480 vega20_disable_dpm_tasks,
3481 /* power state related */
3482 .apply_clocks_adjust_rules =
3483 vega20_apply_clocks_adjust_rules,
3484 .pre_display_config_changed =
3485 vega20_pre_display_configuration_changed_task,
3486 .display_config_changed =
3487 vega20_display_configuration_changed_task,
3488 .check_smc_update_required_for_display_configuration =
3489 vega20_check_smc_update_required_for_display_configuration,
3490 .notify_smc_display_config_after_ps_adjustment =
3491 vega20_notify_smc_display_config_after_ps_adjustment,
3494 vega20_dpm_get_sclk,
3496 vega20_dpm_get_mclk,
3497 .get_dal_power_level =
3498 vega20_get_dal_power_level,
3499 .get_clock_by_type_with_latency =
3500 vega20_get_clock_by_type_with_latency,
3501 .get_clock_by_type_with_voltage =
3502 vega20_get_clock_by_type_with_voltage,
3503 .set_watermarks_for_clocks_ranges =
3504 vega20_set_watermarks_for_clocks_ranges,
3505 .display_clock_voltage_request =
3506 vega20_display_clock_voltage_request,
3507 .get_performance_level =
3508 vega20_get_performance_level,
3509 /* UMD pstate, profile related */
3511 vega20_dpm_force_dpm_level,
3512 .get_power_profile_mode =
3513 vega20_get_power_profile_mode,
3514 .set_power_profile_mode =
3515 vega20_set_power_profile_mode,
3518 vega20_set_power_limit,
3527 .odn_edit_dpm_table =
3528 vega20_odn_edit_dpm_table,
3529 /* for sysfs to retrive/set gfxclk/memclk */
3530 .force_clock_level =
3531 vega20_force_clock_level,
3532 .print_clock_levels =
3533 vega20_print_clock_levels,
3536 /* powergate related */
3538 vega20_power_gate_uvd,
3540 vega20_power_gate_vce,
3541 /* thermal related */
3542 .start_thermal_controller =
3543 vega20_start_thermal_controller,
3544 .stop_thermal_controller =
3545 vega20_thermal_stop_thermal_controller,
3546 .get_thermal_temperature_range =
3547 vega20_get_thermal_temperature_range,
3548 .register_irq_handlers =
3549 smu9_register_irq_handlers,
3550 .disable_smc_firmware_ctf =
3551 vega20_thermal_disable_alert,
3552 /* fan control related */
3553 .get_fan_speed_percent =
3554 vega20_fan_ctrl_get_fan_speed_percent,
3555 .set_fan_speed_percent =
3556 vega20_fan_ctrl_set_fan_speed_percent,
3557 .get_fan_speed_info =
3558 vega20_fan_ctrl_get_fan_speed_info,
3559 .get_fan_speed_rpm =
3560 vega20_fan_ctrl_get_fan_speed_rpm,
3561 .set_fan_speed_rpm =
3562 vega20_fan_ctrl_set_fan_speed_rpm,
3563 .get_fan_control_mode =
3564 vega20_get_fan_control_mode,
3565 .set_fan_control_mode =
3566 vega20_set_fan_control_mode,
3567 /* smu memory related */
3568 .notify_cac_buffer_info =
3569 vega20_notify_cac_buffer_info,
3570 .enable_mgpu_fan_boost =
3571 vega20_enable_mgpu_fan_boost,
3574 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3576 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3577 hwmgr->pptable_func = &vega20_pptable_funcs;