drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "vega20_thermal.h"
  25 #include "vega20_hwmgr.h"
  26 #include "vega20_smumgr.h"
  27 #include "vega20_ppsmc.h"
  28 #include "vega20_inc.h"
  29 #include "soc15_common.h"
  30 #include "pp_debug.h"
  31
  32 static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
  33 {
  34         int ret = 0;
  35
  36         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
  37                                 PPSMC_MSG_GetCurrentRpm)) == 0,
  38                         "Attempt to get current RPM from SMC Failed!",
  39                         return ret);
  40         *current_rpm = smum_get_argument(hwmgr);
  41
  42         return 0;
  43 }
  44
  45 int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
  46                 struct phm_fan_speed_info *fan_speed_info)
  47 {
  48         memset(fan_speed_info, 0, sizeof(*fan_speed_info));
  49         fan_speed_info->supports_percent_read = false;
  50         fan_speed_info->supports_percent_write = false;
  51         fan_speed_info->supports_rpm_read = true;
  52         fan_speed_info->supports_rpm_write = true;
  53
  54         return 0;
  55 }
  56
  57 int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
  58 {
  59         *speed = 0;
  60
  61         return vega20_get_current_rpm(hwmgr, speed);
  62 }
  63
  64 /**
  65 * Reads the remote temperature from the SIslands thermal controller.
  66 *
  67 * @param    hwmgr The address of the hardware manager.
  68 */
  69 int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr)
  70 {
  71         struct amdgpu_device *adev = hwmgr->adev;
  72         int temp = 0;
  73
  74         temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
  75
  76         temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
  77                         CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
  78
  79         temp = temp & 0x1ff;
  80
  81         temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
  82         return temp;
  83 }
  84
  85 /**
  86 * Set the requested temperature range for high and low alert signals
  87 *
  88 * @param    hwmgr The address of the hardware manager.
  89 * @param    range Temperature range to be programmed for
  90 *           high and low alert signals
  91 * @exception PP_Result_BadInput if the input data is not valid.
  92 */
  93 static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
  94                 struct PP_TemperatureRange *range)
  95 {
  96         struct amdgpu_device *adev = hwmgr->adev;
  97         int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP *
  98                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
  99         int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP *
 100                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 101         uint32_t val;
 102
 103         if (low < range->min)
 104                 low = range->min;
 105         if (high > range->max)
 106                 high = range->max;
 107
 108         if (low > high)
 109                 return -EINVAL;
 110
 111         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
 112
 113         val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
 114         val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
 115         val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
 116         val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
 117         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 118
 119         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 120
 121         return 0;
 122 }
 123
 124 /**
 125 * Enable thermal alerts on the RV770 thermal controller.
 126 *
 127 * @param    hwmgr The address of the hardware manager.
 128 */
 129 static int vega20_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 130 {
 131         struct amdgpu_device *adev = hwmgr->adev;
 132         uint32_t val = 0;
 133
 134         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
 135         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
 136         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 137
 138         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
 139
 140         return 0;
 141 }
 142
 143 /**
 144 * Disable thermal alerts on the RV770 thermal controller.
 145 * @param    hwmgr The address of the hardware manager.
 146 */
 147 int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 148 {
 149         struct amdgpu_device *adev = hwmgr->adev;
 150
 151         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
 152
 153         return 0;
 154 }
 155
 156 /**
 157 * Uninitialize the thermal controller.
 158 * Currently just disables alerts.
 159 * @param    hwmgr The address of the hardware manager.
 160 */
 161 int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 162 {
 163         int result = vega20_thermal_disable_alert(hwmgr);
 164
 165         return result;
 166 }
 167
 168 /**
 169 * Set up the fan table to control the fan using the SMC.
 170 * @param    hwmgr  the address of the powerplay hardware manager.
 171 * @param    pInput the pointer to input data
 172 * @param    pOutput the pointer to output data
 173 * @param    pStorage the pointer to temporary storage
 174 * @param    Result the last failure code
 175 * @return   result from set temperature range routine
 176 */
 177 static int vega20_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 178 {
 179         int ret;
 180         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 181         PPTable_t *table = &(data->smc_state_table.pp_table);
 182
 183         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 184                                 PPSMC_MSG_SetFanTemperatureTarget,
 185                                 (uint32_t)table->FanTargetTemperature);
 186
 187         return ret;
 188 }
 189
 190 int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
 191                                 struct PP_TemperatureRange *range)
 192 {
 193         int ret = 0;
 194
 195         if (range == NULL)
 196                 return -EINVAL;
 197
 198         ret = vega20_thermal_set_temperature_range(hwmgr, range);
 199         if (ret)
 200                 return ret;
 201
 202         ret = vega20_thermal_enable_alert(hwmgr);
 203         if (ret)
 204                 return ret;
 205
 206         ret = vega20_thermal_setup_fan_table(hwmgr);
 207
 208         return ret;
 209 };