2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
29 struct smu_hw_power_state {
33 struct smu_power_state;
35 enum smu_state_ui_label {
36 SMU_STATE_UI_LABEL_NONE,
37 SMU_STATE_UI_LABEL_BATTERY,
38 SMU_STATE_UI_TABEL_MIDDLE_LOW,
39 SMU_STATE_UI_LABEL_BALLANCED,
40 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
41 SMU_STATE_UI_LABEL_PERFORMANCE,
42 SMU_STATE_UI_LABEL_BACO,
45 enum smu_state_classification_flag {
46 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
47 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
48 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
49 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
50 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
51 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
52 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
53 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
54 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
55 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
56 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
57 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
58 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
59 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
60 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
61 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
62 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
63 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
64 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
65 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
69 struct smu_state_classification_block {
70 enum smu_state_ui_label ui_label;
71 enum smu_state_classification_flag flags;
77 struct smu_state_pcie_block {
81 enum smu_refreshrate_source {
82 SMU_REFRESHRATE_SOURCE_EDID,
83 SMU_REFRESHRATE_SOURCE_EXPLICIT
86 struct smu_state_display_block {
87 bool disable_frame_modulation;
88 bool limit_refreshrate;
89 enum smu_refreshrate_source refreshrate_source;
90 int explicit_refreshrate;
91 int edid_refreshrate_index;
92 bool enable_vari_bright;
95 struct smu_state_memroy_block {
101 struct smu_state_software_algorithm_block {
102 bool disable_load_balancing;
103 bool enable_sleep_for_timestamps;
106 struct smu_temperature_range {
111 struct smu_state_validation_block {
112 bool single_display_only;
114 uint8_t supported_power_levels;
117 struct smu_uvd_clocks {
123 * Structure to hold a SMU Power State.
125 struct smu_power_state {
127 struct list_head ordered_list;
128 struct list_head all_states_list;
130 struct smu_state_classification_block classification;
131 struct smu_state_validation_block validation;
132 struct smu_state_pcie_block pcie;
133 struct smu_state_display_block display;
134 struct smu_state_memroy_block memory;
135 struct smu_temperature_range temperatures;
136 struct smu_state_software_algorithm_block software;
137 struct smu_uvd_clocks uvd_clocks;
138 struct smu_hw_power_state hardware;
141 enum smu_message_type
143 SMU_MSG_TestMessage = 0,
144 SMU_MSG_GetSmuVersion,
145 SMU_MSG_GetDriverIfVersion,
146 SMU_MSG_SetAllowedFeaturesMaskLow,
147 SMU_MSG_SetAllowedFeaturesMaskHigh,
148 SMU_MSG_EnableAllSmuFeatures,
149 SMU_MSG_DisableAllSmuFeatures,
150 SMU_MSG_EnableSmuFeaturesLow,
151 SMU_MSG_EnableSmuFeaturesHigh,
152 SMU_MSG_DisableSmuFeaturesLow,
153 SMU_MSG_DisableSmuFeaturesHigh,
154 SMU_MSG_GetEnabledSmuFeaturesLow,
155 SMU_MSG_GetEnabledSmuFeaturesHigh,
156 SMU_MSG_SetWorkloadMask,
158 SMU_MSG_SetDriverDramAddrHigh,
159 SMU_MSG_SetDriverDramAddrLow,
160 SMU_MSG_SetToolsDramAddrHigh,
161 SMU_MSG_SetToolsDramAddrLow,
162 SMU_MSG_TransferTableSmu2Dram,
163 SMU_MSG_TransferTableDram2Smu,
164 SMU_MSG_UseDefaultPPTable,
165 SMU_MSG_UseBackupPPTable,
167 SMU_MSG_RequestI2CBus,
168 SMU_MSG_ReleaseI2CBus,
169 SMU_MSG_SetFloorSocVoltage,
171 SMU_MSG_StartBacoMonitor,
172 SMU_MSG_CancelBacoMonitor,
174 SMU_MSG_SetSoftMinByFreq,
175 SMU_MSG_SetSoftMaxByFreq,
176 SMU_MSG_SetHardMinByFreq,
177 SMU_MSG_SetHardMaxByFreq,
178 SMU_MSG_GetMinDpmFreq,
179 SMU_MSG_GetMaxDpmFreq,
180 SMU_MSG_GetDpmFreqByIndex,
181 SMU_MSG_GetDpmClockFreq,
182 SMU_MSG_GetSsVoltageByDpm,
183 SMU_MSG_SetMemoryChannelConfig,
184 SMU_MSG_SetGeminiMode,
185 SMU_MSG_SetGeminiApertureHigh,
186 SMU_MSG_SetGeminiApertureLow,
187 SMU_MSG_SetMinLinkDpmByIndex,
188 SMU_MSG_OverridePcieParameters,
189 SMU_MSG_OverDriveSetPercentage,
190 SMU_MSG_SetMinDeepSleepDcefclk,
191 SMU_MSG_ReenableAcDcInterrupt,
192 SMU_MSG_NotifyPowerSource,
193 SMU_MSG_SetUclkFastSwitch,
194 SMU_MSG_SetUclkDownHyst,
195 SMU_MSG_GfxDeviceDriverReset,
196 SMU_MSG_GetCurrentRpm,
199 SMU_MSG_SetFanTemperatureTarget,
200 SMU_MSG_PrepareMp1ForUnload,
201 SMU_MSG_DramLogSetDramAddrHigh,
202 SMU_MSG_DramLogSetDramAddrLow,
203 SMU_MSG_DramLogSetDramSize,
204 SMU_MSG_SetFanMaxRpm,
205 SMU_MSG_SetFanMinPwm,
206 SMU_MSG_ConfigureGfxDidt,
207 SMU_MSG_NumOfDisplays,
208 SMU_MSG_RemoveMargins,
209 SMU_MSG_ReadSerialNumTop32,
210 SMU_MSG_ReadSerialNumBottom32,
211 SMU_MSG_SetSystemVirtualDramAddrHigh,
212 SMU_MSG_SetSystemVirtualDramAddrLow,
214 SMU_MSG_SetFclkGfxClkRatio,
216 SMU_MSG_DisallowGfxOff,
218 SMU_MSG_GetDcModeMaxDpmFreq,
219 SMU_MSG_GetDebugData,
223 SMU_MSG_PrepareMp1ForReset,
224 SMU_MSG_PrepareMp1ForShutdown,
225 SMU_MSG_SetMGpuFanBoostLimitRpm,
226 SMU_MSG_GetAVFSVoltageByDpm,
246 enum smu_feature_mask
248 SMU_FEATURE_DPM_PREFETCHER_BIT,
249 SMU_FEATURE_DPM_GFXCLK_BIT,
250 SMU_FEATURE_DPM_UCLK_BIT,
251 SMU_FEATURE_DPM_SOCCLK_BIT,
252 SMU_FEATURE_DPM_UVD_BIT,
253 SMU_FEATURE_DPM_VCE_BIT,
255 SMU_FEATURE_DPM_MP0CLK_BIT,
256 SMU_FEATURE_DPM_LINK_BIT,
257 SMU_FEATURE_DPM_DCEFCLK_BIT,
258 SMU_FEATURE_DS_GFXCLK_BIT,
259 SMU_FEATURE_DS_SOCCLK_BIT,
260 SMU_FEATURE_DS_LCLK_BIT,
263 SMU_FEATURE_THERMAL_BIT,
264 SMU_FEATURE_GFX_PER_CU_CG_BIT,
266 SMU_FEATURE_DS_DCEFCLK_BIT,
267 SMU_FEATURE_ACDC_BIT,
268 SMU_FEATURE_VR0HOT_BIT,
269 SMU_FEATURE_VR1HOT_BIT,
270 SMU_FEATURE_FW_CTF_BIT,
271 SMU_FEATURE_LED_DISPLAY_BIT,
272 SMU_FEATURE_FAN_CONTROL_BIT,
273 SMU_FEATURE_GFX_EDC_BIT,
274 SMU_FEATURE_GFXOFF_BIT,
276 SMU_FEATURE_DPM_FCLK_BIT,
277 SMU_FEATURE_DS_FCLK_BIT,
278 SMU_FEATURE_DS_MP1CLK_BIT,
279 SMU_FEATURE_DS_MP0CLK_BIT,
280 SMU_FEATURE_XGMI_BIT,
281 SMU_FEATURE_DPM_GFX_PACE_BIT,
282 SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
283 SMU_FEATURE_MEM_MVDD_SCALING_BIT,
284 SMU_FEATURE_DS_UCLK_BIT,
285 SMU_FEATURE_GFX_ULV_BIT,
286 SMU_FEATURE_FW_DSTATE_BIT,
287 SMU_FEATURE_BACO_BIT,
288 SMU_FEATURE_VCN_PG_BIT,
289 SMU_FEATURE_JPEG_PG_BIT,
290 SMU_FEATURE_USB_PG_BIT,
291 SMU_FEATURE_RSMU_SMN_CG_BIT,
292 SMU_FEATURE_APCC_PLUS_BIT,
293 SMU_FEATURE_GTHR_BIT,
294 SMU_FEATURE_GFX_DCS_BIT,
295 SMU_FEATURE_GFX_SS_BIT,
296 SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
297 SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
298 SMU_FEATURE_MMHUB_PG_BIT,
299 SMU_FEATURE_ATHUB_PG_BIT,
303 enum smu_memory_pool_size
305 SMU_MEMORY_POOL_SIZE_ZERO = 0,
306 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
307 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
308 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
309 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
312 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
314 tables[table_id].size = s; \
315 tables[table_id].align = a; \
316 tables[table_id].domain = d; \
325 struct amdgpu_bo *bo;
328 enum smu_perf_level_designation {
330 PERF_LEVEL_POWER_CONTAINMENT,
333 struct smu_performance_level {
335 uint32_t memory_clock;
338 uint32_t non_local_mem_freq;
339 uint32_t non_local_mem_width;
342 struct smu_clock_info {
343 uint32_t min_mem_clk;
344 uint32_t max_mem_clk;
345 uint32_t min_eng_clk;
346 uint32_t max_eng_clk;
347 uint32_t min_bus_bandwidth;
348 uint32_t max_bus_bandwidth;
351 struct smu_bios_boot_up_values
366 uint32_t pp_table_id;
371 SMU_TABLE_PPTABLE = 0,
372 SMU_TABLE_WATERMARKS,
374 SMU_TABLE_AVFS_PSM_DEBUG,
375 SMU_TABLE_AVFS_FUSE_OVERRIDE,
376 SMU_TABLE_PMSTATUSLOG,
377 SMU_TABLE_SMU_METRICS,
378 SMU_TABLE_DRIVER_SMU_CONFIG,
379 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
381 SMU_TABLE_I2C_COMMANDS,
386 struct smu_table_context
388 void *power_play_table;
389 uint32_t power_play_table_size;
390 void *hardcode_pptable;
392 void *max_sustainable_clocks;
393 struct smu_bios_boot_up_values boot_values;
394 void *driver_pptable;
395 struct smu_table *tables;
396 uint32_t table_count;
397 struct smu_table memory_pool;
398 uint16_t software_shutdown_temp;
399 uint8_t thermal_controller_type;
402 uint8_t *od_feature_capabilities;
403 uint32_t *od_settings_max;
404 uint32_t *od_settings_min;
405 void *overdrive_table;
407 bool od_gfxclk_update;
408 bool od_memclk_update;
411 struct smu_dpm_context {
412 uint32_t dpm_context_size;
414 void *golden_dpm_context;
415 bool enable_umd_pstate;
416 enum amd_dpm_forced_level dpm_level;
417 enum amd_dpm_forced_level saved_dpm_level;
418 enum amd_dpm_forced_level requested_dpm_level;
419 struct smu_power_state *dpm_request_power_state;
420 struct smu_power_state *dpm_current_power_state;
421 struct mclock_latency_table *mclk_latency_table;
424 struct smu_power_context {
426 uint32_t power_context_size;
430 #define SMU_FEATURE_MAX (64)
433 uint32_t feature_num;
434 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
435 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
436 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
441 uint32_t engine_clock;
442 uint32_t memory_clock;
443 uint32_t bus_bandwidth;
444 uint32_t engine_clock_in_sr;
446 uint32_t dcef_clock_in_sr;
449 #define MAX_REGULAR_DPM_NUM 16
450 struct mclk_latency_entries {
454 struct mclock_latency_table {
456 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
459 #define WORKLOAD_POLICY_MAX 7
462 struct amdgpu_device *adev;
464 const struct smu_funcs *funcs;
465 const struct pptable_funcs *ppt_funcs;
469 struct smu_table_context smu_table;
470 struct smu_dpm_context smu_dpm;
471 struct smu_power_context smu_power;
472 struct smu_feature smu_feature;
473 struct amd_pp_display_configuration *display_config;
475 uint32_t pstate_sclk;
476 uint32_t pstate_mclk;
479 uint32_t power_limit;
480 uint32_t default_power_limit;
483 uint32_t ppt_offset_bytes;
484 uint32_t ppt_size_bytes;
485 uint8_t *ppt_start_addr;
487 bool support_power_containment;
488 bool disable_watermark;
490 #define WATERMARKS_EXIST (1 << 0)
491 #define WATERMARKS_LOADED (1 << 1)
492 uint32_t watermarks_bitmap;
494 uint32_t workload_mask;
495 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
496 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
497 uint32_t power_profile_mode;
498 uint32_t default_power_profile_mode;
501 uint32_t smc_if_version;
503 unsigned long metrics_time;
507 struct pptable_funcs {
508 int (*alloc_dpm_context)(struct smu_context *smu);
509 int (*store_powerplay_table)(struct smu_context *smu);
510 int (*check_powerplay_table)(struct smu_context *smu);
511 int (*append_powerplay_table)(struct smu_context *smu);
512 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
513 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
514 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
515 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
516 int (*run_afll_btc)(struct smu_context *smu);
517 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
518 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
519 int (*set_default_dpm_table)(struct smu_context *smu);
520 int (*set_power_state)(struct smu_context *smu);
521 int (*populate_umd_state_clk)(struct smu_context *smu);
522 int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
523 int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
524 int (*set_default_od8_settings)(struct smu_context *smu);
525 int (*update_specified_od8_value)(struct smu_context *smu,
528 int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
529 int (*set_od_percentage)(struct smu_context *smu,
530 enum pp_clock_type type,
532 int (*od_edit_dpm_table)(struct smu_context *smu,
533 enum PP_OD_DPM_TABLE_COMMAND type,
534 long *input, uint32_t size);
535 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
536 enum amd_pp_clock_type type,
538 pp_clock_levels_with_latency
540 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
541 enum amd_pp_clock_type type,
543 pp_clock_levels_with_voltage
545 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
546 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
547 int (*conv_profile_to_workload)(struct smu_context *smu, int power_profile);
548 enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
549 int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
550 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
551 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
552 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
553 void *data, uint32_t *size);
554 int (*pre_display_config_changed)(struct smu_context *smu);
555 int (*display_config_changed)(struct smu_context *smu);
556 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
557 int (*notify_smc_dispaly_config)(struct smu_context *smu);
558 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
559 int (*unforce_dpm_levels)(struct smu_context *smu);
560 int (*upload_dpm_level)(struct smu_context *smu, bool max,
561 uint32_t feature_mask);
562 int (*get_profiling_clk_mask)(struct smu_context *smu,
563 enum amd_dpm_forced_level level,
567 int (*set_cpu_power_state)(struct smu_context *smu);
568 int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
569 int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
570 bool (*is_dpm_running)(struct smu_context *smu);
571 void (*tables_init)(struct smu_context *smu, struct smu_table *tables);
576 int (*init_microcode)(struct smu_context *smu);
577 int (*init_smc_tables)(struct smu_context *smu);
578 int (*fini_smc_tables)(struct smu_context *smu);
579 int (*init_power)(struct smu_context *smu);
580 int (*fini_power)(struct smu_context *smu);
581 int (*load_microcode)(struct smu_context *smu);
582 int (*check_fw_status)(struct smu_context *smu);
583 int (*setup_pptable)(struct smu_context *smu);
584 int (*get_vbios_bootup_values)(struct smu_context *smu);
585 int (*get_clk_info_from_vbios)(struct smu_context *smu);
586 int (*check_pptable)(struct smu_context *smu);
587 int (*parse_pptable)(struct smu_context *smu);
588 int (*populate_smc_pptable)(struct smu_context *smu);
589 int (*check_fw_version)(struct smu_context *smu);
590 int (*write_pptable)(struct smu_context *smu);
591 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
592 int (*set_tool_table_location)(struct smu_context *smu);
593 int (*notify_memory_pool_location)(struct smu_context *smu);
594 int (*write_watermarks_table)(struct smu_context *smu);
595 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
596 int (*system_features_control)(struct smu_context *smu, bool en);
597 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
598 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
599 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
600 int (*init_display)(struct smu_context *smu);
601 int (*set_allowed_mask)(struct smu_context *smu);
602 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
603 int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
604 int (*notify_display_change)(struct smu_context *smu);
605 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
606 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
607 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
608 int (*init_max_sustainable_clocks)(struct smu_context *smu);
609 int (*start_thermal_control)(struct smu_context *smu);
610 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
611 void *data, uint32_t *size);
612 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
613 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
614 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
615 bool cc6_disable, bool pstate_disable,
616 bool pstate_switch_disable);
617 int (*get_clock_by_type)(struct smu_context *smu,
618 enum amd_pp_clock_type type,
619 struct amd_pp_clocks *clocks);
620 int (*get_max_high_clocks)(struct smu_context *smu,
621 struct amd_pp_simple_clock_info *clocks);
622 int (*display_clock_voltage_request)(struct smu_context *smu, struct
623 pp_display_clock_request
625 int (*get_dal_power_level)(struct smu_context *smu,
626 struct amd_pp_simple_clock_info *clocks);
627 int (*get_perf_level)(struct smu_context *smu,
628 enum smu_perf_level_designation designation,
629 struct smu_performance_level *level);
630 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
631 struct smu_clock_info *clocks);
632 int (*notify_smu_enable_pwe)(struct smu_context *smu);
633 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
634 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
635 int (*set_od8_default_settings)(struct smu_context *smu,
637 int (*conv_power_profile_to_pplib_workload)(int power_profile);
638 int (*update_od8_settings)(struct smu_context *smu,
641 uint32_t (*get_sclk)(struct smu_context *smu, bool low);
642 uint32_t (*get_mclk)(struct smu_context *smu, bool low);
643 int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
644 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
645 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
646 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
647 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
648 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
649 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
650 int (*gfx_off_control)(struct smu_context *smu, bool enable);
653 #define smu_init_microcode(smu) \
654 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
655 #define smu_init_smc_tables(smu) \
656 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
657 #define smu_fini_smc_tables(smu) \
658 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
659 #define smu_init_power(smu) \
660 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
661 #define smu_fini_power(smu) \
662 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
663 #define smu_load_microcode(smu) \
664 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
665 #define smu_check_fw_status(smu) \
666 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
667 #define smu_setup_pptable(smu) \
668 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
669 #define smu_get_vbios_bootup_values(smu) \
670 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
671 #define smu_get_clk_info_from_vbios(smu) \
672 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
673 #define smu_check_pptable(smu) \
674 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
675 #define smu_parse_pptable(smu) \
676 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
677 #define smu_populate_smc_pptable(smu) \
678 ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
679 #define smu_check_fw_version(smu) \
680 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
681 #define smu_write_pptable(smu) \
682 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
683 #define smu_set_min_dcef_deep_sleep(smu) \
684 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
685 #define smu_set_tool_table_location(smu) \
686 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
687 #define smu_notify_memory_pool_location(smu) \
688 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
689 #define smu_gfx_off_control(smu, enable) \
690 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
692 #define smu_write_watermarks_table(smu) \
693 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
694 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
695 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
696 #define smu_system_features_control(smu, en) \
697 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
698 #define smu_init_max_sustainable_clocks(smu) \
699 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
700 #define smu_set_od8_default_settings(smu, initialize) \
701 ((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu), (initialize)) : 0)
702 #define smu_update_od8_settings(smu, index, value) \
703 ((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
704 #define smu_get_current_rpm(smu, speed) \
705 ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
706 #define smu_set_fan_speed_rpm(smu, speed) \
707 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
708 #define smu_send_smc_msg(smu, msg) \
709 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
710 #define smu_send_smc_msg_with_param(smu, msg, param) \
711 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
712 #define smu_read_smc_arg(smu, arg) \
713 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
714 #define smu_alloc_dpm_context(smu) \
715 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
716 #define smu_init_display(smu) \
717 ((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
718 #define smu_feature_set_allowed_mask(smu) \
719 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
720 #define smu_feature_get_enabled_mask(smu, mask, num) \
721 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
722 #define smu_is_dpm_running(smu) \
723 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
724 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
725 ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
726 #define smu_notify_display_change(smu) \
727 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
728 #define smu_store_powerplay_table(smu) \
729 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
730 #define smu_check_powerplay_table(smu) \
731 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
732 #define smu_append_powerplay_table(smu) \
733 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
734 #define smu_set_default_dpm_table(smu) \
735 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
736 #define smu_populate_umd_state_clk(smu) \
737 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
738 #define smu_set_default_od8_settings(smu) \
739 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
740 #define smu_update_specified_od8_value(smu, index, value) \
741 ((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
742 #define smu_get_power_limit(smu, limit, def) \
743 ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
744 #define smu_set_power_limit(smu, limit) \
745 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
746 #define smu_get_current_clk_freq(smu, clk_id, value) \
747 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
748 #define smu_print_clk_levels(smu, type, buf) \
749 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
750 #define smu_force_clk_levels(smu, type, level) \
751 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (type), (level)) : 0)
752 #define smu_get_od_percentage(smu, type) \
753 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
754 #define smu_set_od_percentage(smu, type, value) \
755 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
756 #define smu_od_edit_dpm_table(smu, type, input, size) \
757 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
758 #define smu_tables_init(smu, tab) \
759 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
760 #define smu_start_thermal_control(smu) \
761 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
762 #define smu_read_sensor(smu, sensor, data, size) \
763 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
764 #define smu_asic_read_sensor(smu, sensor, data, size) \
765 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
766 #define smu_get_power_profile_mode(smu, buf) \
767 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
768 #define smu_set_power_profile_mode(smu, param, param_size) \
769 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
770 #define smu_get_performance_level(smu) \
771 ((smu)->ppt_funcs->get_performance_level ? (smu)->ppt_funcs->get_performance_level((smu)) : 0)
772 #define smu_force_performance_level(smu, level) \
773 ((smu)->ppt_funcs->force_performance_level ? (smu)->ppt_funcs->force_performance_level((smu), (level)) : 0)
774 #define smu_pre_display_config_changed(smu) \
775 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
776 #define smu_display_config_changed(smu) \
777 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
778 #define smu_apply_clocks_adjust_rules(smu) \
779 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
780 #define smu_notify_smc_dispaly_config(smu) \
781 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
782 #define smu_force_dpm_limit_value(smu, highest) \
783 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
784 #define smu_unforce_dpm_levels(smu) \
785 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
786 #define smu_upload_dpm_level(smu, max, feature_mask) \
787 ((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max), (feature_mask)) : 0)
788 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
789 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
790 #define smu_set_cpu_power_state(smu) \
791 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
792 #define smu_get_fan_control_mode(smu) \
793 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
794 #define smu_set_fan_control_mode(smu, value) \
795 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
796 #define smu_get_fan_speed_percent(smu, speed) \
797 ((smu)->funcs->get_fan_speed_percent ? (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)
798 #define smu_set_fan_speed_percent(smu, speed) \
799 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
801 #define smu_msg_get_index(smu, msg) \
802 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
803 #define smu_clk_get_index(smu, msg) \
804 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
805 #define smu_feature_get_index(smu, msg) \
806 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
807 #define smu_table_get_index(smu, tab) \
808 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
809 #define smu_run_afll_btc(smu) \
810 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
811 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
812 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
813 #define smu_set_deep_sleep_dcefclk(smu, clk) \
814 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
815 #define smu_set_active_display_count(smu, count) \
816 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
817 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
818 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
819 #define smu_get_clock_by_type(smu, type, clocks) \
820 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
821 #define smu_get_max_high_clocks(smu, clocks) \
822 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
823 #define smu_get_clock_by_type_with_latency(smu, type, clocks) \
824 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (type), (clocks)) : 0)
825 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
826 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
827 #define smu_display_clock_voltage_request(smu, clock_req) \
828 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
829 #define smu_get_dal_power_level(smu, clocks) \
830 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
831 #define smu_get_perf_level(smu, designation, level) \
832 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
833 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
834 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
835 #define smu_notify_smu_enable_pwe(smu) \
836 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
837 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
838 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
839 #define smu_conv_profile_to_workload(smu, type) \
840 ((smu)->ppt_funcs->conv_profile_to_workload ? (smu)->ppt_funcs->conv_profile_to_workload((smu), (type)) : 0)
841 #define smu_dpm_set_uvd_enable(smu, enable) \
842 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
843 #define smu_dpm_set_vce_enable(smu, enable) \
844 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
845 #define smu_get_sclk(smu, low) \
846 ((smu)->funcs->get_sclk ? (smu)->funcs->get_sclk((smu), (low)) : 0)
847 #define smu_get_mclk(smu, low) \
848 ((smu)->funcs->get_mclk ? (smu)->funcs->get_mclk((smu), (low)) : 0)
849 #define smu_set_xgmi_pstate(smu, pstate) \
850 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
851 #define smu_set_ppfeature_status(smu, ppfeatures) \
852 ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
853 #define smu_get_ppfeature_status(smu, buf) \
854 ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
856 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
857 uint16_t *size, uint8_t *frev, uint8_t *crev,
860 extern const struct amd_ip_funcs smu_ip_funcs;
862 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
863 extern int smu_feature_init_dpm(struct smu_context *smu);
865 extern int smu_feature_is_enabled(struct smu_context *smu,
866 enum smu_feature_mask mask);
867 extern int smu_feature_set_enabled(struct smu_context *smu,
868 enum smu_feature_mask mask, bool enable);
869 extern int smu_feature_is_supported(struct smu_context *smu,
870 enum smu_feature_mask mask);
871 extern int smu_feature_set_supported(struct smu_context *smu,
872 enum smu_feature_mask mask, bool enable);
874 int smu_update_table_with_arg(struct smu_context *smu, uint16_t table_id, uint16_t exarg,
875 void *table_data, bool drv2smu);
876 #define smu_update_table(smu, table_id, table_data, drv2smu) \
877 smu_update_table_with_arg((smu), (table_id), 0, (table_data), (drv2smu))
879 bool is_support_sw_smu(struct amdgpu_device *adev);
880 int smu_reset(struct smu_context *smu);
881 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
882 void *data, uint32_t *size);
883 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
884 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
885 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
886 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
888 /* smu to display interface */
889 extern int smu_display_configuration_change(struct smu_context *smu, const
890 struct amd_pp_display_configuration
892 extern int smu_get_current_clocks(struct smu_context *smu,
893 struct amd_pp_clock_info *clocks);
894 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
895 extern int smu_handle_task(struct smu_context *smu,
896 enum amd_dpm_forced_level level,
897 enum amd_pp_task task_id);
898 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);