2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
29 struct smu_hw_power_state {
33 struct smu_power_state;
35 enum smu_state_ui_label {
36 SMU_STATE_UI_LABEL_NONE,
37 SMU_STATE_UI_LABEL_BATTERY,
38 SMU_STATE_UI_TABEL_MIDDLE_LOW,
39 SMU_STATE_UI_LABEL_BALLANCED,
40 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
41 SMU_STATE_UI_LABEL_PERFORMANCE,
42 SMU_STATE_UI_LABEL_BACO,
45 enum smu_state_classification_flag {
46 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
47 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
48 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
49 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
50 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
51 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
52 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
53 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
54 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
55 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
56 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
57 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
58 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
59 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
60 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
61 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
62 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
63 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
64 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
65 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
69 struct smu_state_classification_block {
70 enum smu_state_ui_label ui_label;
71 enum smu_state_classification_flag flags;
77 struct smu_state_pcie_block {
81 enum smu_refreshrate_source {
82 SMU_REFRESHRATE_SOURCE_EDID,
83 SMU_REFRESHRATE_SOURCE_EXPLICIT
86 struct smu_state_display_block {
87 bool disable_frame_modulation;
88 bool limit_refreshrate;
89 enum smu_refreshrate_source refreshrate_source;
90 int explicit_refreshrate;
91 int edid_refreshrate_index;
92 bool enable_vari_bright;
95 struct smu_state_memroy_block {
101 struct smu_state_software_algorithm_block {
102 bool disable_load_balancing;
103 bool enable_sleep_for_timestamps;
106 struct smu_temperature_range {
111 struct smu_state_validation_block {
112 bool single_display_only;
114 uint8_t supported_power_levels;
117 struct smu_uvd_clocks {
123 * Structure to hold a SMU Power State.
125 struct smu_power_state {
127 struct list_head ordered_list;
128 struct list_head all_states_list;
130 struct smu_state_classification_block classification;
131 struct smu_state_validation_block validation;
132 struct smu_state_pcie_block pcie;
133 struct smu_state_display_block display;
134 struct smu_state_memroy_block memory;
135 struct smu_temperature_range temperatures;
136 struct smu_state_software_algorithm_block software;
137 struct smu_uvd_clocks uvd_clocks;
138 struct smu_hw_power_state hardware;
141 enum smu_message_type
143 SMU_MSG_TestMessage = 0,
144 SMU_MSG_GetSmuVersion,
145 SMU_MSG_GetDriverIfVersion,
146 SMU_MSG_SetAllowedFeaturesMaskLow,
147 SMU_MSG_SetAllowedFeaturesMaskHigh,
148 SMU_MSG_EnableAllSmuFeatures,
149 SMU_MSG_DisableAllSmuFeatures,
150 SMU_MSG_EnableSmuFeaturesLow,
151 SMU_MSG_EnableSmuFeaturesHigh,
152 SMU_MSG_DisableSmuFeaturesLow,
153 SMU_MSG_DisableSmuFeaturesHigh,
154 SMU_MSG_GetEnabledSmuFeaturesLow,
155 SMU_MSG_GetEnabledSmuFeaturesHigh,
156 SMU_MSG_SetWorkloadMask,
158 SMU_MSG_SetDriverDramAddrHigh,
159 SMU_MSG_SetDriverDramAddrLow,
160 SMU_MSG_SetToolsDramAddrHigh,
161 SMU_MSG_SetToolsDramAddrLow,
162 SMU_MSG_TransferTableSmu2Dram,
163 SMU_MSG_TransferTableDram2Smu,
164 SMU_MSG_UseDefaultPPTable,
165 SMU_MSG_UseBackupPPTable,
167 SMU_MSG_RequestI2CBus,
168 SMU_MSG_ReleaseI2CBus,
169 SMU_MSG_SetFloorSocVoltage,
171 SMU_MSG_StartBacoMonitor,
172 SMU_MSG_CancelBacoMonitor,
174 SMU_MSG_SetSoftMinByFreq,
175 SMU_MSG_SetSoftMaxByFreq,
176 SMU_MSG_SetHardMinByFreq,
177 SMU_MSG_SetHardMaxByFreq,
178 SMU_MSG_GetMinDpmFreq,
179 SMU_MSG_GetMaxDpmFreq,
180 SMU_MSG_GetDpmFreqByIndex,
181 SMU_MSG_GetDpmClockFreq,
182 SMU_MSG_GetSsVoltageByDpm,
183 SMU_MSG_SetMemoryChannelConfig,
184 SMU_MSG_SetGeminiMode,
185 SMU_MSG_SetGeminiApertureHigh,
186 SMU_MSG_SetGeminiApertureLow,
187 SMU_MSG_SetMinLinkDpmByIndex,
188 SMU_MSG_OverridePcieParameters,
189 SMU_MSG_OverDriveSetPercentage,
190 SMU_MSG_SetMinDeepSleepDcefclk,
191 SMU_MSG_ReenableAcDcInterrupt,
192 SMU_MSG_NotifyPowerSource,
193 SMU_MSG_SetUclkFastSwitch,
194 SMU_MSG_SetUclkDownHyst,
195 SMU_MSG_GfxDeviceDriverReset,
196 SMU_MSG_GetCurrentRpm,
199 SMU_MSG_SetFanTemperatureTarget,
200 SMU_MSG_PrepareMp1ForUnload,
201 SMU_MSG_DramLogSetDramAddrHigh,
202 SMU_MSG_DramLogSetDramAddrLow,
203 SMU_MSG_DramLogSetDramSize,
204 SMU_MSG_SetFanMaxRpm,
205 SMU_MSG_SetFanMinPwm,
206 SMU_MSG_ConfigureGfxDidt,
207 SMU_MSG_NumOfDisplays,
208 SMU_MSG_RemoveMargins,
209 SMU_MSG_ReadSerialNumTop32,
210 SMU_MSG_ReadSerialNumBottom32,
211 SMU_MSG_SetSystemVirtualDramAddrHigh,
212 SMU_MSG_SetSystemVirtualDramAddrLow,
214 SMU_MSG_SetFclkGfxClkRatio,
216 SMU_MSG_DisallowGfxOff,
218 SMU_MSG_GetDcModeMaxDpmFreq,
219 SMU_MSG_GetDebugData,
223 SMU_MSG_PrepareMp1ForReset,
224 SMU_MSG_PrepareMp1ForShutdown,
225 SMU_MSG_SetMGpuFanBoostLimitRpm,
226 SMU_MSG_GetAVFSVoltageByDpm,
228 SMU_MSG_PowerDownVcn,
230 SMU_MSG_PowerDownJpeg,
257 enum smu_power_src_type
261 SMU_POWER_SOURCE_COUNT,
264 enum smu_feature_mask
266 SMU_FEATURE_DPM_PREFETCHER_BIT,
267 SMU_FEATURE_DPM_GFXCLK_BIT,
268 SMU_FEATURE_DPM_UCLK_BIT,
269 SMU_FEATURE_DPM_SOCCLK_BIT,
270 SMU_FEATURE_DPM_UVD_BIT,
271 SMU_FEATURE_DPM_VCE_BIT,
273 SMU_FEATURE_DPM_MP0CLK_BIT,
274 SMU_FEATURE_DPM_LINK_BIT,
275 SMU_FEATURE_DPM_DCEFCLK_BIT,
276 SMU_FEATURE_DS_GFXCLK_BIT,
277 SMU_FEATURE_DS_SOCCLK_BIT,
278 SMU_FEATURE_DS_LCLK_BIT,
281 SMU_FEATURE_THERMAL_BIT,
282 SMU_FEATURE_GFX_PER_CU_CG_BIT,
284 SMU_FEATURE_DS_DCEFCLK_BIT,
285 SMU_FEATURE_ACDC_BIT,
286 SMU_FEATURE_VR0HOT_BIT,
287 SMU_FEATURE_VR1HOT_BIT,
288 SMU_FEATURE_FW_CTF_BIT,
289 SMU_FEATURE_LED_DISPLAY_BIT,
290 SMU_FEATURE_FAN_CONTROL_BIT,
291 SMU_FEATURE_GFX_EDC_BIT,
292 SMU_FEATURE_GFXOFF_BIT,
294 SMU_FEATURE_DPM_FCLK_BIT,
295 SMU_FEATURE_DS_FCLK_BIT,
296 SMU_FEATURE_DS_MP1CLK_BIT,
297 SMU_FEATURE_DS_MP0CLK_BIT,
298 SMU_FEATURE_XGMI_BIT,
299 SMU_FEATURE_DPM_GFX_PACE_BIT,
300 SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
301 SMU_FEATURE_MEM_MVDD_SCALING_BIT,
302 SMU_FEATURE_DS_UCLK_BIT,
303 SMU_FEATURE_GFX_ULV_BIT,
304 SMU_FEATURE_FW_DSTATE_BIT,
305 SMU_FEATURE_BACO_BIT,
306 SMU_FEATURE_VCN_PG_BIT,
307 SMU_FEATURE_JPEG_PG_BIT,
308 SMU_FEATURE_USB_PG_BIT,
309 SMU_FEATURE_RSMU_SMN_CG_BIT,
310 SMU_FEATURE_APCC_PLUS_BIT,
311 SMU_FEATURE_GTHR_BIT,
312 SMU_FEATURE_GFX_DCS_BIT,
313 SMU_FEATURE_GFX_SS_BIT,
314 SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
315 SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
316 SMU_FEATURE_MMHUB_PG_BIT,
317 SMU_FEATURE_ATHUB_PG_BIT,
321 enum smu_memory_pool_size
323 SMU_MEMORY_POOL_SIZE_ZERO = 0,
324 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
325 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
326 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
327 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
330 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
332 tables[table_id].size = s; \
333 tables[table_id].align = a; \
334 tables[table_id].domain = d; \
343 struct amdgpu_bo *bo;
346 enum smu_perf_level_designation {
348 PERF_LEVEL_POWER_CONTAINMENT,
351 struct smu_performance_level {
353 uint32_t memory_clock;
356 uint32_t non_local_mem_freq;
357 uint32_t non_local_mem_width;
360 struct smu_clock_info {
361 uint32_t min_mem_clk;
362 uint32_t max_mem_clk;
363 uint32_t min_eng_clk;
364 uint32_t max_eng_clk;
365 uint32_t min_bus_bandwidth;
366 uint32_t max_bus_bandwidth;
369 struct smu_bios_boot_up_values
384 uint32_t pp_table_id;
389 SMU_TABLE_PPTABLE = 0,
390 SMU_TABLE_WATERMARKS,
392 SMU_TABLE_AVFS_PSM_DEBUG,
393 SMU_TABLE_AVFS_FUSE_OVERRIDE,
394 SMU_TABLE_PMSTATUSLOG,
395 SMU_TABLE_SMU_METRICS,
396 SMU_TABLE_DRIVER_SMU_CONFIG,
397 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
399 SMU_TABLE_I2C_COMMANDS,
404 struct smu_table_context
406 void *power_play_table;
407 uint32_t power_play_table_size;
408 void *hardcode_pptable;
410 void *max_sustainable_clocks;
411 struct smu_bios_boot_up_values boot_values;
412 void *driver_pptable;
413 struct smu_table *tables;
414 uint32_t table_count;
415 struct smu_table memory_pool;
416 uint16_t software_shutdown_temp;
417 uint8_t thermal_controller_type;
420 uint8_t *od_feature_capabilities;
421 uint32_t *od_settings_max;
422 uint32_t *od_settings_min;
423 void *overdrive_table;
425 bool od_gfxclk_update;
426 bool od_memclk_update;
429 struct smu_dpm_context {
430 uint32_t dpm_context_size;
432 void *golden_dpm_context;
433 bool enable_umd_pstate;
434 enum amd_dpm_forced_level dpm_level;
435 enum amd_dpm_forced_level saved_dpm_level;
436 enum amd_dpm_forced_level requested_dpm_level;
437 struct smu_power_state *dpm_request_power_state;
438 struct smu_power_state *dpm_current_power_state;
439 struct mclock_latency_table *mclk_latency_table;
442 struct smu_power_gate {
447 struct smu_power_context {
449 uint32_t power_context_size;
450 struct smu_power_gate power_gate;
454 #define SMU_FEATURE_MAX (64)
457 uint32_t feature_num;
458 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
459 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
460 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
465 uint32_t engine_clock;
466 uint32_t memory_clock;
467 uint32_t bus_bandwidth;
468 uint32_t engine_clock_in_sr;
470 uint32_t dcef_clock_in_sr;
473 #define MAX_REGULAR_DPM_NUM 16
474 struct mclk_latency_entries {
478 struct mclock_latency_table {
480 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
483 #define WORKLOAD_POLICY_MAX 7
486 struct amdgpu_device *adev;
488 const struct smu_funcs *funcs;
489 const struct pptable_funcs *ppt_funcs;
493 struct smu_table_context smu_table;
494 struct smu_dpm_context smu_dpm;
495 struct smu_power_context smu_power;
496 struct smu_feature smu_feature;
497 struct amd_pp_display_configuration *display_config;
499 uint32_t pstate_sclk;
500 uint32_t pstate_mclk;
503 uint32_t power_limit;
504 uint32_t default_power_limit;
507 uint32_t ppt_offset_bytes;
508 uint32_t ppt_size_bytes;
509 uint8_t *ppt_start_addr;
511 bool support_power_containment;
512 bool disable_watermark;
514 #define WATERMARKS_EXIST (1 << 0)
515 #define WATERMARKS_LOADED (1 << 1)
516 uint32_t watermarks_bitmap;
518 uint32_t workload_mask;
519 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
520 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
521 uint32_t power_profile_mode;
522 uint32_t default_power_profile_mode;
525 uint32_t smc_if_version;
527 unsigned long metrics_time;
531 struct pptable_funcs {
532 int (*alloc_dpm_context)(struct smu_context *smu);
533 int (*store_powerplay_table)(struct smu_context *smu);
534 int (*check_powerplay_table)(struct smu_context *smu);
535 int (*append_powerplay_table)(struct smu_context *smu);
536 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
537 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
538 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
539 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
540 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
541 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
542 int (*run_afll_btc)(struct smu_context *smu);
543 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
544 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
545 int (*set_default_dpm_table)(struct smu_context *smu);
546 int (*set_power_state)(struct smu_context *smu);
547 int (*populate_umd_state_clk)(struct smu_context *smu);
548 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
549 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
550 int (*set_default_od8_settings)(struct smu_context *smu);
551 int (*update_specified_od8_value)(struct smu_context *smu,
554 int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
555 int (*set_od_percentage)(struct smu_context *smu,
556 enum pp_clock_type type,
558 int (*od_edit_dpm_table)(struct smu_context *smu,
559 enum PP_OD_DPM_TABLE_COMMAND type,
560 long *input, uint32_t size);
561 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
562 enum smu_clk_type clk_type,
564 pp_clock_levels_with_latency
566 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
567 enum amd_pp_clock_type type,
569 pp_clock_levels_with_voltage
571 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
572 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
573 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
574 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
575 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
576 void *data, uint32_t *size);
577 int (*pre_display_config_changed)(struct smu_context *smu);
578 int (*display_config_changed)(struct smu_context *smu);
579 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
580 int (*notify_smc_dispaly_config)(struct smu_context *smu);
581 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
582 int (*unforce_dpm_levels)(struct smu_context *smu);
583 int (*get_profiling_clk_mask)(struct smu_context *smu,
584 enum amd_dpm_forced_level level,
588 int (*set_cpu_power_state)(struct smu_context *smu);
589 int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
590 int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
591 bool (*is_dpm_running)(struct smu_context *smu);
592 void (*tables_init)(struct smu_context *smu, struct smu_table *tables);
593 int (*set_thermal_fan_table)(struct smu_context *smu);
594 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
595 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
596 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
597 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
598 enum smu_clk_type clk_type,
604 int (*init_microcode)(struct smu_context *smu);
605 int (*init_smc_tables)(struct smu_context *smu);
606 int (*fini_smc_tables)(struct smu_context *smu);
607 int (*init_power)(struct smu_context *smu);
608 int (*fini_power)(struct smu_context *smu);
609 int (*load_microcode)(struct smu_context *smu);
610 int (*check_fw_status)(struct smu_context *smu);
611 int (*setup_pptable)(struct smu_context *smu);
612 int (*get_vbios_bootup_values)(struct smu_context *smu);
613 int (*get_clk_info_from_vbios)(struct smu_context *smu);
614 int (*check_pptable)(struct smu_context *smu);
615 int (*parse_pptable)(struct smu_context *smu);
616 int (*populate_smc_pptable)(struct smu_context *smu);
617 int (*check_fw_version)(struct smu_context *smu);
618 int (*write_pptable)(struct smu_context *smu);
619 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
620 int (*set_tool_table_location)(struct smu_context *smu);
621 int (*notify_memory_pool_location)(struct smu_context *smu);
622 int (*write_watermarks_table)(struct smu_context *smu);
623 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
624 int (*system_features_control)(struct smu_context *smu, bool en);
625 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
626 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
627 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
628 int (*init_display)(struct smu_context *smu);
629 int (*set_allowed_mask)(struct smu_context *smu);
630 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
631 int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
632 int (*notify_display_change)(struct smu_context *smu);
633 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
634 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
635 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
636 int (*init_max_sustainable_clocks)(struct smu_context *smu);
637 int (*start_thermal_control)(struct smu_context *smu);
638 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
639 void *data, uint32_t *size);
640 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
641 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
642 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
643 bool cc6_disable, bool pstate_disable,
644 bool pstate_switch_disable);
645 int (*get_clock_by_type)(struct smu_context *smu,
646 enum amd_pp_clock_type type,
647 struct amd_pp_clocks *clocks);
648 int (*get_max_high_clocks)(struct smu_context *smu,
649 struct amd_pp_simple_clock_info *clocks);
650 int (*display_clock_voltage_request)(struct smu_context *smu, struct
651 pp_display_clock_request
653 int (*get_dal_power_level)(struct smu_context *smu,
654 struct amd_pp_simple_clock_info *clocks);
655 int (*get_perf_level)(struct smu_context *smu,
656 enum smu_perf_level_designation designation,
657 struct smu_performance_level *level);
658 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
659 struct smu_clock_info *clocks);
660 int (*notify_smu_enable_pwe)(struct smu_context *smu);
661 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
662 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
663 int (*set_od8_default_settings)(struct smu_context *smu,
665 int (*conv_power_profile_to_pplib_workload)(int power_profile);
666 int (*update_od8_settings)(struct smu_context *smu,
669 uint32_t (*get_sclk)(struct smu_context *smu, bool low);
670 uint32_t (*get_mclk)(struct smu_context *smu, bool low);
671 int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
672 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
673 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
674 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
675 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
676 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
677 int (*gfx_off_control)(struct smu_context *smu, bool enable);
680 #define smu_init_microcode(smu) \
681 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
682 #define smu_init_smc_tables(smu) \
683 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
684 #define smu_fini_smc_tables(smu) \
685 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
686 #define smu_init_power(smu) \
687 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
688 #define smu_fini_power(smu) \
689 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
690 #define smu_load_microcode(smu) \
691 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
692 #define smu_check_fw_status(smu) \
693 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
694 #define smu_setup_pptable(smu) \
695 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
696 #define smu_get_vbios_bootup_values(smu) \
697 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
698 #define smu_get_clk_info_from_vbios(smu) \
699 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
700 #define smu_check_pptable(smu) \
701 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
702 #define smu_parse_pptable(smu) \
703 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
704 #define smu_populate_smc_pptable(smu) \
705 ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
706 #define smu_check_fw_version(smu) \
707 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
708 #define smu_write_pptable(smu) \
709 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
710 #define smu_set_min_dcef_deep_sleep(smu) \
711 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
712 #define smu_set_tool_table_location(smu) \
713 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
714 #define smu_notify_memory_pool_location(smu) \
715 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
716 #define smu_gfx_off_control(smu, enable) \
717 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
719 #define smu_write_watermarks_table(smu) \
720 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
721 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
722 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
723 #define smu_system_features_control(smu, en) \
724 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
725 #define smu_init_max_sustainable_clocks(smu) \
726 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
727 #define smu_set_od8_default_settings(smu, initialize) \
728 ((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu), (initialize)) : 0)
729 #define smu_update_od8_settings(smu, index, value) \
730 ((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
731 #define smu_get_current_rpm(smu, speed) \
732 ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
733 #define smu_set_fan_speed_rpm(smu, speed) \
734 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
735 #define smu_send_smc_msg(smu, msg) \
736 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
737 #define smu_send_smc_msg_with_param(smu, msg, param) \
738 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
739 #define smu_read_smc_arg(smu, arg) \
740 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
741 #define smu_alloc_dpm_context(smu) \
742 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
743 #define smu_init_display(smu) \
744 ((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
745 #define smu_feature_set_allowed_mask(smu) \
746 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
747 #define smu_feature_get_enabled_mask(smu, mask, num) \
748 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
749 #define smu_is_dpm_running(smu) \
750 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
751 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
752 ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
753 #define smu_notify_display_change(smu) \
754 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
755 #define smu_store_powerplay_table(smu) \
756 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
757 #define smu_check_powerplay_table(smu) \
758 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
759 #define smu_append_powerplay_table(smu) \
760 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
761 #define smu_set_default_dpm_table(smu) \
762 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
763 #define smu_populate_umd_state_clk(smu) \
764 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
765 #define smu_set_default_od8_settings(smu) \
766 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
767 #define smu_update_specified_od8_value(smu, index, value) \
768 ((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
769 #define smu_get_power_limit(smu, limit, def) \
770 ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
771 #define smu_set_power_limit(smu, limit) \
772 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
773 #define smu_get_current_clk_freq(smu, clk_id, value) \
774 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
775 #define smu_print_clk_levels(smu, clk_type, buf) \
776 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
777 #define smu_force_clk_levels(smu, clk_type, level) \
778 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
779 #define smu_get_od_percentage(smu, type) \
780 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
781 #define smu_set_od_percentage(smu, type, value) \
782 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
783 #define smu_od_edit_dpm_table(smu, type, input, size) \
784 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
785 #define smu_tables_init(smu, tab) \
786 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
787 #define smu_set_thermal_fan_table(smu) \
788 ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
789 #define smu_start_thermal_control(smu) \
790 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
791 #define smu_read_sensor(smu, sensor, data, size) \
792 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
793 #define smu_asic_read_sensor(smu, sensor, data, size) \
794 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
795 #define smu_get_power_profile_mode(smu, buf) \
796 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
797 #define smu_set_power_profile_mode(smu, param, param_size) \
798 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
799 #define smu_pre_display_config_changed(smu) \
800 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
801 #define smu_display_config_changed(smu) \
802 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
803 #define smu_apply_clocks_adjust_rules(smu) \
804 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
805 #define smu_notify_smc_dispaly_config(smu) \
806 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
807 #define smu_force_dpm_limit_value(smu, highest) \
808 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
809 #define smu_unforce_dpm_levels(smu) \
810 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
811 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
812 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
813 #define smu_set_cpu_power_state(smu) \
814 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
815 #define smu_get_fan_control_mode(smu) \
816 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
817 #define smu_set_fan_control_mode(smu, value) \
818 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
819 #define smu_get_fan_speed_percent(smu, speed) \
820 ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
821 #define smu_set_fan_speed_percent(smu, speed) \
822 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
824 #define smu_msg_get_index(smu, msg) \
825 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
826 #define smu_clk_get_index(smu, msg) \
827 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
828 #define smu_feature_get_index(smu, msg) \
829 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
830 #define smu_table_get_index(smu, tab) \
831 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
832 #define smu_power_get_index(smu, src) \
833 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
834 #define smu_workload_get_type(smu, profile) \
835 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
836 #define smu_run_afll_btc(smu) \
837 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
838 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
839 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
840 #define smu_set_deep_sleep_dcefclk(smu, clk) \
841 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
842 #define smu_set_active_display_count(smu, count) \
843 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
844 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
845 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
846 #define smu_get_clock_by_type(smu, type, clocks) \
847 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
848 #define smu_get_max_high_clocks(smu, clocks) \
849 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
850 #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
851 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
852 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
853 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
854 #define smu_display_clock_voltage_request(smu, clock_req) \
855 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
856 #define smu_get_dal_power_level(smu, clocks) \
857 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
858 #define smu_get_perf_level(smu, designation, level) \
859 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
860 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
861 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
862 #define smu_notify_smu_enable_pwe(smu) \
863 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
864 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
865 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
866 #define smu_dpm_set_uvd_enable(smu, enable) \
867 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
868 #define smu_dpm_set_vce_enable(smu, enable) \
869 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
870 #define smu_get_sclk(smu, low) \
871 ((smu)->funcs->get_sclk ? (smu)->funcs->get_sclk((smu), (low)) : 0)
872 #define smu_get_mclk(smu, low) \
873 ((smu)->funcs->get_mclk ? (smu)->funcs->get_mclk((smu), (low)) : 0)
874 #define smu_set_xgmi_pstate(smu, pstate) \
875 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
876 #define smu_set_ppfeature_status(smu, ppfeatures) \
877 ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
878 #define smu_get_ppfeature_status(smu, buf) \
879 ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
880 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
881 ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
882 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
883 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
885 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
886 uint16_t *size, uint8_t *frev, uint8_t *crev,
889 extern const struct amd_ip_funcs smu_ip_funcs;
891 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
892 extern int smu_feature_init_dpm(struct smu_context *smu);
894 extern int smu_feature_is_enabled(struct smu_context *smu,
895 enum smu_feature_mask mask);
896 extern int smu_feature_set_enabled(struct smu_context *smu,
897 enum smu_feature_mask mask, bool enable);
898 extern int smu_feature_is_supported(struct smu_context *smu,
899 enum smu_feature_mask mask);
900 extern int smu_feature_set_supported(struct smu_context *smu,
901 enum smu_feature_mask mask, bool enable);
903 int smu_update_table(struct smu_context *smu, uint32_t table_index,
904 void *table_data, bool drv2smu);
906 bool is_support_sw_smu(struct amdgpu_device *adev);
907 int smu_reset(struct smu_context *smu);
908 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
909 void *data, uint32_t *size);
910 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
911 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
912 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
913 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
915 /* smu to display interface */
916 extern int smu_display_configuration_change(struct smu_context *smu, const
917 struct amd_pp_display_configuration
919 extern int smu_get_current_clocks(struct smu_context *smu,
920 struct amd_pp_clock_info *clocks);
921 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
922 extern int smu_handle_task(struct smu_context *smu,
923 enum amd_dpm_forced_level level,
924 enum amd_pp_task task_id);
925 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
926 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
927 uint16_t level, uint32_t *value);
928 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
930 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
931 uint32_t *min, uint32_t *max);
932 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
933 uint32_t min, uint32_t max);
934 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
935 uint32_t min, uint32_t max);
936 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
937 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);