2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
35 struct smu_hw_power_state {
39 struct smu_power_state;
41 enum smu_state_ui_label {
42 SMU_STATE_UI_LABEL_NONE,
43 SMU_STATE_UI_LABEL_BATTERY,
44 SMU_STATE_UI_TABEL_MIDDLE_LOW,
45 SMU_STATE_UI_LABEL_BALLANCED,
46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
47 SMU_STATE_UI_LABEL_PERFORMANCE,
48 SMU_STATE_UI_LABEL_BACO,
51 enum smu_state_classification_flag {
52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
75 struct smu_state_classification_block {
76 enum smu_state_ui_label ui_label;
77 enum smu_state_classification_flag flags;
83 struct smu_state_pcie_block {
87 enum smu_refreshrate_source {
88 SMU_REFRESHRATE_SOURCE_EDID,
89 SMU_REFRESHRATE_SOURCE_EXPLICIT
92 struct smu_state_display_block {
93 bool disable_frame_modulation;
94 bool limit_refreshrate;
95 enum smu_refreshrate_source refreshrate_source;
96 int explicit_refreshrate;
97 int edid_refreshrate_index;
98 bool enable_vari_bright;
101 struct smu_state_memroy_block {
107 struct smu_state_software_algorithm_block {
108 bool disable_load_balancing;
109 bool enable_sleep_for_timestamps;
112 struct smu_temperature_range {
115 int edge_emergency_max;
117 int hotspot_crit_max;
118 int hotspot_emergency_max;
121 int mem_emergency_max;
124 struct smu_state_validation_block {
125 bool single_display_only;
127 uint8_t supported_power_levels;
130 struct smu_uvd_clocks {
136 * Structure to hold a SMU Power State.
138 struct smu_power_state {
140 struct list_head ordered_list;
141 struct list_head all_states_list;
143 struct smu_state_classification_block classification;
144 struct smu_state_validation_block validation;
145 struct smu_state_pcie_block pcie;
146 struct smu_state_display_block display;
147 struct smu_state_memroy_block memory;
148 struct smu_temperature_range temperatures;
149 struct smu_state_software_algorithm_block software;
150 struct smu_uvd_clocks uvd_clocks;
151 struct smu_hw_power_state hardware;
154 enum smu_power_src_type
158 SMU_POWER_SOURCE_COUNT,
161 enum smu_memory_pool_size
163 SMU_MEMORY_POOL_SIZE_ZERO = 0,
164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
170 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
172 tables[table_id].size = s; \
173 tables[table_id].align = a; \
174 tables[table_id].domain = d; \
183 struct amdgpu_bo *bo;
186 enum smu_perf_level_designation {
188 PERF_LEVEL_POWER_CONTAINMENT,
191 struct smu_performance_level {
193 uint32_t memory_clock;
196 uint32_t non_local_mem_freq;
197 uint32_t non_local_mem_width;
200 struct smu_clock_info {
201 uint32_t min_mem_clk;
202 uint32_t max_mem_clk;
203 uint32_t min_eng_clk;
204 uint32_t max_eng_clk;
205 uint32_t min_bus_bandwidth;
206 uint32_t max_bus_bandwidth;
209 struct smu_bios_boot_up_values
224 uint32_t pp_table_id;
225 uint32_t format_revision;
226 uint32_t content_revision;
232 SMU_TABLE_PPTABLE = 0,
233 SMU_TABLE_WATERMARKS,
234 SMU_TABLE_CUSTOM_DPM,
237 SMU_TABLE_AVFS_PSM_DEBUG,
238 SMU_TABLE_AVFS_FUSE_OVERRIDE,
239 SMU_TABLE_PMSTATUSLOG,
240 SMU_TABLE_SMU_METRICS,
241 SMU_TABLE_DRIVER_SMU_CONFIG,
242 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
244 SMU_TABLE_I2C_COMMANDS,
249 struct smu_table_context
251 void *power_play_table;
252 uint32_t power_play_table_size;
253 void *hardcode_pptable;
254 unsigned long metrics_time;
258 void *max_sustainable_clocks;
259 struct smu_bios_boot_up_values boot_values;
260 void *driver_pptable;
261 struct smu_table *tables;
262 uint32_t table_count;
263 struct smu_table memory_pool;
264 uint8_t thermal_controller_type;
267 void *overdrive_table;
270 struct smu_dpm_context {
271 uint32_t dpm_context_size;
273 void *golden_dpm_context;
274 bool enable_umd_pstate;
275 enum amd_dpm_forced_level dpm_level;
276 enum amd_dpm_forced_level saved_dpm_level;
277 enum amd_dpm_forced_level requested_dpm_level;
278 struct smu_power_state *dpm_request_power_state;
279 struct smu_power_state *dpm_current_power_state;
280 struct mclock_latency_table *mclk_latency_table;
283 struct smu_power_gate {
289 struct smu_power_context {
291 uint32_t power_context_size;
292 struct smu_power_gate power_gate;
296 #define SMU_FEATURE_MAX (64)
299 uint32_t feature_num;
300 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
301 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
302 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
307 uint32_t engine_clock;
308 uint32_t memory_clock;
309 uint32_t bus_bandwidth;
310 uint32_t engine_clock_in_sr;
312 uint32_t dcef_clock_in_sr;
315 #define MAX_REGULAR_DPM_NUM 16
316 struct mclk_latency_entries {
320 struct mclock_latency_table {
322 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
327 SMU_BACO_STATE_ENTER = 0,
331 struct smu_baco_context
335 bool platform_support;
338 #define WORKLOAD_POLICY_MAX 7
341 struct amdgpu_device *adev;
342 struct amdgpu_irq_src *irq_source;
344 const struct smu_funcs *funcs;
345 const struct pptable_funcs *ppt_funcs;
347 struct mutex sensor_lock;
350 struct smu_table_context smu_table;
351 struct smu_dpm_context smu_dpm;
352 struct smu_power_context smu_power;
353 struct smu_feature smu_feature;
354 struct amd_pp_display_configuration *display_config;
355 struct smu_baco_context smu_baco;
358 uint32_t pstate_sclk;
359 uint32_t pstate_mclk;
362 uint32_t power_limit;
363 uint32_t default_power_limit;
366 uint32_t ppt_offset_bytes;
367 uint32_t ppt_size_bytes;
368 uint8_t *ppt_start_addr;
370 bool support_power_containment;
371 bool disable_watermark;
373 #define WATERMARKS_EXIST (1 << 0)
374 #define WATERMARKS_LOADED (1 << 1)
375 uint32_t watermarks_bitmap;
376 uint32_t hard_min_uclk_req_from_dal;
377 bool disable_uclk_switch;
379 uint32_t workload_mask;
380 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
381 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
382 uint32_t power_profile_mode;
383 uint32_t default_power_profile_mode;
386 uint32_t smc_if_version;
390 struct pptable_funcs {
391 int (*alloc_dpm_context)(struct smu_context *smu);
392 int (*store_powerplay_table)(struct smu_context *smu);
393 int (*check_powerplay_table)(struct smu_context *smu);
394 int (*append_powerplay_table)(struct smu_context *smu);
395 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
396 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
397 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
398 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
399 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
400 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
401 int (*run_afll_btc)(struct smu_context *smu);
402 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
403 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
404 int (*set_default_dpm_table)(struct smu_context *smu);
405 int (*set_power_state)(struct smu_context *smu);
406 int (*populate_umd_state_clk)(struct smu_context *smu);
407 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
408 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
409 int (*set_default_od8_settings)(struct smu_context *smu);
410 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
411 int (*set_od_percentage)(struct smu_context *smu,
412 enum smu_clk_type clk_type,
414 int (*od_edit_dpm_table)(struct smu_context *smu,
415 enum PP_OD_DPM_TABLE_COMMAND type,
416 long *input, uint32_t size);
417 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
418 enum smu_clk_type clk_type,
420 pp_clock_levels_with_latency
422 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
423 enum amd_pp_clock_type type,
425 pp_clock_levels_with_voltage
427 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
428 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
429 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
430 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
431 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
432 void *data, uint32_t *size);
433 int (*pre_display_config_changed)(struct smu_context *smu);
434 int (*display_config_changed)(struct smu_context *smu);
435 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
436 int (*notify_smc_dispaly_config)(struct smu_context *smu);
437 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
438 int (*unforce_dpm_levels)(struct smu_context *smu);
439 int (*get_profiling_clk_mask)(struct smu_context *smu,
440 enum amd_dpm_forced_level level,
444 int (*set_cpu_power_state)(struct smu_context *smu);
445 bool (*is_dpm_running)(struct smu_context *smu);
446 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
447 int (*set_thermal_fan_table)(struct smu_context *smu);
448 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
449 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
450 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
451 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
452 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
453 enum smu_clk_type clk_type,
455 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
456 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
457 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
458 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
459 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
460 void (*dump_pptable)(struct smu_context *smu);
461 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
462 int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
467 int (*init_microcode)(struct smu_context *smu);
468 int (*init_smc_tables)(struct smu_context *smu);
469 int (*fini_smc_tables)(struct smu_context *smu);
470 int (*init_power)(struct smu_context *smu);
471 int (*fini_power)(struct smu_context *smu);
472 int (*load_microcode)(struct smu_context *smu);
473 int (*check_fw_status)(struct smu_context *smu);
474 int (*setup_pptable)(struct smu_context *smu);
475 int (*get_vbios_bootup_values)(struct smu_context *smu);
476 int (*get_clk_info_from_vbios)(struct smu_context *smu);
477 int (*check_pptable)(struct smu_context *smu);
478 int (*parse_pptable)(struct smu_context *smu);
479 int (*populate_smc_tables)(struct smu_context *smu);
480 int (*check_fw_version)(struct smu_context *smu);
481 int (*powergate_sdma)(struct smu_context *smu, bool gate);
482 int (*powergate_vcn)(struct smu_context *smu, bool gate);
483 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
484 int (*write_pptable)(struct smu_context *smu);
485 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
486 int (*set_tool_table_location)(struct smu_context *smu);
487 int (*notify_memory_pool_location)(struct smu_context *smu);
488 int (*write_watermarks_table)(struct smu_context *smu);
489 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
490 int (*system_features_control)(struct smu_context *smu, bool en);
491 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
492 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
493 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
494 int (*init_display_count)(struct smu_context *smu, uint32_t count);
495 int (*set_allowed_mask)(struct smu_context *smu);
496 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
497 int (*notify_display_change)(struct smu_context *smu);
498 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
499 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
500 int (*init_max_sustainable_clocks)(struct smu_context *smu);
501 int (*start_thermal_control)(struct smu_context *smu);
502 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
503 void *data, uint32_t *size);
504 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
505 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
506 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
507 bool cc6_disable, bool pstate_disable,
508 bool pstate_switch_disable);
509 int (*get_clock_by_type)(struct smu_context *smu,
510 enum amd_pp_clock_type type,
511 struct amd_pp_clocks *clocks);
512 int (*get_max_high_clocks)(struct smu_context *smu,
513 struct amd_pp_simple_clock_info *clocks);
514 int (*display_clock_voltage_request)(struct smu_context *smu, struct
515 pp_display_clock_request
517 int (*get_dal_power_level)(struct smu_context *smu,
518 struct amd_pp_simple_clock_info *clocks);
519 int (*get_perf_level)(struct smu_context *smu,
520 enum smu_perf_level_designation designation,
521 struct smu_performance_level *level);
522 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
523 struct smu_clock_info *clocks);
524 int (*notify_smu_enable_pwe)(struct smu_context *smu);
525 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
526 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
527 int (*conv_power_profile_to_pplib_workload)(int power_profile);
528 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
529 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
530 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
531 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
532 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
533 int (*gfx_off_control)(struct smu_context *smu, bool enable);
534 int (*register_irq_handler)(struct smu_context *smu);
535 int (*set_azalia_d3_pme)(struct smu_context *smu);
536 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
537 bool (*baco_is_support)(struct smu_context *smu);
538 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
539 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
540 int (*baco_reset)(struct smu_context *smu);
541 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
544 #define smu_init_microcode(smu) \
545 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
546 #define smu_init_smc_tables(smu) \
547 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
548 #define smu_fini_smc_tables(smu) \
549 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
550 #define smu_init_power(smu) \
551 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
552 #define smu_fini_power(smu) \
553 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
554 #define smu_load_microcode(smu) \
555 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
556 #define smu_check_fw_status(smu) \
557 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
558 #define smu_setup_pptable(smu) \
559 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
560 #define smu_powergate_sdma(smu, gate) \
561 ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
562 #define smu_powergate_vcn(smu, gate) \
563 ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
564 #define smu_set_gfx_cgpg(smu, enabled) \
565 ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
566 #define smu_get_vbios_bootup_values(smu) \
567 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
568 #define smu_get_clk_info_from_vbios(smu) \
569 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
570 #define smu_check_pptable(smu) \
571 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
572 #define smu_parse_pptable(smu) \
573 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
574 #define smu_populate_smc_tables(smu) \
575 ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
576 #define smu_check_fw_version(smu) \
577 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
578 #define smu_write_pptable(smu) \
579 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
580 #define smu_set_min_dcef_deep_sleep(smu) \
581 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
582 #define smu_set_tool_table_location(smu) \
583 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
584 #define smu_notify_memory_pool_location(smu) \
585 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
586 #define smu_gfx_off_control(smu, enable) \
587 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
589 #define smu_write_watermarks_table(smu) \
590 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
591 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
592 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
593 #define smu_system_features_control(smu, en) \
594 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
595 #define smu_init_max_sustainable_clocks(smu) \
596 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
597 #define smu_set_default_od_settings(smu, initialize) \
598 ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
599 #define smu_set_fan_speed_rpm(smu, speed) \
600 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
601 #define smu_send_smc_msg(smu, msg) \
602 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
603 #define smu_send_smc_msg_with_param(smu, msg, param) \
604 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
605 #define smu_read_smc_arg(smu, arg) \
606 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
607 #define smu_alloc_dpm_context(smu) \
608 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
609 #define smu_init_display_count(smu, count) \
610 ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
611 #define smu_feature_set_allowed_mask(smu) \
612 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
613 #define smu_feature_get_enabled_mask(smu, mask, num) \
614 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
615 #define smu_is_dpm_running(smu) \
616 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
617 #define smu_notify_display_change(smu) \
618 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
619 #define smu_store_powerplay_table(smu) \
620 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
621 #define smu_check_powerplay_table(smu) \
622 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
623 #define smu_append_powerplay_table(smu) \
624 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
625 #define smu_set_default_dpm_table(smu) \
626 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
627 #define smu_populate_umd_state_clk(smu) \
628 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
629 #define smu_set_default_od8_settings(smu) \
630 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
631 #define smu_get_power_limit(smu, limit, def) \
632 ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
633 #define smu_set_power_limit(smu, limit) \
634 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
635 #define smu_get_current_clk_freq(smu, clk_id, value) \
636 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
637 #define smu_print_clk_levels(smu, clk_type, buf) \
638 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
639 #define smu_force_clk_levels(smu, clk_type, level) \
640 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
641 #define smu_get_od_percentage(smu, type) \
642 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
643 #define smu_set_od_percentage(smu, type, value) \
644 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
645 #define smu_od_edit_dpm_table(smu, type, input, size) \
646 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
647 #define smu_tables_init(smu, tab) \
648 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
649 #define smu_set_thermal_fan_table(smu) \
650 ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
651 #define smu_start_thermal_control(smu) \
652 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
653 #define smu_read_sensor(smu, sensor, data, size) \
654 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
655 #define smu_smc_read_sensor(smu, sensor, data, size) \
656 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
657 #define smu_get_power_profile_mode(smu, buf) \
658 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
659 #define smu_set_power_profile_mode(smu, param, param_size) \
660 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
661 #define smu_pre_display_config_changed(smu) \
662 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
663 #define smu_display_config_changed(smu) \
664 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
665 #define smu_apply_clocks_adjust_rules(smu) \
666 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
667 #define smu_notify_smc_dispaly_config(smu) \
668 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
669 #define smu_force_dpm_limit_value(smu, highest) \
670 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
671 #define smu_unforce_dpm_levels(smu) \
672 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
673 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
674 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
675 #define smu_set_cpu_power_state(smu) \
676 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
677 #define smu_get_fan_control_mode(smu) \
678 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
679 #define smu_set_fan_control_mode(smu, value) \
680 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
681 #define smu_get_fan_speed_percent(smu, speed) \
682 ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
683 #define smu_set_fan_speed_percent(smu, speed) \
684 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
685 #define smu_get_fan_speed_rpm(smu, speed) \
686 ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
688 #define smu_msg_get_index(smu, msg) \
689 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
690 #define smu_clk_get_index(smu, msg) \
691 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
692 #define smu_feature_get_index(smu, msg) \
693 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
694 #define smu_table_get_index(smu, tab) \
695 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
696 #define smu_power_get_index(smu, src) \
697 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
698 #define smu_workload_get_type(smu, profile) \
699 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
700 #define smu_run_afll_btc(smu) \
701 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
702 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
703 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
704 #define smu_set_deep_sleep_dcefclk(smu, clk) \
705 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
706 #define smu_set_active_display_count(smu, count) \
707 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
708 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
709 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
710 #define smu_get_clock_by_type(smu, type, clocks) \
711 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
712 #define smu_get_max_high_clocks(smu, clocks) \
713 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
714 #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
715 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
716 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
717 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
718 #define smu_display_clock_voltage_request(smu, clock_req) \
719 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
720 #define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
721 ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
722 #define smu_get_dal_power_level(smu, clocks) \
723 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
724 #define smu_get_perf_level(smu, designation, level) \
725 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
726 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
727 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
728 #define smu_notify_smu_enable_pwe(smu) \
729 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
730 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
731 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
732 #define smu_dpm_set_uvd_enable(smu, enable) \
733 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
734 #define smu_dpm_set_vce_enable(smu, enable) \
735 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
736 #define smu_set_xgmi_pstate(smu, pstate) \
737 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
738 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
739 ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
740 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
741 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
742 #define smu_thermal_temperature_range_update(smu, range, rw) \
743 ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
744 #define smu_get_thermal_temperature_range(smu, range) \
745 ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
746 #define smu_register_irq_handler(smu) \
747 ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
748 #define smu_set_azalia_d3_pme(smu) \
749 ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
750 #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
751 ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
752 #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
753 ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
754 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
755 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
756 #define smu_baco_is_support(smu) \
757 ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
758 #define smu_baco_get_state(smu, state) \
759 ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
760 #define smu_baco_reset(smu) \
761 ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
762 #define smu_asic_set_performance_level(smu, level) \
763 ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
764 #define smu_dump_pptable(smu) \
765 ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
766 #define smu_get_dpm_uclk_limited(smu, clock, max) \
767 ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
770 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
771 uint16_t *size, uint8_t *frev, uint8_t *crev,
774 extern const struct amd_ip_funcs smu_ip_funcs;
776 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
777 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
779 extern int smu_feature_init_dpm(struct smu_context *smu);
781 extern int smu_feature_is_enabled(struct smu_context *smu,
782 enum smu_feature_mask mask);
783 extern int smu_feature_set_enabled(struct smu_context *smu,
784 enum smu_feature_mask mask, bool enable);
785 extern int smu_feature_is_supported(struct smu_context *smu,
786 enum smu_feature_mask mask);
787 extern int smu_feature_set_supported(struct smu_context *smu,
788 enum smu_feature_mask mask, bool enable);
790 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
791 void *table_data, bool drv2smu);
793 bool is_support_sw_smu(struct amdgpu_device *adev);
794 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
795 int smu_reset(struct smu_context *smu);
796 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
797 void *data, uint32_t *size);
798 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
799 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
800 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
801 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
803 /* smu to display interface */
804 extern int smu_display_configuration_change(struct smu_context *smu, const
805 struct amd_pp_display_configuration
807 extern int smu_get_current_clocks(struct smu_context *smu,
808 struct amd_pp_clock_info *clocks);
809 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
810 extern int smu_handle_task(struct smu_context *smu,
811 enum amd_dpm_forced_level level,
812 enum amd_pp_task task_id);
813 int smu_switch_power_profile(struct smu_context *smu,
814 enum PP_SMC_POWER_PROFILE type,
816 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
817 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
818 uint16_t level, uint32_t *value);
819 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
821 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
822 uint32_t *min, uint32_t *max);
823 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
824 uint32_t min, uint32_t max);
825 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
826 uint32_t min, uint32_t max);
827 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
828 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
829 int smu_set_display_count(struct smu_context *smu, uint32_t count);
830 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
831 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
832 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
833 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
834 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
835 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);