2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
30 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
31 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
32 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34 struct smu_hw_power_state {
38 struct smu_power_state;
40 enum smu_state_ui_label {
41 SMU_STATE_UI_LABEL_NONE,
42 SMU_STATE_UI_LABEL_BATTERY,
43 SMU_STATE_UI_TABEL_MIDDLE_LOW,
44 SMU_STATE_UI_LABEL_BALLANCED,
45 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
46 SMU_STATE_UI_LABEL_PERFORMANCE,
47 SMU_STATE_UI_LABEL_BACO,
50 enum smu_state_classification_flag {
51 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
52 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
53 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
54 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
55 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
56 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
58 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
59 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
60 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
61 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
62 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
63 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
64 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
66 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
67 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
68 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
69 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
70 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
71 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
74 struct smu_state_classification_block {
75 enum smu_state_ui_label ui_label;
76 enum smu_state_classification_flag flags;
82 struct smu_state_pcie_block {
86 enum smu_refreshrate_source {
87 SMU_REFRESHRATE_SOURCE_EDID,
88 SMU_REFRESHRATE_SOURCE_EXPLICIT
91 struct smu_state_display_block {
92 bool disable_frame_modulation;
93 bool limit_refreshrate;
94 enum smu_refreshrate_source refreshrate_source;
95 int explicit_refreshrate;
96 int edid_refreshrate_index;
97 bool enable_vari_bright;
100 struct smu_state_memroy_block {
106 struct smu_state_software_algorithm_block {
107 bool disable_load_balancing;
108 bool enable_sleep_for_timestamps;
111 struct smu_temperature_range {
114 int edge_emergency_max;
116 int hotspot_crit_max;
117 int hotspot_emergency_max;
120 int mem_emergency_max;
123 struct smu_state_validation_block {
124 bool single_display_only;
126 uint8_t supported_power_levels;
129 struct smu_uvd_clocks {
135 * Structure to hold a SMU Power State.
137 struct smu_power_state {
139 struct list_head ordered_list;
140 struct list_head all_states_list;
142 struct smu_state_classification_block classification;
143 struct smu_state_validation_block validation;
144 struct smu_state_pcie_block pcie;
145 struct smu_state_display_block display;
146 struct smu_state_memroy_block memory;
147 struct smu_temperature_range temperatures;
148 struct smu_state_software_algorithm_block software;
149 struct smu_uvd_clocks uvd_clocks;
150 struct smu_hw_power_state hardware;
153 enum smu_message_type
155 SMU_MSG_TestMessage = 0,
156 SMU_MSG_GetSmuVersion,
157 SMU_MSG_GetDriverIfVersion,
158 SMU_MSG_SetAllowedFeaturesMaskLow,
159 SMU_MSG_SetAllowedFeaturesMaskHigh,
160 SMU_MSG_EnableAllSmuFeatures,
161 SMU_MSG_DisableAllSmuFeatures,
162 SMU_MSG_EnableSmuFeaturesLow,
163 SMU_MSG_EnableSmuFeaturesHigh,
164 SMU_MSG_DisableSmuFeaturesLow,
165 SMU_MSG_DisableSmuFeaturesHigh,
166 SMU_MSG_GetEnabledSmuFeaturesLow,
167 SMU_MSG_GetEnabledSmuFeaturesHigh,
168 SMU_MSG_SetWorkloadMask,
170 SMU_MSG_SetDriverDramAddrHigh,
171 SMU_MSG_SetDriverDramAddrLow,
172 SMU_MSG_SetToolsDramAddrHigh,
173 SMU_MSG_SetToolsDramAddrLow,
174 SMU_MSG_TransferTableSmu2Dram,
175 SMU_MSG_TransferTableDram2Smu,
176 SMU_MSG_UseDefaultPPTable,
177 SMU_MSG_UseBackupPPTable,
179 SMU_MSG_RequestI2CBus,
180 SMU_MSG_ReleaseI2CBus,
181 SMU_MSG_SetFloorSocVoltage,
183 SMU_MSG_StartBacoMonitor,
184 SMU_MSG_CancelBacoMonitor,
186 SMU_MSG_SetSoftMinByFreq,
187 SMU_MSG_SetSoftMaxByFreq,
188 SMU_MSG_SetHardMinByFreq,
189 SMU_MSG_SetHardMaxByFreq,
190 SMU_MSG_GetMinDpmFreq,
191 SMU_MSG_GetMaxDpmFreq,
192 SMU_MSG_GetDpmFreqByIndex,
193 SMU_MSG_GetDpmClockFreq,
194 SMU_MSG_GetSsVoltageByDpm,
195 SMU_MSG_SetMemoryChannelConfig,
196 SMU_MSG_SetGeminiMode,
197 SMU_MSG_SetGeminiApertureHigh,
198 SMU_MSG_SetGeminiApertureLow,
199 SMU_MSG_SetMinLinkDpmByIndex,
200 SMU_MSG_OverridePcieParameters,
201 SMU_MSG_OverDriveSetPercentage,
202 SMU_MSG_SetMinDeepSleepDcefclk,
203 SMU_MSG_ReenableAcDcInterrupt,
204 SMU_MSG_NotifyPowerSource,
205 SMU_MSG_SetUclkFastSwitch,
206 SMU_MSG_SetUclkDownHyst,
207 SMU_MSG_GfxDeviceDriverReset,
208 SMU_MSG_GetCurrentRpm,
211 SMU_MSG_SetFanTemperatureTarget,
212 SMU_MSG_PrepareMp1ForUnload,
213 SMU_MSG_DramLogSetDramAddrHigh,
214 SMU_MSG_DramLogSetDramAddrLow,
215 SMU_MSG_DramLogSetDramSize,
216 SMU_MSG_SetFanMaxRpm,
217 SMU_MSG_SetFanMinPwm,
218 SMU_MSG_ConfigureGfxDidt,
219 SMU_MSG_NumOfDisplays,
220 SMU_MSG_RemoveMargins,
221 SMU_MSG_ReadSerialNumTop32,
222 SMU_MSG_ReadSerialNumBottom32,
223 SMU_MSG_SetSystemVirtualDramAddrHigh,
224 SMU_MSG_SetSystemVirtualDramAddrLow,
226 SMU_MSG_SetFclkGfxClkRatio,
228 SMU_MSG_DisallowGfxOff,
230 SMU_MSG_GetDcModeMaxDpmFreq,
231 SMU_MSG_GetDebugData,
235 SMU_MSG_PrepareMp1ForReset,
236 SMU_MSG_PrepareMp1ForShutdown,
237 SMU_MSG_SetMGpuFanBoostLimitRpm,
238 SMU_MSG_GetAVFSVoltageByDpm,
240 SMU_MSG_PowerDownVcn,
242 SMU_MSG_PowerDownJpeg,
243 SMU_MSG_BacoAudioD3PME,
271 enum smu_power_src_type
275 SMU_POWER_SOURCE_COUNT,
278 enum smu_feature_mask
280 SMU_FEATURE_DPM_PREFETCHER_BIT,
281 SMU_FEATURE_DPM_GFXCLK_BIT,
282 SMU_FEATURE_DPM_UCLK_BIT,
283 SMU_FEATURE_DPM_SOCCLK_BIT,
284 SMU_FEATURE_DPM_UVD_BIT,
285 SMU_FEATURE_DPM_VCE_BIT,
287 SMU_FEATURE_DPM_MP0CLK_BIT,
288 SMU_FEATURE_DPM_LINK_BIT,
289 SMU_FEATURE_DPM_DCEFCLK_BIT,
290 SMU_FEATURE_DS_GFXCLK_BIT,
291 SMU_FEATURE_DS_SOCCLK_BIT,
292 SMU_FEATURE_DS_LCLK_BIT,
295 SMU_FEATURE_THERMAL_BIT,
296 SMU_FEATURE_GFX_PER_CU_CG_BIT,
298 SMU_FEATURE_DS_DCEFCLK_BIT,
299 SMU_FEATURE_ACDC_BIT,
300 SMU_FEATURE_VR0HOT_BIT,
301 SMU_FEATURE_VR1HOT_BIT,
302 SMU_FEATURE_FW_CTF_BIT,
303 SMU_FEATURE_LED_DISPLAY_BIT,
304 SMU_FEATURE_FAN_CONTROL_BIT,
305 SMU_FEATURE_GFX_EDC_BIT,
306 SMU_FEATURE_GFXOFF_BIT,
308 SMU_FEATURE_DPM_FCLK_BIT,
309 SMU_FEATURE_DS_FCLK_BIT,
310 SMU_FEATURE_DS_MP1CLK_BIT,
311 SMU_FEATURE_DS_MP0CLK_BIT,
312 SMU_FEATURE_XGMI_BIT,
313 SMU_FEATURE_DPM_GFX_PACE_BIT,
314 SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
315 SMU_FEATURE_MEM_MVDD_SCALING_BIT,
316 SMU_FEATURE_DS_UCLK_BIT,
317 SMU_FEATURE_GFX_ULV_BIT,
318 SMU_FEATURE_FW_DSTATE_BIT,
319 SMU_FEATURE_BACO_BIT,
320 SMU_FEATURE_VCN_PG_BIT,
321 SMU_FEATURE_JPEG_PG_BIT,
322 SMU_FEATURE_USB_PG_BIT,
323 SMU_FEATURE_RSMU_SMN_CG_BIT,
324 SMU_FEATURE_APCC_PLUS_BIT,
325 SMU_FEATURE_GTHR_BIT,
326 SMU_FEATURE_GFX_DCS_BIT,
327 SMU_FEATURE_GFX_SS_BIT,
328 SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
329 SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
330 SMU_FEATURE_MMHUB_PG_BIT,
331 SMU_FEATURE_ATHUB_PG_BIT,
335 enum smu_memory_pool_size
337 SMU_MEMORY_POOL_SIZE_ZERO = 0,
338 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
339 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
340 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
341 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
344 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
346 tables[table_id].size = s; \
347 tables[table_id].align = a; \
348 tables[table_id].domain = d; \
357 struct amdgpu_bo *bo;
360 enum smu_perf_level_designation {
362 PERF_LEVEL_POWER_CONTAINMENT,
365 struct smu_performance_level {
367 uint32_t memory_clock;
370 uint32_t non_local_mem_freq;
371 uint32_t non_local_mem_width;
374 struct smu_clock_info {
375 uint32_t min_mem_clk;
376 uint32_t max_mem_clk;
377 uint32_t min_eng_clk;
378 uint32_t max_eng_clk;
379 uint32_t min_bus_bandwidth;
380 uint32_t max_bus_bandwidth;
383 struct smu_bios_boot_up_values
398 uint32_t pp_table_id;
403 SMU_TABLE_PPTABLE = 0,
404 SMU_TABLE_WATERMARKS,
406 SMU_TABLE_AVFS_PSM_DEBUG,
407 SMU_TABLE_AVFS_FUSE_OVERRIDE,
408 SMU_TABLE_PMSTATUSLOG,
409 SMU_TABLE_SMU_METRICS,
410 SMU_TABLE_DRIVER_SMU_CONFIG,
411 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
413 SMU_TABLE_I2C_COMMANDS,
418 struct smu_table_context
420 void *power_play_table;
421 uint32_t power_play_table_size;
422 void *hardcode_pptable;
423 unsigned long metrics_time;
426 void *max_sustainable_clocks;
427 struct smu_bios_boot_up_values boot_values;
428 void *driver_pptable;
429 struct smu_table *tables;
430 uint32_t table_count;
431 struct smu_table memory_pool;
432 uint16_t software_shutdown_temp;
433 uint8_t thermal_controller_type;
436 void *overdrive_table;
439 struct smu_dpm_context {
440 uint32_t dpm_context_size;
442 void *golden_dpm_context;
443 bool enable_umd_pstate;
444 enum amd_dpm_forced_level dpm_level;
445 enum amd_dpm_forced_level saved_dpm_level;
446 enum amd_dpm_forced_level requested_dpm_level;
447 struct smu_power_state *dpm_request_power_state;
448 struct smu_power_state *dpm_current_power_state;
449 struct mclock_latency_table *mclk_latency_table;
452 struct smu_power_gate {
457 struct smu_power_context {
459 uint32_t power_context_size;
460 struct smu_power_gate power_gate;
464 #define SMU_FEATURE_MAX (64)
467 uint32_t feature_num;
468 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
469 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
470 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
475 uint32_t engine_clock;
476 uint32_t memory_clock;
477 uint32_t bus_bandwidth;
478 uint32_t engine_clock_in_sr;
480 uint32_t dcef_clock_in_sr;
483 #define MAX_REGULAR_DPM_NUM 16
484 struct mclk_latency_entries {
488 struct mclock_latency_table {
490 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
495 SMU_BACO_STATE_ENTER = 0,
499 struct smu_baco_context
503 bool platform_support;
506 #define WORKLOAD_POLICY_MAX 7
509 struct amdgpu_device *adev;
510 struct amdgpu_irq_src *irq_source;
512 const struct smu_funcs *funcs;
513 const struct pptable_funcs *ppt_funcs;
517 struct smu_table_context smu_table;
518 struct smu_dpm_context smu_dpm;
519 struct smu_power_context smu_power;
520 struct smu_feature smu_feature;
521 struct amd_pp_display_configuration *display_config;
522 struct smu_baco_context smu_baco;
525 uint32_t pstate_sclk;
526 uint32_t pstate_mclk;
529 uint32_t power_limit;
530 uint32_t default_power_limit;
533 uint32_t ppt_offset_bytes;
534 uint32_t ppt_size_bytes;
535 uint8_t *ppt_start_addr;
537 bool support_power_containment;
538 bool disable_watermark;
540 #define WATERMARKS_EXIST (1 << 0)
541 #define WATERMARKS_LOADED (1 << 1)
542 uint32_t watermarks_bitmap;
544 uint32_t workload_mask;
545 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
546 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
547 uint32_t power_profile_mode;
548 uint32_t default_power_profile_mode;
551 uint32_t smc_if_version;
555 struct pptable_funcs {
556 int (*alloc_dpm_context)(struct smu_context *smu);
557 int (*store_powerplay_table)(struct smu_context *smu);
558 int (*check_powerplay_table)(struct smu_context *smu);
559 int (*append_powerplay_table)(struct smu_context *smu);
560 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
561 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
562 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
563 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
564 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
565 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
566 int (*run_afll_btc)(struct smu_context *smu);
567 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
568 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
569 int (*set_default_dpm_table)(struct smu_context *smu);
570 int (*set_power_state)(struct smu_context *smu);
571 int (*populate_umd_state_clk)(struct smu_context *smu);
572 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
573 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
574 int (*set_default_od8_settings)(struct smu_context *smu);
575 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
576 int (*set_od_percentage)(struct smu_context *smu,
577 enum smu_clk_type clk_type,
579 int (*od_edit_dpm_table)(struct smu_context *smu,
580 enum PP_OD_DPM_TABLE_COMMAND type,
581 long *input, uint32_t size);
582 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
583 enum smu_clk_type clk_type,
585 pp_clock_levels_with_latency
587 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
588 enum amd_pp_clock_type type,
590 pp_clock_levels_with_voltage
592 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
593 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
594 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
595 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
596 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
597 void *data, uint32_t *size);
598 int (*pre_display_config_changed)(struct smu_context *smu);
599 int (*display_config_changed)(struct smu_context *smu);
600 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
601 int (*notify_smc_dispaly_config)(struct smu_context *smu);
602 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
603 int (*unforce_dpm_levels)(struct smu_context *smu);
604 int (*get_profiling_clk_mask)(struct smu_context *smu,
605 enum amd_dpm_forced_level level,
609 int (*set_cpu_power_state)(struct smu_context *smu);
610 int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
611 int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
612 bool (*is_dpm_running)(struct smu_context *smu);
613 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
614 int (*set_thermal_fan_table)(struct smu_context *smu);
615 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
616 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
617 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
618 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
619 enum smu_clk_type clk_type,
621 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
622 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
623 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
628 int (*init_microcode)(struct smu_context *smu);
629 int (*init_smc_tables)(struct smu_context *smu);
630 int (*fini_smc_tables)(struct smu_context *smu);
631 int (*init_power)(struct smu_context *smu);
632 int (*fini_power)(struct smu_context *smu);
633 int (*load_microcode)(struct smu_context *smu);
634 int (*check_fw_status)(struct smu_context *smu);
635 int (*setup_pptable)(struct smu_context *smu);
636 int (*get_vbios_bootup_values)(struct smu_context *smu);
637 int (*get_clk_info_from_vbios)(struct smu_context *smu);
638 int (*check_pptable)(struct smu_context *smu);
639 int (*parse_pptable)(struct smu_context *smu);
640 int (*populate_smc_pptable)(struct smu_context *smu);
641 int (*check_fw_version)(struct smu_context *smu);
642 int (*write_pptable)(struct smu_context *smu);
643 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
644 int (*set_tool_table_location)(struct smu_context *smu);
645 int (*notify_memory_pool_location)(struct smu_context *smu);
646 int (*write_watermarks_table)(struct smu_context *smu);
647 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
648 int (*system_features_control)(struct smu_context *smu, bool en);
649 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
650 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
651 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
652 int (*init_display_count)(struct smu_context *smu, uint32_t count);
653 int (*set_allowed_mask)(struct smu_context *smu);
654 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
655 int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
656 int (*notify_display_change)(struct smu_context *smu);
657 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
658 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
659 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
660 int (*init_max_sustainable_clocks)(struct smu_context *smu);
661 int (*start_thermal_control)(struct smu_context *smu);
662 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
663 void *data, uint32_t *size);
664 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
665 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
666 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
667 bool cc6_disable, bool pstate_disable,
668 bool pstate_switch_disable);
669 int (*get_clock_by_type)(struct smu_context *smu,
670 enum amd_pp_clock_type type,
671 struct amd_pp_clocks *clocks);
672 int (*get_max_high_clocks)(struct smu_context *smu,
673 struct amd_pp_simple_clock_info *clocks);
674 int (*display_clock_voltage_request)(struct smu_context *smu, struct
675 pp_display_clock_request
677 int (*get_dal_power_level)(struct smu_context *smu,
678 struct amd_pp_simple_clock_info *clocks);
679 int (*get_perf_level)(struct smu_context *smu,
680 enum smu_perf_level_designation designation,
681 struct smu_performance_level *level);
682 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
683 struct smu_clock_info *clocks);
684 int (*notify_smu_enable_pwe)(struct smu_context *smu);
685 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
686 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
687 int (*conv_power_profile_to_pplib_workload)(int power_profile);
688 int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
689 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
690 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
691 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
692 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
693 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
694 int (*gfx_off_control)(struct smu_context *smu, bool enable);
695 int (*register_irq_handler)(struct smu_context *smu);
696 int (*set_azalia_d3_pme)(struct smu_context *smu);
697 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
698 bool (*baco_is_support)(struct smu_context *smu);
699 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
700 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
701 int (*baco_reset)(struct smu_context *smu);
705 #define smu_init_microcode(smu) \
706 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
707 #define smu_init_smc_tables(smu) \
708 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
709 #define smu_fini_smc_tables(smu) \
710 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
711 #define smu_init_power(smu) \
712 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
713 #define smu_fini_power(smu) \
714 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
715 #define smu_load_microcode(smu) \
716 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
717 #define smu_check_fw_status(smu) \
718 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
719 #define smu_setup_pptable(smu) \
720 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
721 #define smu_get_vbios_bootup_values(smu) \
722 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
723 #define smu_get_clk_info_from_vbios(smu) \
724 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
725 #define smu_check_pptable(smu) \
726 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
727 #define smu_parse_pptable(smu) \
728 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
729 #define smu_populate_smc_pptable(smu) \
730 ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
731 #define smu_check_fw_version(smu) \
732 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
733 #define smu_write_pptable(smu) \
734 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
735 #define smu_set_min_dcef_deep_sleep(smu) \
736 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
737 #define smu_set_tool_table_location(smu) \
738 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
739 #define smu_notify_memory_pool_location(smu) \
740 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
741 #define smu_gfx_off_control(smu, enable) \
742 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
744 #define smu_write_watermarks_table(smu) \
745 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
746 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
747 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
748 #define smu_system_features_control(smu, en) \
749 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
750 #define smu_init_max_sustainable_clocks(smu) \
751 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
752 #define smu_set_default_od_settings(smu, initialize) \
753 ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
754 #define smu_get_current_rpm(smu, speed) \
755 ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
756 #define smu_set_fan_speed_rpm(smu, speed) \
757 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
758 #define smu_send_smc_msg(smu, msg) \
759 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
760 #define smu_send_smc_msg_with_param(smu, msg, param) \
761 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
762 #define smu_read_smc_arg(smu, arg) \
763 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
764 #define smu_alloc_dpm_context(smu) \
765 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
766 #define smu_init_display_count(smu, count) \
767 ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
768 #define smu_feature_set_allowed_mask(smu) \
769 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
770 #define smu_feature_get_enabled_mask(smu, mask, num) \
771 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
772 #define smu_is_dpm_running(smu) \
773 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
774 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
775 ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
776 #define smu_notify_display_change(smu) \
777 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
778 #define smu_store_powerplay_table(smu) \
779 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
780 #define smu_check_powerplay_table(smu) \
781 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
782 #define smu_append_powerplay_table(smu) \
783 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
784 #define smu_set_default_dpm_table(smu) \
785 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
786 #define smu_populate_umd_state_clk(smu) \
787 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
788 #define smu_set_default_od8_settings(smu) \
789 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
790 #define smu_get_power_limit(smu, limit, def) \
791 ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
792 #define smu_set_power_limit(smu, limit) \
793 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
794 #define smu_get_current_clk_freq(smu, clk_id, value) \
795 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
796 #define smu_print_clk_levels(smu, clk_type, buf) \
797 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
798 #define smu_force_clk_levels(smu, clk_type, level) \
799 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
800 #define smu_get_od_percentage(smu, type) \
801 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
802 #define smu_set_od_percentage(smu, type, value) \
803 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
804 #define smu_od_edit_dpm_table(smu, type, input, size) \
805 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
806 #define smu_tables_init(smu, tab) \
807 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
808 #define smu_set_thermal_fan_table(smu) \
809 ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
810 #define smu_start_thermal_control(smu) \
811 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
812 #define smu_read_sensor(smu, sensor, data, size) \
813 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
814 #define smu_asic_read_sensor(smu, sensor, data, size) \
815 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
816 #define smu_get_power_profile_mode(smu, buf) \
817 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
818 #define smu_set_power_profile_mode(smu, param, param_size) \
819 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
820 #define smu_pre_display_config_changed(smu) \
821 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
822 #define smu_display_config_changed(smu) \
823 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
824 #define smu_apply_clocks_adjust_rules(smu) \
825 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
826 #define smu_notify_smc_dispaly_config(smu) \
827 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
828 #define smu_force_dpm_limit_value(smu, highest) \
829 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
830 #define smu_unforce_dpm_levels(smu) \
831 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
832 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
833 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
834 #define smu_set_cpu_power_state(smu) \
835 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
836 #define smu_get_fan_control_mode(smu) \
837 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
838 #define smu_set_fan_control_mode(smu, value) \
839 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
840 #define smu_get_fan_speed_percent(smu, speed) \
841 ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
842 #define smu_set_fan_speed_percent(smu, speed) \
843 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
845 #define smu_msg_get_index(smu, msg) \
846 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
847 #define smu_clk_get_index(smu, msg) \
848 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
849 #define smu_feature_get_index(smu, msg) \
850 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
851 #define smu_table_get_index(smu, tab) \
852 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
853 #define smu_power_get_index(smu, src) \
854 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
855 #define smu_workload_get_type(smu, profile) \
856 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
857 #define smu_run_afll_btc(smu) \
858 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
859 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
860 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
861 #define smu_set_deep_sleep_dcefclk(smu, clk) \
862 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
863 #define smu_set_active_display_count(smu, count) \
864 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
865 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
866 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
867 #define smu_get_clock_by_type(smu, type, clocks) \
868 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
869 #define smu_get_max_high_clocks(smu, clocks) \
870 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
871 #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
872 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
873 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
874 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
875 #define smu_display_clock_voltage_request(smu, clock_req) \
876 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
877 #define smu_get_dal_power_level(smu, clocks) \
878 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
879 #define smu_get_perf_level(smu, designation, level) \
880 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
881 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
882 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
883 #define smu_notify_smu_enable_pwe(smu) \
884 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
885 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
886 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
887 #define smu_dpm_set_uvd_enable(smu, enable) \
888 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
889 #define smu_dpm_set_vce_enable(smu, enable) \
890 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
891 #define smu_set_xgmi_pstate(smu, pstate) \
892 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
893 #define smu_set_ppfeature_status(smu, ppfeatures) \
894 ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
895 #define smu_get_ppfeature_status(smu, buf) \
896 ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
897 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
898 ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
899 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
900 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
901 #define smu_thermal_temperature_range_update(smu, range, rw) \
902 ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
903 #define smu_get_thermal_temperature_range(smu, range) \
904 ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
905 #define smu_register_irq_handler(smu) \
906 ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
907 #define smu_set_azalia_d3_pme(smu) \
908 ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
909 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
910 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
911 #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
912 ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
913 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
914 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
915 #define smu_baco_is_support(smu) \
916 ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
917 #define smu_baco_get_state(smu, state) \
918 ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
919 #define smu_baco_reset(smu) \
920 ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
922 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
923 uint16_t *size, uint8_t *frev, uint8_t *crev,
926 extern const struct amd_ip_funcs smu_ip_funcs;
928 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
929 extern int smu_feature_init_dpm(struct smu_context *smu);
931 extern int smu_feature_is_enabled(struct smu_context *smu,
932 enum smu_feature_mask mask);
933 extern int smu_feature_set_enabled(struct smu_context *smu,
934 enum smu_feature_mask mask, bool enable);
935 extern int smu_feature_is_supported(struct smu_context *smu,
936 enum smu_feature_mask mask);
937 extern int smu_feature_set_supported(struct smu_context *smu,
938 enum smu_feature_mask mask, bool enable);
940 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
941 void *table_data, bool drv2smu);
943 bool is_support_sw_smu(struct amdgpu_device *adev);
944 int smu_reset(struct smu_context *smu);
945 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
946 void *data, uint32_t *size);
947 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
948 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
949 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
950 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
952 /* smu to display interface */
953 extern int smu_display_configuration_change(struct smu_context *smu, const
954 struct amd_pp_display_configuration
956 extern int smu_get_current_clocks(struct smu_context *smu,
957 struct amd_pp_clock_info *clocks);
958 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
959 extern int smu_handle_task(struct smu_context *smu,
960 enum amd_dpm_forced_level level,
961 enum amd_pp_task task_id);
962 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
963 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
964 uint16_t level, uint32_t *value);
965 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
967 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
968 uint32_t *min, uint32_t *max);
969 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
970 uint32_t min, uint32_t max);
971 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
972 uint32_t min, uint32_t max);
973 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
974 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
975 int smu_set_display_count(struct smu_context *smu, uint32_t count);
976 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);