2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
35 struct smu_hw_power_state {
39 struct smu_power_state;
41 enum smu_state_ui_label {
42 SMU_STATE_UI_LABEL_NONE,
43 SMU_STATE_UI_LABEL_BATTERY,
44 SMU_STATE_UI_TABEL_MIDDLE_LOW,
45 SMU_STATE_UI_LABEL_BALLANCED,
46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
47 SMU_STATE_UI_LABEL_PERFORMANCE,
48 SMU_STATE_UI_LABEL_BACO,
51 enum smu_state_classification_flag {
52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
75 struct smu_state_classification_block {
76 enum smu_state_ui_label ui_label;
77 enum smu_state_classification_flag flags;
83 struct smu_state_pcie_block {
87 enum smu_refreshrate_source {
88 SMU_REFRESHRATE_SOURCE_EDID,
89 SMU_REFRESHRATE_SOURCE_EXPLICIT
92 struct smu_state_display_block {
93 bool disable_frame_modulation;
94 bool limit_refreshrate;
95 enum smu_refreshrate_source refreshrate_source;
96 int explicit_refreshrate;
97 int edid_refreshrate_index;
98 bool enable_vari_bright;
101 struct smu_state_memroy_block {
107 struct smu_state_software_algorithm_block {
108 bool disable_load_balancing;
109 bool enable_sleep_for_timestamps;
112 struct smu_temperature_range {
115 int edge_emergency_max;
117 int hotspot_crit_max;
118 int hotspot_emergency_max;
121 int mem_emergency_max;
124 struct smu_state_validation_block {
125 bool single_display_only;
127 uint8_t supported_power_levels;
130 struct smu_uvd_clocks {
136 * Structure to hold a SMU Power State.
138 struct smu_power_state {
140 struct list_head ordered_list;
141 struct list_head all_states_list;
143 struct smu_state_classification_block classification;
144 struct smu_state_validation_block validation;
145 struct smu_state_pcie_block pcie;
146 struct smu_state_display_block display;
147 struct smu_state_memroy_block memory;
148 struct smu_temperature_range temperatures;
149 struct smu_state_software_algorithm_block software;
150 struct smu_uvd_clocks uvd_clocks;
151 struct smu_hw_power_state hardware;
154 enum smu_power_src_type
158 SMU_POWER_SOURCE_COUNT,
161 enum smu_memory_pool_size
163 SMU_MEMORY_POOL_SIZE_ZERO = 0,
164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
170 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
172 tables[table_id].size = s; \
173 tables[table_id].align = a; \
174 tables[table_id].domain = d; \
183 struct amdgpu_bo *bo;
186 enum smu_perf_level_designation {
188 PERF_LEVEL_POWER_CONTAINMENT,
191 struct smu_performance_level {
193 uint32_t memory_clock;
196 uint32_t non_local_mem_freq;
197 uint32_t non_local_mem_width;
200 struct smu_clock_info {
201 uint32_t min_mem_clk;
202 uint32_t max_mem_clk;
203 uint32_t min_eng_clk;
204 uint32_t max_eng_clk;
205 uint32_t min_bus_bandwidth;
206 uint32_t max_bus_bandwidth;
209 struct smu_bios_boot_up_values
224 uint32_t pp_table_id;
225 uint32_t format_revision;
226 uint32_t content_revision;
232 SMU_TABLE_PPTABLE = 0,
233 SMU_TABLE_WATERMARKS,
234 SMU_TABLE_CUSTOM_DPM,
237 SMU_TABLE_AVFS_PSM_DEBUG,
238 SMU_TABLE_AVFS_FUSE_OVERRIDE,
239 SMU_TABLE_PMSTATUSLOG,
240 SMU_TABLE_SMU_METRICS,
241 SMU_TABLE_DRIVER_SMU_CONFIG,
242 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
244 SMU_TABLE_I2C_COMMANDS,
249 struct smu_table_context
251 void *power_play_table;
252 uint32_t power_play_table_size;
253 void *hardcode_pptable;
254 unsigned long metrics_time;
258 void *max_sustainable_clocks;
259 struct smu_bios_boot_up_values boot_values;
260 void *driver_pptable;
261 struct smu_table *tables;
262 struct smu_table memory_pool;
263 uint8_t thermal_controller_type;
265 void *overdrive_table;
268 struct smu_dpm_context {
269 uint32_t dpm_context_size;
271 void *golden_dpm_context;
272 bool enable_umd_pstate;
273 enum amd_dpm_forced_level dpm_level;
274 enum amd_dpm_forced_level saved_dpm_level;
275 enum amd_dpm_forced_level requested_dpm_level;
276 struct smu_power_state *dpm_request_power_state;
277 struct smu_power_state *dpm_current_power_state;
278 struct mclock_latency_table *mclk_latency_table;
281 struct smu_power_gate {
287 struct smu_power_context {
289 uint32_t power_context_size;
290 struct smu_power_gate power_gate;
294 #define SMU_FEATURE_MAX (64)
297 uint32_t feature_num;
298 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
299 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
300 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
305 uint32_t engine_clock;
306 uint32_t memory_clock;
307 uint32_t bus_bandwidth;
308 uint32_t engine_clock_in_sr;
310 uint32_t dcef_clock_in_sr;
313 #define MAX_REGULAR_DPM_NUM 16
314 struct mclk_latency_entries {
318 struct mclock_latency_table {
320 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
332 SMU_BACO_STATE_ENTER = 0,
336 struct smu_baco_context
340 bool platform_support;
343 #define WORKLOAD_POLICY_MAX 7
346 struct amdgpu_device *adev;
347 struct amdgpu_irq_src *irq_source;
349 const struct pptable_funcs *ppt_funcs;
351 struct mutex sensor_lock;
354 struct smu_table_context smu_table;
355 struct smu_dpm_context smu_dpm;
356 struct smu_power_context smu_power;
357 struct smu_feature smu_feature;
358 struct amd_pp_display_configuration *display_config;
359 struct smu_baco_context smu_baco;
362 uint32_t pstate_sclk;
363 uint32_t pstate_mclk;
366 uint32_t power_limit;
367 uint32_t default_power_limit;
370 uint32_t ppt_offset_bytes;
371 uint32_t ppt_size_bytes;
372 uint8_t *ppt_start_addr;
374 bool support_power_containment;
375 bool disable_watermark;
377 #define WATERMARKS_EXIST (1 << 0)
378 #define WATERMARKS_LOADED (1 << 1)
379 uint32_t watermarks_bitmap;
380 uint32_t hard_min_uclk_req_from_dal;
381 bool disable_uclk_switch;
383 uint32_t workload_mask;
384 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
385 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
386 uint32_t power_profile_mode;
387 uint32_t default_power_profile_mode;
391 uint32_t smc_if_version;
393 bool uploading_custom_pp_table;
398 struct pptable_funcs {
399 int (*alloc_dpm_context)(struct smu_context *smu);
400 int (*store_powerplay_table)(struct smu_context *smu);
401 int (*check_powerplay_table)(struct smu_context *smu);
402 int (*append_powerplay_table)(struct smu_context *smu);
403 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
404 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
405 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
406 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
407 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
408 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
409 int (*run_btc)(struct smu_context *smu);
410 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
411 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
412 int (*set_default_dpm_table)(struct smu_context *smu);
413 int (*set_power_state)(struct smu_context *smu);
414 int (*populate_umd_state_clk)(struct smu_context *smu);
415 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
416 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
417 int (*set_default_od8_settings)(struct smu_context *smu);
418 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
419 int (*set_od_percentage)(struct smu_context *smu,
420 enum smu_clk_type clk_type,
422 int (*od_edit_dpm_table)(struct smu_context *smu,
423 enum PP_OD_DPM_TABLE_COMMAND type,
424 long *input, uint32_t size);
425 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
426 enum smu_clk_type clk_type,
428 pp_clock_levels_with_latency
430 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
431 enum amd_pp_clock_type type,
433 pp_clock_levels_with_voltage
435 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
436 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
437 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
438 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
439 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
440 void *data, uint32_t *size);
441 int (*pre_display_config_changed)(struct smu_context *smu);
442 int (*display_config_changed)(struct smu_context *smu);
443 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
444 int (*notify_smc_dispaly_config)(struct smu_context *smu);
445 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
446 int (*unforce_dpm_levels)(struct smu_context *smu);
447 int (*get_profiling_clk_mask)(struct smu_context *smu,
448 enum amd_dpm_forced_level level,
452 int (*set_cpu_power_state)(struct smu_context *smu);
453 bool (*is_dpm_running)(struct smu_context *smu);
454 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
455 int (*set_thermal_fan_table)(struct smu_context *smu);
456 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
457 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
458 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
459 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
460 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
461 enum smu_clk_type clk_type,
463 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
464 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
465 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
466 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
467 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
468 void (*dump_pptable)(struct smu_context *smu);
469 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
470 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
471 uint32_t dpm_level, uint32_t *freq);
472 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
473 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
474 int (*i2c_eeprom_init)(struct i2c_adapter *control);
475 void (*i2c_eeprom_fini)(struct i2c_adapter *control);
476 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
477 int (*init_microcode)(struct smu_context *smu);
478 int (*load_microcode)(struct smu_context *smu);
479 int (*init_smc_tables)(struct smu_context *smu);
480 int (*fini_smc_tables)(struct smu_context *smu);
481 int (*init_power)(struct smu_context *smu);
482 int (*fini_power)(struct smu_context *smu);
483 int (*check_fw_status)(struct smu_context *smu);
484 int (*setup_pptable)(struct smu_context *smu);
485 int (*get_vbios_bootup_values)(struct smu_context *smu);
486 int (*get_clk_info_from_vbios)(struct smu_context *smu);
487 int (*check_pptable)(struct smu_context *smu);
488 int (*parse_pptable)(struct smu_context *smu);
489 int (*populate_smc_tables)(struct smu_context *smu);
490 int (*check_fw_version)(struct smu_context *smu);
491 int (*powergate_sdma)(struct smu_context *smu, bool gate);
492 int (*powergate_vcn)(struct smu_context *smu, bool gate);
493 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
494 int (*write_pptable)(struct smu_context *smu);
495 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
496 int (*set_tool_table_location)(struct smu_context *smu);
497 int (*notify_memory_pool_location)(struct smu_context *smu);
498 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
499 int (*system_features_control)(struct smu_context *smu, bool en);
500 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
501 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
502 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
503 int (*init_display_count)(struct smu_context *smu, uint32_t count);
504 int (*set_allowed_mask)(struct smu_context *smu);
505 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
506 int (*notify_display_change)(struct smu_context *smu);
507 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
508 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
509 int (*init_max_sustainable_clocks)(struct smu_context *smu);
510 int (*start_thermal_control)(struct smu_context *smu);
511 int (*stop_thermal_control)(struct smu_context *smu);
512 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
513 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
514 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
515 bool cc6_disable, bool pstate_disable,
516 bool pstate_switch_disable);
517 int (*get_clock_by_type)(struct smu_context *smu,
518 enum amd_pp_clock_type type,
519 struct amd_pp_clocks *clocks);
520 int (*get_max_high_clocks)(struct smu_context *smu,
521 struct amd_pp_simple_clock_info *clocks);
522 int (*display_clock_voltage_request)(struct smu_context *smu, struct
523 pp_display_clock_request
525 int (*get_dal_power_level)(struct smu_context *smu,
526 struct amd_pp_simple_clock_info *clocks);
527 int (*get_perf_level)(struct smu_context *smu,
528 enum smu_perf_level_designation designation,
529 struct smu_performance_level *level);
530 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
531 struct smu_clock_info *clocks);
532 int (*notify_smu_enable_pwe)(struct smu_context *smu);
533 int (*conv_power_profile_to_pplib_workload)(int power_profile);
534 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
535 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
536 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
537 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
538 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
539 int (*gfx_off_control)(struct smu_context *smu, bool enable);
540 int (*register_irq_handler)(struct smu_context *smu);
541 int (*set_azalia_d3_pme)(struct smu_context *smu);
542 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
543 bool (*baco_is_support)(struct smu_context *smu);
544 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
545 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
546 int (*baco_reset)(struct smu_context *smu);
547 int (*mode2_reset)(struct smu_context *smu);
548 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
549 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
550 int (*override_pcie_parameters)(struct smu_context *smu);
551 uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
554 int smu_load_microcode(struct smu_context *smu);
556 int smu_check_fw_status(struct smu_context *smu);
558 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
560 #define smu_i2c_eeprom_init(smu, control) \
561 ((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL)
562 #define smu_i2c_eeprom_fini(smu, control) \
563 ((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL)
565 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
567 int smu_get_power_limit(struct smu_context *smu,
572 int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
573 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
574 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
575 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
577 int smu_od_edit_dpm_table(struct smu_context *smu,
578 enum PP_OD_DPM_TABLE_COMMAND type,
579 long *input, uint32_t size);
581 int smu_read_sensor(struct smu_context *smu,
582 enum amd_pp_sensors sensor,
583 void *data, uint32_t *size);
584 int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
586 int smu_set_power_profile_mode(struct smu_context *smu,
590 int smu_get_fan_control_mode(struct smu_context *smu);
591 int smu_set_fan_control_mode(struct smu_context *smu, int value);
592 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
593 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
594 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
596 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
597 int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
599 int smu_get_clock_by_type(struct smu_context *smu,
600 enum amd_pp_clock_type type,
601 struct amd_pp_clocks *clocks);
603 int smu_get_max_high_clocks(struct smu_context *smu,
604 struct amd_pp_simple_clock_info *clocks);
606 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
607 enum smu_clk_type clk_type,
608 struct pp_clock_levels_with_latency *clocks);
610 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
611 enum amd_pp_clock_type type,
612 struct pp_clock_levels_with_voltage *clocks);
614 int smu_display_clock_voltage_request(struct smu_context *smu,
615 struct pp_display_clock_request *clock_req);
616 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
617 int smu_notify_smu_enable_pwe(struct smu_context *smu);
619 int smu_set_xgmi_pstate(struct smu_context *smu,
622 int smu_set_azalia_d3_pme(struct smu_context *smu);
624 bool smu_baco_is_support(struct smu_context *smu);
626 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
628 int smu_baco_reset(struct smu_context *smu);
630 int smu_mode2_reset(struct smu_context *smu);
632 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
633 uint16_t *size, uint8_t *frev, uint8_t *crev,
636 extern const struct amd_ip_funcs smu_ip_funcs;
638 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
639 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
641 extern int smu_feature_init_dpm(struct smu_context *smu);
643 extern int smu_feature_is_enabled(struct smu_context *smu,
644 enum smu_feature_mask mask);
645 extern int smu_feature_set_enabled(struct smu_context *smu,
646 enum smu_feature_mask mask, bool enable);
647 extern int smu_feature_is_supported(struct smu_context *smu,
648 enum smu_feature_mask mask);
649 extern int smu_feature_set_supported(struct smu_context *smu,
650 enum smu_feature_mask mask, bool enable);
652 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
653 void *table_data, bool drv2smu);
655 bool is_support_sw_smu(struct amdgpu_device *adev);
656 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
657 int smu_reset(struct smu_context *smu);
658 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
659 void *data, uint32_t *size);
660 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
661 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
662 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
663 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
664 int smu_write_watermarks_table(struct smu_context *smu);
665 int smu_set_watermarks_for_clock_ranges(
666 struct smu_context *smu,
667 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
669 /* smu to display interface */
670 extern int smu_display_configuration_change(struct smu_context *smu, const
671 struct amd_pp_display_configuration
673 extern int smu_get_current_clocks(struct smu_context *smu,
674 struct amd_pp_clock_info *clocks);
675 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
676 extern int smu_handle_task(struct smu_context *smu,
677 enum amd_dpm_forced_level level,
678 enum amd_pp_task task_id,
680 int smu_switch_power_profile(struct smu_context *smu,
681 enum PP_SMC_POWER_PROFILE type,
683 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
684 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
685 uint16_t level, uint32_t *value);
686 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
688 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
689 uint32_t *min, uint32_t *max, bool lock_needed);
690 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
691 uint32_t min, uint32_t max);
692 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
693 uint32_t min, uint32_t max);
694 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
695 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
696 int smu_set_display_count(struct smu_context *smu, uint32_t count);
697 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
698 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
699 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
700 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
701 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
702 int smu_force_clk_levels(struct smu_context *smu,
703 enum smu_clk_type clk_type,
706 int smu_set_mp1_state(struct smu_context *smu,
707 enum pp_mp1_state mp1_state);
708 int smu_set_df_cstate(struct smu_context *smu,
709 enum pp_df_cstate state);
711 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
712 struct pp_smu_nv_clock_table *max_clocks);
714 int smu_get_uclk_dpm_states(struct smu_context *smu,
715 unsigned int *clock_values_in_khz,
716 unsigned int *num_states);
718 int smu_get_dpm_clock_table(struct smu_context *smu,
719 struct dpm_clocks *clock_table);
721 uint32_t smu_get_pptable_power_limit(struct smu_context *smu);