2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/seq_file.h>
27 #include "amd_powerplay.h"
28 #include "hardwaremanager.h"
29 #include "hwmgr_ppt.h"
30 #include "ppatomctrl.h"
31 #include "hwmgr_ppt.h"
32 #include "power_state.h"
33 #include "smu_helper.h"
36 struct phm_fan_speed_info;
37 struct pp_atomctrl_voltage_table;
39 #define VOLTAGE_SCALE 4
40 #define VOLTAGE_VID_OFFSET_SCALE1 625
41 #define VOLTAGE_VID_OFFSET_SCALE2 100
44 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
45 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
46 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
47 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
49 typedef enum DISPLAY_GAP DISPLAY_GAP;
59 struct vi_dpm_level dpm_level[1];
62 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0
63 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1
64 #define PCIE_PERF_REQ_GEN1 2
65 #define PCIE_PERF_REQ_GEN2 3
66 #define PCIE_PERF_REQ_GEN3 4
68 enum PHM_BackEnd_Magic {
69 PHM_Dummy_Magic = 0xAA5555AA,
70 PHM_RV770_Magic = 0xDCBAABCD,
71 PHM_Kong_Magic = 0x239478DF,
72 PHM_NIslands_Magic = 0x736C494E,
73 PHM_Sumo_Magic = 0x8339FA11,
74 PHM_SIslands_Magic = 0x369431AC,
75 PHM_Trinity_Magic = 0x96751873,
76 PHM_CIslands_Magic = 0x38AC78B0,
77 PHM_Kv_Magic = 0xDCBBABC0,
78 PHM_VIslands_Magic = 0x20130307,
79 PHM_Cz_Magic = 0x67DCBA25,
80 PHM_Rv_Magic = 0x20161121
83 struct phm_set_power_state_input {
84 const struct pp_hw_power_state *pcurrent_state;
85 const struct pp_hw_power_state *pnew_state;
88 struct phm_clock_array {
93 struct phm_clock_voltage_dependency_record {
98 struct phm_vceclock_voltage_dependency_record {
104 struct phm_uvdclock_voltage_dependency_record {
110 struct phm_samuclock_voltage_dependency_record {
115 struct phm_acpclock_voltage_dependency_record {
120 struct phm_clock_voltage_dependency_table {
121 uint32_t count; /* Number of entries. */
122 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
125 struct phm_phase_shedding_limits_record {
131 struct phm_uvd_clock_voltage_dependency_record {
137 struct phm_uvd_clock_voltage_dependency_table {
139 struct phm_uvd_clock_voltage_dependency_record entries[1];
142 struct phm_acp_clock_voltage_dependency_record {
147 struct phm_acp_clock_voltage_dependency_table {
149 struct phm_acp_clock_voltage_dependency_record entries[1];
152 struct phm_vce_clock_voltage_dependency_record {
158 struct phm_phase_shedding_limits_table {
160 struct phm_phase_shedding_limits_record entries[1];
163 struct phm_vceclock_voltage_dependency_table {
164 uint8_t count; /* Number of entries. */
165 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
168 struct phm_uvdclock_voltage_dependency_table {
169 uint8_t count; /* Number of entries. */
170 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
173 struct phm_samuclock_voltage_dependency_table {
174 uint8_t count; /* Number of entries. */
175 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
178 struct phm_acpclock_voltage_dependency_table {
179 uint32_t count; /* Number of entries. */
180 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
183 struct phm_vce_clock_voltage_dependency_table {
185 struct phm_vce_clock_voltage_dependency_record entries[1];
188 struct pp_smumgr_func {
189 int (*smu_init)(struct pp_hwmgr *hwmgr);
190 int (*smu_fini)(struct pp_hwmgr *hwmgr);
191 int (*start_smu)(struct pp_hwmgr *hwmgr);
192 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
194 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
195 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
197 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
198 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
199 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
200 uint16_t msg, uint32_t parameter);
201 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
203 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
204 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
205 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
206 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
207 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
208 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
209 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
210 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
211 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
212 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
213 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
214 uint32_t (*get_mac_definition)(uint32_t value);
215 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
216 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
217 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
218 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
221 struct pp_hwmgr_func {
222 int (*backend_init)(struct pp_hwmgr *hw_mgr);
223 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
224 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
225 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
227 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
228 struct pp_power_state *prequest_ps,
229 const struct pp_power_state *pcurrent_ps);
231 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
233 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
234 enum amd_dpm_forced_level level);
236 int (*dynamic_state_management_enable)(
237 struct pp_hwmgr *hw_mgr);
238 int (*dynamic_state_management_disable)(
239 struct pp_hwmgr *hw_mgr);
241 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
242 struct pp_hw_power_state *hw_ps);
244 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
245 unsigned long, struct pp_power_state *);
246 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
247 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
248 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
249 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
250 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
251 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
252 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
253 int (*power_state_set)(struct pp_hwmgr *hwmgr,
255 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
256 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
257 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
258 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
259 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
260 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
261 const uint32_t *msg_id);
262 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
263 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
264 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
265 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
266 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
267 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
268 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
269 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
270 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
271 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
272 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
273 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
274 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
275 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
276 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
277 const struct pp_hw_power_state *pstate1,
278 const struct pp_hw_power_state *pstate2,
280 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
281 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
282 bool cc6_disable, bool pstate_disable,
283 bool pstate_switch_disable);
284 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
285 struct amd_pp_simple_clock_info *info);
286 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
287 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
288 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
289 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
290 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
291 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
292 enum amd_pp_clock_type type,
293 struct pp_clock_levels_with_latency *clocks);
294 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
295 enum amd_pp_clock_type type,
296 struct pp_clock_levels_with_voltage *clocks);
297 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
298 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
299 struct pp_display_clock_request *clock);
300 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
301 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
302 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
303 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
304 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
305 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
306 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
307 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
308 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
309 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
310 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
311 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
312 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
313 int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
314 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
315 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
316 uint32_t virtual_addr_low,
317 uint32_t virtual_addr_hi,
318 uint32_t mc_addr_low,
321 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
322 struct PP_TemperatureRange *range);
323 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
324 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
325 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
326 enum PP_OD_DPM_TABLE_COMMAND type,
327 long *input, uint32_t size);
328 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
329 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
330 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
331 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
334 struct pp_table_func {
335 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
336 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
337 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
338 int (*pptable_get_vce_state_table_entry)(
339 struct pp_hwmgr *hwmgr,
341 struct amd_vce_state *vce_state,
343 unsigned long *flag);
346 union phm_cac_leakage_record {
348 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
349 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
358 struct phm_cac_leakage_table {
360 union phm_cac_leakage_record entries[1];
363 struct phm_samu_clock_voltage_dependency_record {
369 struct phm_samu_clock_voltage_dependency_table {
371 struct phm_samu_clock_voltage_dependency_record entries[1];
374 struct phm_cac_tdp_table {
376 uint16_t usConfigurableTDP;
378 uint16_t usBatteryPowerLimit;
379 uint16_t usSmallPowerLimit;
380 uint16_t usLowCACLeakage;
381 uint16_t usHighCACLeakage;
382 uint16_t usMaximumPowerDeliveryLimit;
384 uint16_t usOperatingTempMinLimit;
385 uint16_t usOperatingTempMaxLimit;
386 uint16_t usOperatingTempStep;
387 uint16_t usOperatingTempHyst;
388 uint16_t usDefaultTargetOperatingTemp;
389 uint16_t usTargetOperatingTemp;
390 uint16_t usPowerTuneDataSetID;
391 uint16_t usSoftwareShutdownTemp;
392 uint16_t usClockStretchAmount;
393 uint16_t usTemperatureLimitHotspot;
394 uint16_t usTemperatureLimitLiquid1;
395 uint16_t usTemperatureLimitLiquid2;
396 uint16_t usTemperatureLimitVrVddc;
397 uint16_t usTemperatureLimitVrMvdd;
398 uint16_t usTemperatureLimitPlx;
399 uint8_t ucLiquid1_I2C_address;
400 uint8_t ucLiquid2_I2C_address;
401 uint8_t ucLiquid_I2C_Line;
402 uint8_t ucVr_I2C_address;
403 uint8_t ucVr_I2C_Line;
404 uint8_t ucPlx_I2C_address;
405 uint8_t ucPlx_I2C_Line;
406 uint32_t usBoostPowerLimit;
407 uint8_t ucCKS_LDO_REFSEL;
410 struct phm_tdp_table {
412 uint16_t usConfigurableTDP;
414 uint16_t usBatteryPowerLimit;
415 uint16_t usSmallPowerLimit;
416 uint16_t usLowCACLeakage;
417 uint16_t usHighCACLeakage;
418 uint16_t usMaximumPowerDeliveryLimit;
420 uint16_t usOperatingTempMinLimit;
421 uint16_t usOperatingTempMaxLimit;
422 uint16_t usOperatingTempStep;
423 uint16_t usOperatingTempHyst;
424 uint16_t usDefaultTargetOperatingTemp;
425 uint16_t usTargetOperatingTemp;
426 uint16_t usPowerTuneDataSetID;
427 uint16_t usSoftwareShutdownTemp;
428 uint16_t usClockStretchAmount;
429 uint16_t usTemperatureLimitTedge;
430 uint16_t usTemperatureLimitHotspot;
431 uint16_t usTemperatureLimitLiquid1;
432 uint16_t usTemperatureLimitLiquid2;
433 uint16_t usTemperatureLimitHBM;
434 uint16_t usTemperatureLimitVrVddc;
435 uint16_t usTemperatureLimitVrMvdd;
436 uint16_t usTemperatureLimitPlx;
437 uint8_t ucLiquid1_I2C_address;
438 uint8_t ucLiquid2_I2C_address;
439 uint8_t ucLiquid_I2C_Line;
440 uint8_t ucVr_I2C_address;
441 uint8_t ucVr_I2C_Line;
442 uint8_t ucPlx_I2C_address;
443 uint8_t ucPlx_I2C_Line;
444 uint8_t ucLiquid_I2C_LineSDA;
445 uint8_t ucVr_I2C_LineSDA;
446 uint8_t ucPlx_I2C_LineSDA;
447 uint32_t usBoostPowerLimit;
448 uint16_t usBoostStartTemperature;
449 uint16_t usBoostStopTemperature;
450 uint32_t ulBoostClock;
453 struct phm_ppm_table {
455 uint16_t cpu_core_number;
456 uint32_t platform_tdp;
457 uint32_t small_ac_platform_tdp;
458 uint32_t platform_tdc;
459 uint32_t small_ac_platform_tdc;
462 uint32_t dgpu_ulv_power;
466 struct phm_vq_budgeting_record {
468 uint32_t ulSustainableSOCPowerLimitLow;
469 uint32_t ulSustainableSOCPowerLimitHigh;
470 uint32_t ulMinSclkLow;
471 uint32_t ulMinSclkHigh;
472 uint8_t ucDispConfig;
475 uint32_t ulSustainableSclk;
476 uint32_t ulSustainableCUs;
479 struct phm_vq_budgeting_table {
481 struct phm_vq_budgeting_record entries[1];
484 struct phm_clock_and_voltage_limits {
494 /* Structure to hold PPTable information */
496 struct phm_ppt_v1_information {
497 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
498 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
499 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
500 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
501 struct phm_clock_array *valid_sclk_values;
502 struct phm_clock_array *valid_mclk_values;
503 struct phm_clock_array *valid_socclk_values;
504 struct phm_clock_array *valid_dcefclk_values;
505 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
506 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
507 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
508 struct phm_ppm_table *ppm_parameter_table;
509 struct phm_cac_tdp_table *cac_dtp_table;
510 struct phm_tdp_table *tdp_table;
511 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
512 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
513 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
514 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
515 struct phm_ppt_v1_pcie_table *pcie_table;
516 struct phm_ppt_v1_gpio_table *gpio_table;
517 uint16_t us_ulv_voltage_offset;
518 uint16_t us_ulv_smnclk_did;
519 uint16_t us_ulv_mp1clk_did;
520 uint16_t us_ulv_gfxclk_bypass;
521 uint16_t us_gfxclk_slew_rate;
522 uint16_t us_min_gfxclk_freq_limit;
525 struct phm_ppt_v2_information {
526 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
527 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
528 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
529 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
530 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
531 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
532 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
533 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
535 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
537 struct phm_clock_array *valid_sclk_values;
538 struct phm_clock_array *valid_mclk_values;
539 struct phm_clock_array *valid_socclk_values;
540 struct phm_clock_array *valid_dcefclk_values;
542 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
543 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
545 struct phm_ppm_table *ppm_parameter_table;
546 struct phm_cac_tdp_table *cac_dtp_table;
547 struct phm_tdp_table *tdp_table;
549 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
550 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
551 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
552 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
554 struct phm_ppt_v1_pcie_table *pcie_table;
556 uint16_t us_ulv_voltage_offset;
557 uint16_t us_ulv_smnclk_did;
558 uint16_t us_ulv_mp1clk_did;
559 uint16_t us_ulv_gfxclk_bypass;
560 uint16_t us_gfxclk_slew_rate;
561 uint16_t us_min_gfxclk_freq_limit;
563 uint8_t uc_gfx_dpm_voltage_mode;
564 uint8_t uc_soc_dpm_voltage_mode;
565 uint8_t uc_uclk_dpm_voltage_mode;
566 uint8_t uc_uvd_dpm_voltage_mode;
567 uint8_t uc_vce_dpm_voltage_mode;
568 uint8_t uc_mp0_dpm_voltage_mode;
569 uint8_t uc_dcef_dpm_voltage_mode;
572 struct phm_ppt_v3_information
574 uint8_t uc_thermal_controller_type;
576 uint16_t us_small_power_limit1;
577 uint16_t us_small_power_limit2;
578 uint16_t us_boost_power_limit;
580 uint16_t us_od_turbo_power_limit;
581 uint16_t us_od_powersave_power_limit;
582 uint16_t us_software_shutdown_temp;
584 uint32_t *power_saving_clock_max;
585 uint32_t *power_saving_clock_min;
587 uint8_t *od_feature_capabilities;
588 uint32_t *od_settings_max;
589 uint32_t *od_settings_min;
594 struct phm_dynamic_state_info {
595 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
596 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
597 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
598 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
599 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
600 struct phm_clock_array *valid_sclk_values;
601 struct phm_clock_array *valid_mclk_values;
602 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
603 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
604 uint32_t mclk_sclk_ratio;
605 uint32_t sclk_mclk_delta;
606 uint32_t vddc_vddci_delta;
607 uint32_t min_vddc_for_pcie_gen2;
608 struct phm_cac_leakage_table *cac_leakage_table;
609 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
611 struct phm_vce_clock_voltage_dependency_table
612 *vce_clock_voltage_dependency_table;
613 struct phm_uvd_clock_voltage_dependency_table
614 *uvd_clock_voltage_dependency_table;
615 struct phm_acp_clock_voltage_dependency_table
616 *acp_clock_voltage_dependency_table;
617 struct phm_samu_clock_voltage_dependency_table
618 *samu_clock_voltage_dependency_table;
620 struct phm_ppm_table *ppm_parameter_table;
621 struct phm_cac_tdp_table *cac_dtp_table;
622 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
627 uint8_t ucTachometerPulsesPerRevolution;
632 struct pp_advance_fan_control_parameters {
633 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
634 uint16_t usTMed; /* The middle temperature where we change slopes. */
635 uint16_t usTHigh; /* The high temperature for setting the second slope. */
636 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
637 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
638 uint16_t usPWMHigh; /* The PWM value at THigh. */
639 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
640 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
641 uint16_t usTMax; /* The max temperature */
642 uint8_t ucFanControlMode;
643 uint16_t usFanPWMMinLimit;
644 uint16_t usFanPWMMaxLimit;
645 uint16_t usFanPWMStep;
646 uint16_t usDefaultMaxFanPWM;
647 uint16_t usFanOutputSensitivity;
648 uint16_t usDefaultFanOutputSensitivity;
649 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
650 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
651 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
652 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
653 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
654 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
655 uint16_t usFanCurrentLow; /* Low current */
656 uint16_t usFanCurrentHigh; /* High current */
657 uint16_t usFanRPMLow; /* Low RPM */
658 uint16_t usFanRPMHigh; /* High RPM */
659 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
660 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
661 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
662 uint16_t usFanGainEdge; /* The following is added for Fiji */
663 uint16_t usFanGainHotspot;
664 uint16_t usFanGainLiquid;
665 uint16_t usFanGainVrVddc;
666 uint16_t usFanGainVrMvdd;
667 uint16_t usFanGainPlx;
668 uint16_t usFanGainHbm;
669 uint8_t ucEnableZeroRPM;
670 uint8_t ucFanStopTemperature;
671 uint8_t ucFanStartTemperature;
672 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
673 uint32_t ulTargetGfxClk;
674 uint16_t usZeroRPMStartTemperature;
675 uint16_t usZeroRPMStopTemperature;
678 struct pp_thermal_controller_info {
681 uint8_t ucI2cAddress;
682 struct pp_fan_info fanInfo;
683 struct pp_advance_fan_control_parameters advanceFanControlParameters;
686 struct phm_microcode_version_info {
693 enum PP_TABLE_VERSION {
701 * The main hardware manager structure.
703 #define Workload_Policy_Max 5
707 uint32_t chip_family;
709 uint32_t smu_version;
712 struct mutex smu_lock;
714 uint32_t pp_table_version;
716 struct pp_smumgr *smumgr;
717 const void *soft_pp_table;
718 uint32_t soft_pp_table_size;
719 void *hardcode_pp_table;
720 bool need_pp_table_upload;
722 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
723 uint32_t num_vce_state_tables;
725 enum amd_dpm_forced_level dpm_level;
726 enum amd_dpm_forced_level saved_dpm_level;
727 enum amd_dpm_forced_level request_dpm_level;
728 uint32_t usec_timeout;
730 struct phm_platform_descriptor platform_descriptor;
734 const struct pp_smumgr_func *smumgr_funcs;
738 enum PP_DAL_POWERLEVEL dal_power_level;
739 struct phm_dynamic_state_info dyn_state;
740 const struct pp_hwmgr_func *hwmgr_func;
741 const struct pp_table_func *pptable_func;
743 struct pp_power_state *ps;
745 struct pp_thermal_controller_info thermal_controller;
746 bool fan_ctrl_is_in_default_mode;
747 uint32_t fan_ctrl_default_mode;
748 bool fan_ctrl_enabled;
750 struct phm_microcode_version_info microcode_version_info;
752 struct pp_power_state *current_ps;
753 struct pp_power_state *request_ps;
754 struct pp_power_state *boot_ps;
755 struct pp_power_state *uvd_ps;
756 const struct amd_pp_display_configuration *display_config;
757 uint32_t feature_mask;
761 uint32_t power_profile_mode;
762 uint32_t default_power_profile_mode;
763 uint32_t pstate_sclk;
764 uint32_t pstate_mclk;
766 uint32_t power_limit;
767 uint32_t default_power_limit;
768 uint32_t workload_mask;
769 uint32_t workload_prority[Workload_Policy_Max];
770 uint32_t workload_setting[Workload_Policy_Max];
773 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
774 int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
775 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
776 int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
777 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
778 int hwmgr_suspend(struct pp_hwmgr *hwmgr);
779 int hwmgr_resume(struct pp_hwmgr *hwmgr);
781 int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
782 enum amd_pp_task task_id,
783 enum amd_pm_state_type *user_state);
786 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
789 #endif /* _HWMGR_H_ */