2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU11_DRIVER_IF_ARCTURUS_H
25 #define SMU11_DRIVER_IF_ARCTURUS_H
28 // SMU TEAM: Always increment the interface version if
29 // any structure is changed in this file
30 //#define SMU11_DRIVER_IF_VERSION 0x08
32 #define PPTABLE_ARCTURUS_SMU_VERSION 4
34 #define NUM_GFXCLK_DPM_LEVELS 16
35 #define NUM_VCLK_DPM_LEVELS 8
36 #define NUM_DCLK_DPM_LEVELS 8
37 #define NUM_MP0CLK_DPM_LEVELS 2
38 #define NUM_SOCCLK_DPM_LEVELS 8
39 #define NUM_UCLK_DPM_LEVELS 4
40 #define NUM_FCLK_DPM_LEVELS 8
41 #define NUM_XGMI_LEVELS 2
42 #define NUM_XGMI_PSTATE_LEVELS 4
44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
54 // Feature Control Defines
56 #define FEATURE_DPM_PREFETCHER_BIT 0
57 #define FEATURE_DPM_GFXCLK_BIT 1
58 #define FEATURE_DPM_UCLK_BIT 2
59 #define FEATURE_DPM_SOCCLK_BIT 3
60 #define FEATURE_DPM_FCLK_BIT 4
61 #define FEATURE_DPM_MP0CLK_BIT 5
62 #define FEATURE_DPM_XGMI_BIT 6
64 #define FEATURE_DS_GFXCLK_BIT 7
65 #define FEATURE_DS_SOCCLK_BIT 8
66 #define FEATURE_DS_LCLK_BIT 9
67 #define FEATURE_DS_FCLK_BIT 10
68 #define FEATURE_DS_UCLK_BIT 11
69 #define FEATURE_GFX_ULV_BIT 12
70 #define FEATURE_DPM_VCN_BIT 13
71 #define FEATURE_RSMU_SMN_CG_BIT 14
72 #define FEATURE_WAFL_CG_BIT 15
74 #define FEATURE_PPT_BIT 16
75 #define FEATURE_TDC_BIT 17
76 #define FEATURE_APCC_PLUS_BIT 18
77 #define FEATURE_VR0HOT_BIT 19
78 #define FEATURE_VR1HOT_BIT 20
79 #define FEATURE_FW_CTF_BIT 21
80 #define FEATURE_FAN_CONTROL_BIT 22
81 #define FEATURE_THERMAL_BIT 23
83 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 24
84 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25
86 #define FEATURE_SPARE_26_BIT 26
87 #define FEATURE_SPARE_27_BIT 27
88 #define FEATURE_SPARE_28_BIT 28
89 #define FEATURE_SPARE_29_BIT 29
90 #define FEATURE_SPARE_30_BIT 30
91 #define FEATURE_SPARE_31_BIT 31
92 #define FEATURE_SPARE_32_BIT 32
93 #define FEATURE_SPARE_33_BIT 33
94 #define FEATURE_SPARE_34_BIT 34
95 #define FEATURE_SPARE_35_BIT 35
96 #define FEATURE_SPARE_36_BIT 36
97 #define FEATURE_SPARE_37_BIT 37
98 #define FEATURE_SPARE_38_BIT 38
99 #define FEATURE_SPARE_39_BIT 39
100 #define FEATURE_SPARE_40_BIT 40
101 #define FEATURE_SPARE_41_BIT 41
102 #define FEATURE_SPARE_42_BIT 42
103 #define FEATURE_SPARE_43_BIT 43
104 #define FEATURE_SPARE_44_BIT 44
105 #define FEATURE_SPARE_45_BIT 45
106 #define FEATURE_SPARE_46_BIT 46
107 #define FEATURE_SPARE_47_BIT 47
108 #define FEATURE_SPARE_48_BIT 48
109 #define FEATURE_SPARE_49_BIT 49
110 #define FEATURE_SPARE_50_BIT 50
111 #define FEATURE_SPARE_51_BIT 51
112 #define FEATURE_SPARE_52_BIT 52
113 #define FEATURE_SPARE_53_BIT 53
114 #define FEATURE_SPARE_54_BIT 54
115 #define FEATURE_SPARE_55_BIT 55
116 #define FEATURE_SPARE_56_BIT 56
117 #define FEATURE_SPARE_57_BIT 57
118 #define FEATURE_SPARE_58_BIT 58
119 #define FEATURE_SPARE_59_BIT 59
120 #define FEATURE_SPARE_60_BIT 60
121 #define FEATURE_SPARE_61_BIT 61
122 #define FEATURE_SPARE_62_BIT 62
123 #define FEATURE_SPARE_63_BIT 63
125 #define NUM_FEATURES 64
128 #define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
129 #define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
130 #define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
131 #define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
132 #define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT )
133 #define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
134 #define FEATURE_DPM_XGMI_MASK (1 << FEATURE_DPM_XGMI_BIT )
136 #define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
137 #define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
138 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
139 #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
140 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
141 #define FEATURE_GFX_ULV_MASK (1 << FEATURE_GFX_ULV_BIT )
142 #define FEATURE_VCN_PG_MASK (1 << FEATURE_VCN_PG_BIT )
143 #define FEATURE_RSMU_SMN_CG_MASK (1 << FEATURE_RSMU_SMN_CG_BIT )
144 #define FEATURE_WAFL_CG_MASK (1 << FEATURE_WAFL_CG_BIT )
146 #define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
147 #define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
148 #define FEATURE_APCC_MASK (1 << FEATURE_APCC_BIT )
149 #define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
150 #define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
151 #define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
152 #define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
153 #define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
155 #define FEATURE_OUT_OF_BAND_MONITOR_MASK (1 << EATURE_OUT_OF_BAND_MONITOR_BIT )
156 #define FEATURE_TEMP_DEPENDENT_VMIN_MASK (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK )
159 //FIXME need updating
160 // Debug Overrides Bitmask
161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001
162 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK 0x00000002
164 // I2C Config Bit Defines
165 #define I2C_CONTROLLER_ENABLED 1
166 #define I2C_CONTROLLER_DISABLED 0
168 // VR Mapping Bit Defines
169 #define VR_MAPPING_VR_SELECT_MASK 0x01
170 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
172 #define VR_MAPPING_PLANE_SELECT_MASK 0x02
173 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
176 #define PSI_SEL_VR0_PLANE0_PSI0 0x01
177 #define PSI_SEL_VR0_PLANE0_PSI1 0x02
178 #define PSI_SEL_VR0_PLANE1_PSI0 0x04
179 #define PSI_SEL_VR0_PLANE1_PSI1 0x08
180 #define PSI_SEL_VR1_PLANE0_PSI0 0x10
181 #define PSI_SEL_VR1_PLANE0_PSI1 0x20
182 #define PSI_SEL_VR1_PLANE1_PSI0 0x40
183 #define PSI_SEL_VR1_PLANE1_PSI1 0x80
185 // Throttler Control/Status Bits
186 #define THROTTLER_PADDING_BIT 0
187 #define THROTTLER_TEMP_EDGE_BIT 1
188 #define THROTTLER_TEMP_HOTSPOT_BIT 2
189 #define THROTTLER_TEMP_MEM_BIT 3
190 #define THROTTLER_TEMP_VR_GFX_BIT 4
191 #define THROTTLER_TEMP_VR_MEM_BIT 5
192 #define THROTTLER_TEMP_VR_SOC_BIT 6
193 #define THROTTLER_TDC_GFX_BIT 7
194 #define THROTTLER_TDC_SOC_BIT 8
195 #define THROTTLER_PPT0_BIT 9
196 #define THROTTLER_PPT1_BIT 10
197 #define THROTTLER_PPT2_BIT 11
198 #define THROTTLER_PPT3_BIT 12
199 #define THROTTLER_PPM_BIT 13
200 #define THROTTLER_FIT_BIT 14
201 #define THROTTLER_APCC_BIT 15
203 // Table transfer status
204 #define TABLE_TRANSFER_OK 0x0
205 #define TABLE_TRANSFER_FAILED 0xFF
206 #define TABLE_TRANSFER_PENDING 0xAB
209 #define WORKLOAD_PPLIB_DEFAULT_BIT 0
210 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 1
211 #define WORKLOAD_PPLIB_VIDEO_BIT 2
212 #define WORKLOAD_PPLIB_COMPUTE_BIT 3
213 #define WORKLOAD_PPLIB_CUSTOM_BIT 4
214 #define WORKLOAD_PPLIB_COUNT 5
216 //XGMI performance states
217 #define XGMI_STATE_D0 1
218 #define XGMI_STATE_D3 0
220 #define NUM_I2C_CONTROLLERS 8
222 #define I2C_CONTROLLER_ENABLED 1
223 #define I2C_CONTROLLER_DISABLED 0
225 #define MAX_SW_I2C_COMMANDS 8
228 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0
229 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1
230 I2C_CONTROLLER_PORT_COUNT,
231 } I2cControllerPort_e;
234 I2C_CONTROLLER_NAME_VR_GFX = 0,
235 I2C_CONTROLLER_NAME_VR_SOC,
236 I2C_CONTROLLER_NAME_VR_MEM,
237 I2C_CONTROLLER_NAME_SPARE,
238 I2C_CONTROLLER_NAME_COUNT,
239 } I2cControllerName_e;
242 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
243 I2C_CONTROLLER_THROTTLER_VR_GFX,
244 I2C_CONTROLLER_THROTTLER_VR_SOC,
245 I2C_CONTROLLER_THROTTLER_VR_MEM,
246 I2C_CONTROLLER_THROTTLER_COUNT,
247 } I2cControllerThrottler_e;
250 I2C_CONTROLLER_PROTOCOL_VR_0,
251 I2C_CONTROLLER_PROTOCOL_VR_1,
252 I2C_CONTROLLER_PROTOCOL_TMP_0,
253 I2C_CONTROLLER_PROTOCOL_TMP_1,
254 I2C_CONTROLLER_PROTOCOL_SPARE_0,
255 I2C_CONTROLLER_PROTOCOL_SPARE_1,
256 I2C_CONTROLLER_PROTOCOL_COUNT,
257 } I2cControllerProtocol_e;
263 uint32_t SlaveAddress;
264 uint8_t ControllerPort;
265 uint8_t ControllerName;
266 uint8_t ThermalThrotter;
268 } I2cControllerConfig_t;
271 I2C_PORT_SVD_SCL = 0,
276 I2C_SPEED_FAST_50K = 0, //50 Kbits/s
277 I2C_SPEED_FAST_100K, //100 Kbits/s
278 I2C_SPEED_FAST_400K, //400 Kbits/s
279 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
280 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
281 I2C_SPEED_HIGH_2M, //2.3 Mbits/s
291 #define CMDCONFIG_STOP_BIT 0
292 #define CMDCONFIG_RESTART_BIT 1
294 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
295 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
298 uint8_t RegisterAddr; ////only valid for write, ignored for read
299 uint8_t Cmd; //Read(0) or Write(1)
300 uint8_t Data; //Return data for read. Data to send for write
301 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command
302 } SwI2cCmd_t; //SW I2C Command Table
305 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
306 uint8_t I2CSpeed; //Slow(0) or Fast(1)
307 uint16_t SlaveAddress;
308 uint8_t NumCmds; //Number of commands
311 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
313 uint32_t MmHubPadding[8]; // SMU internal use
315 } SwI2cRequest_t; // SW I2C Request Table
323 D3HOT_SEQUENCE_COUNT,
326 //THis is aligned with RSMU PGFSM Register Mapping
332 //This is aligned with RSMU PGFSM Register Mapping
336 } PowerGatingSettings_e;
339 uint32_t a; // store in IEEE float format in this variable
340 uint32_t b; // store in IEEE float format in this variable
341 uint32_t c; // store in IEEE float format in this variable
345 uint32_t m; // store in IEEE float format in this variable
346 uint32_t b; // store in IEEE float format in this variable
350 uint32_t a; // store in IEEE float format in this variable
351 uint32_t b; // store in IEEE float format in this variable
352 uint32_t c; // store in IEEE float format in this variable
356 GFXCLK_SOURCE_PLL = 0,
396 VOLTAGE_MODE_AVFS = 0,
397 VOLTAGE_MODE_AVFS_SS,
403 AVFS_VOLTAGE_GFX = 0,
406 } AVFS_VOLTAGE_TYPE_e;
409 GPIO_INT_POLARITY_ACTIVE_LOW = 0,
410 GPIO_INT_POLARITY_ACTIVE_HIGH,
414 MEMORY_TYPE_GDDR6 = 0,
421 PWR_CONFIG_TCP_ESTIMATED,
422 PWR_CONFIG_TCP_MEASURED,
426 XGMI_LINK_RATE_12 = 0, // 12Gbps
427 XGMI_LINK_RATE_16, // 16Gbps
428 XGMI_LINK_RATE_22, // 22Gbps
429 XGMI_LINK_RATE_25, // 25Gbps
434 XGMI_LINK_WIDTH_2 = 0, // x2
435 XGMI_LINK_WIDTH_4, // x4
436 XGMI_LINK_WIDTH_8, // x8
437 XGMI_LINK_WIDTH_16, // x16
438 XGMI_LINK_WIDTH_COUNT
442 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
443 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
444 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
446 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
447 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
448 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
455 // SECTION: Feature Enablement
456 uint32_t FeaturesToRun[2];
458 // SECTION: Infrastructure Limits
459 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
460 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
461 uint16_t TdcLimitSoc; // Amps
462 uint16_t TdcLimitSocTau; // Time constant of LPF in ms
463 uint16_t TdcLimitGfx; // Amps
464 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms
466 uint16_t TedgeLimit; // Celcius
467 uint16_t ThotspotLimit; // Celcius
468 uint16_t TmemLimit; // Celcius
469 uint16_t Tvr_gfxLimit; // Celcius
470 uint16_t Tvr_memLimit; // Celcius
471 uint16_t Tvr_socLimit; // Celcius
472 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
474 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold
475 uint16_t PpmTemperatureThreshold;
477 // SECTION: Throttler settings
478 uint32_t ThrottlerControlMask; // See Throtter masks defines
480 // SECTION: ULV Settings
481 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
482 uint16_t UlvPadding; // Padding
484 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV
485 uint8_t Padding234[3];
487 // SECTION: Voltage Control Parameters
488 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
489 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
490 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
491 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
493 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits
494 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits
496 //SECTION: DPM Config 1
497 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
499 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
500 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
501 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
502 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
503 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
504 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
506 uint32_t Paddingclks[16];
508 // SECTION: DPM Config 2
509 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
510 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
513 uint16_t GfxclkFidle; // In MHz
514 uint16_t GfxclkSlewRate; // for PLL babystepping???
515 uint8_t Padding567[4];
516 uint16_t GfxclkDsMaxFreq; // In MHz
517 uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL
520 // GFXCLK Thermal DPM (formerly 'Boost' Settings)
522 uint16_t TdpmHighHystTemperature;
523 uint16_t TdpmLowHystTemperature;
524 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability.
526 // SECTION: Fan Control
527 uint16_t FanStopTemp; //Celcius
528 uint16_t FanStartTemp; //Celcius
530 uint16_t FanGainEdge;
531 uint16_t FanGainHotspot;
532 uint16_t FanGainVrGfx;
533 uint16_t FanGainVrSoc;
534 uint16_t FanGainVrMem;
537 uint16_t FanAcousticLimitRpm;
538 uint16_t FanThrottlingRpm;
539 uint16_t FanMaximumRpm;
540 uint16_t FanTargetTemperature;
541 uint16_t FanTargetGfxclk;
542 uint8_t FanZeroRpmEnable;
543 uint8_t FanTachEdgePerRev;
544 uint8_t FanTempInputSelect;
545 uint8_t padding8_Fan;
547 // The following are AFC override parameters. Leave at 0 to use FW defaults.
548 int16_t FuzzyFan_ErrorSetDelta;
549 int16_t FuzzyFan_ErrorRateSetDelta;
550 int16_t FuzzyFan_PwmSetDelta;
551 uint16_t FuzzyFan_Reserved;
556 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
557 uint8_t Padding8_Avfs[2];
559 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
560 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
561 DroopInt_t dBtcGbGfxAfll; // GHz->V BtcGb
562 DroopInt_t dBtcGbSoc; // GHz->V BtcGb
563 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
565 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
567 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
569 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
570 uint8_t Padding8_GfxBtc[2];
572 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
573 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
575 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
578 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.
579 uint8_t XgmiDpmSpare[2];
581 // Temperature Dependent Vmin
582 uint16_t VDDGFX_TVmin; //Celcius
583 uint16_t VDDSOC_TVmin; //Celcius
584 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2
585 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
586 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
587 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
589 uint16_t VDDGFX_TVminHystersis; // Celcius
590 uint16_t VDDSOC_TVminHystersis; // Celcius
593 // SECTION: Advanced Options
594 uint32_t DebugOverrides;
595 QuadraticInt_t ReservedEquation0;
596 QuadraticInt_t ReservedEquation1;
597 QuadraticInt_t ReservedEquation2;
598 QuadraticInt_t ReservedEquation3;
600 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
601 uint16_t PaddingUlv; // Padding
603 // Total Power configuration, use defines from PwrConfig_e
604 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured
605 uint8_t TotalPowerSpare1;
606 uint16_t TotalPowerSpare2;
609 uint16_t PccThresholdLow;
610 uint16_t PccThresholdHigh;
611 uint32_t PaddingAPCC[6]; //FIXME pending SPEC
614 uint32_t Reserved[11];
616 // SECTION: BOARD PARAMETERS
618 // SVI2 Board Parameters
619 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
620 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
622 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
623 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
624 uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields
625 uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields
627 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
628 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
629 uint8_t Padding8_V[2];
631 // Telemetry Settings
632 uint16_t GfxMaxCurrent; // in Amps
633 int8_t GfxOffset; // in Amps
634 uint8_t Padding_TelemetryGfx;
636 uint16_t SocMaxCurrent; // in Amps
637 int8_t SocOffset; // in Amps
638 uint8_t Padding_TelemetrySoc;
640 uint16_t MemMaxCurrent; // in Amps
641 int8_t MemOffset; // in Amps
642 uint8_t Padding_TelemetryMem;
644 uint16_t BoardMaxCurrent; // in Amps
645 int8_t BoardOffset; // in Amps
646 uint8_t Padding_TelemetryBoardInput;
649 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
650 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
651 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
652 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
654 // GFXCLK PLL Spread Spectrum
655 uint8_t PllGfxclkSpreadEnabled; // on or off
656 uint8_t PllGfxclkSpreadPercent; // Q4.4
657 uint16_t PllGfxclkSpreadFreq; // kHz
659 // UCLK Spread Spectrum
660 uint8_t UclkSpreadEnabled; // on or off
661 uint8_t UclkSpreadPercent; // Q4.4
662 uint16_t UclkSpreadFreq; // kHz
664 // FCLK Spread Spectrum
665 uint8_t FclkSpreadEnabled; // on or off
666 uint8_t FclkSpreadPercent; // Q4.4
667 uint16_t FclkSpreadFreq; // kHz
669 // GFXCLK Fll Spread Spectrum
670 uint8_t FllGfxclkSpreadEnabled; // on or off
671 uint8_t FllGfxclkSpreadPercent; // Q4.4
672 uint16_t FllGfxclkSpreadFreq; // kHz
674 // I2C Controller Structure
675 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
678 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
680 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
681 uint8_t PaddingMem[3];
684 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
685 uint16_t BoardPadding;
687 // SECTION: XGMI Training
688 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
689 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
691 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
692 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
694 uint32_t BoardReserved[10];
696 // Padding for MMHUB - do not modify this
697 uint32_t MmHubPadding[8]; // SMU internal use
702 // Time constant parameters for clock averages in ms
703 uint16_t GfxclkAverageLpfTau;
704 uint16_t SocclkAverageLpfTau;
705 uint16_t UclkAverageLpfTau;
706 uint16_t GfxActivityLpfTau;
707 uint16_t UclkActivityLpfTau;
709 uint16_t SocketPowerLpfTau;
712 uint32_t MmHubPadding[8]; // SMU internal use
716 uint16_t CurrClock[PPCLK_COUNT];
717 uint16_t AverageGfxclkFrequency;
718 uint16_t AverageSocclkFrequency;
719 uint16_t AverageUclkFrequency ;
720 uint16_t AverageGfxActivity ;
721 uint16_t AverageUclkActivity ;
722 uint8_t CurrSocVoltageOffset ;
723 uint8_t CurrGfxVoltageOffset ;
724 uint8_t CurrMemVidOffset ;
726 uint16_t AverageSocketPower ;
727 uint16_t TemperatureEdge ;
728 uint16_t TemperatureHotspot ;
729 uint16_t TemperatureHBM ;
730 uint16_t TemperatureVrGfx ;
731 uint16_t TemperatureVrSoc ;
732 uint16_t TemperatureVrMem ;
733 uint32_t ThrottlerStatus ;
735 uint16_t CurrFanSpeed ;
741 uint32_t MmHubPadding[7]; // SMU internal use
746 uint16_t avgPsmCount[75];
747 uint16_t minPsmCount[75];
748 float avgPsmVoltage[75];
749 float minPsmVoltage[75];
751 uint32_t MmHubPadding[3]; // SMU internal use
757 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
759 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
760 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
762 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT];
763 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT];
764 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT];
765 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
767 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
768 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
769 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32
771 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
772 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
773 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32
775 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
776 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
777 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32
779 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
780 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
781 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32
783 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
784 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
785 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32
787 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
788 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
789 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
791 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
794 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
795 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
796 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32
798 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
800 uint32_t EnabledAvfsModules;
802 uint32_t MmHubPadding[7]; // SMU internal use
803 } AvfsFuseOverride_t;
805 /* NOT CURRENTLY USED
807 uint8_t Gfx_ActiveHystLimit;
808 uint8_t Gfx_IdleHystLimit;
810 uint8_t Gfx_MinActiveFreqType;
811 uint8_t Gfx_BoosterFreqType;
812 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
813 uint8_t Gfx_UseRlcBusy;
814 uint8_t PaddingGfx[3];
815 uint16_t Gfx_MinActiveFreq; // MHz
816 uint16_t Gfx_BoosterFreq; // MHz
817 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms
818 uint32_t Gfx_PD_Data_limit_a; // Q16
819 uint32_t Gfx_PD_Data_limit_b; // Q16
820 uint32_t Gfx_PD_Data_limit_c; // Q16
821 uint32_t Gfx_PD_Data_error_coeff; // Q16
822 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
824 uint8_t Mem_ActiveHystLimit;
825 uint8_t Mem_IdleHystLimit;
827 uint8_t Mem_MinActiveFreqType;
828 uint8_t Mem_BoosterFreqType;
829 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
830 uint8_t Mem_UseRlcBusy;
831 uint8_t PaddingMem[3];
832 uint16_t Mem_MinActiveFreq; // MHz
833 uint16_t Mem_BoosterFreq; // MHz
834 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms
835 uint32_t Mem_PD_Data_limit_a; // Q16
836 uint32_t Mem_PD_Data_limit_b; // Q16
837 uint32_t Mem_PD_Data_limit_c; // Q16
838 uint32_t Mem_PD_Data_error_coeff; // Q16
839 uint32_t Mem_PD_Data_error_rate_coeff; // Q16
841 uint32_t Mem_UpThreshold_Limit; // Q16
842 uint8_t Mem_UpHystLimit;
843 uint8_t Mem_DownHystLimit;
846 uint32_t MmHubPadding[8]; // SMU internal use
847 } DpmActivityMonitorCoeffInt_t;
850 // These defines are used with the following messages:
851 // SMC_MSG_TransferTableDram2Smu
852 // SMC_MSG_TransferTableSmu2Dram
853 #define TABLE_PPTABLE 0
855 #define TABLE_AVFS_PSM_DEBUG 2
856 #define TABLE_AVFS_FUSE_OVERRIDE 3
857 #define TABLE_PMSTATUSLOG 4
858 #define TABLE_SMU_METRICS 5
859 #define TABLE_DRIVER_SMU_CONFIG 6
860 //#define TABLE_ACTIVITY_MONITOR_COEFF 7
861 #define TABLE_OVERDRIVE 7
862 #define TABLE_WAFL_XGMI_TOPOLOGY 8
863 #define TABLE_COUNT 9
865 // These defines are used with the SMC_MSG_SetUclkFastSwitch message.
867 DF_SWITCH_TYPE_FAST = 0,
869 DF_SWITCH_TYPE_COUNT,
873 DRAM_BIT_WIDTH_DISABLED = 0,
877 DRAM_BIT_WIDTH_X_64, // NOT USED.
878 DRAM_BIT_WIDTH_X_128,
879 DRAM_BIT_WIDTH_COUNT,
880 } DRAM_BIT_WIDTH_TYPE_e;
882 #define REMOVE_FMAX_MARGIN_BIT 0x0
883 #define REMOVE_DCTOL_MARGIN_BIT 0x1
884 #define REMOVE_PLATFORM_MARGIN_BIT 0x2