2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU74_DISCRETE_H
25 #define SMU74_DISCRETE_H
32 #define NUM_SCLK_RANGE 8
37 #define POSTDIV_DIV_BY_1 0
38 #define POSTDIV_DIV_BY_2 1
39 #define POSTDIV_DIV_BY_4 2
40 #define POSTDIV_DIV_BY_8 3
41 #define POSTDIV_DIV_BY_16 4
43 struct sclkFcwRange_t {
48 uint16_t fcw_trans_upper;
49 uint16_t fcw_trans_lower;
51 typedef struct sclkFcwRange_t sclkFcwRange_t;
59 typedef struct SMIO_Pattern SMIO_Pattern;
62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
65 typedef struct SMIO_Table SMIO_Table;
67 struct SMU_SclkSetting {
68 uint32_t SclkFrequency;
74 uint16_t Sclk_slew_rate;
75 uint16_t Pcc_up_slew_rate;
76 uint16_t Pcc_down_slew_rate;
79 uint16_t Sclk_ss_slew_rate;
81 typedef struct SMU_SclkSetting SMU_SclkSetting;
83 struct SMU74_Discrete_GraphicsLevel {
84 SMU_VoltageLevel MinVoltage;
86 uint8_t DeepSleepDivId;
87 uint16_t ActivityLevel;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
100 SMU_SclkSetting SclkSetting;
103 typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
105 struct SMU74_Discrete_ACPILevel {
107 SMU_VoltageLevel MinVoltage;
108 uint32_t SclkFrequency;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
114 uint32_t CcPwrDynRm1;
116 SMU_SclkSetting SclkSetting;
119 typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
121 struct SMU74_Discrete_Ulv {
123 uint32_t CcPwrDynRm1;
125 uint8_t VddcOffsetVid;
131 typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
133 struct SMU74_Discrete_MemoryLevel {
134 SMU_VoltageLevel MinVoltage;
137 uint32_t MclkFrequency;
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
146 uint8_t VoltageDownHyst;
149 uint16_t ActivityLevel;
150 uint8_t DisplayWatermark;
154 typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
156 struct SMU74_Discrete_LinkLevel {
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
161 uint32_t DownThreshold;
162 uint32_t UpThreshold;
167 typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
169 struct SMU74_Discrete_MCArbDramTimingTableEntry {
170 uint32_t McArbDramTiming;
171 uint32_t McArbDramTiming2;
172 uint8_t McArbBurstTime;
176 typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
178 struct SMU74_Discrete_MCArbDramTimingTable {
179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
182 typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
184 struct SMU74_Discrete_UvdLevel {
185 uint32_t VclkFrequency;
186 uint32_t DclkFrequency;
187 SMU_VoltageLevel MinVoltage;
193 typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
195 struct SMU74_Discrete_ExtClkLevel {
197 SMU_VoltageLevel MinVoltage;
202 typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
204 struct SMU74_Discrete_StateInfo {
205 uint32_t SclkFrequency;
206 uint32_t MclkFrequency;
207 uint32_t VclkFrequency;
208 uint32_t DclkFrequency;
209 uint32_t SamclkFrequency;
210 uint32_t AclkFrequency;
211 uint32_t EclkFrequency;
212 uint16_t MvddVoltage;
214 uint8_t DisplayWatermark;
224 typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
226 struct SMU74_Discrete_DpmTable {
228 SMU74_PIDController GraphicsPIDController;
229 SMU74_PIDController MemoryPIDController;
230 SMU74_PIDController LinkPIDController;
232 uint32_t SystemFlags;
237 SMIO_Table SmioTable1;
238 SMIO_Table SmioTable2;
240 uint32_t MvddLevelCount;
243 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
244 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
245 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
247 uint8_t GraphicsDpmLevelCount;
248 uint8_t MemoryDpmLevelCount;
249 uint8_t LinkLevelCount;
250 uint8_t MasterDeepSleepControl;
252 uint8_t UvdLevelCount;
253 uint8_t VceLevelCount;
254 uint8_t AcpLevelCount;
255 uint8_t SamuLevelCount;
257 uint8_t ThermOutGpio;
258 uint8_t ThermOutPolarity;
259 uint8_t ThermOutMode;
261 uint32_t Reserved[4];
263 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
264 SMU74_Discrete_MemoryLevel MemoryACPILevel;
265 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
266 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
267 SMU74_Discrete_ACPILevel ACPILevel;
268 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
269 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
270 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
271 SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
272 SMU74_Discrete_Ulv Ulv;
274 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
276 uint32_t SclkStepSize;
277 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
279 uint8_t UvdBootLevel;
280 uint8_t VceBootLevel;
281 uint8_t AcpBootLevel;
282 uint8_t SamuBootLevel;
284 uint8_t GraphicsBootLevel;
285 uint8_t GraphicsVoltageChangeEnable;
286 uint8_t GraphicsThermThrottleEnable;
287 uint8_t GraphicsInterval;
289 uint8_t VoltageInterval;
290 uint8_t ThermalInterval;
291 uint16_t TemperatureLimitHigh;
293 uint16_t TemperatureLimitLow;
294 uint8_t MemoryBootLevel;
295 uint8_t MemoryVoltageChangeEnable;
298 uint8_t MemoryInterval;
299 uint8_t MemoryThermThrottleEnable;
301 uint16_t VoltageResponseTime;
302 uint16_t PhaseResponseTime;
304 uint8_t PCIeBootLinkLevel;
305 uint8_t PCIeGenInterval;
314 uint16_t PPM_PkgPwrLimit;
315 uint16_t PPM_TemperatureLimit;
320 uint16_t FpsHighThreshold;
321 uint16_t FpsLowThreshold;
323 uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
324 uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
326 uint16_t TemperatureLimitEdge;
327 uint16_t TemperatureLimitHotspot;
332 uint16_t FanGainEdge;
333 uint16_t FanGainHotspot;
335 uint32_t LowSclkInterruptThreshold;
336 uint32_t VddGfxReChkWait;
338 uint8_t ClockStretcherAmount;
339 uint8_t Sclk_CKS_masterEn0_7;
340 uint8_t Sclk_CKS_masterEn8_15;
341 uint8_t DPMFreezeAndForced;
343 uint8_t Sclk_voltageOffset[8];
345 SMU_ClockStretcherDataTable ClockStretcherDataTable;
346 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
348 uint32_t CurrSclkPllRange;
349 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
352 typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
355 struct SMU74_Discrete_FanTable {
370 uint32_t RefreshPeriod;
376 typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
378 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
379 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
382 struct SMU7_MclkDpmScoreboard {
383 uint32_t PercentageBusy;
389 uint32_t SigmaDeltaAccum;
390 uint32_t SigmaDeltaOutput;
391 uint32_t SigmaDeltaLevel;
393 uint32_t UtilizationSetpoint;
395 uint8_t TdpClampMode;
396 uint8_t TdcClampMode;
397 uint8_t ThermClampMode;
402 uint8_t LevelChangeInProgress;
406 uint8_t VoltageDownHyst;
411 uint8_t DpmForceLevel;
415 uint32_t MinimumPerfMclk;
419 uint8_t MclkSwitchInProgress;
420 uint8_t MclkSwitchCritical;
422 uint8_t IgnoreVBlank;
423 uint8_t TargetMclkIndex;
424 uint16_t VbiFailureCount;
425 uint8_t VbiWaitCounter;
426 uint8_t EnabledLevelsChange;
428 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
429 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
431 void (*TargetStateCalculator)(uint8_t);
432 void (*SavedTargetStateCalculator)(uint8_t);
434 uint16_t AutoDpmInterval;
435 uint16_t AutoDpmRange;
437 uint16_t VbiTimeoutCount;
438 uint16_t MclkSwitchingTime;
441 uint8_t Save_PIC_VDDGFX_EXIT;
442 uint8_t Save_PIC_VDDGFX_ENTER;
446 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
448 struct SMU7_UlvScoreboard {
452 uint8_t WaitingForUlv;
455 uint8_t UlvMasterEnable;
457 uint32_t UlvAbortedCount;
458 uint32_t UlvTimeStamp;
461 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
463 struct VddgfxSavedRegisters {
465 uint32_t MEC_BaseAddress_Hi;
466 uint32_t MEC_BaseAddress_Lo;
467 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
468 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
469 uint32_t CP_INT_CNTL;
472 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
474 struct SMU7_VddGfxScoreboard {
475 uint8_t VddGfxEnable;
476 uint8_t VddGfxActive;
477 uint8_t VPUResetOccured;
480 uint32_t VddGfxEnteredCount;
481 uint32_t VddGfxAbortedCount;
485 VddgfxSavedRegisters SavedRegisters;
488 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
490 struct SMU7_TdcLimitScoreboard {
494 uint32_t FilteredIddc;
497 SMU7_HystController_Data HystControllerData;
500 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
502 struct SMU7_PkgPwrLimitScoreboard {
506 uint32_t FilteredPkgPwr;
509 uint32_t LimitFromDriver;
510 SMU7_HystController_Data HystControllerData;
513 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
515 struct SMU7_BapmScoreboard {
516 uint32_t source_powers[SMU74_DTE_SOURCES];
517 uint32_t source_powers_last[SMU74_DTE_SOURCES];
518 int32_t entity_temperatures[SMU74_NUM_GPU_TES];
519 int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
522 int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
523 int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
524 uint16_t ConfigTDPPowerScalar;
525 uint16_t FanSpeedPowerScalar;
526 uint16_t OverDrivePowerScalar;
527 uint16_t OverDriveLimitScalar;
528 uint16_t FinalPowerScalar;
532 SMU7_HystController_Data HystControllerData;
534 int32_t temperature_gradient_slope;
535 int32_t temperature_gradient;
536 uint32_t measured_temperature;
540 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
542 struct SMU7_AcpiScoreboard {
543 uint32_t SavedInterruptMask[2];
544 uint8_t LastACPIRequest;
548 SMU74_Discrete_ACPILevel D0Level;
551 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
553 struct SMU_QuadraticCoeffs {
561 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
563 struct SMU74_Discrete_PmFuses {
564 uint8_t BapmVddCVidHiSidd[8];
565 uint8_t BapmVddCVidLoSidd[8];
567 uint8_t SviLoadLineEn;
568 uint8_t SviLoadLineVddC;
569 uint8_t SviLoadLineTrimVddC;
570 uint8_t SviLoadLineOffsetVddC;
571 uint16_t TDC_VDDC_PkgLimit;
572 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
574 uint8_t TdcWaterfallCtl;
575 uint8_t LPMLTemperatureMin;
576 uint8_t LPMLTemperatureMax;
579 uint8_t LPMLTemperatureScaler[16];
581 int16_t FuzzyFan_ErrorSetDelta;
582 int16_t FuzzyFan_ErrorRateSetDelta;
583 int16_t FuzzyFan_PwmSetDelta;
588 uint8_t GnbLPMLMaxVid;
589 uint8_t GnbLPMLMinVid;
590 uint8_t Reserved1[2];
592 uint16_t BapmVddCBaseLeakageHiSidd;
593 uint16_t BapmVddCBaseLeakageLoSidd;
595 uint16_t VFT_Temp[3];
598 SMU_QuadraticCoeffs VFT_ATE[3];
600 SMU_QuadraticCoeffs AVFS_GB;
601 SMU_QuadraticCoeffs ATE_ACBTC_GB;
603 SMU_QuadraticCoeffs P2V;
605 uint32_t PsmCharzFreq;
607 uint16_t InversionVoltage;
608 uint16_t PsmCharzTemp;
610 uint32_t EnabledAvfsModules;
613 typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
615 struct SMU7_Discrete_Log_Header_Table {
621 uint32_t num_of_entries;
625 uint32_t filler_1[2];
628 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
630 struct SMU7_Discrete_Log_Cntl {
635 uint32_t SamplesLogged;
641 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
643 #if defined SMU__DGPU_ONLY
644 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
648 struct SMU7_Discrete_Cac_Collection_Table {
649 uint32_t temperature;
650 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
653 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
655 struct SMU7_Discrete_Cac_Verification_Table {
656 uint32_t VddcTotalPower;
657 uint32_t VddcLeakagePower;
658 uint32_t VddcConstantPower;
659 uint32_t VddcGfxDynamicPower;
660 uint32_t VddcUvdDynamicPower;
661 uint32_t VddcVceDynamicPower;
662 uint32_t VddcAcpDynamicPower;
663 uint32_t VddcPcieDynamicPower;
664 uint32_t VddcDceDynamicPower;
665 uint32_t VddcCurrent;
666 uint32_t VddcVoltage;
667 uint32_t VddciTotalPower;
668 uint32_t VddciLeakagePower;
669 uint32_t VddciConstantPower;
670 uint32_t VddciDynamicPower;
671 uint32_t Vddr1TotalPower;
672 uint32_t Vddr1LeakagePower;
673 uint32_t Vddr1ConstantPower;
674 uint32_t Vddr1DynamicPower;
676 uint32_t temperature;
679 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
681 struct SMU7_Discrete_Pm_Status_Table {
686 uint32_t P_scalar_acc;
692 uint32_t I_calc_acc_vddci;
693 uint32_t V_calc_noload_acc;
694 uint32_t V_calc_load_acc;
695 uint32_t V_calc_noload_acc_vddci;
697 uint32_t V_meas_noload_acc;
698 uint32_t V_meas_load_acc;
700 uint32_t P_meas_acc_vddci;
701 uint32_t V_meas_noload_acc_vddci;
702 uint32_t V_meas_load_acc_vddci;
703 uint32_t I_meas_acc_vddci;
705 uint16_t Sclk_dpm_residency[8];
706 uint16_t Uvd_dpm_residency[8];
707 uint16_t Vce_dpm_residency[8];
708 uint16_t Mclk_dpm_residency[4];
710 uint32_t P_vddci_acc;
711 uint32_t P_vddr1_acc;
715 uint32_t MclkSwitchingTime_max;
716 uint32_t MclkSwitchingTime_acc;
723 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
725 #define SMU7_MAX_GFX_CU_COUNT 16
727 struct SMU7_GfxCuPgScoreboard {
730 uint8_t WaterfallDown;
731 uint8_t WaterfallLimit;
736 uint8_t MaxSupportedCu;
737 uint8_t MinSupportedCu;
738 uint8_t PendingGfxCuHostInterrupt;
739 uint8_t LastFilteredMaxCuInteger;
740 uint16_t FilteredMaxCu;
741 uint16_t FilteredMaxCuAlpha;
742 uint16_t FilterResetCount;
743 uint16_t FilterResetCountLimit;
745 uint8_t ForceCuCount;
749 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
751 #define SMU7_SCLK_CAC 0x561
752 #define SMU7_MCLK_CAC 0xF9
753 #define SMU7_VCLK_CAC 0x2DE
754 #define SMU7_DCLK_CAC 0x2DE
755 #define SMU7_ECLK_CAC 0x25E
756 #define SMU7_ACLK_CAC 0x25E
757 #define SMU7_SAMCLK_CAC 0x25E
758 #define SMU7_DISPCLK_CAC 0x100
759 #define SMU7_CAC_CONSTANT 0x2EE3430
760 #define SMU7_CAC_CONSTANT_SHIFT 18
762 #define SMU7_VDDCI_MCLK_CONST 1765
763 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16
764 #define SMU7_VDDCI_VDDCI_CONST 50958
765 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
766 #define SMU7_VDDCI_CONST 11781
767 #define SMU7_VDDCI_STROBE_PWR 1331
769 #define SMU7_VDDR1_CONST 693
770 #define SMU7_VDDR1_CAC_WEIGHT 20
771 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
772 #define SMU7_VDDR1_STROBE_PWR 512
774 #define SMU7_AREA_COEFF_UVD 0xA78
775 #define SMU7_AREA_COEFF_VCE 0x190A
776 #define SMU7_AREA_COEFF_ACP 0x22D1
777 #define SMU7_AREA_COEFF_SAMU 0x534
779 #define SMU7_THERM_OUT_MODE_DISABLE 0x0
780 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
781 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
784 #define SQ_Enable_MASK 0x1
785 #define SQ_IR_MASK 0x2
786 #define SQ_PCC_MASK 0x4
787 #define SQ_EDC_MASK 0x8
789 #define TCP_Enable_MASK 0x100
790 #define TCP_IR_MASK 0x200
791 #define TCP_PCC_MASK 0x400
792 #define TCP_EDC_MASK 0x800
794 #define TD_Enable_MASK 0x10000
795 #define TD_IR_MASK 0x20000
796 #define TD_PCC_MASK 0x40000
797 #define TD_EDC_MASK 0x80000
799 #define DB_Enable_MASK 0x1000000
800 #define DB_IR_MASK 0x2000000
801 #define DB_PCC_MASK 0x4000000
802 #define DB_EDC_MASK 0x8000000
804 #define SQ_Enable_SHIFT 0
805 #define SQ_IR_SHIFT 1
806 #define SQ_PCC_SHIFT 2
807 #define SQ_EDC_SHIFT 3
809 #define TCP_Enable_SHIFT 8
810 #define TCP_IR_SHIFT 9
811 #define TCP_PCC_SHIFT 10
812 #define TCP_EDC_SHIFT 11
814 #define TD_Enable_SHIFT 16
815 #define TD_IR_SHIFT 17
816 #define TD_PCC_SHIFT 18
817 #define TD_EDC_SHIFT 19
819 #define DB_Enable_SHIFT 24
820 #define DB_IR_SHIFT 25
821 #define DB_PCC_SHIFT 26
822 #define DB_EDC_SHIFT 27