2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __SMU_V11_0_H__
24 #define __SMU_V11_0_H__
26 #include "amdgpu_smu.h"
28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_VG20 0x13
30 #define SMU11_DRIVER_IF_VERSION_ARCT 0x10
31 #define SMU11_DRIVER_IF_VERSION_NV10 0x33
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x34
35 #define MP0_Public 0x03800000
36 #define MP0_SRAM 0x03900000
37 #define MP1_Public 0x03b00000
38 #define MP1_SRAM 0x03c00004
39 #define MP1_SMC_SIZE 0x40000
42 #define smnMP1_FIRMWARE_FLAGS 0x3010024
43 #define smnMP0_FW_INTF 0x30101c0
44 #define smnMP1_PUB_CTRL 0x3010b14
46 #define TEMP_RANGE_MIN (0)
47 #define TEMP_RANGE_MAX (80 * 1000)
49 #define SMU11_TOOL_SIZE 0x19000
51 #define MAX_PCIE_CONF 2
53 #define CLK_MAP(clk, index) \
54 [SMU_##clk] = {1, (index)}
56 #define FEA_MAP(fea) \
57 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
59 #define TAB_MAP(tab) \
60 [SMU_TABLE_##tab] = {1, TABLE_##tab}
62 #define PWR_MAP(tab) \
63 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
65 #define WORKLOAD_MAP(profile, workload) \
66 [profile] = {1, (workload)}
68 static const struct smu_temperature_range smu11_thermal_policy[] =
70 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
71 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
74 struct smu_11_0_cmn2aisc_mapping {
79 struct smu_11_0_max_sustainable_clocks {
80 uint32_t display_clock;
88 struct smu_11_0_dpm_table {
89 uint32_t min; /* MHz */
90 uint32_t max; /* MHz */
93 struct smu_11_0_pcie_table {
94 uint8_t pcie_gen[MAX_PCIE_CONF];
95 uint8_t pcie_lane[MAX_PCIE_CONF];
98 struct smu_11_0_dpm_tables {
99 struct smu_11_0_dpm_table soc_table;
100 struct smu_11_0_dpm_table gfx_table;
101 struct smu_11_0_dpm_table uclk_table;
102 struct smu_11_0_dpm_table eclk_table;
103 struct smu_11_0_dpm_table vclk_table;
104 struct smu_11_0_dpm_table dclk_table;
105 struct smu_11_0_dpm_table dcef_table;
106 struct smu_11_0_dpm_table pixel_table;
107 struct smu_11_0_dpm_table display_table;
108 struct smu_11_0_dpm_table phy_table;
109 struct smu_11_0_dpm_table fclk_table;
110 struct smu_11_0_pcie_table pcie_table;
113 struct smu_11_0_dpm_context {
114 struct smu_11_0_dpm_tables dpm_tables;
115 uint32_t workload_policy_mask;
116 uint32_t dcef_min_ds_clk;
119 enum smu_11_0_power_state {
120 SMU_11_0_POWER_STATE__D0 = 0,
121 SMU_11_0_POWER_STATE__D1,
122 SMU_11_0_POWER_STATE__D3, /* Sleep*/
123 SMU_11_0_POWER_STATE__D4, /* Hibernate*/
124 SMU_11_0_POWER_STATE__D5, /* Power off*/
127 struct smu_11_0_power_context {
128 uint32_t power_source;
129 uint8_t in_power_limit_boost_mode;
130 enum smu_11_0_power_state power_state;
133 enum smu_v11_0_baco_seq {
141 int smu_v11_0_init_microcode(struct smu_context *smu);
143 int smu_v11_0_load_microcode(struct smu_context *smu);
145 int smu_v11_0_init_smc_tables(struct smu_context *smu);
147 int smu_v11_0_fini_smc_tables(struct smu_context *smu);
149 int smu_v11_0_init_power(struct smu_context *smu);
151 int smu_v11_0_fini_power(struct smu_context *smu);
153 int smu_v11_0_check_fw_status(struct smu_context *smu);
155 int smu_v11_0_setup_pptable(struct smu_context *smu);
157 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
159 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
161 int smu_v11_0_check_pptable(struct smu_context *smu);
163 int smu_v11_0_parse_pptable(struct smu_context *smu);
165 int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
167 int smu_v11_0_check_fw_version(struct smu_context *smu);
169 int smu_v11_0_write_pptable(struct smu_context *smu);
171 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
173 int smu_v11_0_set_tool_table_location(struct smu_context *smu);
175 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
177 int smu_v11_0_system_features_control(struct smu_context *smu,
180 int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
183 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
186 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
188 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
190 int smu_v11_0_set_allowed_mask(struct smu_context *smu);
192 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
193 uint32_t *feature_mask, uint32_t num);
195 int smu_v11_0_notify_display_change(struct smu_context *smu);
197 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
199 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
200 enum smu_clk_type clk_id,
203 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
205 int smu_v11_0_start_thermal_control(struct smu_context *smu);
207 int smu_v11_0_stop_thermal_control(struct smu_context *smu);
209 int smu_v11_0_read_sensor(struct smu_context *smu,
210 enum amd_pp_sensors sensor,
211 void *data, uint32_t *size);
213 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
216 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
217 struct pp_display_clock_request
221 smu_v11_0_get_fan_control_mode(struct smu_context *smu);
224 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
228 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
230 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
233 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
236 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
238 int smu_v11_0_register_irq_handler(struct smu_context *smu);
240 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
242 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
243 struct pp_smu_nv_clock_table *max_clocks);
245 bool smu_v11_0_baco_is_support(struct smu_context *smu);
247 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
249 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
251 int smu_v11_0_baco_reset(struct smu_context *smu);
253 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
254 uint32_t *min, uint32_t *max);
256 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
257 uint32_t min, uint32_t max);
259 int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
261 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
263 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu);