drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  39
  40 #define FEATURE_MASK(feature) (1UL << feature)
  41 #define SMC_DPM_FEATURE ( \
  42         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  43         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  44         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  45         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  46         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  48         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = index
  53
  54 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  55         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  56         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  57         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  58         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  59         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  60         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  61         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  62         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  63         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  64         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  65         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  66         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  67         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  68         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  69         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  70         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  71         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  72         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  73         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  74         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  75         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  76         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  77         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  78         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  79         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  80         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  81         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  82         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  83         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  84         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  85         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  86         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  87         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  88         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  89         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  90         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  91         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  92         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  93         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  94         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  95         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  96         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  97         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  98         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  99         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 100         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 101         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 102         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 103         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 104         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 105         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 106         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 107         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 108         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 109         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 110         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 111         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 112         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 113         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 114         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 115         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 116         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 117 };
 118
 119 static int navi10_clk_map[SMU_CLK_COUNT] = {
 120         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 121         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 122         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 123         CLK_MAP(FCLK, PPCLK_SOCCLK),
 124         CLK_MAP(UCLK, PPCLK_UCLK),
 125         CLK_MAP(MCLK, PPCLK_UCLK),
 126         CLK_MAP(DCLK, PPCLK_DCLK),
 127         CLK_MAP(VCLK, PPCLK_VCLK),
 128         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 129         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 130         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 131         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 132 };
 133
 134 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 135         FEA_MAP(DPM_PREFETCHER),
 136         FEA_MAP(DPM_GFXCLK),
 137         FEA_MAP(DPM_GFX_PACE),
 138         FEA_MAP(DPM_UCLK),
 139         FEA_MAP(DPM_SOCCLK),
 140         FEA_MAP(DPM_MP0CLK),
 141         FEA_MAP(DPM_LINK),
 142         FEA_MAP(DPM_DCEFCLK),
 143         FEA_MAP(MEM_VDDCI_SCALING),
 144         FEA_MAP(MEM_MVDD_SCALING),
 145         FEA_MAP(DS_GFXCLK),
 146         FEA_MAP(DS_SOCCLK),
 147         FEA_MAP(DS_LCLK),
 148         FEA_MAP(DS_DCEFCLK),
 149         FEA_MAP(DS_UCLK),
 150         FEA_MAP(GFX_ULV),
 151         FEA_MAP(FW_DSTATE),
 152         FEA_MAP(GFXOFF),
 153         FEA_MAP(BACO),
 154         FEA_MAP(VCN_PG),
 155         FEA_MAP(JPEG_PG),
 156         FEA_MAP(USB_PG),
 157         FEA_MAP(RSMU_SMN_CG),
 158         FEA_MAP(PPT),
 159         FEA_MAP(TDC),
 160         FEA_MAP(GFX_EDC),
 161         FEA_MAP(APCC_PLUS),
 162         FEA_MAP(GTHR),
 163         FEA_MAP(ACDC),
 164         FEA_MAP(VR0HOT),
 165         FEA_MAP(VR1HOT),
 166         FEA_MAP(FW_CTF),
 167         FEA_MAP(FAN_CONTROL),
 168         FEA_MAP(THERMAL),
 169         FEA_MAP(GFX_DCS),
 170         FEA_MAP(RM),
 171         FEA_MAP(LED_DISPLAY),
 172         FEA_MAP(GFX_SS),
 173         FEA_MAP(OUT_OF_BAND_MONITOR),
 174         FEA_MAP(TEMP_DEPENDENT_VMIN),
 175         FEA_MAP(MMHUB_PG),
 176         FEA_MAP(ATHUB_PG),
 177 };
 178
 179 static int navi10_table_map[SMU_TABLE_COUNT] = {
 180         TAB_MAP(PPTABLE),
 181         TAB_MAP(WATERMARKS),
 182         TAB_MAP(AVFS),
 183         TAB_MAP(AVFS_PSM_DEBUG),
 184         TAB_MAP(AVFS_FUSE_OVERRIDE),
 185         TAB_MAP(PMSTATUSLOG),
 186         TAB_MAP(SMU_METRICS),
 187         TAB_MAP(DRIVER_SMU_CONFIG),
 188         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 189         TAB_MAP(OVERDRIVE),
 190         TAB_MAP(I2C_COMMANDS),
 191         TAB_MAP(PACE),
 192 };
 193
 194 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 195         PWR_MAP(AC),
 196         PWR_MAP(DC),
 197 };
 198
 199 static int navi10_workload_map[] = {
 200         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 201         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 202         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 207 };
 208
 209 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 210 {
 211         int val;
 212         if (index > SMU_MSG_MAX_COUNT)
 213                 return -EINVAL;
 214
 215         val = navi10_message_map[index];
 216         if (val > PPSMC_Message_Count)
 217                 return -EINVAL;
 218
 219         return val;
 220 }
 221
 222 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 223 {
 224         int val;
 225         if (index >= SMU_CLK_COUNT)
 226                 return -EINVAL;
 227
 228         val = navi10_clk_map[index];
 229         if (val >= PPCLK_COUNT)
 230                 return -EINVAL;
 231
 232         return val;
 233 }
 234
 235 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 236 {
 237         int val;
 238         if (index >= SMU_FEATURE_COUNT)
 239                 return -EINVAL;
 240
 241         val = navi10_feature_mask_map[index];
 242         if (val > 64)
 243                 return -EINVAL;
 244
 245         return val;
 246 }
 247
 248 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 249 {
 250         int val;
 251         if (index >= SMU_TABLE_COUNT)
 252                 return -EINVAL;
 253
 254         val = navi10_table_map[index];
 255         if (val >= TABLE_COUNT)
 256                 return -EINVAL;
 257
 258         return val;
 259 }
 260
 261 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 262 {
 263         int val;
 264         if (index >= SMU_POWER_SOURCE_COUNT)
 265                 return -EINVAL;
 266
 267         val = navi10_pwr_src_map[index];
 268         if (val >= POWER_SOURCE_COUNT)
 269                 return -EINVAL;
 270
 271         return val;
 272 }
 273
 274
 275 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 276 {
 277         int val;
 278         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 279                 return -EINVAL;
 280
 281         val = navi10_workload_map[profile];
 282
 283         return val;
 284 }
 285
 286 static bool is_asic_secure(struct smu_context *smu)
 287 {
 288         struct amdgpu_device *adev = smu->adev;
 289         bool is_secure = true;
 290         uint32_t mp0_fw_intf;
 291
 292         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 293                                    (smnMP0_FW_INTF & 0xffffffff));
 294
 295         if (!(mp0_fw_intf & (1 << 19)))
 296                 is_secure = false;
 297
 298         return is_secure;
 299 }
 300
 301 static int
 302 navi10_get_allowed_feature_mask(struct smu_context *smu,
 303                                   uint32_t *feature_mask, uint32_t num)
 304 {
 305         struct amdgpu_device *adev = smu->adev;
 306
 307         if (num > 2)
 308                 return -EINVAL;
 309
 310         memset(feature_mask, 0, sizeof(uint32_t) * num);
 311
 312         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 313                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 314                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 315                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 316                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 317                                 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 318                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 319                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)
 320                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 321                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 322                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 323                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 324                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 325                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 326                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 327                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 328                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 329                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 330                                 | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
 331                                 | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
 332                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 333                                 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
 334                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 335                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 336                                 | FEATURE_MASK(FEATURE_ACDC_BIT);
 337
 338         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 339                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 340                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 341
 342         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 343                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 344
 345         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 346         if (is_asic_secure(smu)) {
 347                 /* only for navi10 A0 */
 348                 if ((adev->asic_type == CHIP_NAVI10) &&
 349                         (adev->rev_id == 0)) {
 350                         *(uint64_t *)feature_mask &=
 351                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 352                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 353                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 354                         *(uint64_t *)feature_mask &=
 355                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 356                 }
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int navi10_check_powerplay_table(struct smu_context *smu)
 363 {
 364         return 0;
 365 }
 366
 367 static int navi10_append_powerplay_table(struct smu_context *smu)
 368 {
 369         struct amdgpu_device *adev = smu->adev;
 370         struct smu_table_context *table_context = &smu->smu_table;
 371         PPTable_t *smc_pptable = table_context->driver_pptable;
 372         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 373         int index, ret;
 374
 375         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 376                                            smc_dpm_info);
 377
 378         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 379                                       (uint8_t **)&smc_dpm_table);
 380         if (ret)
 381                 return ret;
 382
 383         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 384                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 385
 386         /* SVI2 Board Parameters */
 387         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 388         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 389         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 390         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 391         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 392         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 393         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 394         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 395         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 396         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 397
 398         /* Telemetry Settings */
 399         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 400         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 401         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 402         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 403         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 404         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 405         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 406         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 407         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 408         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 409         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 410         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 411
 412         /* GPIO Settings */
 413         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 414         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 415         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 416         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 417         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 418         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 419         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 420         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 421
 422         /* LED Display Settings */
 423         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 424         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 425         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 426         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 427
 428         /* GFXCLK PLL Spread Spectrum */
 429         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 430         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 431         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 432
 433         /* GFXCLK DFLL Spread Spectrum */
 434         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 435         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 436         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 437
 438         /* UCLK Spread Spectrum */
 439         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 440         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 441         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 442
 443         /* SOCCLK Spread Spectrum */
 444         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 445         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 446         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 447
 448         /* Total board power */
 449         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 450         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 451
 452         /* Mvdd Svi2 Div Ratio Setting */
 453         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 454
 455         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 456                 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 457                                         | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 458
 459                 /* TODO: remove it once SMU fw fix it */
 460                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static int navi10_store_powerplay_table(struct smu_context *smu)
 467 {
 468         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 469         struct smu_table_context *table_context = &smu->smu_table;
 470
 471         if (!table_context->power_play_table)
 472                 return -EINVAL;
 473
 474         powerplay_table = table_context->power_play_table;
 475
 476         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 477                sizeof(PPTable_t));
 478
 479         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 480
 481         return 0;
 482 }
 483
 484 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 485 {
 486         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 487                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 488         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 489                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 490         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 491                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 492         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 493                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 494         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 495                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 496         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 497                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 498                        AMDGPU_GEM_DOMAIN_VRAM);
 499
 500         return 0;
 501 }
 502
 503 static int navi10_allocate_dpm_context(struct smu_context *smu)
 504 {
 505         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 506
 507         if (smu_dpm->dpm_context)
 508                 return -EINVAL;
 509
 510         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 511                                        GFP_KERNEL);
 512         if (!smu_dpm->dpm_context)
 513                 return -ENOMEM;
 514
 515         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 516
 517         return 0;
 518 }
 519
 520 static int navi10_set_default_dpm_table(struct smu_context *smu)
 521 {
 522         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 523         struct smu_table_context *table_context = &smu->smu_table;
 524         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 525         PPTable_t *driver_ppt = NULL;
 526
 527         driver_ppt = table_context->driver_pptable;
 528
 529         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 530         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 531
 532         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 533         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 534
 535         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 536         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 537
 538         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 539         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 540
 541         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 542         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 543
 544         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 545         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 546
 547         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 548         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 549
 550         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 551         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 552
 553         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 554         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 555
 556         return 0;
 557 }
 558
 559 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 560 {
 561         int ret = 0;
 562         struct smu_power_context *smu_power = &smu->smu_power;
 563         struct smu_power_gate *power_gate = &smu_power->power_gate;
 564
 565         if (enable && power_gate->uvd_gated) {
 566                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 567                 if (ret)
 568                         return ret;
 569                 power_gate->uvd_gated = false;
 570         } else {
 571                 if (!enable && !power_gate->uvd_gated) {
 572                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 573                         if (ret)
 574                                 return ret;
 575                         power_gate->uvd_gated = true;
 576                 }
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 583                                        enum smu_clk_type clk_type,
 584                                        uint32_t *value)
 585 {
 586         static SmuMetrics_t metrics = {0};
 587         int ret = 0, clk_id = 0;
 588
 589         if (!value)
 590                 return -EINVAL;
 591
 592         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
 593         if (ret)
 594                 return ret;
 595
 596         clk_id = smu_clk_get_index(smu, clk_type);
 597         if (clk_id < 0)
 598                 return clk_id;
 599
 600         *value = metrics.CurrClock[clk_id];
 601
 602         return ret;
 603 }
 604
 605 static int navi10_print_clk_levels(struct smu_context *smu,
 606                         enum smu_clk_type clk_type, char *buf)
 607 {
 608         int i, size = 0, ret = 0;
 609         uint32_t cur_value = 0, value = 0, count = 0;
 610
 611         switch (clk_type) {
 612         case SMU_GFXCLK:
 613         case SMU_SCLK:
 614         case SMU_SOCCLK:
 615         case SMU_MCLK:
 616         case SMU_UCLK:
 617         case SMU_FCLK:
 618         case SMU_DCEFCLK:
 619                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 620                 if (ret)
 621                         return size;
 622                 /* 10KHz -> MHz */
 623                 cur_value = cur_value / 100;
 624
 625                 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 626
 627                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 628                 if (ret)
 629                         return size;
 630
 631                 for (i = 0; i < count; i++) {
 632                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 633                         if (ret)
 634                                 return size;
 635
 636                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 637                                         cur_value == value ? "*" : "");
 638                 }
 639                 break;
 640         default:
 641                 break;
 642         }
 643
 644         return size;
 645 }
 646
 647 static int navi10_force_clk_levels(struct smu_context *smu,
 648                                    enum smu_clk_type clk_type, uint32_t mask)
 649 {
 650
 651         int ret = 0, size = 0;
 652         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 653
 654         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 655         soft_max_level = mask ? (fls(mask) - 1) : 0;
 656
 657         switch (clk_type) {
 658         case SMU_GFXCLK:
 659         case SMU_SCLK:
 660         case SMU_SOCCLK:
 661         case SMU_MCLK:
 662         case SMU_UCLK:
 663         case SMU_DCEFCLK:
 664         case SMU_FCLK:
 665                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 666                 if (ret)
 667                         return size;
 668
 669                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 670                 if (ret)
 671                         return size;
 672
 673                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 674                 if (ret)
 675                         return size;
 676                 break;
 677         default:
 678                 break;
 679         }
 680
 681         return size;
 682 }
 683
 684 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 685 {
 686         int ret = 0;
 687         uint32_t min_sclk_freq = 0;
 688
 689         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
 690         if (ret)
 691                 return ret;
 692
 693         smu->pstate_sclk = min_sclk_freq * 100;
 694
 695         return ret;
 696 }
 697
 698 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 699                                                  enum smu_clk_type clk_type,
 700                                                  struct pp_clock_levels_with_latency *clocks)
 701 {
 702         int ret = 0, i = 0;
 703         uint32_t level_count = 0, freq = 0;
 704
 705         switch (clk_type) {
 706         case SMU_GFXCLK:
 707         case SMU_DCEFCLK:
 708         case SMU_SOCCLK:
 709                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 710                 if (ret)
 711                         return ret;
 712
 713                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 714                 clocks->num_levels = level_count;
 715
 716                 for (i = 0; i < level_count; i++) {
 717                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 718                         if (ret)
 719                                 return ret;
 720
 721                         clocks->data[i].clocks_in_khz = freq * 1000;
 722                         clocks->data[i].latency_in_us = 0;
 723                 }
 724                 break;
 725         default:
 726                 break;
 727         }
 728
 729         return ret;
 730 }
 731
 732 static int navi10_pre_display_config_changed(struct smu_context *smu)
 733 {
 734         int ret = 0;
 735         uint32_t max_freq = 0;
 736
 737         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 738         if (ret)
 739                 return ret;
 740
 741         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 742                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
 743                 if (ret)
 744                         return ret;
 745                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 746                 if (ret)
 747                         return ret;
 748         }
 749
 750         return ret;
 751 }
 752
 753 static int navi10_display_config_changed(struct smu_context *smu)
 754 {
 755         int ret = 0;
 756
 757         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 758             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 759                 ret = smu_write_watermarks_table(smu);
 760                 if (ret)
 761                         return ret;
 762
 763                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 764         }
 765
 766         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 767             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 768             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 769                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 770                                                   smu->display_config->num_display);
 771                 if (ret)
 772                         return ret;
 773         }
 774
 775         return ret;
 776 }
 777
 778 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 779 {
 780         int ret = 0, i = 0;
 781         uint32_t min_freq, max_freq, force_freq;
 782         enum smu_clk_type clk_type;
 783
 784         enum smu_clk_type clks[] = {
 785                 SMU_GFXCLK,
 786                 SMU_MCLK,
 787                 SMU_SOCCLK,
 788         };
 789
 790         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 791                 clk_type = clks[i];
 792                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 793                 if (ret)
 794                         return ret;
 795
 796                 force_freq = highest ? max_freq : min_freq;
 797                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 798                 if (ret)
 799                         return ret;
 800         }
 801
 802         return ret;
 803 }
 804
 805 static int navi10_unforce_dpm_levels(struct smu_context *smu) {
 806
 807         int ret = 0, i = 0;
 808         uint32_t min_freq, max_freq;
 809         enum smu_clk_type clk_type;
 810
 811         enum smu_clk_type clks[] = {
 812                 SMU_GFXCLK,
 813                 SMU_MCLK,
 814                 SMU_SOCCLK,
 815         };
 816
 817         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 818                 clk_type = clks[i];
 819                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 820                 if (ret)
 821                         return ret;
 822
 823                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 824                 if (ret)
 825                         return ret;
 826         }
 827
 828         return ret;
 829 }
 830
 831 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 832 {
 833         int ret = 0;
 834         SmuMetrics_t metrics;
 835
 836         if (!value)
 837                 return -EINVAL;
 838
 839         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
 840                                false);
 841         if (ret)
 842                 return ret;
 843
 844         *value = metrics.CurrSocketPower << 8;
 845
 846         return 0;
 847 }
 848
 849 static int navi10_get_current_activity_percent(struct smu_context *smu,
 850                                                uint32_t *value)
 851 {
 852         int ret = 0;
 853         SmuMetrics_t metrics;
 854
 855         if (!value)
 856                 return -EINVAL;
 857
 858         msleep(1);
 859
 860         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
 861                                (void *)&metrics, false);
 862         if (ret)
 863                 return ret;
 864
 865         *value = metrics.AverageGfxActivity;
 866
 867         return 0;
 868 }
 869
 870 static bool navi10_is_dpm_running(struct smu_context *smu)
 871 {
 872         int ret = 0;
 873         uint32_t feature_mask[2];
 874         unsigned long feature_enabled;
 875         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 876         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 877                            ((uint64_t)feature_mask[1] << 32));
 878         return !!(feature_enabled & SMC_DPM_FEATURE);
 879 }
 880
 881 static int navi10_set_thermal_fan_table(struct smu_context *smu)
 882 {
 883         int ret;
 884         struct smu_table_context *table_context = &smu->smu_table;
 885         PPTable_t *pptable = table_context->driver_pptable;
 886
 887         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
 888                         (uint32_t)pptable->FanTargetTemperature);
 889
 890         return ret;
 891 }
 892
 893 static int navi10_get_fan_speed_percent(struct smu_context *smu,
 894                                         uint32_t *speed)
 895 {
 896         int ret = 0;
 897         uint32_t percent = 0;
 898         uint32_t current_rpm;
 899         PPTable_t *pptable = smu->smu_table.driver_pptable;
 900
 901         ret = smu_get_current_rpm(smu, &current_rpm);
 902         if (ret)
 903                 return ret;
 904
 905         percent = current_rpm * 100 / pptable->FanMaximumRpm;
 906         *speed = percent > 100 ? 100 : percent;
 907
 908         return ret;
 909 }
 910
 911 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
 912 {
 913         DpmActivityMonitorCoeffInt_t activity_monitor;
 914         uint32_t i, size = 0;
 915         uint16_t workload_type = 0;
 916         static const char *profile_name[] = {
 917                                         "BOOTUP_DEFAULT",
 918                                         "3D_FULL_SCREEN",
 919                                         "POWER_SAVING",
 920                                         "VIDEO",
 921                                         "VR",
 922                                         "COMPUTE",
 923                                         "CUSTOM"};
 924         static const char *title[] = {
 925                         "PROFILE_INDEX(NAME)",
 926                         "CLOCK_TYPE(NAME)",
 927                         "FPS",
 928                         "MinFreqType",
 929                         "MinActiveFreqType",
 930                         "MinActiveFreq",
 931                         "BoosterFreqType",
 932                         "BoosterFreq",
 933                         "PD_Data_limit_c",
 934                         "PD_Data_error_coeff",
 935                         "PD_Data_error_rate_coeff"};
 936         int result = 0;
 937
 938         if (!buf)
 939                 return -EINVAL;
 940
 941         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
 942                         title[0], title[1], title[2], title[3], title[4], title[5],
 943                         title[6], title[7], title[8], title[9], title[10]);
 944
 945         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 946                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 947                 workload_type = smu_workload_get_type(smu, i);
 948                 result = smu_update_table(smu,
 949                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
 950                                           (void *)(&activity_monitor), false);
 951                 if (result) {
 952                         pr_err("[%s] Failed to get activity monitor!", __func__);
 953                         return result;
 954                 }
 955
 956                 size += sprintf(buf + size, "%2d %14s%s:\n",
 957                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 958
 959                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 960                         " ",
 961                         0,
 962                         "GFXCLK",
 963                         activity_monitor.Gfx_FPS,
 964                         activity_monitor.Gfx_MinFreqStep,
 965                         activity_monitor.Gfx_MinActiveFreqType,
 966                         activity_monitor.Gfx_MinActiveFreq,
 967                         activity_monitor.Gfx_BoosterFreqType,
 968                         activity_monitor.Gfx_BoosterFreq,
 969                         activity_monitor.Gfx_PD_Data_limit_c,
 970                         activity_monitor.Gfx_PD_Data_error_coeff,
 971                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
 972
 973                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 974                         " ",
 975                         1,
 976                         "SOCCLK",
 977                         activity_monitor.Soc_FPS,
 978                         activity_monitor.Soc_MinFreqStep,
 979                         activity_monitor.Soc_MinActiveFreqType,
 980                         activity_monitor.Soc_MinActiveFreq,
 981                         activity_monitor.Soc_BoosterFreqType,
 982                         activity_monitor.Soc_BoosterFreq,
 983                         activity_monitor.Soc_PD_Data_limit_c,
 984                         activity_monitor.Soc_PD_Data_error_coeff,
 985                         activity_monitor.Soc_PD_Data_error_rate_coeff);
 986
 987                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 988                         " ",
 989                         2,
 990                         "MEMLK",
 991                         activity_monitor.Mem_FPS,
 992                         activity_monitor.Mem_MinFreqStep,
 993                         activity_monitor.Mem_MinActiveFreqType,
 994                         activity_monitor.Mem_MinActiveFreq,
 995                         activity_monitor.Mem_BoosterFreqType,
 996                         activity_monitor.Mem_BoosterFreq,
 997                         activity_monitor.Mem_PD_Data_limit_c,
 998                         activity_monitor.Mem_PD_Data_error_coeff,
 999                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1000         }
1001
1002         return size;
1003 }
1004
1005 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1006 {
1007         DpmActivityMonitorCoeffInt_t activity_monitor;
1008         int workload_type, ret = 0;
1009
1010         smu->power_profile_mode = input[size];
1011
1012         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1013                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1014                 return -EINVAL;
1015         }
1016
1017         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1018                 if (size < 0)
1019                         return -EINVAL;
1020
1021                 ret = smu_update_table(smu,
1022                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1023                                        (void *)(&activity_monitor), false);
1024                 if (ret) {
1025                         pr_err("[%s] Failed to get activity monitor!", __func__);
1026                         return ret;
1027                 }
1028
1029                 switch (input[0]) {
1030                 case 0: /* Gfxclk */
1031                         activity_monitor.Gfx_FPS = input[1];
1032                         activity_monitor.Gfx_MinFreqStep = input[2];
1033                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1034                         activity_monitor.Gfx_MinActiveFreq = input[4];
1035                         activity_monitor.Gfx_BoosterFreqType = input[5];
1036                         activity_monitor.Gfx_BoosterFreq = input[6];
1037                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1038                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1039                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1040                         break;
1041                 case 1: /* Socclk */
1042                         activity_monitor.Soc_FPS = input[1];
1043                         activity_monitor.Soc_MinFreqStep = input[2];
1044                         activity_monitor.Soc_MinActiveFreqType = input[3];
1045                         activity_monitor.Soc_MinActiveFreq = input[4];
1046                         activity_monitor.Soc_BoosterFreqType = input[5];
1047                         activity_monitor.Soc_BoosterFreq = input[6];
1048                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1049                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1050                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1051                         break;
1052                 case 2: /* Memlk */
1053                         activity_monitor.Mem_FPS = input[1];
1054                         activity_monitor.Mem_MinFreqStep = input[2];
1055                         activity_monitor.Mem_MinActiveFreqType = input[3];
1056                         activity_monitor.Mem_MinActiveFreq = input[4];
1057                         activity_monitor.Mem_BoosterFreqType = input[5];
1058                         activity_monitor.Mem_BoosterFreq = input[6];
1059                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1060                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1061                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1062                         break;
1063                 }
1064
1065                 ret = smu_update_table(smu,
1066                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1067                                        (void *)(&activity_monitor), true);
1068                 if (ret) {
1069                         pr_err("[%s] Failed to set activity monitor!", __func__);
1070                         return ret;
1071                 }
1072         }
1073
1074         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1075         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1076         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1077                                     1 << workload_type);
1078
1079         return ret;
1080 }
1081
1082 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1083                                          enum amd_dpm_forced_level level,
1084                                          uint32_t *sclk_mask,
1085                                          uint32_t *mclk_mask,
1086                                          uint32_t *soc_mask)
1087 {
1088         int ret = 0;
1089         uint32_t level_count = 0;
1090
1091         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1092                 if (sclk_mask)
1093                         *sclk_mask = 0;
1094         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1095                 if (mclk_mask)
1096                         *mclk_mask = 0;
1097         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1098                 if(sclk_mask) {
1099                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1100                         if (ret)
1101                                 return ret;
1102                         *sclk_mask = level_count - 1;
1103                 }
1104
1105                 if(mclk_mask) {
1106                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1107                         if (ret)
1108                                 return ret;
1109                         *sclk_mask = level_count - 1;
1110                 }
1111
1112                 if(soc_mask) {
1113                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1114                         if (ret)
1115                                 return ret;
1116                         *sclk_mask = level_count - 1;
1117                 }
1118         }
1119
1120         return ret;
1121 }
1122
1123 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1124 {
1125         struct smu_clocks min_clocks = {0};
1126         struct pp_display_clock_request clock_req;
1127         int ret = 0;
1128
1129         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1130         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1131         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1132
1133         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1134                 clock_req.clock_type = amd_pp_dcef_clock;
1135                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1136                 if (!smu_display_clock_voltage_request(smu, &clock_req)) {
1137                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1138                                 ret = smu_send_smc_msg_with_param(smu,
1139                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1140                                                                   min_clocks.dcef_clock_in_sr/100);
1141                                 if (ret) {
1142                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1143                                         return ret;
1144                                 }
1145                         }
1146                 } else {
1147                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1148                 }
1149         }
1150
1151         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1152                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1153                 if (ret) {
1154                         pr_err("[%s] Set hard min uclk failed!", __func__);
1155                         return ret;
1156                 }
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int navi10_set_watermarks_table(struct smu_context *smu,
1163                                        void *watermarks, struct
1164                                        dm_pp_wm_sets_with_clock_ranges_soc15
1165                                        *clock_ranges)
1166 {
1167         int i;
1168         Watermarks_t *table = watermarks;
1169
1170         if (!table || !clock_ranges)
1171                 return -EINVAL;
1172
1173         if (clock_ranges->num_wm_dmif_sets > 4 ||
1174             clock_ranges->num_wm_mcif_sets > 4)
1175                 return -EINVAL;
1176
1177         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1178                 table->WatermarkRow[1][i].MinClock =
1179                         cpu_to_le16((uint16_t)
1180                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1181                         1000));
1182                 table->WatermarkRow[1][i].MaxClock =
1183                         cpu_to_le16((uint16_t)
1184                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1185                         1000));
1186                 table->WatermarkRow[1][i].MinUclk =
1187                         cpu_to_le16((uint16_t)
1188                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1189                         1000));
1190                 table->WatermarkRow[1][i].MaxUclk =
1191                         cpu_to_le16((uint16_t)
1192                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1193                         1000));
1194                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1195                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1196         }
1197
1198         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1199                 table->WatermarkRow[0][i].MinClock =
1200                         cpu_to_le16((uint16_t)
1201                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1202                         1000));
1203                 table->WatermarkRow[0][i].MaxClock =
1204                         cpu_to_le16((uint16_t)
1205                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1206                         1000));
1207                 table->WatermarkRow[0][i].MinUclk =
1208                         cpu_to_le16((uint16_t)
1209                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1210                         1000));
1211                 table->WatermarkRow[0][i].MaxUclk =
1212                         cpu_to_le16((uint16_t)
1213                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1214                         1000));
1215                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1216                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1217         }
1218
1219         return 0;
1220 }
1221
1222 static int navi10_read_sensor(struct smu_context *smu,
1223                                  enum amd_pp_sensors sensor,
1224                                  void *data, uint32_t *size)
1225 {
1226         int ret = 0;
1227         struct smu_table_context *table_context = &smu->smu_table;
1228         PPTable_t *pptable = table_context->driver_pptable;
1229
1230         switch (sensor) {
1231         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1232                 *(uint32_t *)data = pptable->FanMaximumRpm;
1233                 *size = 4;
1234                 break;
1235         case AMDGPU_PP_SENSOR_GPU_LOAD:
1236                 ret = navi10_get_current_activity_percent(smu, (uint32_t *)data);
1237                 *size = 4;
1238                 break;
1239         case AMDGPU_PP_SENSOR_GPU_POWER:
1240                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1241                 *size = 4;
1242                 break;
1243         default:
1244                 return -EINVAL;
1245         }
1246
1247         return ret;
1248 }
1249
1250 static const struct pptable_funcs navi10_ppt_funcs = {
1251         .tables_init = navi10_tables_init,
1252         .alloc_dpm_context = navi10_allocate_dpm_context,
1253         .store_powerplay_table = navi10_store_powerplay_table,
1254         .check_powerplay_table = navi10_check_powerplay_table,
1255         .append_powerplay_table = navi10_append_powerplay_table,
1256         .get_smu_msg_index = navi10_get_smu_msg_index,
1257         .get_smu_clk_index = navi10_get_smu_clk_index,
1258         .get_smu_feature_index = navi10_get_smu_feature_index,
1259         .get_smu_table_index = navi10_get_smu_table_index,
1260         .get_smu_power_index = navi10_get_pwr_src_index,
1261         .get_workload_type = navi10_get_workload_type,
1262         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1263         .set_default_dpm_table = navi10_set_default_dpm_table,
1264         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1265         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1266         .print_clk_levels = navi10_print_clk_levels,
1267         .force_clk_levels = navi10_force_clk_levels,
1268         .populate_umd_state_clk = navi10_populate_umd_state_clk,
1269         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1270         .pre_display_config_changed = navi10_pre_display_config_changed,
1271         .display_config_changed = navi10_display_config_changed,
1272         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1273         .force_dpm_limit_value = navi10_force_dpm_limit_value,
1274         .unforce_dpm_levels = navi10_unforce_dpm_levels,
1275         .is_dpm_running = navi10_is_dpm_running,
1276         .set_thermal_fan_table = navi10_set_thermal_fan_table,
1277         .get_fan_speed_percent = navi10_get_fan_speed_percent,
1278         .get_power_profile_mode = navi10_get_power_profile_mode,
1279         .set_power_profile_mode = navi10_set_power_profile_mode,
1280         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1281         .set_watermarks_table = navi10_set_watermarks_table,
1282         .read_sensor = navi10_read_sensor,
1283 };
1284
1285 void navi10_set_ppt_funcs(struct smu_context *smu)
1286 {
1287         struct smu_table_context *smu_table = &smu->smu_table;
1288
1289         smu->ppt_funcs = &navi10_ppt_funcs;
1290         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1291         smu_table->table_count = TABLE_COUNT;
1292 }