drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  48         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  51         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  52         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  53
  54 #define MSG_MAP(msg, index) \
  55         [SMU_MSG_##msg] = {1, (index)}
  56
  57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  61         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  62         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  63         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  64         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  65         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  66         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  67         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  68         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  69         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  70         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  71         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  72         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  73         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  74         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  75         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  76         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  77         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  79         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  80         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  81         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  82         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  83         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  84         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  85         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  86         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  87         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  88         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  89         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  90         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  91         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  92         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  93         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  94         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  95         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  96         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  97         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  98         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  99         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 100         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 101         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 102         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 103         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 104         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 105         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 113         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 114         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 115         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 116         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 117         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 118         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 119         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 120         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 121         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 122 };
 123
 124 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 125         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 126         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 127         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 128         CLK_MAP(FCLK, PPCLK_SOCCLK),
 129         CLK_MAP(UCLK, PPCLK_UCLK),
 130         CLK_MAP(MCLK, PPCLK_UCLK),
 131         CLK_MAP(DCLK, PPCLK_DCLK),
 132         CLK_MAP(VCLK, PPCLK_VCLK),
 133         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 134         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 135         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 136         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 137 };
 138
 139 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 140         FEA_MAP(DPM_PREFETCHER),
 141         FEA_MAP(DPM_GFXCLK),
 142         FEA_MAP(DPM_GFX_PACE),
 143         FEA_MAP(DPM_UCLK),
 144         FEA_MAP(DPM_SOCCLK),
 145         FEA_MAP(DPM_MP0CLK),
 146         FEA_MAP(DPM_LINK),
 147         FEA_MAP(DPM_DCEFCLK),
 148         FEA_MAP(MEM_VDDCI_SCALING),
 149         FEA_MAP(MEM_MVDD_SCALING),
 150         FEA_MAP(DS_GFXCLK),
 151         FEA_MAP(DS_SOCCLK),
 152         FEA_MAP(DS_LCLK),
 153         FEA_MAP(DS_DCEFCLK),
 154         FEA_MAP(DS_UCLK),
 155         FEA_MAP(GFX_ULV),
 156         FEA_MAP(FW_DSTATE),
 157         FEA_MAP(GFXOFF),
 158         FEA_MAP(BACO),
 159         FEA_MAP(VCN_PG),
 160         FEA_MAP(JPEG_PG),
 161         FEA_MAP(USB_PG),
 162         FEA_MAP(RSMU_SMN_CG),
 163         FEA_MAP(PPT),
 164         FEA_MAP(TDC),
 165         FEA_MAP(GFX_EDC),
 166         FEA_MAP(APCC_PLUS),
 167         FEA_MAP(GTHR),
 168         FEA_MAP(ACDC),
 169         FEA_MAP(VR0HOT),
 170         FEA_MAP(VR1HOT),
 171         FEA_MAP(FW_CTF),
 172         FEA_MAP(FAN_CONTROL),
 173         FEA_MAP(THERMAL),
 174         FEA_MAP(GFX_DCS),
 175         FEA_MAP(RM),
 176         FEA_MAP(LED_DISPLAY),
 177         FEA_MAP(GFX_SS),
 178         FEA_MAP(OUT_OF_BAND_MONITOR),
 179         FEA_MAP(TEMP_DEPENDENT_VMIN),
 180         FEA_MAP(MMHUB_PG),
 181         FEA_MAP(ATHUB_PG),
 182         FEA_MAP(APCC_DFLL),
 183 };
 184
 185 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(WATERMARKS),
 188         TAB_MAP(AVFS),
 189         TAB_MAP(AVFS_PSM_DEBUG),
 190         TAB_MAP(AVFS_FUSE_OVERRIDE),
 191         TAB_MAP(PMSTATUSLOG),
 192         TAB_MAP(SMU_METRICS),
 193         TAB_MAP(DRIVER_SMU_CONFIG),
 194         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 195         TAB_MAP(OVERDRIVE),
 196         TAB_MAP(I2C_COMMANDS),
 197         TAB_MAP(PACE),
 198 };
 199
 200 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 201         PWR_MAP(AC),
 202         PWR_MAP(DC),
 203 };
 204
 205 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 213 };
 214
 215 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 216 {
 217         struct smu_11_0_cmn2aisc_mapping mapping;
 218
 219         if (index >= SMU_MSG_MAX_COUNT)
 220                 return -EINVAL;
 221
 222         mapping = navi10_message_map[index];
 223         if (!(mapping.valid_mapping)) {
 224                 return -EINVAL;
 225         }
 226
 227         return mapping.map_to;
 228 }
 229
 230 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 231 {
 232         struct smu_11_0_cmn2aisc_mapping mapping;
 233
 234         if (index >= SMU_CLK_COUNT)
 235                 return -EINVAL;
 236
 237         mapping = navi10_clk_map[index];
 238         if (!(mapping.valid_mapping)) {
 239                 return -EINVAL;
 240         }
 241
 242         return mapping.map_to;
 243 }
 244
 245 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 246 {
 247         struct smu_11_0_cmn2aisc_mapping mapping;
 248
 249         if (index >= SMU_FEATURE_COUNT)
 250                 return -EINVAL;
 251
 252         mapping = navi10_feature_mask_map[index];
 253         if (!(mapping.valid_mapping)) {
 254                 return -EINVAL;
 255         }
 256
 257         return mapping.map_to;
 258 }
 259
 260 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 261 {
 262         struct smu_11_0_cmn2aisc_mapping mapping;
 263
 264         if (index >= SMU_TABLE_COUNT)
 265                 return -EINVAL;
 266
 267         mapping = navi10_table_map[index];
 268         if (!(mapping.valid_mapping)) {
 269                 return -EINVAL;
 270         }
 271
 272         return mapping.map_to;
 273 }
 274
 275 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (index >= SMU_POWER_SOURCE_COUNT)
 280                 return -EINVAL;
 281
 282         mapping = navi10_pwr_src_map[index];
 283         if (!(mapping.valid_mapping)) {
 284                 return -EINVAL;
 285         }
 286
 287         return mapping.map_to;
 288 }
 289
 290
 291 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 292 {
 293         struct smu_11_0_cmn2aisc_mapping mapping;
 294
 295         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 296                 return -EINVAL;
 297
 298         mapping = navi10_workload_map[profile];
 299         if (!(mapping.valid_mapping)) {
 300                 return -EINVAL;
 301         }
 302
 303         return mapping.map_to;
 304 }
 305
 306 static bool is_asic_secure(struct smu_context *smu)
 307 {
 308         struct amdgpu_device *adev = smu->adev;
 309         bool is_secure = true;
 310         uint32_t mp0_fw_intf;
 311
 312         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 313                                    (smnMP0_FW_INTF & 0xffffffff));
 314
 315         if (!(mp0_fw_intf & (1 << 19)))
 316                 is_secure = false;
 317
 318         return is_secure;
 319 }
 320
 321 static int
 322 navi10_get_allowed_feature_mask(struct smu_context *smu,
 323                                   uint32_t *feature_mask, uint32_t num)
 324 {
 325         struct amdgpu_device *adev = smu->adev;
 326
 327         if (num > 2)
 328                 return -EINVAL;
 329
 330         memset(feature_mask, 0, sizeof(uint32_t) * num);
 331
 332         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 333                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 334                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 335                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 336                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 337                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 338                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 339                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 340                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 341                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 342                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 343                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 344                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 345                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 346                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 347                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 348                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 349                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 350                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 351                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 352                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 353
 354         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 355                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 356
 357         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 358                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 359
 360         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 361                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 362
 363         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 364                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 365
 366         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 367                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 368                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 369                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 370
 371         if (adev->pm.pp_feature & PP_ULV_MASK)
 372                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 373
 374         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 375                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 376
 377         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 378                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 379
 380         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 381                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 382
 383         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 384                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 385
 386         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 387                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
 388                                 | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 389
 390         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 391         if (is_asic_secure(smu)) {
 392                 /* only for navi10 A0 */
 393                 if ((adev->asic_type == CHIP_NAVI10) &&
 394                         (adev->rev_id == 0)) {
 395                         *(uint64_t *)feature_mask &=
 396                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 397                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 398                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 399                         *(uint64_t *)feature_mask &=
 400                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 401                 }
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int navi10_check_powerplay_table(struct smu_context *smu)
 408 {
 409         return 0;
 410 }
 411
 412 static int navi10_append_powerplay_table(struct smu_context *smu)
 413 {
 414         struct amdgpu_device *adev = smu->adev;
 415         struct smu_table_context *table_context = &smu->smu_table;
 416         PPTable_t *smc_pptable = table_context->driver_pptable;
 417         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 418         int index, ret;
 419
 420         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 421                                            smc_dpm_info);
 422
 423         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 424                                       (uint8_t **)&smc_dpm_table);
 425         if (ret)
 426                 return ret;
 427
 428         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 429                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 430
 431         /* SVI2 Board Parameters */
 432         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 433         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 434         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 435         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 436         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 437         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 438         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 439         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 440         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 441         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 442
 443         /* Telemetry Settings */
 444         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 445         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 446         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 447         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 448         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 449         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 450         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 451         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 452         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 453         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 454         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 455         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 456
 457         /* GPIO Settings */
 458         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 459         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 460         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 461         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 462         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 463         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 464         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 465         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 466
 467         /* LED Display Settings */
 468         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 469         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 470         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 471         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 472
 473         /* GFXCLK PLL Spread Spectrum */
 474         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 475         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 476         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 477
 478         /* GFXCLK DFLL Spread Spectrum */
 479         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 480         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 481         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 482
 483         /* UCLK Spread Spectrum */
 484         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 485         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 486         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 487
 488         /* SOCCLK Spread Spectrum */
 489         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 490         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 491         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 492
 493         /* Total board power */
 494         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 495         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 496
 497         /* Mvdd Svi2 Div Ratio Setting */
 498         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 499
 500         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 501                 /* TODO: remove it once SMU fw fix it */
 502                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int navi10_store_powerplay_table(struct smu_context *smu)
 509 {
 510         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 511         struct smu_table_context *table_context = &smu->smu_table;
 512         struct smu_baco_context *smu_baco = &smu->smu_baco;
 513
 514         if (!table_context->power_play_table)
 515                 return -EINVAL;
 516
 517         powerplay_table = table_context->power_play_table;
 518
 519         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 520                sizeof(PPTable_t));
 521
 522         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 523
 524         mutex_lock(&smu_baco->mutex);
 525         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 526             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 527                 smu_baco->platform_support = true;
 528         mutex_unlock(&smu_baco->mutex);
 529
 530         return 0;
 531 }
 532
 533 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 534 {
 535         struct smu_table_context *smu_table = &smu->smu_table;
 536
 537         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 538                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 539         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 540                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 541         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 542                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 543         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 544                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 545         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 546                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 547         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 548                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 549                        AMDGPU_GEM_DOMAIN_VRAM);
 550
 551         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 552         if (!smu_table->metrics_table)
 553                 return -ENOMEM;
 554         smu_table->metrics_time = 0;
 555
 556         return 0;
 557 }
 558
 559 static int navi10_get_metrics_table(struct smu_context *smu,
 560                                     SmuMetrics_t *metrics_table)
 561 {
 562         struct smu_table_context *smu_table= &smu->smu_table;
 563         int ret = 0;
 564
 565         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 566                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 567                                 (void *)smu_table->metrics_table, false);
 568                 if (ret) {
 569                         pr_info("Failed to export SMU metrics table!\n");
 570                         return ret;
 571                 }
 572                 smu_table->metrics_time = jiffies;
 573         }
 574
 575         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 576
 577         return ret;
 578 }
 579
 580 static int navi10_allocate_dpm_context(struct smu_context *smu)
 581 {
 582         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 583
 584         if (smu_dpm->dpm_context)
 585                 return -EINVAL;
 586
 587         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 588                                        GFP_KERNEL);
 589         if (!smu_dpm->dpm_context)
 590                 return -ENOMEM;
 591
 592         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 593
 594         return 0;
 595 }
 596
 597 static int navi10_set_default_dpm_table(struct smu_context *smu)
 598 {
 599         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 600         struct smu_table_context *table_context = &smu->smu_table;
 601         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 602         PPTable_t *driver_ppt = NULL;
 603         int i;
 604
 605         driver_ppt = table_context->driver_pptable;
 606
 607         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 608         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 609
 610         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 611         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 612
 613         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 614         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 615
 616         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 617         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 618
 619         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 620         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 621
 622         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 623         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 624
 625         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 626         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 627
 628         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 629         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 630
 631         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 632         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 633
 634         for (i = 0; i < MAX_PCIE_CONF; i++) {
 635                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 636                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 643 {
 644         struct smu_power_context *smu_power = &smu->smu_power;
 645         struct smu_power_gate *power_gate = &smu_power->power_gate;
 646         int ret = 0;
 647
 648         if (enable) {
 649                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 650                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 651                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 652                         if (ret)
 653                                 return ret;
 654                 }
 655                 power_gate->vcn_gated = false;
 656         } else {
 657                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 658                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 659                         if (ret)
 660                                 return ret;
 661                 }
 662                 power_gate->vcn_gated = true;
 663         }
 664
 665         return ret;
 666 }
 667
 668 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 669                                        enum smu_clk_type clk_type,
 670                                        uint32_t *value)
 671 {
 672         int ret = 0, clk_id = 0;
 673         SmuMetrics_t metrics;
 674
 675         ret = navi10_get_metrics_table(smu, &metrics);
 676         if (ret)
 677                 return ret;
 678
 679         clk_id = smu_clk_get_index(smu, clk_type);
 680         if (clk_id < 0)
 681                 return clk_id;
 682
 683         *value = metrics.CurrClock[clk_id];
 684
 685         return ret;
 686 }
 687
 688 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 689 {
 690         PPTable_t *pptable = smu->smu_table.driver_pptable;
 691         DpmDescriptor_t *dpm_desc = NULL;
 692         uint32_t clk_index = 0;
 693
 694         clk_index = smu_clk_get_index(smu, clk_type);
 695         dpm_desc = &pptable->DpmDescriptor[clk_index];
 696
 697         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 698         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 699 }
 700
 701 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
 702 {
 703         return od_table->cap[feature];
 704 }
 705
 706
 707 static int navi10_print_clk_levels(struct smu_context *smu,
 708                         enum smu_clk_type clk_type, char *buf)
 709 {
 710         uint16_t *curve_settings;
 711         int i, size = 0, ret = 0;
 712         uint32_t cur_value = 0, value = 0, count = 0;
 713         uint32_t freq_values[3] = {0};
 714         uint32_t mark_index = 0;
 715         struct smu_table_context *table_context = &smu->smu_table;
 716         uint32_t gen_speed, lane_width;
 717         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 718         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 719         struct amdgpu_device *adev = smu->adev;
 720         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 721         OverDriveTable_t *od_table =
 722                 (OverDriveTable_t *)table_context->overdrive_table;
 723         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 724
 725         switch (clk_type) {
 726         case SMU_GFXCLK:
 727         case SMU_SCLK:
 728         case SMU_SOCCLK:
 729         case SMU_MCLK:
 730         case SMU_UCLK:
 731         case SMU_FCLK:
 732         case SMU_DCEFCLK:
 733                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 734                 if (ret)
 735                         return size;
 736
 737                 /* 10KHz -> MHz */
 738                 cur_value = cur_value / 100;
 739
 740                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 741                 if (ret)
 742                         return size;
 743
 744                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 745                         for (i = 0; i < count; i++) {
 746                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 747                                 if (ret)
 748                                         return size;
 749
 750                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 751                                                 cur_value == value ? "*" : "");
 752                         }
 753                 } else {
 754                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 755                         if (ret)
 756                                 return size;
 757                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 758                         if (ret)
 759                                 return size;
 760
 761                         freq_values[1] = cur_value;
 762                         mark_index = cur_value == freq_values[0] ? 0 :
 763                                      cur_value == freq_values[2] ? 2 : 1;
 764                         if (mark_index != 1)
 765                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 766
 767                         for (i = 0; i < 3; i++) {
 768                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 769                                                 i == mark_index ? "*" : "");
 770                         }
 771
 772                 }
 773                 break;
 774         case SMU_PCIE:
 775                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 776                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 777                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 778                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 779                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 780                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 781                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 782                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 783                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 784                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 785                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 786                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 787                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 788                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 789                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 790                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 791                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 792                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 793                                         pptable->LclkFreq[i],
 794                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 795                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 796                                         "*" : "");
 797                 break;
 798         case SMU_OD_SCLK:
 799                 if (!smu->od_enabled || !od_table || !od_settings)
 800                         break;
 801                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
 802                         break;
 803                 size += sprintf(buf + size, "OD_SCLK:\n");
 804                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 805                 break;
 806         case SMU_OD_MCLK:
 807                 if (!smu->od_enabled || !od_table || !od_settings)
 808                         break;
 809                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
 810                         break;
 811                 size += sprintf(buf + size, "OD_MCLK:\n");
 812                 size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
 813                 break;
 814         case SMU_OD_VDDC_CURVE:
 815                 if (!smu->od_enabled || !od_table || !od_settings)
 816                         break;
 817                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
 818                         break;
 819                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 820                 for (i = 0; i < 3; i++) {
 821                         switch (i) {
 822                         case 0:
 823                                 curve_settings = &od_table->GfxclkFreq1;
 824                                 break;
 825                         case 1:
 826                                 curve_settings = &od_table->GfxclkFreq2;
 827                                 break;
 828                         case 2:
 829                                 curve_settings = &od_table->GfxclkFreq3;
 830                                 break;
 831                         default:
 832                                 break;
 833                         }
 834                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 835                 }
 836                 break;
 837         default:
 838                 break;
 839         }
 840
 841         return size;
 842 }
 843
 844 static int navi10_force_clk_levels(struct smu_context *smu,
 845                                    enum smu_clk_type clk_type, uint32_t mask)
 846 {
 847
 848         int ret = 0, size = 0;
 849         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 850
 851         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 852         soft_max_level = mask ? (fls(mask) - 1) : 0;
 853
 854         switch (clk_type) {
 855         case SMU_GFXCLK:
 856         case SMU_SCLK:
 857         case SMU_SOCCLK:
 858         case SMU_MCLK:
 859         case SMU_UCLK:
 860         case SMU_DCEFCLK:
 861         case SMU_FCLK:
 862                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 863                 if (ret)
 864                         return size;
 865
 866                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 867                 if (ret)
 868                         return size;
 869
 870                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 871                 if (ret)
 872                         return size;
 873                 break;
 874         default:
 875                 break;
 876         }
 877
 878         return size;
 879 }
 880
 881 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 882 {
 883         int ret = 0;
 884         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 885
 886         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 887         if (ret)
 888                 return ret;
 889
 890         smu->pstate_sclk = min_sclk_freq * 100;
 891
 892         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 893         if (ret)
 894                 return ret;
 895
 896         smu->pstate_mclk = min_mclk_freq * 100;
 897
 898         return ret;
 899 }
 900
 901 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 902                                                  enum smu_clk_type clk_type,
 903                                                  struct pp_clock_levels_with_latency *clocks)
 904 {
 905         int ret = 0, i = 0;
 906         uint32_t level_count = 0, freq = 0;
 907
 908         switch (clk_type) {
 909         case SMU_GFXCLK:
 910         case SMU_DCEFCLK:
 911         case SMU_SOCCLK:
 912                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 913                 if (ret)
 914                         return ret;
 915
 916                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 917                 clocks->num_levels = level_count;
 918
 919                 for (i = 0; i < level_count; i++) {
 920                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 921                         if (ret)
 922                                 return ret;
 923
 924                         clocks->data[i].clocks_in_khz = freq * 1000;
 925                         clocks->data[i].latency_in_us = 0;
 926                 }
 927                 break;
 928         default:
 929                 break;
 930         }
 931
 932         return ret;
 933 }
 934
 935 static int navi10_pre_display_config_changed(struct smu_context *smu)
 936 {
 937         int ret = 0;
 938         uint32_t max_freq = 0;
 939
 940         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 941         if (ret)
 942                 return ret;
 943
 944         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 945                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 946                 if (ret)
 947                         return ret;
 948                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 949                 if (ret)
 950                         return ret;
 951         }
 952
 953         return ret;
 954 }
 955
 956 static int navi10_display_config_changed(struct smu_context *smu)
 957 {
 958         int ret = 0;
 959
 960         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 961             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 962                 ret = smu_write_watermarks_table(smu);
 963                 if (ret)
 964                         return ret;
 965
 966                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 967         }
 968
 969         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 970             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 971             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 972                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 973                                                   smu->display_config->num_display);
 974                 if (ret)
 975                         return ret;
 976         }
 977
 978         return ret;
 979 }
 980
 981 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 982 {
 983         int ret = 0, i = 0;
 984         uint32_t min_freq, max_freq, force_freq;
 985         enum smu_clk_type clk_type;
 986
 987         enum smu_clk_type clks[] = {
 988                 SMU_GFXCLK,
 989                 SMU_MCLK,
 990                 SMU_SOCCLK,
 991         };
 992
 993         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 994                 clk_type = clks[i];
 995                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 996                 if (ret)
 997                         return ret;
 998
 999                 force_freq = highest ? max_freq : min_freq;
1000                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1001                 if (ret)
1002                         return ret;
1003         }
1004
1005         return ret;
1006 }
1007
1008 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1009 {
1010         int ret = 0, i = 0;
1011         uint32_t min_freq, max_freq;
1012         enum smu_clk_type clk_type;
1013
1014         enum smu_clk_type clks[] = {
1015                 SMU_GFXCLK,
1016                 SMU_MCLK,
1017                 SMU_SOCCLK,
1018         };
1019
1020         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1021                 clk_type = clks[i];
1022                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1023                 if (ret)
1024                         return ret;
1025
1026                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1027                 if (ret)
1028                         return ret;
1029         }
1030
1031         return ret;
1032 }
1033
1034 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1035 {
1036         int ret = 0;
1037         SmuMetrics_t metrics;
1038
1039         if (!value)
1040                 return -EINVAL;
1041
1042         ret = navi10_get_metrics_table(smu, &metrics);
1043         if (ret)
1044                 return ret;
1045
1046         *value = metrics.AverageSocketPower << 8;
1047
1048         return 0;
1049 }
1050
1051 static int navi10_get_current_activity_percent(struct smu_context *smu,
1052                                                enum amd_pp_sensors sensor,
1053                                                uint32_t *value)
1054 {
1055         int ret = 0;
1056         SmuMetrics_t metrics;
1057
1058         if (!value)
1059                 return -EINVAL;
1060
1061         ret = navi10_get_metrics_table(smu, &metrics);
1062         if (ret)
1063                 return ret;
1064
1065         switch (sensor) {
1066         case AMDGPU_PP_SENSOR_GPU_LOAD:
1067                 *value = metrics.AverageGfxActivity;
1068                 break;
1069         case AMDGPU_PP_SENSOR_MEM_LOAD:
1070                 *value = metrics.AverageUclkActivity;
1071                 break;
1072         default:
1073                 pr_err("Invalid sensor for retrieving clock activity\n");
1074                 return -EINVAL;
1075         }
1076
1077         return 0;
1078 }
1079
1080 static bool navi10_is_dpm_running(struct smu_context *smu)
1081 {
1082         int ret = 0;
1083         uint32_t feature_mask[2];
1084         unsigned long feature_enabled;
1085         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1086         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1087                            ((uint64_t)feature_mask[1] << 32));
1088         return !!(feature_enabled & SMC_DPM_FEATURE);
1089 }
1090
1091 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1092                                     uint32_t *speed)
1093 {
1094         SmuMetrics_t metrics;
1095         int ret = 0;
1096
1097         if (!speed)
1098                 return -EINVAL;
1099
1100         ret = navi10_get_metrics_table(smu, &metrics);
1101         if (ret)
1102                 return ret;
1103
1104         *speed = metrics.CurrFanSpeed;
1105
1106         return ret;
1107 }
1108
1109 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1110                                         uint32_t *speed)
1111 {
1112         int ret = 0;
1113         uint32_t percent = 0;
1114         uint32_t current_rpm;
1115         PPTable_t *pptable = smu->smu_table.driver_pptable;
1116
1117         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1118         if (ret)
1119                 return ret;
1120
1121         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1122         *speed = percent > 100 ? 100 : percent;
1123
1124         return ret;
1125 }
1126
1127 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1128 {
1129         DpmActivityMonitorCoeffInt_t activity_monitor;
1130         uint32_t i, size = 0;
1131         int16_t workload_type = 0;
1132         static const char *profile_name[] = {
1133                                         "BOOTUP_DEFAULT",
1134                                         "3D_FULL_SCREEN",
1135                                         "POWER_SAVING",
1136                                         "VIDEO",
1137                                         "VR",
1138                                         "COMPUTE",
1139                                         "CUSTOM"};
1140         static const char *title[] = {
1141                         "PROFILE_INDEX(NAME)",
1142                         "CLOCK_TYPE(NAME)",
1143                         "FPS",
1144                         "MinFreqType",
1145                         "MinActiveFreqType",
1146                         "MinActiveFreq",
1147                         "BoosterFreqType",
1148                         "BoosterFreq",
1149                         "PD_Data_limit_c",
1150                         "PD_Data_error_coeff",
1151                         "PD_Data_error_rate_coeff"};
1152         int result = 0;
1153
1154         if (!buf)
1155                 return -EINVAL;
1156
1157         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1158                         title[0], title[1], title[2], title[3], title[4], title[5],
1159                         title[6], title[7], title[8], title[9], title[10]);
1160
1161         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1162                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1163                 workload_type = smu_workload_get_type(smu, i);
1164                 if (workload_type < 0)
1165                         return -EINVAL;
1166
1167                 result = smu_update_table(smu,
1168                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1169                                           (void *)(&activity_monitor), false);
1170                 if (result) {
1171                         pr_err("[%s] Failed to get activity monitor!", __func__);
1172                         return result;
1173                 }
1174
1175                 size += sprintf(buf + size, "%2d %14s%s:\n",
1176                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1177
1178                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1179                         " ",
1180                         0,
1181                         "GFXCLK",
1182                         activity_monitor.Gfx_FPS,
1183                         activity_monitor.Gfx_MinFreqStep,
1184                         activity_monitor.Gfx_MinActiveFreqType,
1185                         activity_monitor.Gfx_MinActiveFreq,
1186                         activity_monitor.Gfx_BoosterFreqType,
1187                         activity_monitor.Gfx_BoosterFreq,
1188                         activity_monitor.Gfx_PD_Data_limit_c,
1189                         activity_monitor.Gfx_PD_Data_error_coeff,
1190                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1191
1192                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1193                         " ",
1194                         1,
1195                         "SOCCLK",
1196                         activity_monitor.Soc_FPS,
1197                         activity_monitor.Soc_MinFreqStep,
1198                         activity_monitor.Soc_MinActiveFreqType,
1199                         activity_monitor.Soc_MinActiveFreq,
1200                         activity_monitor.Soc_BoosterFreqType,
1201                         activity_monitor.Soc_BoosterFreq,
1202                         activity_monitor.Soc_PD_Data_limit_c,
1203                         activity_monitor.Soc_PD_Data_error_coeff,
1204                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1205
1206                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1207                         " ",
1208                         2,
1209                         "MEMLK",
1210                         activity_monitor.Mem_FPS,
1211                         activity_monitor.Mem_MinFreqStep,
1212                         activity_monitor.Mem_MinActiveFreqType,
1213                         activity_monitor.Mem_MinActiveFreq,
1214                         activity_monitor.Mem_BoosterFreqType,
1215                         activity_monitor.Mem_BoosterFreq,
1216                         activity_monitor.Mem_PD_Data_limit_c,
1217                         activity_monitor.Mem_PD_Data_error_coeff,
1218                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1219         }
1220
1221         return size;
1222 }
1223
1224 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1225 {
1226         DpmActivityMonitorCoeffInt_t activity_monitor;
1227         int workload_type, ret = 0;
1228
1229         smu->power_profile_mode = input[size];
1230
1231         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1232                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1233                 return -EINVAL;
1234         }
1235
1236         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1237                 if (size < 0)
1238                         return -EINVAL;
1239
1240                 ret = smu_update_table(smu,
1241                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1242                                        (void *)(&activity_monitor), false);
1243                 if (ret) {
1244                         pr_err("[%s] Failed to get activity monitor!", __func__);
1245                         return ret;
1246                 }
1247
1248                 switch (input[0]) {
1249                 case 0: /* Gfxclk */
1250                         activity_monitor.Gfx_FPS = input[1];
1251                         activity_monitor.Gfx_MinFreqStep = input[2];
1252                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1253                         activity_monitor.Gfx_MinActiveFreq = input[4];
1254                         activity_monitor.Gfx_BoosterFreqType = input[5];
1255                         activity_monitor.Gfx_BoosterFreq = input[6];
1256                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1257                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1258                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1259                         break;
1260                 case 1: /* Socclk */
1261                         activity_monitor.Soc_FPS = input[1];
1262                         activity_monitor.Soc_MinFreqStep = input[2];
1263                         activity_monitor.Soc_MinActiveFreqType = input[3];
1264                         activity_monitor.Soc_MinActiveFreq = input[4];
1265                         activity_monitor.Soc_BoosterFreqType = input[5];
1266                         activity_monitor.Soc_BoosterFreq = input[6];
1267                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1268                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1269                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1270                         break;
1271                 case 2: /* Memlk */
1272                         activity_monitor.Mem_FPS = input[1];
1273                         activity_monitor.Mem_MinFreqStep = input[2];
1274                         activity_monitor.Mem_MinActiveFreqType = input[3];
1275                         activity_monitor.Mem_MinActiveFreq = input[4];
1276                         activity_monitor.Mem_BoosterFreqType = input[5];
1277                         activity_monitor.Mem_BoosterFreq = input[6];
1278                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1279                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1280                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1281                         break;
1282                 }
1283
1284                 ret = smu_update_table(smu,
1285                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1286                                        (void *)(&activity_monitor), true);
1287                 if (ret) {
1288                         pr_err("[%s] Failed to set activity monitor!", __func__);
1289                         return ret;
1290                 }
1291         }
1292
1293         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1294         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1295         if (workload_type < 0)
1296                 return -EINVAL;
1297         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1298                                     1 << workload_type);
1299
1300         return ret;
1301 }
1302
1303 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1304                                          enum amd_dpm_forced_level level,
1305                                          uint32_t *sclk_mask,
1306                                          uint32_t *mclk_mask,
1307                                          uint32_t *soc_mask)
1308 {
1309         int ret = 0;
1310         uint32_t level_count = 0;
1311
1312         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1313                 if (sclk_mask)
1314                         *sclk_mask = 0;
1315         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1316                 if (mclk_mask)
1317                         *mclk_mask = 0;
1318         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1319                 if(sclk_mask) {
1320                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1321                         if (ret)
1322                                 return ret;
1323                         *sclk_mask = level_count - 1;
1324                 }
1325
1326                 if(mclk_mask) {
1327                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1328                         if (ret)
1329                                 return ret;
1330                         *mclk_mask = level_count - 1;
1331                 }
1332
1333                 if(soc_mask) {
1334                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1335                         if (ret)
1336                                 return ret;
1337                         *soc_mask = level_count - 1;
1338                 }
1339         }
1340
1341         return ret;
1342 }
1343
1344 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1345 {
1346         struct smu_clocks min_clocks = {0};
1347         struct pp_display_clock_request clock_req;
1348         int ret = 0;
1349
1350         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1351         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1352         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1353
1354         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1355                 clock_req.clock_type = amd_pp_dcef_clock;
1356                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1357
1358                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1359                 if (!ret) {
1360                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1361                                 ret = smu_send_smc_msg_with_param(smu,
1362                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1363                                                                   min_clocks.dcef_clock_in_sr/100);
1364                                 if (ret) {
1365                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1366                                         return ret;
1367                                 }
1368                         }
1369                 } else {
1370                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1371                 }
1372         }
1373
1374         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1375                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1376                 if (ret) {
1377                         pr_err("[%s] Set hard min uclk failed!", __func__);
1378                         return ret;
1379                 }
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int navi10_set_watermarks_table(struct smu_context *smu,
1386                                        void *watermarks, struct
1387                                        dm_pp_wm_sets_with_clock_ranges_soc15
1388                                        *clock_ranges)
1389 {
1390         int i;
1391         Watermarks_t *table = watermarks;
1392
1393         if (!table || !clock_ranges)
1394                 return -EINVAL;
1395
1396         if (clock_ranges->num_wm_dmif_sets > 4 ||
1397             clock_ranges->num_wm_mcif_sets > 4)
1398                 return -EINVAL;
1399
1400         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1401                 table->WatermarkRow[1][i].MinClock =
1402                         cpu_to_le16((uint16_t)
1403                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1404                         1000));
1405                 table->WatermarkRow[1][i].MaxClock =
1406                         cpu_to_le16((uint16_t)
1407                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1408                         1000));
1409                 table->WatermarkRow[1][i].MinUclk =
1410                         cpu_to_le16((uint16_t)
1411                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1412                         1000));
1413                 table->WatermarkRow[1][i].MaxUclk =
1414                         cpu_to_le16((uint16_t)
1415                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1416                         1000));
1417                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1418                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1419         }
1420
1421         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1422                 table->WatermarkRow[0][i].MinClock =
1423                         cpu_to_le16((uint16_t)
1424                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1425                         1000));
1426                 table->WatermarkRow[0][i].MaxClock =
1427                         cpu_to_le16((uint16_t)
1428                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1429                         1000));
1430                 table->WatermarkRow[0][i].MinUclk =
1431                         cpu_to_le16((uint16_t)
1432                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1433                         1000));
1434                 table->WatermarkRow[0][i].MaxUclk =
1435                         cpu_to_le16((uint16_t)
1436                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1437                         1000));
1438                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1439                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int navi10_thermal_get_temperature(struct smu_context *smu,
1446                                              enum amd_pp_sensors sensor,
1447                                              uint32_t *value)
1448 {
1449         SmuMetrics_t metrics;
1450         int ret = 0;
1451
1452         if (!value)
1453                 return -EINVAL;
1454
1455         ret = navi10_get_metrics_table(smu, &metrics);
1456         if (ret)
1457                 return ret;
1458
1459         switch (sensor) {
1460         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1461                 *value = metrics.TemperatureHotspot *
1462                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1463                 break;
1464         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1465                 *value = metrics.TemperatureEdge *
1466                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1467                 break;
1468         case AMDGPU_PP_SENSOR_MEM_TEMP:
1469                 *value = metrics.TemperatureMem *
1470                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1471                 break;
1472         default:
1473                 pr_err("Invalid sensor for retrieving temp\n");
1474                 return -EINVAL;
1475         }
1476
1477         return 0;
1478 }
1479
1480 static int navi10_read_sensor(struct smu_context *smu,
1481                                  enum amd_pp_sensors sensor,
1482                                  void *data, uint32_t *size)
1483 {
1484         int ret = 0;
1485         struct smu_table_context *table_context = &smu->smu_table;
1486         PPTable_t *pptable = table_context->driver_pptable;
1487
1488         if(!data || !size)
1489                 return -EINVAL;
1490
1491         mutex_lock(&smu->sensor_lock);
1492         switch (sensor) {
1493         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1494                 *(uint32_t *)data = pptable->FanMaximumRpm;
1495                 *size = 4;
1496                 break;
1497         case AMDGPU_PP_SENSOR_MEM_LOAD:
1498         case AMDGPU_PP_SENSOR_GPU_LOAD:
1499                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1500                 *size = 4;
1501                 break;
1502         case AMDGPU_PP_SENSOR_GPU_POWER:
1503                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1504                 *size = 4;
1505                 break;
1506         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1507         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1508         case AMDGPU_PP_SENSOR_MEM_TEMP:
1509                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1510                 *size = 4;
1511                 break;
1512         default:
1513                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1514         }
1515         mutex_unlock(&smu->sensor_lock);
1516
1517         return ret;
1518 }
1519
1520 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1521 {
1522         uint32_t num_discrete_levels = 0;
1523         uint16_t *dpm_levels = NULL;
1524         uint16_t i = 0;
1525         struct smu_table_context *table_context = &smu->smu_table;
1526         PPTable_t *driver_ppt = NULL;
1527
1528         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1529                 return -EINVAL;
1530
1531         driver_ppt = table_context->driver_pptable;
1532         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1533         dpm_levels = driver_ppt->FreqTableUclk;
1534
1535         if (num_discrete_levels == 0 || dpm_levels == NULL)
1536                 return -EINVAL;
1537
1538         *num_states = num_discrete_levels;
1539         for (i = 0; i < num_discrete_levels; i++) {
1540                 /* convert to khz */
1541                 *clocks_in_khz = (*dpm_levels) * 1000;
1542                 clocks_in_khz++;
1543                 dpm_levels++;
1544         }
1545
1546         return 0;
1547 }
1548
1549 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1550 {
1551         struct amdgpu_device *adev = smu->adev;
1552         int ret = 0;
1553         uint32_t sclk_freq = 0, uclk_freq = 0;
1554         uint32_t uclk_level = 0;
1555
1556         switch (adev->asic_type) {
1557         case CHIP_NAVI10:
1558                 switch (adev->pdev->revision) {
1559                 case 0xf0: /* XTX */
1560                 case 0xc0:
1561                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1562                         break;
1563                 case 0xf1: /* XT */
1564                 case 0xc1:
1565                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1566                         break;
1567                 default: /* XL */
1568                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1569                         break;
1570                 }
1571                 break;
1572         case CHIP_NAVI14:
1573                 switch (adev->pdev->revision) {
1574                 case 0xc7: /* XT */
1575                 case 0xf4:
1576                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1577                         break;
1578                 case 0xc1: /* XTM */
1579                 case 0xf2:
1580                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1581                         break;
1582                 case 0xc3: /* XLM */
1583                 case 0xf3:
1584                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1585                         break;
1586                 case 0xc5: /* XTX */
1587                 case 0xf6:
1588                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1589                         break;
1590                 default: /* XL */
1591                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1592                         break;
1593                 }
1594                 break;
1595         default:
1596                 return -EINVAL;
1597         }
1598
1599         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1600         if (ret)
1601                 return ret;
1602         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1603         if (ret)
1604                 return ret;
1605
1606         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1607         if (ret)
1608                 return ret;
1609         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1610         if (ret)
1611                 return ret;
1612
1613         return ret;
1614 }
1615
1616 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1617 {
1618         int ret = 0;
1619
1620         switch (level) {
1621         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1622                 ret = navi10_set_peak_clock_by_device(smu);
1623                 break;
1624         default:
1625                 ret = -EINVAL;
1626                 break;
1627         }
1628
1629         return ret;
1630 }
1631
1632 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1633                                                 struct smu_temperature_range *range)
1634 {
1635         struct smu_table_context *table_context = &smu->smu_table;
1636         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1637
1638         if (!range || !powerplay_table)
1639                 return -EINVAL;
1640
1641         range->max = powerplay_table->software_shutdown_temp *
1642                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1643
1644         return 0;
1645 }
1646
1647 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1648                                                 bool disable_memory_clock_switch)
1649 {
1650         int ret = 0;
1651         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1652                 (struct smu_11_0_max_sustainable_clocks *)
1653                         smu->smu_table.max_sustainable_clocks;
1654         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1655         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1656
1657         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1658                 return 0;
1659
1660         if(disable_memory_clock_switch)
1661                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1662         else
1663                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1664
1665         if(!ret)
1666                 smu->disable_uclk_switch = disable_memory_clock_switch;
1667
1668         return ret;
1669 }
1670
1671 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1672 {
1673         PPTable_t *pptable = smu->smu_table.driver_pptable;
1674         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1675 }
1676
1677 static int navi10_get_power_limit(struct smu_context *smu,
1678                                      uint32_t *limit,
1679                                      bool cap)
1680 {
1681         PPTable_t *pptable = smu->smu_table.driver_pptable;
1682         uint32_t asic_default_power_limit = 0;
1683         int ret = 0;
1684         int power_src;
1685
1686         if (!smu->power_limit) {
1687                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1688                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1689                         if (power_src < 0)
1690                                 return -EINVAL;
1691
1692                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1693                                 power_src << 16);
1694                         if (ret) {
1695                                 pr_err("[%s] get PPT limit failed!", __func__);
1696                                 return ret;
1697                         }
1698                         smu_read_smc_arg(smu, &asic_default_power_limit);
1699                 } else {
1700                         /* the last hope to figure out the ppt limit */
1701                         if (!pptable) {
1702                                 pr_err("Cannot get PPT limit due to pptable missing!");
1703                                 return -EINVAL;
1704                         }
1705                         asic_default_power_limit =
1706                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1707                 }
1708
1709                 smu->power_limit = asic_default_power_limit;
1710         }
1711
1712         if (cap)
1713                 *limit = smu_v11_0_get_max_power_limit(smu);
1714         else
1715                 *limit = smu->power_limit;
1716
1717         return 0;
1718 }
1719
1720 static int navi10_update_pcie_parameters(struct smu_context *smu,
1721                                      uint32_t pcie_gen_cap,
1722                                      uint32_t pcie_width_cap)
1723 {
1724         PPTable_t *pptable = smu->smu_table.driver_pptable;
1725         int ret, i;
1726         uint32_t smu_pcie_arg;
1727
1728         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1729         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1730
1731         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1732                 smu_pcie_arg = (i << 16) |
1733                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1734                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1735                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1736                 ret = smu_send_smc_msg_with_param(smu,
1737                                           SMU_MSG_OverridePcieParameters,
1738                                           smu_pcie_arg);
1739
1740                 if (ret)
1741                         return ret;
1742
1743                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1744                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1745                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1746                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1753         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1754         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1755         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1756         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1757         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1758         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1759 }
1760
1761 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1762 {
1763         if (value < od_table->min[setting]) {
1764                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1765                 return -EINVAL;
1766         }
1767         if (value > od_table->max[setting]) {
1768                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1769                 return -EINVAL;
1770         }
1771         return 0;
1772 }
1773
1774 static int navi10_setup_od_limits(struct smu_context *smu) {
1775         struct smu_11_0_overdrive_table *overdrive_table = NULL;
1776         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1777
1778         if (!smu->smu_table.power_play_table) {
1779                 pr_err("powerplay table uninitialized!\n");
1780                 return -ENOENT;
1781         }
1782         powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1783         overdrive_table = &powerplay_table->overdrive_table;
1784         if (!smu->od_settings) {
1785                 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1786         } else {
1787                 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1788         }
1789         return 0;
1790 }
1791
1792 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1793         OverDriveTable_t *od_table;
1794         int ret = 0;
1795
1796         ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1797         if (ret)
1798                 return ret;
1799
1800         if (initialize) {
1801                 ret = navi10_setup_od_limits(smu);
1802                 if (ret) {
1803                         pr_err("Failed to retrieve board OD limits\n");
1804                         return ret;
1805                 }
1806
1807         }
1808
1809         od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1810         if (od_table) {
1811                 navi10_dump_od_table(od_table);
1812         }
1813
1814         return ret;
1815 }
1816
1817 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
1818         int i;
1819         int ret = 0;
1820         struct smu_table_context *table_context = &smu->smu_table;
1821         OverDriveTable_t *od_table;
1822         struct smu_11_0_overdrive_table *od_settings;
1823         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
1824         uint16_t *freq_ptr, *voltage_ptr;
1825         od_table = (OverDriveTable_t *)table_context->overdrive_table;
1826
1827         if (!smu->od_enabled) {
1828                 pr_warn("OverDrive is not enabled!\n");
1829                 return -EINVAL;
1830         }
1831
1832         if (!smu->od_settings) {
1833                 pr_err("OD board limits are not set!\n");
1834                 return -ENOENT;
1835         }
1836
1837         od_settings = smu->od_settings;
1838
1839         switch (type) {
1840         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1841                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
1842                         pr_warn("GFXCLK_LIMITS not supported!\n");
1843                         return -ENOTSUPP;
1844                 }
1845                 if (!table_context->overdrive_table) {
1846                         pr_err("Overdrive is not initialized\n");
1847                         return -EINVAL;
1848                 }
1849                 for (i = 0; i < size; i += 2) {
1850                         if (i + 2 > size) {
1851                                 pr_info("invalid number of input parameters %d\n", size);
1852                                 return -EINVAL;
1853                         }
1854                         switch (input[i]) {
1855                         case 0:
1856                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
1857                                 freq_ptr = &od_table->GfxclkFmin;
1858                                 if (input[i + 1] > od_table->GfxclkFmax) {
1859                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1860                                                 input[i + 1],
1861                                                 od_table->GfxclkFmin);
1862                                         return -EINVAL;
1863                                 }
1864                                 break;
1865                         case 1:
1866                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
1867                                 freq_ptr = &od_table->GfxclkFmax;
1868                                 if (input[i + 1] < od_table->GfxclkFmin) {
1869                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1870                                                 input[i + 1],
1871                                                 od_table->GfxclkFmax);
1872                                         return -EINVAL;
1873                                 }
1874                                 break;
1875                         default:
1876                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1877                                 pr_info("Supported indices: [0:min,1:max]\n");
1878                                 return -EINVAL;
1879                         }
1880                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
1881                         if (ret)
1882                                 return ret;
1883                         *freq_ptr = input[i + 1];
1884                 }
1885                 break;
1886         case PP_OD_EDIT_MCLK_VDDC_TABLE:
1887                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
1888                         pr_warn("UCLK_MAX not supported!\n");
1889                         return -ENOTSUPP;
1890                 }
1891                 if (size < 2) {
1892                         pr_info("invalid number of parameters: %d\n", size);
1893                         return -EINVAL;
1894                 }
1895                 if (input[0] != 1) {
1896                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
1897                         pr_info("Supported indices: [1:max]\n");
1898                         return -EINVAL;
1899                 }
1900                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
1901                 if (ret)
1902                         return ret;
1903                 od_table->UclkFmax = input[1];
1904                 break;
1905         case PP_OD_COMMIT_DPM_TABLE:
1906                 navi10_dump_od_table(od_table);
1907                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
1908                 if (ret) {
1909                         pr_err("Failed to import overdrive table!\n");
1910                         return ret;
1911                 }
1912                 // no lock needed because smu_od_edit_dpm_table has it
1913                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
1914                         AMD_PP_TASK_READJUST_POWER_STATE,
1915                         false);
1916                 if (ret) {
1917                         return ret;
1918                 }
1919                 break;
1920         case PP_OD_EDIT_VDDC_CURVE:
1921                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
1922                         pr_warn("GFXCLK_CURVE not supported!\n");
1923                         return -ENOTSUPP;
1924                 }
1925                 if (size < 3) {
1926                         pr_info("invalid number of parameters: %d\n", size);
1927                         return -EINVAL;
1928                 }
1929                 if (!od_table) {
1930                         pr_info("Overdrive is not initialized\n");
1931                         return -EINVAL;
1932                 }
1933
1934                 switch (input[0]) {
1935                 case 0:
1936                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
1937                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
1938                         freq_ptr = &od_table->GfxclkFreq1;
1939                         voltage_ptr = &od_table->GfxclkVolt1;
1940                         break;
1941                 case 1:
1942                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
1943                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
1944                         freq_ptr = &od_table->GfxclkFreq2;
1945                         voltage_ptr = &od_table->GfxclkVolt2;
1946                         break;
1947                 case 2:
1948                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
1949                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
1950                         freq_ptr = &od_table->GfxclkFreq3;
1951                         voltage_ptr = &od_table->GfxclkVolt3;
1952                         break;
1953                 default:
1954                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
1955                         pr_info("Supported indices: [0, 1, 2]\n");
1956                         return -EINVAL;
1957                 }
1958                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
1959                 if (ret)
1960                         return ret;
1961                 // Allow setting zero to disable the OverDrive VDDC curve
1962                 if (input[2] != 0) {
1963                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
1964                         if (ret)
1965                                 return ret;
1966                         *freq_ptr = input[1];
1967                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
1968                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
1969                 } else {
1970                         // If setting 0, disable all voltage curve settings
1971                         od_table->GfxclkVolt1 = 0;
1972                         od_table->GfxclkVolt2 = 0;
1973                         od_table->GfxclkVolt3 = 0;
1974                 }
1975                 navi10_dump_od_table(od_table);
1976                 break;
1977         default:
1978                 return -ENOSYS;
1979         }
1980         return ret;
1981 }
1982
1983 static const struct pptable_funcs navi10_ppt_funcs = {
1984         .tables_init = navi10_tables_init,
1985         .alloc_dpm_context = navi10_allocate_dpm_context,
1986         .store_powerplay_table = navi10_store_powerplay_table,
1987         .check_powerplay_table = navi10_check_powerplay_table,
1988         .append_powerplay_table = navi10_append_powerplay_table,
1989         .get_smu_msg_index = navi10_get_smu_msg_index,
1990         .get_smu_clk_index = navi10_get_smu_clk_index,
1991         .get_smu_feature_index = navi10_get_smu_feature_index,
1992         .get_smu_table_index = navi10_get_smu_table_index,
1993         .get_smu_power_index = navi10_get_pwr_src_index,
1994         .get_workload_type = navi10_get_workload_type,
1995         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1996         .set_default_dpm_table = navi10_set_default_dpm_table,
1997         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1998         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1999         .print_clk_levels = navi10_print_clk_levels,
2000         .force_clk_levels = navi10_force_clk_levels,
2001         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2002         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2003         .pre_display_config_changed = navi10_pre_display_config_changed,
2004         .display_config_changed = navi10_display_config_changed,
2005         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
2006         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2007         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2008         .is_dpm_running = navi10_is_dpm_running,
2009         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2010         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2011         .get_power_profile_mode = navi10_get_power_profile_mode,
2012         .set_power_profile_mode = navi10_set_power_profile_mode,
2013         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2014         .set_watermarks_table = navi10_set_watermarks_table,
2015         .read_sensor = navi10_read_sensor,
2016         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2017         .set_performance_level = navi10_set_performance_level,
2018         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2019         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2020         .get_power_limit = navi10_get_power_limit,
2021         .update_pcie_parameters = navi10_update_pcie_parameters,
2022         .init_microcode = smu_v11_0_init_microcode,
2023         .load_microcode = smu_v11_0_load_microcode,
2024         .init_smc_tables = smu_v11_0_init_smc_tables,
2025         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2026         .init_power = smu_v11_0_init_power,
2027         .fini_power = smu_v11_0_fini_power,
2028         .check_fw_status = smu_v11_0_check_fw_status,
2029         .setup_pptable = smu_v11_0_setup_pptable,
2030         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2031         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2032         .check_pptable = smu_v11_0_check_pptable,
2033         .parse_pptable = smu_v11_0_parse_pptable,
2034         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2035         .check_fw_version = smu_v11_0_check_fw_version,
2036         .write_pptable = smu_v11_0_write_pptable,
2037         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2038         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2039         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2040         .system_features_control = smu_v11_0_system_features_control,
2041         .send_smc_msg = smu_v11_0_send_msg,
2042         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2043         .read_smc_arg = smu_v11_0_read_arg,
2044         .init_display_count = smu_v11_0_init_display_count,
2045         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2046         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2047         .notify_display_change = smu_v11_0_notify_display_change,
2048         .set_power_limit = smu_v11_0_set_power_limit,
2049         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2050         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2051         .start_thermal_control = smu_v11_0_start_thermal_control,
2052         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2053         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2054         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2055         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2056         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2057         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2058         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2059         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2060         .gfx_off_control = smu_v11_0_gfx_off_control,
2061         .register_irq_handler = smu_v11_0_register_irq_handler,
2062         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2063         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2064         .baco_is_support= smu_v11_0_baco_is_support,
2065         .baco_get_state = smu_v11_0_baco_get_state,
2066         .baco_set_state = smu_v11_0_baco_set_state,
2067         .baco_reset = smu_v11_0_baco_reset,
2068         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2069         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2070         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2071         .set_default_od_settings = navi10_set_default_od_settings,
2072         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2073         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2074 };
2075
2076 void navi10_set_ppt_funcs(struct smu_context *smu)
2077 {
2078         smu->ppt_funcs = &navi10_ppt_funcs;
2079 }