2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
28 #include "amdgpu_smu.h"
29 #include "smu_internal.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_navi10.h"
34 #include "soc15_common.h"
36 #include "navi10_ppt.h"
37 #include "smu_v11_0_pptable.h"
38 #include "smu_v11_0_ppsmc.h"
40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
42 #define FEATURE_MASK(feature) (1ULL << feature)
43 #define SMC_DPM_FEATURE ( \
44 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
45 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
46 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
48 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
49 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
50 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
53 #define MSG_MAP(msg, index) \
54 [SMU_MSG_##msg] = {1, (index)}
56 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
57 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
58 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
71 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
79 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
80 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
81 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
82 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
83 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
84 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
85 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
86 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
87 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
88 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
89 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
90 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
91 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
92 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
93 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
94 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
95 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
96 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
97 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
98 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
99 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
100 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
101 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
102 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
103 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
104 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
105 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
106 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
107 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
108 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
109 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
110 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
111 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
112 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
113 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
114 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
115 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
116 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
117 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
118 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
119 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
120 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
123 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
124 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
125 CLK_MAP(SCLK, PPCLK_GFXCLK),
126 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
127 CLK_MAP(FCLK, PPCLK_SOCCLK),
128 CLK_MAP(UCLK, PPCLK_UCLK),
129 CLK_MAP(MCLK, PPCLK_UCLK),
130 CLK_MAP(DCLK, PPCLK_DCLK),
131 CLK_MAP(VCLK, PPCLK_VCLK),
132 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
133 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
134 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
135 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
138 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
139 FEA_MAP(DPM_PREFETCHER),
141 FEA_MAP(DPM_GFX_PACE),
146 FEA_MAP(DPM_DCEFCLK),
147 FEA_MAP(MEM_VDDCI_SCALING),
148 FEA_MAP(MEM_MVDD_SCALING),
161 FEA_MAP(RSMU_SMN_CG),
171 FEA_MAP(FAN_CONTROL),
175 FEA_MAP(LED_DISPLAY),
177 FEA_MAP(OUT_OF_BAND_MONITOR),
178 FEA_MAP(TEMP_DEPENDENT_VMIN),
184 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
188 TAB_MAP(AVFS_PSM_DEBUG),
189 TAB_MAP(AVFS_FUSE_OVERRIDE),
190 TAB_MAP(PMSTATUSLOG),
191 TAB_MAP(SMU_METRICS),
192 TAB_MAP(DRIVER_SMU_CONFIG),
193 TAB_MAP(ACTIVITY_MONITOR_COEFF),
195 TAB_MAP(I2C_COMMANDS),
199 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
204 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
214 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
216 struct smu_11_0_cmn2aisc_mapping mapping;
218 if (index >= SMU_MSG_MAX_COUNT)
221 mapping = navi10_message_map[index];
222 if (!(mapping.valid_mapping)) {
226 return mapping.map_to;
229 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
231 struct smu_11_0_cmn2aisc_mapping mapping;
233 if (index >= SMU_CLK_COUNT)
236 mapping = navi10_clk_map[index];
237 if (!(mapping.valid_mapping)) {
241 return mapping.map_to;
244 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
246 struct smu_11_0_cmn2aisc_mapping mapping;
248 if (index >= SMU_FEATURE_COUNT)
251 mapping = navi10_feature_mask_map[index];
252 if (!(mapping.valid_mapping)) {
256 return mapping.map_to;
259 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
261 struct smu_11_0_cmn2aisc_mapping mapping;
263 if (index >= SMU_TABLE_COUNT)
266 mapping = navi10_table_map[index];
267 if (!(mapping.valid_mapping)) {
271 return mapping.map_to;
274 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
276 struct smu_11_0_cmn2aisc_mapping mapping;
278 if (index >= SMU_POWER_SOURCE_COUNT)
281 mapping = navi10_pwr_src_map[index];
282 if (!(mapping.valid_mapping)) {
286 return mapping.map_to;
290 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
292 struct smu_11_0_cmn2aisc_mapping mapping;
294 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
297 mapping = navi10_workload_map[profile];
298 if (!(mapping.valid_mapping)) {
302 return mapping.map_to;
305 static bool is_asic_secure(struct smu_context *smu)
307 struct amdgpu_device *adev = smu->adev;
308 bool is_secure = true;
309 uint32_t mp0_fw_intf;
311 mp0_fw_intf = RREG32_PCIE(MP0_Public |
312 (smnMP0_FW_INTF & 0xffffffff));
314 if (!(mp0_fw_intf & (1 << 19)))
321 navi10_get_allowed_feature_mask(struct smu_context *smu,
322 uint32_t *feature_mask, uint32_t num)
324 struct amdgpu_device *adev = smu->adev;
329 memset(feature_mask, 0, sizeof(uint32_t) * num);
331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
332 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
333 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
334 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
335 | FEATURE_MASK(FEATURE_PPT_BIT)
336 | FEATURE_MASK(FEATURE_TDC_BIT)
337 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
338 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
339 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
340 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
341 | FEATURE_MASK(FEATURE_THERMAL_BIT)
342 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
343 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
344 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
345 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
346 | FEATURE_MASK(FEATURE_BACO_BIT)
347 | FEATURE_MASK(FEATURE_ACDC_BIT)
348 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
349 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
350 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
351 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
353 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
356 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
359 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
360 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
362 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
363 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
365 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
366 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
367 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
368 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
370 if (adev->pm.pp_feature & PP_ULV_MASK)
371 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
373 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
374 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
376 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
377 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
379 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
380 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
382 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
383 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
385 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
386 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
387 | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
389 /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
390 if (is_asic_secure(smu)) {
391 /* only for navi10 A0 */
392 if ((adev->asic_type == CHIP_NAVI10) &&
393 (adev->rev_id == 0)) {
394 *(uint64_t *)feature_mask &=
395 ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
396 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
397 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
398 *(uint64_t *)feature_mask &=
399 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
406 static int navi10_check_powerplay_table(struct smu_context *smu)
411 static int navi10_append_powerplay_table(struct smu_context *smu)
413 struct amdgpu_device *adev = smu->adev;
414 struct smu_table_context *table_context = &smu->smu_table;
415 PPTable_t *smc_pptable = table_context->driver_pptable;
416 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
419 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
422 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
423 (uint8_t **)&smc_dpm_table);
427 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
428 sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
430 /* SVI2 Board Parameters */
431 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
432 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
433 smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
434 smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
435 smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
436 smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
437 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
438 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
439 smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
440 smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
442 /* Telemetry Settings */
443 smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
444 smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
445 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
446 smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
447 smc_pptable->SocOffset = smc_dpm_table->SocOffset;
448 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
449 smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
450 smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
451 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
452 smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
453 smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
454 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
457 smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
458 smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
459 smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
460 smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
461 smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
462 smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
463 smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
464 smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
466 /* LED Display Settings */
467 smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
468 smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
469 smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
470 smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
472 /* GFXCLK PLL Spread Spectrum */
473 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
474 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
475 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
477 /* GFXCLK DFLL Spread Spectrum */
478 smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
479 smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
480 smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
482 /* UCLK Spread Spectrum */
483 smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
484 smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
485 smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
487 /* SOCCLK Spread Spectrum */
488 smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
489 smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
490 smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
492 /* Total board power */
493 smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
494 smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
496 /* Mvdd Svi2 Div Ratio Setting */
497 smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
499 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
500 /* TODO: remove it once SMU fw fix it */
501 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
507 static int navi10_store_powerplay_table(struct smu_context *smu)
509 struct smu_11_0_powerplay_table *powerplay_table = NULL;
510 struct smu_table_context *table_context = &smu->smu_table;
511 struct smu_baco_context *smu_baco = &smu->smu_baco;
513 if (!table_context->power_play_table)
516 powerplay_table = table_context->power_play_table;
518 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
521 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
523 mutex_lock(&smu_baco->mutex);
524 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
525 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
526 smu_baco->platform_support = true;
527 mutex_unlock(&smu_baco->mutex);
532 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
534 struct smu_table_context *smu_table = &smu->smu_table;
536 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
537 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
538 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
547 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
548 AMDGPU_GEM_DOMAIN_VRAM);
550 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
551 if (!smu_table->metrics_table)
553 smu_table->metrics_time = 0;
558 static int navi10_get_metrics_table(struct smu_context *smu,
559 SmuMetrics_t *metrics_table)
561 struct smu_table_context *smu_table= &smu->smu_table;
564 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
565 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
566 (void *)smu_table->metrics_table, false);
568 pr_info("Failed to export SMU metrics table!\n");
571 smu_table->metrics_time = jiffies;
574 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
579 static int navi10_allocate_dpm_context(struct smu_context *smu)
581 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
583 if (smu_dpm->dpm_context)
586 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
588 if (!smu_dpm->dpm_context)
591 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
596 static int navi10_set_default_dpm_table(struct smu_context *smu)
598 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
599 struct smu_table_context *table_context = &smu->smu_table;
600 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
601 PPTable_t *driver_ppt = NULL;
603 driver_ppt = table_context->driver_pptable;
605 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
606 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
608 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
609 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
611 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
612 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
614 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
615 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
617 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
618 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
620 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
621 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
623 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
624 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
626 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
627 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
629 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
630 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
635 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
637 struct smu_power_context *smu_power = &smu->smu_power;
638 struct smu_power_gate *power_gate = &smu_power->power_gate;
642 /* vcn dpm on is a prerequisite for vcn power gate messages */
643 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
644 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
648 power_gate->vcn_gated = false;
650 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
651 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
655 power_gate->vcn_gated = true;
661 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
662 enum smu_clk_type clk_type,
665 int ret = 0, clk_id = 0;
666 SmuMetrics_t metrics;
668 ret = navi10_get_metrics_table(smu, &metrics);
672 clk_id = smu_clk_get_index(smu, clk_type);
676 *value = metrics.CurrClock[clk_id];
681 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
683 PPTable_t *pptable = smu->smu_table.driver_pptable;
684 DpmDescriptor_t *dpm_desc = NULL;
685 uint32_t clk_index = 0;
687 clk_index = smu_clk_get_index(smu, clk_type);
688 dpm_desc = &pptable->DpmDescriptor[clk_index];
690 /* 0 - Fine grained DPM, 1 - Discrete DPM */
691 return dpm_desc->SnapToDiscrete == 0 ? true : false;
694 static int navi10_print_clk_levels(struct smu_context *smu,
695 enum smu_clk_type clk_type, char *buf)
697 int i, size = 0, ret = 0;
698 uint32_t cur_value = 0, value = 0, count = 0;
699 uint32_t freq_values[3] = {0};
700 uint32_t mark_index = 0;
710 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
715 cur_value = cur_value / 100;
717 ret = smu_get_dpm_level_count(smu, clk_type, &count);
721 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
722 for (i = 0; i < count; i++) {
723 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
727 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
728 cur_value == value ? "*" : "");
731 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
734 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
738 freq_values[1] = cur_value;
739 mark_index = cur_value == freq_values[0] ? 0 :
740 cur_value == freq_values[2] ? 2 : 1;
742 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
744 for (i = 0; i < 3; i++) {
745 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
746 i == mark_index ? "*" : "");
758 static int navi10_force_clk_levels(struct smu_context *smu,
759 enum smu_clk_type clk_type, uint32_t mask)
762 int ret = 0, size = 0;
763 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
765 soft_min_level = mask ? (ffs(mask) - 1) : 0;
766 soft_max_level = mask ? (fls(mask) - 1) : 0;
776 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
780 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
784 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
795 static int navi10_populate_umd_state_clk(struct smu_context *smu)
798 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
800 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
804 smu->pstate_sclk = min_sclk_freq * 100;
806 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
810 smu->pstate_mclk = min_mclk_freq * 100;
815 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
816 enum smu_clk_type clk_type,
817 struct pp_clock_levels_with_latency *clocks)
820 uint32_t level_count = 0, freq = 0;
826 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
830 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
831 clocks->num_levels = level_count;
833 for (i = 0; i < level_count; i++) {
834 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
838 clocks->data[i].clocks_in_khz = freq * 1000;
839 clocks->data[i].latency_in_us = 0;
849 static int navi10_pre_display_config_changed(struct smu_context *smu)
852 uint32_t max_freq = 0;
854 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
858 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
859 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
862 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
870 static int navi10_display_config_changed(struct smu_context *smu)
874 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
875 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
876 ret = smu_write_watermarks_table(smu);
880 smu->watermarks_bitmap |= WATERMARKS_LOADED;
883 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
884 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
885 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
886 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
887 smu->display_config->num_display);
895 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
898 uint32_t min_freq, max_freq, force_freq;
899 enum smu_clk_type clk_type;
901 enum smu_clk_type clks[] = {
907 for (i = 0; i < ARRAY_SIZE(clks); i++) {
909 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
913 force_freq = highest ? max_freq : min_freq;
914 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
922 static int navi10_unforce_dpm_levels(struct smu_context *smu)
925 uint32_t min_freq, max_freq;
926 enum smu_clk_type clk_type;
928 enum smu_clk_type clks[] = {
934 for (i = 0; i < ARRAY_SIZE(clks); i++) {
936 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
940 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
948 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
951 SmuMetrics_t metrics;
956 ret = navi10_get_metrics_table(smu, &metrics);
960 *value = metrics.AverageSocketPower << 8;
965 static int navi10_get_current_activity_percent(struct smu_context *smu,
966 enum amd_pp_sensors sensor,
970 SmuMetrics_t metrics;
975 ret = navi10_get_metrics_table(smu, &metrics);
980 case AMDGPU_PP_SENSOR_GPU_LOAD:
981 *value = metrics.AverageGfxActivity;
983 case AMDGPU_PP_SENSOR_MEM_LOAD:
984 *value = metrics.AverageUclkActivity;
987 pr_err("Invalid sensor for retrieving clock activity\n");
994 static bool navi10_is_dpm_running(struct smu_context *smu)
997 uint32_t feature_mask[2];
998 unsigned long feature_enabled;
999 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1000 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1001 ((uint64_t)feature_mask[1] << 32));
1002 return !!(feature_enabled & SMC_DPM_FEATURE);
1005 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1008 SmuMetrics_t metrics;
1014 ret = navi10_get_metrics_table(smu, &metrics);
1018 *speed = metrics.CurrFanSpeed;
1023 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1027 uint32_t percent = 0;
1028 uint32_t current_rpm;
1029 PPTable_t *pptable = smu->smu_table.driver_pptable;
1031 ret = navi10_get_fan_speed_rpm(smu, ¤t_rpm);
1035 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1036 *speed = percent > 100 ? 100 : percent;
1041 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1043 DpmActivityMonitorCoeffInt_t activity_monitor;
1044 uint32_t i, size = 0;
1045 int16_t workload_type = 0;
1046 static const char *profile_name[] = {
1054 static const char *title[] = {
1055 "PROFILE_INDEX(NAME)",
1059 "MinActiveFreqType",
1064 "PD_Data_error_coeff",
1065 "PD_Data_error_rate_coeff"};
1071 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1072 title[0], title[1], title[2], title[3], title[4], title[5],
1073 title[6], title[7], title[8], title[9], title[10]);
1075 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1076 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1077 workload_type = smu_workload_get_type(smu, i);
1078 if (workload_type < 0)
1081 result = smu_update_table(smu,
1082 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1083 (void *)(&activity_monitor), false);
1085 pr_err("[%s] Failed to get activity monitor!", __func__);
1089 size += sprintf(buf + size, "%2d %14s%s:\n",
1090 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1092 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1096 activity_monitor.Gfx_FPS,
1097 activity_monitor.Gfx_MinFreqStep,
1098 activity_monitor.Gfx_MinActiveFreqType,
1099 activity_monitor.Gfx_MinActiveFreq,
1100 activity_monitor.Gfx_BoosterFreqType,
1101 activity_monitor.Gfx_BoosterFreq,
1102 activity_monitor.Gfx_PD_Data_limit_c,
1103 activity_monitor.Gfx_PD_Data_error_coeff,
1104 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1106 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1110 activity_monitor.Soc_FPS,
1111 activity_monitor.Soc_MinFreqStep,
1112 activity_monitor.Soc_MinActiveFreqType,
1113 activity_monitor.Soc_MinActiveFreq,
1114 activity_monitor.Soc_BoosterFreqType,
1115 activity_monitor.Soc_BoosterFreq,
1116 activity_monitor.Soc_PD_Data_limit_c,
1117 activity_monitor.Soc_PD_Data_error_coeff,
1118 activity_monitor.Soc_PD_Data_error_rate_coeff);
1120 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1124 activity_monitor.Mem_FPS,
1125 activity_monitor.Mem_MinFreqStep,
1126 activity_monitor.Mem_MinActiveFreqType,
1127 activity_monitor.Mem_MinActiveFreq,
1128 activity_monitor.Mem_BoosterFreqType,
1129 activity_monitor.Mem_BoosterFreq,
1130 activity_monitor.Mem_PD_Data_limit_c,
1131 activity_monitor.Mem_PD_Data_error_coeff,
1132 activity_monitor.Mem_PD_Data_error_rate_coeff);
1138 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1140 DpmActivityMonitorCoeffInt_t activity_monitor;
1141 int workload_type, ret = 0;
1143 smu->power_profile_mode = input[size];
1145 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1146 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1150 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1154 ret = smu_update_table(smu,
1155 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1156 (void *)(&activity_monitor), false);
1158 pr_err("[%s] Failed to get activity monitor!", __func__);
1163 case 0: /* Gfxclk */
1164 activity_monitor.Gfx_FPS = input[1];
1165 activity_monitor.Gfx_MinFreqStep = input[2];
1166 activity_monitor.Gfx_MinActiveFreqType = input[3];
1167 activity_monitor.Gfx_MinActiveFreq = input[4];
1168 activity_monitor.Gfx_BoosterFreqType = input[5];
1169 activity_monitor.Gfx_BoosterFreq = input[6];
1170 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1171 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1172 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1174 case 1: /* Socclk */
1175 activity_monitor.Soc_FPS = input[1];
1176 activity_monitor.Soc_MinFreqStep = input[2];
1177 activity_monitor.Soc_MinActiveFreqType = input[3];
1178 activity_monitor.Soc_MinActiveFreq = input[4];
1179 activity_monitor.Soc_BoosterFreqType = input[5];
1180 activity_monitor.Soc_BoosterFreq = input[6];
1181 activity_monitor.Soc_PD_Data_limit_c = input[7];
1182 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1183 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1186 activity_monitor.Mem_FPS = input[1];
1187 activity_monitor.Mem_MinFreqStep = input[2];
1188 activity_monitor.Mem_MinActiveFreqType = input[3];
1189 activity_monitor.Mem_MinActiveFreq = input[4];
1190 activity_monitor.Mem_BoosterFreqType = input[5];
1191 activity_monitor.Mem_BoosterFreq = input[6];
1192 activity_monitor.Mem_PD_Data_limit_c = input[7];
1193 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1194 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1198 ret = smu_update_table(smu,
1199 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1200 (void *)(&activity_monitor), true);
1202 pr_err("[%s] Failed to set activity monitor!", __func__);
1207 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1208 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1209 if (workload_type < 0)
1211 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1212 1 << workload_type);
1217 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1218 enum amd_dpm_forced_level level,
1219 uint32_t *sclk_mask,
1220 uint32_t *mclk_mask,
1224 uint32_t level_count = 0;
1226 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1229 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1232 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1234 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1237 *sclk_mask = level_count - 1;
1241 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1244 *mclk_mask = level_count - 1;
1248 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1251 *soc_mask = level_count - 1;
1258 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1260 struct smu_clocks min_clocks = {0};
1261 struct pp_display_clock_request clock_req;
1264 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1265 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1266 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1268 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1269 clock_req.clock_type = amd_pp_dcef_clock;
1270 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1272 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1274 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1275 ret = smu_send_smc_msg_with_param(smu,
1276 SMU_MSG_SetMinDeepSleepDcefclk,
1277 min_clocks.dcef_clock_in_sr/100);
1279 pr_err("Attempt to set divider for DCEFCLK Failed!");
1284 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1288 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1289 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1291 pr_err("[%s] Set hard min uclk failed!", __func__);
1299 static int navi10_set_watermarks_table(struct smu_context *smu,
1300 void *watermarks, struct
1301 dm_pp_wm_sets_with_clock_ranges_soc15
1305 Watermarks_t *table = watermarks;
1307 if (!table || !clock_ranges)
1310 if (clock_ranges->num_wm_dmif_sets > 4 ||
1311 clock_ranges->num_wm_mcif_sets > 4)
1314 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1315 table->WatermarkRow[1][i].MinClock =
1316 cpu_to_le16((uint16_t)
1317 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1319 table->WatermarkRow[1][i].MaxClock =
1320 cpu_to_le16((uint16_t)
1321 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1323 table->WatermarkRow[1][i].MinUclk =
1324 cpu_to_le16((uint16_t)
1325 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1327 table->WatermarkRow[1][i].MaxUclk =
1328 cpu_to_le16((uint16_t)
1329 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1331 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1332 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1335 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1336 table->WatermarkRow[0][i].MinClock =
1337 cpu_to_le16((uint16_t)
1338 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1340 table->WatermarkRow[0][i].MaxClock =
1341 cpu_to_le16((uint16_t)
1342 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1344 table->WatermarkRow[0][i].MinUclk =
1345 cpu_to_le16((uint16_t)
1346 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1348 table->WatermarkRow[0][i].MaxUclk =
1349 cpu_to_le16((uint16_t)
1350 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1352 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1353 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1359 static int navi10_thermal_get_temperature(struct smu_context *smu,
1360 enum amd_pp_sensors sensor,
1363 SmuMetrics_t metrics;
1369 ret = navi10_get_metrics_table(smu, &metrics);
1374 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1375 *value = metrics.TemperatureHotspot *
1376 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1378 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1379 *value = metrics.TemperatureEdge *
1380 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1382 case AMDGPU_PP_SENSOR_MEM_TEMP:
1383 *value = metrics.TemperatureMem *
1384 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1387 pr_err("Invalid sensor for retrieving temp\n");
1394 static int navi10_read_sensor(struct smu_context *smu,
1395 enum amd_pp_sensors sensor,
1396 void *data, uint32_t *size)
1399 struct smu_table_context *table_context = &smu->smu_table;
1400 PPTable_t *pptable = table_context->driver_pptable;
1405 mutex_lock(&smu->sensor_lock);
1407 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1408 *(uint32_t *)data = pptable->FanMaximumRpm;
1411 case AMDGPU_PP_SENSOR_MEM_LOAD:
1412 case AMDGPU_PP_SENSOR_GPU_LOAD:
1413 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1416 case AMDGPU_PP_SENSOR_GPU_POWER:
1417 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1420 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1421 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1422 case AMDGPU_PP_SENSOR_MEM_TEMP:
1423 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1427 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1429 mutex_unlock(&smu->sensor_lock);
1434 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1436 uint32_t num_discrete_levels = 0;
1437 uint16_t *dpm_levels = NULL;
1439 struct smu_table_context *table_context = &smu->smu_table;
1440 PPTable_t *driver_ppt = NULL;
1442 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1445 driver_ppt = table_context->driver_pptable;
1446 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1447 dpm_levels = driver_ppt->FreqTableUclk;
1449 if (num_discrete_levels == 0 || dpm_levels == NULL)
1452 *num_states = num_discrete_levels;
1453 for (i = 0; i < num_discrete_levels; i++) {
1454 /* convert to khz */
1455 *clocks_in_khz = (*dpm_levels) * 1000;
1463 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1465 struct amdgpu_device *adev = smu->adev;
1467 uint32_t sclk_freq = 0, uclk_freq = 0;
1468 uint32_t uclk_level = 0;
1470 switch (adev->asic_type) {
1472 switch (adev->pdev->revision) {
1473 case 0xf0: /* XTX */
1475 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1479 sclk_freq = NAVI10_PEAK_SCLK_XT;
1482 sclk_freq = NAVI10_PEAK_SCLK_XL;
1487 switch (adev->pdev->revision) {
1490 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1492 case 0xc1: /* XTM */
1494 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1496 case 0xc3: /* XLM */
1498 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1500 case 0xc5: /* XTX */
1502 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1505 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1513 ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1516 ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1520 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1523 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1530 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1535 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1536 ret = navi10_set_peak_clock_by_device(smu);
1546 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1547 struct smu_temperature_range *range)
1549 struct smu_table_context *table_context = &smu->smu_table;
1550 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1552 if (!range || !powerplay_table)
1555 range->max = powerplay_table->software_shutdown_temp *
1556 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1561 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1562 bool disable_memory_clock_switch)
1565 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1566 (struct smu_11_0_max_sustainable_clocks *)
1567 smu->smu_table.max_sustainable_clocks;
1568 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1569 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1571 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1574 if(disable_memory_clock_switch)
1575 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1577 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1580 smu->disable_uclk_switch = disable_memory_clock_switch;
1585 static int navi10_get_power_limit(struct smu_context *smu,
1589 PPTable_t *pptable = smu->smu_table.driver_pptable;
1590 uint32_t asic_default_power_limit = 0;
1594 if (!smu->default_power_limit ||
1595 !smu->power_limit) {
1596 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1597 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1601 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1604 pr_err("[%s] get PPT limit failed!", __func__);
1607 smu_read_smc_arg(smu, &asic_default_power_limit);
1609 /* the last hope to figure out the ppt limit */
1611 pr_err("Cannot get PPT limit due to pptable missing!");
1614 asic_default_power_limit =
1615 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1618 if (smu->od_enabled) {
1619 asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1620 asic_default_power_limit /= 100;
1623 smu->default_power_limit = asic_default_power_limit;
1624 smu->power_limit = asic_default_power_limit;
1628 *limit = smu->default_power_limit;
1630 *limit = smu->power_limit;
1635 static int navi10_update_pcie_parameters(struct smu_context *smu,
1636 uint32_t pcie_gen_cap,
1637 uint32_t pcie_width_cap)
1639 PPTable_t *pptable = smu->smu_table.driver_pptable;
1641 uint32_t smu_pcie_arg;
1643 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1644 smu_pcie_arg = (i << 16) |
1645 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1646 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1647 pptable->PcieLaneCount[i] : pcie_width_cap);
1648 ret = smu_send_smc_msg_with_param(smu,
1649 SMU_MSG_OverridePcieParameters,
1657 static const struct pptable_funcs navi10_ppt_funcs = {
1658 .tables_init = navi10_tables_init,
1659 .alloc_dpm_context = navi10_allocate_dpm_context,
1660 .store_powerplay_table = navi10_store_powerplay_table,
1661 .check_powerplay_table = navi10_check_powerplay_table,
1662 .append_powerplay_table = navi10_append_powerplay_table,
1663 .get_smu_msg_index = navi10_get_smu_msg_index,
1664 .get_smu_clk_index = navi10_get_smu_clk_index,
1665 .get_smu_feature_index = navi10_get_smu_feature_index,
1666 .get_smu_table_index = navi10_get_smu_table_index,
1667 .get_smu_power_index = navi10_get_pwr_src_index,
1668 .get_workload_type = navi10_get_workload_type,
1669 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1670 .set_default_dpm_table = navi10_set_default_dpm_table,
1671 .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1672 .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1673 .print_clk_levels = navi10_print_clk_levels,
1674 .force_clk_levels = navi10_force_clk_levels,
1675 .populate_umd_state_clk = navi10_populate_umd_state_clk,
1676 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1677 .pre_display_config_changed = navi10_pre_display_config_changed,
1678 .display_config_changed = navi10_display_config_changed,
1679 .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1680 .force_dpm_limit_value = navi10_force_dpm_limit_value,
1681 .unforce_dpm_levels = navi10_unforce_dpm_levels,
1682 .is_dpm_running = navi10_is_dpm_running,
1683 .get_fan_speed_percent = navi10_get_fan_speed_percent,
1684 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
1685 .get_power_profile_mode = navi10_get_power_profile_mode,
1686 .set_power_profile_mode = navi10_set_power_profile_mode,
1687 .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1688 .set_watermarks_table = navi10_set_watermarks_table,
1689 .read_sensor = navi10_read_sensor,
1690 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1691 .set_performance_level = navi10_set_performance_level,
1692 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
1693 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
1694 .get_power_limit = navi10_get_power_limit,
1695 .update_pcie_parameters = navi10_update_pcie_parameters,
1696 .init_microcode = smu_v11_0_init_microcode,
1697 .load_microcode = smu_v11_0_load_microcode,
1698 .init_smc_tables = smu_v11_0_init_smc_tables,
1699 .fini_smc_tables = smu_v11_0_fini_smc_tables,
1700 .init_power = smu_v11_0_init_power,
1701 .fini_power = smu_v11_0_fini_power,
1702 .check_fw_status = smu_v11_0_check_fw_status,
1703 .setup_pptable = smu_v11_0_setup_pptable,
1704 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1705 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1706 .check_pptable = smu_v11_0_check_pptable,
1707 .parse_pptable = smu_v11_0_parse_pptable,
1708 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
1709 .check_fw_version = smu_v11_0_check_fw_version,
1710 .write_pptable = smu_v11_0_write_pptable,
1711 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1712 .set_tool_table_location = smu_v11_0_set_tool_table_location,
1713 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1714 .system_features_control = smu_v11_0_system_features_control,
1715 .send_smc_msg = smu_v11_0_send_msg,
1716 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1717 .read_smc_arg = smu_v11_0_read_arg,
1718 .init_display_count = smu_v11_0_init_display_count,
1719 .set_allowed_mask = smu_v11_0_set_allowed_mask,
1720 .get_enabled_mask = smu_v11_0_get_enabled_mask,
1721 .notify_display_change = smu_v11_0_notify_display_change,
1722 .set_power_limit = smu_v11_0_set_power_limit,
1723 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1724 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1725 .start_thermal_control = smu_v11_0_start_thermal_control,
1726 .stop_thermal_control = smu_v11_0_stop_thermal_control,
1727 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1728 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1729 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1730 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1731 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1732 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1733 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1734 .gfx_off_control = smu_v11_0_gfx_off_control,
1735 .register_irq_handler = smu_v11_0_register_irq_handler,
1736 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1737 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1738 .baco_is_support= smu_v11_0_baco_is_support,
1739 .baco_get_state = smu_v11_0_baco_get_state,
1740 .baco_set_state = smu_v11_0_baco_set_state,
1741 .baco_reset = smu_v11_0_baco_reset,
1742 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
1743 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
1744 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
1747 void navi10_set_ppt_funcs(struct smu_context *smu)
1749 smu->ppt_funcs = &navi10_ppt_funcs;