drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  39
  40 #define FEATURE_MASK(feature) (1ULL << feature)
  41 #define SMC_DPM_FEATURE ( \
  42         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  43         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  44         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  45         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  46         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  48         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = index
  53
  54 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  55         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  56         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  57         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  58         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  59         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  60         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  61         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  62         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  63         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  64         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  65         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  66         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  67         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  68         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  69         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  70         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  71         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  72         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  73         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  74         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  75         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  76         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  77         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  78         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  79         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  80         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  81         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  82         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  83         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  84         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  85         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  86         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  87         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  88         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  89         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  90         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  91         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  92         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  93         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  94         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  95         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  96         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  97         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  98         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  99         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 100         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 101         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 102         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 103         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 104         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 105         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 106         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 107         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 108         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 109         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 110         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 111         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 112         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 113         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 114         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 115         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 116         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 117         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 118         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 119 };
 120
 121 static int navi10_clk_map[SMU_CLK_COUNT] = {
 122         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 123         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 124         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 125         CLK_MAP(FCLK, PPCLK_SOCCLK),
 126         CLK_MAP(UCLK, PPCLK_UCLK),
 127         CLK_MAP(MCLK, PPCLK_UCLK),
 128         CLK_MAP(DCLK, PPCLK_DCLK),
 129         CLK_MAP(VCLK, PPCLK_VCLK),
 130         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 131         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 132         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 133         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 134 };
 135
 136 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 137         FEA_MAP(DPM_PREFETCHER),
 138         FEA_MAP(DPM_GFXCLK),
 139         FEA_MAP(DPM_GFX_PACE),
 140         FEA_MAP(DPM_UCLK),
 141         FEA_MAP(DPM_SOCCLK),
 142         FEA_MAP(DPM_MP0CLK),
 143         FEA_MAP(DPM_LINK),
 144         FEA_MAP(DPM_DCEFCLK),
 145         FEA_MAP(MEM_VDDCI_SCALING),
 146         FEA_MAP(MEM_MVDD_SCALING),
 147         FEA_MAP(DS_GFXCLK),
 148         FEA_MAP(DS_SOCCLK),
 149         FEA_MAP(DS_LCLK),
 150         FEA_MAP(DS_DCEFCLK),
 151         FEA_MAP(DS_UCLK),
 152         FEA_MAP(GFX_ULV),
 153         FEA_MAP(FW_DSTATE),
 154         FEA_MAP(GFXOFF),
 155         FEA_MAP(BACO),
 156         FEA_MAP(VCN_PG),
 157         FEA_MAP(JPEG_PG),
 158         FEA_MAP(USB_PG),
 159         FEA_MAP(RSMU_SMN_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(GFX_EDC),
 163         FEA_MAP(APCC_PLUS),
 164         FEA_MAP(GTHR),
 165         FEA_MAP(ACDC),
 166         FEA_MAP(VR0HOT),
 167         FEA_MAP(VR1HOT),
 168         FEA_MAP(FW_CTF),
 169         FEA_MAP(FAN_CONTROL),
 170         FEA_MAP(THERMAL),
 171         FEA_MAP(GFX_DCS),
 172         FEA_MAP(RM),
 173         FEA_MAP(LED_DISPLAY),
 174         FEA_MAP(GFX_SS),
 175         FEA_MAP(OUT_OF_BAND_MONITOR),
 176         FEA_MAP(TEMP_DEPENDENT_VMIN),
 177         FEA_MAP(MMHUB_PG),
 178         FEA_MAP(ATHUB_PG),
 179 };
 180
 181 static int navi10_table_map[SMU_TABLE_COUNT] = {
 182         TAB_MAP(PPTABLE),
 183         TAB_MAP(WATERMARKS),
 184         TAB_MAP(AVFS),
 185         TAB_MAP(AVFS_PSM_DEBUG),
 186         TAB_MAP(AVFS_FUSE_OVERRIDE),
 187         TAB_MAP(PMSTATUSLOG),
 188         TAB_MAP(SMU_METRICS),
 189         TAB_MAP(DRIVER_SMU_CONFIG),
 190         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 191         TAB_MAP(OVERDRIVE),
 192         TAB_MAP(I2C_COMMANDS),
 193         TAB_MAP(PACE),
 194 };
 195
 196 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 197         PWR_MAP(AC),
 198         PWR_MAP(DC),
 199 };
 200
 201 static int navi10_workload_map[] = {
 202         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 209 };
 210
 211 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 212 {
 213         int val;
 214         if (index > SMU_MSG_MAX_COUNT)
 215                 return -EINVAL;
 216
 217         val = navi10_message_map[index];
 218         if (val > PPSMC_Message_Count)
 219                 return -EINVAL;
 220
 221         return val;
 222 }
 223
 224 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 225 {
 226         int val;
 227         if (index >= SMU_CLK_COUNT)
 228                 return -EINVAL;
 229
 230         val = navi10_clk_map[index];
 231         if (val >= PPCLK_COUNT)
 232                 return -EINVAL;
 233
 234         return val;
 235 }
 236
 237 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 238 {
 239         int val;
 240         if (index >= SMU_FEATURE_COUNT)
 241                 return -EINVAL;
 242
 243         val = navi10_feature_mask_map[index];
 244         if (val > 64)
 245                 return -EINVAL;
 246
 247         return val;
 248 }
 249
 250 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 251 {
 252         int val;
 253         if (index >= SMU_TABLE_COUNT)
 254                 return -EINVAL;
 255
 256         val = navi10_table_map[index];
 257         if (val >= TABLE_COUNT)
 258                 return -EINVAL;
 259
 260         return val;
 261 }
 262
 263 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 264 {
 265         int val;
 266         if (index >= SMU_POWER_SOURCE_COUNT)
 267                 return -EINVAL;
 268
 269         val = navi10_pwr_src_map[index];
 270         if (val >= POWER_SOURCE_COUNT)
 271                 return -EINVAL;
 272
 273         return val;
 274 }
 275
 276
 277 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 278 {
 279         int val;
 280         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 281                 return -EINVAL;
 282
 283         val = navi10_workload_map[profile];
 284
 285         return val;
 286 }
 287
 288 static bool is_asic_secure(struct smu_context *smu)
 289 {
 290         struct amdgpu_device *adev = smu->adev;
 291         bool is_secure = true;
 292         uint32_t mp0_fw_intf;
 293
 294         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 295                                    (smnMP0_FW_INTF & 0xffffffff));
 296
 297         if (!(mp0_fw_intf & (1 << 19)))
 298                 is_secure = false;
 299
 300         return is_secure;
 301 }
 302
 303 static int
 304 navi10_get_allowed_feature_mask(struct smu_context *smu,
 305                                   uint32_t *feature_mask, uint32_t num)
 306 {
 307         struct amdgpu_device *adev = smu->adev;
 308
 309         if (num > 2)
 310                 return -EINVAL;
 311
 312         memset(feature_mask, 0, sizeof(uint32_t) * num);
 313
 314         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 315                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 316                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 317                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 318                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 319                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 320                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 321                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 322                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 323                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 324                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 325                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 326                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 327                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 328                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 329                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 330                                 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
 331                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 332                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 333                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 334                                 | FEATURE_MASK(FEATURE_ACDC_BIT);
 335
 336         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 337                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 338                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 339                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 340
 341         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 343                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 344                 /* TODO: remove it once fw fix the bug */
 345                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 346         }
 347
 348         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 349                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 350
 351         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 352                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 353
 354         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 355                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 356
 357         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 358         if (is_asic_secure(smu)) {
 359                 /* only for navi10 A0 */
 360                 if ((adev->asic_type == CHIP_NAVI10) &&
 361                         (adev->rev_id == 0)) {
 362                         *(uint64_t *)feature_mask &=
 363                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 364                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 365                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 366                         *(uint64_t *)feature_mask &=
 367                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 368                 }
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int navi10_check_powerplay_table(struct smu_context *smu)
 375 {
 376         return 0;
 377 }
 378
 379 static int navi10_append_powerplay_table(struct smu_context *smu)
 380 {
 381         struct amdgpu_device *adev = smu->adev;
 382         struct smu_table_context *table_context = &smu->smu_table;
 383         PPTable_t *smc_pptable = table_context->driver_pptable;
 384         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 385         int index, ret;
 386
 387         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 388                                            smc_dpm_info);
 389
 390         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 391                                       (uint8_t **)&smc_dpm_table);
 392         if (ret)
 393                 return ret;
 394
 395         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 396                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 397
 398         /* SVI2 Board Parameters */
 399         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 400         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 401         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 402         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 403         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 404         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 405         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 406         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 407         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 408         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 409
 410         /* Telemetry Settings */
 411         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 412         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 413         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 414         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 415         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 416         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 417         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 418         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 419         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 420         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 421         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 422         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 423
 424         /* GPIO Settings */
 425         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 426         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 427         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 428         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 429         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 430         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 431         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 432         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 433
 434         /* LED Display Settings */
 435         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 436         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 437         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 438         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 439
 440         /* GFXCLK PLL Spread Spectrum */
 441         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 442         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 443         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 444
 445         /* GFXCLK DFLL Spread Spectrum */
 446         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 447         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 448         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 449
 450         /* UCLK Spread Spectrum */
 451         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 452         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 453         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 454
 455         /* SOCCLK Spread Spectrum */
 456         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 457         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 458         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 459
 460         /* Total board power */
 461         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 462         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 463
 464         /* Mvdd Svi2 Div Ratio Setting */
 465         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 466
 467         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 468                 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 469                                         | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 470
 471                 /* TODO: remove it once SMU fw fix it */
 472                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int navi10_store_powerplay_table(struct smu_context *smu)
 479 {
 480         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 481         struct smu_table_context *table_context = &smu->smu_table;
 482         struct smu_baco_context *smu_baco = &smu->smu_baco;
 483
 484         if (!table_context->power_play_table)
 485                 return -EINVAL;
 486
 487         powerplay_table = table_context->power_play_table;
 488
 489         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 490                sizeof(PPTable_t));
 491
 492         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 493
 494         mutex_lock(&smu_baco->mutex);
 495         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 496             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 497                 smu_baco->platform_support = true;
 498         mutex_unlock(&smu_baco->mutex);
 499
 500         return 0;
 501 }
 502
 503 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 504 {
 505         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 506                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 507         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 508                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 509         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 510                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 511         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 512                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 513         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 514                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 515         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 516                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 517                        AMDGPU_GEM_DOMAIN_VRAM);
 518
 519         return 0;
 520 }
 521
 522 static int navi10_allocate_dpm_context(struct smu_context *smu)
 523 {
 524         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 525
 526         if (smu_dpm->dpm_context)
 527                 return -EINVAL;
 528
 529         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 530                                        GFP_KERNEL);
 531         if (!smu_dpm->dpm_context)
 532                 return -ENOMEM;
 533
 534         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 535
 536         return 0;
 537 }
 538
 539 static int navi10_set_default_dpm_table(struct smu_context *smu)
 540 {
 541         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 542         struct smu_table_context *table_context = &smu->smu_table;
 543         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 544         PPTable_t *driver_ppt = NULL;
 545
 546         driver_ppt = table_context->driver_pptable;
 547
 548         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 549         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 550
 551         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 552         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 553
 554         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 555         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 556
 557         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 558         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 559
 560         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 561         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 562
 563         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 564         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 565
 566         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 567         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 568
 569         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 570         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 571
 572         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 573         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 574
 575         return 0;
 576 }
 577
 578 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 579 {
 580         int ret = 0;
 581         struct smu_power_context *smu_power = &smu->smu_power;
 582         struct smu_power_gate *power_gate = &smu_power->power_gate;
 583
 584         if (enable && power_gate->uvd_gated) {
 585                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 586                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 587                         if (ret)
 588                                 return ret;
 589                 }
 590                 power_gate->uvd_gated = false;
 591         } else {
 592                 if (!enable && !power_gate->uvd_gated) {
 593                         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 594                                 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 595                                 if (ret)
 596                                         return ret;
 597                         }
 598                         power_gate->uvd_gated = true;
 599                 }
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 606                                        enum smu_clk_type clk_type,
 607                                        uint32_t *value)
 608 {
 609         static SmuMetrics_t metrics;
 610         int ret = 0, clk_id = 0;
 611
 612         if (!value)
 613                 return -EINVAL;
 614
 615         memset(&metrics, 0, sizeof(metrics));
 616
 617         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
 618         if (ret)
 619                 return ret;
 620
 621         clk_id = smu_clk_get_index(smu, clk_type);
 622         if (clk_id < 0)
 623                 return clk_id;
 624
 625         *value = metrics.CurrClock[clk_id];
 626
 627         return ret;
 628 }
 629
 630 static int navi10_print_clk_levels(struct smu_context *smu,
 631                         enum smu_clk_type clk_type, char *buf)
 632 {
 633         int i, size = 0, ret = 0;
 634         uint32_t cur_value = 0, value = 0, count = 0;
 635
 636         switch (clk_type) {
 637         case SMU_GFXCLK:
 638         case SMU_SCLK:
 639         case SMU_SOCCLK:
 640         case SMU_MCLK:
 641         case SMU_UCLK:
 642         case SMU_FCLK:
 643         case SMU_DCEFCLK:
 644                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 645                 if (ret)
 646                         return size;
 647                 /* 10KHz -> MHz */
 648                 cur_value = cur_value / 100;
 649
 650                 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 651
 652                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 653                 if (ret)
 654                         return size;
 655
 656                 for (i = 0; i < count; i++) {
 657                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 658                         if (ret)
 659                                 return size;
 660
 661                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 662                                         cur_value == value ? "*" : "");
 663                 }
 664                 break;
 665         default:
 666                 break;
 667         }
 668
 669         return size;
 670 }
 671
 672 static int navi10_force_clk_levels(struct smu_context *smu,
 673                                    enum smu_clk_type clk_type, uint32_t mask)
 674 {
 675
 676         int ret = 0, size = 0;
 677         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 678
 679         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 680         soft_max_level = mask ? (fls(mask) - 1) : 0;
 681
 682         switch (clk_type) {
 683         case SMU_GFXCLK:
 684         case SMU_SCLK:
 685         case SMU_SOCCLK:
 686         case SMU_MCLK:
 687         case SMU_UCLK:
 688         case SMU_DCEFCLK:
 689         case SMU_FCLK:
 690                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 691                 if (ret)
 692                         return size;
 693
 694                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 695                 if (ret)
 696                         return size;
 697
 698                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 699                 if (ret)
 700                         return size;
 701                 break;
 702         default:
 703                 break;
 704         }
 705
 706         return size;
 707 }
 708
 709 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 710 {
 711         int ret = 0;
 712         uint32_t min_sclk_freq = 0;
 713
 714         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
 715         if (ret)
 716                 return ret;
 717
 718         smu->pstate_sclk = min_sclk_freq * 100;
 719
 720         return ret;
 721 }
 722
 723 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 724                                                  enum smu_clk_type clk_type,
 725                                                  struct pp_clock_levels_with_latency *clocks)
 726 {
 727         int ret = 0, i = 0;
 728         uint32_t level_count = 0, freq = 0;
 729
 730         switch (clk_type) {
 731         case SMU_GFXCLK:
 732         case SMU_DCEFCLK:
 733         case SMU_SOCCLK:
 734                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 735                 if (ret)
 736                         return ret;
 737
 738                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 739                 clocks->num_levels = level_count;
 740
 741                 for (i = 0; i < level_count; i++) {
 742                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 743                         if (ret)
 744                                 return ret;
 745
 746                         clocks->data[i].clocks_in_khz = freq * 1000;
 747                         clocks->data[i].latency_in_us = 0;
 748                 }
 749                 break;
 750         default:
 751                 break;
 752         }
 753
 754         return ret;
 755 }
 756
 757 static int navi10_pre_display_config_changed(struct smu_context *smu)
 758 {
 759         int ret = 0;
 760         uint32_t max_freq = 0;
 761
 762         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 763         if (ret)
 764                 return ret;
 765
 766         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 767                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
 768                 if (ret)
 769                         return ret;
 770                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 771                 if (ret)
 772                         return ret;
 773         }
 774
 775         return ret;
 776 }
 777
 778 static int navi10_display_config_changed(struct smu_context *smu)
 779 {
 780         int ret = 0;
 781
 782         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 783             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 784                 ret = smu_write_watermarks_table(smu);
 785                 if (ret)
 786                         return ret;
 787
 788                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 789         }
 790
 791         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 792             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 793             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 794                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 795                                                   smu->display_config->num_display);
 796                 if (ret)
 797                         return ret;
 798         }
 799
 800         return ret;
 801 }
 802
 803 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 804 {
 805         int ret = 0, i = 0;
 806         uint32_t min_freq, max_freq, force_freq;
 807         enum smu_clk_type clk_type;
 808
 809         enum smu_clk_type clks[] = {
 810                 SMU_GFXCLK,
 811                 SMU_MCLK,
 812                 SMU_SOCCLK,
 813         };
 814
 815         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 816                 clk_type = clks[i];
 817                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 818                 if (ret)
 819                         return ret;
 820
 821                 force_freq = highest ? max_freq : min_freq;
 822                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 823                 if (ret)
 824                         return ret;
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int navi10_unforce_dpm_levels(struct smu_context *smu) {
 831
 832         int ret = 0, i = 0;
 833         uint32_t min_freq, max_freq;
 834         enum smu_clk_type clk_type;
 835
 836         struct clk_feature_map {
 837                 enum smu_clk_type clk_type;
 838                 uint32_t        feature;
 839         } clk_feature_map[] = {
 840                 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
 841                 {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
 842                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
 843         };
 844
 845         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
 846                 if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
 847                         continue;
 848
 849                 clk_type = clk_feature_map[i].clk_type;
 850
 851                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 852                 if (ret)
 853                         return ret;
 854
 855                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 856                 if (ret)
 857                         return ret;
 858         }
 859
 860         return ret;
 861 }
 862
 863 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 864 {
 865         int ret = 0;
 866         SmuMetrics_t metrics;
 867
 868         if (!value)
 869                 return -EINVAL;
 870
 871         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
 872                                false);
 873         if (ret)
 874                 return ret;
 875
 876         *value = metrics.AverageSocketPower << 8;
 877
 878         return 0;
 879 }
 880
 881 static int navi10_get_current_activity_percent(struct smu_context *smu,
 882                                                uint32_t *value)
 883 {
 884         int ret = 0;
 885         SmuMetrics_t metrics;
 886
 887         if (!value)
 888                 return -EINVAL;
 889
 890         msleep(1);
 891
 892         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
 893                                (void *)&metrics, false);
 894         if (ret)
 895                 return ret;
 896
 897         *value = metrics.AverageGfxActivity;
 898
 899         return 0;
 900 }
 901
 902 static bool navi10_is_dpm_running(struct smu_context *smu)
 903 {
 904         int ret = 0;
 905         uint32_t feature_mask[2];
 906         unsigned long feature_enabled;
 907         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 908         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 909                            ((uint64_t)feature_mask[1] << 32));
 910         return !!(feature_enabled & SMC_DPM_FEATURE);
 911 }
 912
 913 static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
 914 {
 915         SmuMetrics_t metrics;
 916         int ret = 0;
 917
 918         if (!value)
 919                 return -EINVAL;
 920
 921         memset(&metrics, 0, sizeof(metrics));
 922
 923         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
 924                                (void *)&metrics, false);
 925         if (ret)
 926                 return ret;
 927
 928         *value = metrics.CurrFanSpeed;
 929
 930         return ret;
 931 }
 932
 933 static int navi10_get_fan_speed_percent(struct smu_context *smu,
 934                                         uint32_t *speed)
 935 {
 936         int ret = 0;
 937         uint32_t percent = 0;
 938         uint16_t current_rpm;
 939         PPTable_t *pptable = smu->smu_table.driver_pptable;
 940
 941         ret = navi10_get_fan_speed(smu, &current_rpm);
 942         if (ret)
 943                 return ret;
 944
 945         percent = current_rpm * 100 / pptable->FanMaximumRpm;
 946         *speed = percent > 100 ? 100 : percent;
 947
 948         return ret;
 949 }
 950
 951 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
 952 {
 953         DpmActivityMonitorCoeffInt_t activity_monitor;
 954         uint32_t i, size = 0;
 955         uint16_t workload_type = 0;
 956         static const char *profile_name[] = {
 957                                         "BOOTUP_DEFAULT",
 958                                         "3D_FULL_SCREEN",
 959                                         "POWER_SAVING",
 960                                         "VIDEO",
 961                                         "VR",
 962                                         "COMPUTE",
 963                                         "CUSTOM"};
 964         static const char *title[] = {
 965                         "PROFILE_INDEX(NAME)",
 966                         "CLOCK_TYPE(NAME)",
 967                         "FPS",
 968                         "MinFreqType",
 969                         "MinActiveFreqType",
 970                         "MinActiveFreq",
 971                         "BoosterFreqType",
 972                         "BoosterFreq",
 973                         "PD_Data_limit_c",
 974                         "PD_Data_error_coeff",
 975                         "PD_Data_error_rate_coeff"};
 976         int result = 0;
 977
 978         if (!buf)
 979                 return -EINVAL;
 980
 981         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
 982                         title[0], title[1], title[2], title[3], title[4], title[5],
 983                         title[6], title[7], title[8], title[9], title[10]);
 984
 985         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 986                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 987                 workload_type = smu_workload_get_type(smu, i);
 988                 result = smu_update_table(smu,
 989                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
 990                                           (void *)(&activity_monitor), false);
 991                 if (result) {
 992                         pr_err("[%s] Failed to get activity monitor!", __func__);
 993                         return result;
 994                 }
 995
 996                 size += sprintf(buf + size, "%2d %14s%s:\n",
 997                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 998
 999                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1000                         " ",
1001                         0,
1002                         "GFXCLK",
1003                         activity_monitor.Gfx_FPS,
1004                         activity_monitor.Gfx_MinFreqStep,
1005                         activity_monitor.Gfx_MinActiveFreqType,
1006                         activity_monitor.Gfx_MinActiveFreq,
1007                         activity_monitor.Gfx_BoosterFreqType,
1008                         activity_monitor.Gfx_BoosterFreq,
1009                         activity_monitor.Gfx_PD_Data_limit_c,
1010                         activity_monitor.Gfx_PD_Data_error_coeff,
1011                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1012
1013                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1014                         " ",
1015                         1,
1016                         "SOCCLK",
1017                         activity_monitor.Soc_FPS,
1018                         activity_monitor.Soc_MinFreqStep,
1019                         activity_monitor.Soc_MinActiveFreqType,
1020                         activity_monitor.Soc_MinActiveFreq,
1021                         activity_monitor.Soc_BoosterFreqType,
1022                         activity_monitor.Soc_BoosterFreq,
1023                         activity_monitor.Soc_PD_Data_limit_c,
1024                         activity_monitor.Soc_PD_Data_error_coeff,
1025                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1026
1027                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1028                         " ",
1029                         2,
1030                         "MEMLK",
1031                         activity_monitor.Mem_FPS,
1032                         activity_monitor.Mem_MinFreqStep,
1033                         activity_monitor.Mem_MinActiveFreqType,
1034                         activity_monitor.Mem_MinActiveFreq,
1035                         activity_monitor.Mem_BoosterFreqType,
1036                         activity_monitor.Mem_BoosterFreq,
1037                         activity_monitor.Mem_PD_Data_limit_c,
1038                         activity_monitor.Mem_PD_Data_error_coeff,
1039                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1040         }
1041
1042         return size;
1043 }
1044
1045 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1046 {
1047         DpmActivityMonitorCoeffInt_t activity_monitor;
1048         int workload_type, ret = 0;
1049
1050         smu->power_profile_mode = input[size];
1051
1052         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1053                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1054                 return -EINVAL;
1055         }
1056
1057         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1058                 if (size < 0)
1059                         return -EINVAL;
1060
1061                 ret = smu_update_table(smu,
1062                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1063                                        (void *)(&activity_monitor), false);
1064                 if (ret) {
1065                         pr_err("[%s] Failed to get activity monitor!", __func__);
1066                         return ret;
1067                 }
1068
1069                 switch (input[0]) {
1070                 case 0: /* Gfxclk */
1071                         activity_monitor.Gfx_FPS = input[1];
1072                         activity_monitor.Gfx_MinFreqStep = input[2];
1073                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1074                         activity_monitor.Gfx_MinActiveFreq = input[4];
1075                         activity_monitor.Gfx_BoosterFreqType = input[5];
1076                         activity_monitor.Gfx_BoosterFreq = input[6];
1077                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1078                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1079                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1080                         break;
1081                 case 1: /* Socclk */
1082                         activity_monitor.Soc_FPS = input[1];
1083                         activity_monitor.Soc_MinFreqStep = input[2];
1084                         activity_monitor.Soc_MinActiveFreqType = input[3];
1085                         activity_monitor.Soc_MinActiveFreq = input[4];
1086                         activity_monitor.Soc_BoosterFreqType = input[5];
1087                         activity_monitor.Soc_BoosterFreq = input[6];
1088                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1089                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1090                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1091                         break;
1092                 case 2: /* Memlk */
1093                         activity_monitor.Mem_FPS = input[1];
1094                         activity_monitor.Mem_MinFreqStep = input[2];
1095                         activity_monitor.Mem_MinActiveFreqType = input[3];
1096                         activity_monitor.Mem_MinActiveFreq = input[4];
1097                         activity_monitor.Mem_BoosterFreqType = input[5];
1098                         activity_monitor.Mem_BoosterFreq = input[6];
1099                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1100                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1101                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1102                         break;
1103                 }
1104
1105                 ret = smu_update_table(smu,
1106                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1107                                        (void *)(&activity_monitor), true);
1108                 if (ret) {
1109                         pr_err("[%s] Failed to set activity monitor!", __func__);
1110                         return ret;
1111                 }
1112         }
1113
1114         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1115         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1116         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1117                                     1 << workload_type);
1118
1119         return ret;
1120 }
1121
1122 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1123                                          enum amd_dpm_forced_level level,
1124                                          uint32_t *sclk_mask,
1125                                          uint32_t *mclk_mask,
1126                                          uint32_t *soc_mask)
1127 {
1128         int ret = 0;
1129         uint32_t level_count = 0;
1130
1131         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1132                 if (sclk_mask)
1133                         *sclk_mask = 0;
1134         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1135                 if (mclk_mask)
1136                         *mclk_mask = 0;
1137         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1138                 if(sclk_mask) {
1139                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1140                         if (ret)
1141                                 return ret;
1142                         *sclk_mask = level_count - 1;
1143                 }
1144
1145                 if(mclk_mask) {
1146                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1147                         if (ret)
1148                                 return ret;
1149                         *sclk_mask = level_count - 1;
1150                 }
1151
1152                 if(soc_mask) {
1153                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1154                         if (ret)
1155                                 return ret;
1156                         *sclk_mask = level_count - 1;
1157                 }
1158         }
1159
1160         return ret;
1161 }
1162
1163 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1164 {
1165         struct smu_clocks min_clocks = {0};
1166         struct pp_display_clock_request clock_req;
1167         int ret = 0;
1168
1169         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1170         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1171         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1172
1173         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1174                 clock_req.clock_type = amd_pp_dcef_clock;
1175                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1176                 if (!smu_display_clock_voltage_request(smu, &clock_req)) {
1177                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1178                                 ret = smu_send_smc_msg_with_param(smu,
1179                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1180                                                                   min_clocks.dcef_clock_in_sr/100);
1181                                 if (ret) {
1182                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1183                                         return ret;
1184                                 }
1185                         }
1186                 } else {
1187                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1188                 }
1189         }
1190
1191         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1192                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1193                 if (ret) {
1194                         pr_err("[%s] Set hard min uclk failed!", __func__);
1195                         return ret;
1196                 }
1197         }
1198
1199         return 0;
1200 }
1201
1202 static int navi10_set_watermarks_table(struct smu_context *smu,
1203                                        void *watermarks, struct
1204                                        dm_pp_wm_sets_with_clock_ranges_soc15
1205                                        *clock_ranges)
1206 {
1207         int i;
1208         Watermarks_t *table = watermarks;
1209
1210         if (!table || !clock_ranges)
1211                 return -EINVAL;
1212
1213         if (clock_ranges->num_wm_dmif_sets > 4 ||
1214             clock_ranges->num_wm_mcif_sets > 4)
1215                 return -EINVAL;
1216
1217         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1218                 table->WatermarkRow[1][i].MinClock =
1219                         cpu_to_le16((uint16_t)
1220                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1221                         1000));
1222                 table->WatermarkRow[1][i].MaxClock =
1223                         cpu_to_le16((uint16_t)
1224                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1225                         1000));
1226                 table->WatermarkRow[1][i].MinUclk =
1227                         cpu_to_le16((uint16_t)
1228                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1229                         1000));
1230                 table->WatermarkRow[1][i].MaxUclk =
1231                         cpu_to_le16((uint16_t)
1232                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1233                         1000));
1234                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1235                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1236         }
1237
1238         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1239                 table->WatermarkRow[0][i].MinClock =
1240                         cpu_to_le16((uint16_t)
1241                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1242                         1000));
1243                 table->WatermarkRow[0][i].MaxClock =
1244                         cpu_to_le16((uint16_t)
1245                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1246                         1000));
1247                 table->WatermarkRow[0][i].MinUclk =
1248                         cpu_to_le16((uint16_t)
1249                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1250                         1000));
1251                 table->WatermarkRow[0][i].MaxUclk =
1252                         cpu_to_le16((uint16_t)
1253                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1254                         1000));
1255                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1256                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int navi10_thermal_get_temperature(struct smu_context *smu,
1263                                              enum amd_pp_sensors sensor,
1264                                              uint32_t *value)
1265 {
1266         SmuMetrics_t metrics;
1267         int ret = 0;
1268
1269         if (!value)
1270                 return -EINVAL;
1271
1272         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
1273         if (ret)
1274                 return ret;
1275
1276         switch (sensor) {
1277         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1278                 *value = metrics.TemperatureHotspot *
1279                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1280                 break;
1281         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1282                 *value = metrics.TemperatureEdge *
1283                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1284                 break;
1285         case AMDGPU_PP_SENSOR_MEM_TEMP:
1286                 *value = metrics.TemperatureMem *
1287                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1288                 break;
1289         default:
1290                 pr_err("Invalid sensor for retrieving temp\n");
1291                 return -EINVAL;
1292         }
1293
1294         return 0;
1295 }
1296
1297 static int navi10_read_sensor(struct smu_context *smu,
1298                                  enum amd_pp_sensors sensor,
1299                                  void *data, uint32_t *size)
1300 {
1301         int ret = 0;
1302         struct smu_table_context *table_context = &smu->smu_table;
1303         PPTable_t *pptable = table_context->driver_pptable;
1304
1305         switch (sensor) {
1306         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1307                 *(uint32_t *)data = pptable->FanMaximumRpm;
1308                 *size = 4;
1309                 break;
1310         case AMDGPU_PP_SENSOR_GPU_LOAD:
1311                 ret = navi10_get_current_activity_percent(smu, (uint32_t *)data);
1312                 *size = 4;
1313                 break;
1314         case AMDGPU_PP_SENSOR_GPU_POWER:
1315                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1316                 *size = 4;
1317                 break;
1318         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1319         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1320         case AMDGPU_PP_SENSOR_MEM_TEMP:
1321                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1322                 *size = 4;
1323                 break;
1324         default:
1325                 return -EINVAL;
1326         }
1327
1328         return ret;
1329 }
1330
1331 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1332 {
1333         uint32_t num_discrete_levels = 0;
1334         uint16_t *dpm_levels = NULL;
1335         uint16_t i = 0;
1336         struct smu_table_context *table_context = &smu->smu_table;
1337         PPTable_t *driver_ppt = NULL;
1338
1339         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1340                 return -EINVAL;
1341
1342         driver_ppt = table_context->driver_pptable;
1343         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1344         dpm_levels = driver_ppt->FreqTableUclk;
1345
1346         if (num_discrete_levels == 0 || dpm_levels == NULL)
1347                 return -EINVAL;
1348
1349         *num_states = num_discrete_levels;
1350         for (i = 0; i < num_discrete_levels; i++) {
1351                 /* convert to khz */
1352                 *clocks_in_khz = (*dpm_levels) * 1000;
1353                 clocks_in_khz++;
1354                 dpm_levels++;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int navi10_get_ppfeature_status(struct smu_context *smu,
1361                                        char *buf)
1362 {
1363         static const char *ppfeature_name[] = {
1364                                 "DPM_PREFETCHER",
1365                                 "DPM_GFXCLK",
1366                                 "DPM_GFX_PACE",
1367                                 "DPM_UCLK",
1368                                 "DPM_SOCCLK",
1369                                 "DPM_MP0CLK",
1370                                 "DPM_LINK",
1371                                 "DPM_DCEFCLK",
1372                                 "MEM_VDDCI_SCALING",
1373                                 "MEM_MVDD_SCALING",
1374                                 "DS_GFXCLK",
1375                                 "DS_SOCCLK",
1376                                 "DS_LCLK",
1377                                 "DS_DCEFCLK",
1378                                 "DS_UCLK",
1379                                 "GFX_ULV",
1380                                 "FW_DSTATE",
1381                                 "GFXOFF",
1382                                 "BACO",
1383                                 "VCN_PG",
1384                                 "JPEG_PG",
1385                                 "USB_PG",
1386                                 "RSMU_SMN_CG",
1387                                 "PPT",
1388                                 "TDC",
1389                                 "GFX_EDC",
1390                                 "APCC_PLUS",
1391                                 "GTHR",
1392                                 "ACDC",
1393                                 "VR0HOT",
1394                                 "VR1HOT",
1395                                 "FW_CTF",
1396                                 "FAN_CONTROL",
1397                                 "THERMAL",
1398                                 "GFX_DCS",
1399                                 "RM",
1400                                 "LED_DISPLAY",
1401                                 "GFX_SS",
1402                                 "OUT_OF_BAND_MONITOR",
1403                                 "TEMP_DEPENDENT_VMIN",
1404                                 "MMHUB_PG",
1405                                 "ATHUB_PG"};
1406         static const char *output_title[] = {
1407                                 "FEATURES",
1408                                 "BITMASK",
1409                                 "ENABLEMENT"};
1410         uint64_t features_enabled;
1411         uint32_t feature_mask[2];
1412         int i;
1413         int ret = 0;
1414         int size = 0;
1415
1416         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1417         PP_ASSERT_WITH_CODE(!ret,
1418                         "[GetPPfeatureStatus] Failed to get enabled smc features!",
1419                         return ret);
1420         features_enabled = (uint64_t)feature_mask[0] |
1421                            (uint64_t)feature_mask[1] << 32;
1422
1423         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
1424         size += sprintf(buf + size, "%-19s %-22s %s\n",
1425                                 output_title[0],
1426                                 output_title[1],
1427                                 output_title[2]);
1428         for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
1429                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
1430                                         ppfeature_name[i],
1431                                         1ULL << i,
1432                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
1433         }
1434
1435         return size;
1436 }
1437
1438 static int navi10_enable_smc_features(struct smu_context *smu,
1439                                       bool enabled,
1440                                       uint64_t feature_masks)
1441 {
1442         struct smu_feature *feature = &smu->smu_feature;
1443         uint32_t feature_low, feature_high;
1444         uint32_t feature_mask[2];
1445         int ret = 0;
1446
1447         feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
1448         feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
1449
1450         if (enabled) {
1451                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
1452                                                   feature_low);
1453                 if (ret)
1454                         return ret;
1455                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
1456                                                   feature_high);
1457                 if (ret)
1458                         return ret;
1459         } else {
1460                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
1461                                                   feature_low);
1462                 if (ret)
1463                         return ret;
1464                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
1465                                                   feature_high);
1466                 if (ret)
1467                         return ret;
1468         }
1469
1470         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1471         if (ret)
1472                 return ret;
1473
1474         mutex_lock(&feature->mutex);
1475         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1476                     feature->feature_num);
1477         mutex_unlock(&feature->mutex);
1478
1479         return 0;
1480 }
1481
1482 static int navi10_set_ppfeature_status(struct smu_context *smu,
1483                                        uint64_t new_ppfeature_masks)
1484 {
1485         uint64_t features_enabled;
1486         uint32_t feature_mask[2];
1487         uint64_t features_to_enable;
1488         uint64_t features_to_disable;
1489         int ret = 0;
1490
1491         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1492         PP_ASSERT_WITH_CODE(!ret,
1493                         "[SetPPfeatureStatus] Failed to get enabled smc features!",
1494                         return ret);
1495         features_enabled = (uint64_t)feature_mask[0] |
1496                            (uint64_t)feature_mask[1] << 32;
1497
1498         features_to_disable =
1499                 features_enabled & ~new_ppfeature_masks;
1500         features_to_enable =
1501                 ~features_enabled & new_ppfeature_masks;
1502
1503         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
1504         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
1505
1506         if (features_to_disable) {
1507                 ret = navi10_enable_smc_features(smu, false, features_to_disable);
1508                 PP_ASSERT_WITH_CODE(!ret,
1509                                 "[SetPPfeatureStatus] Failed to disable smc features!",
1510                                 return ret);
1511         }
1512
1513         if (features_to_enable) {
1514                 ret = navi10_enable_smc_features(smu, true, features_to_enable);
1515                 PP_ASSERT_WITH_CODE(!ret,
1516                                 "[SetPPfeatureStatus] Failed to enable smc features!",
1517                                 return ret);
1518         }
1519
1520         return 0;
1521 }
1522
1523 static const struct pptable_funcs navi10_ppt_funcs = {
1524         .tables_init = navi10_tables_init,
1525         .alloc_dpm_context = navi10_allocate_dpm_context,
1526         .store_powerplay_table = navi10_store_powerplay_table,
1527         .check_powerplay_table = navi10_check_powerplay_table,
1528         .append_powerplay_table = navi10_append_powerplay_table,
1529         .get_smu_msg_index = navi10_get_smu_msg_index,
1530         .get_smu_clk_index = navi10_get_smu_clk_index,
1531         .get_smu_feature_index = navi10_get_smu_feature_index,
1532         .get_smu_table_index = navi10_get_smu_table_index,
1533         .get_smu_power_index = navi10_get_pwr_src_index,
1534         .get_workload_type = navi10_get_workload_type,
1535         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1536         .set_default_dpm_table = navi10_set_default_dpm_table,
1537         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1538         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1539         .print_clk_levels = navi10_print_clk_levels,
1540         .force_clk_levels = navi10_force_clk_levels,
1541         .populate_umd_state_clk = navi10_populate_umd_state_clk,
1542         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1543         .pre_display_config_changed = navi10_pre_display_config_changed,
1544         .display_config_changed = navi10_display_config_changed,
1545         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1546         .force_dpm_limit_value = navi10_force_dpm_limit_value,
1547         .unforce_dpm_levels = navi10_unforce_dpm_levels,
1548         .is_dpm_running = navi10_is_dpm_running,
1549         .get_fan_speed_percent = navi10_get_fan_speed_percent,
1550         .get_power_profile_mode = navi10_get_power_profile_mode,
1551         .set_power_profile_mode = navi10_set_power_profile_mode,
1552         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1553         .set_watermarks_table = navi10_set_watermarks_table,
1554         .read_sensor = navi10_read_sensor,
1555         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1556         .get_ppfeature_status = navi10_get_ppfeature_status,
1557         .set_ppfeature_status = navi10_set_ppfeature_status,
1558 };
1559
1560 void navi10_set_ppt_funcs(struct smu_context *smu)
1561 {
1562         struct smu_table_context *smu_table = &smu->smu_table;
1563
1564         smu->ppt_funcs = &navi10_ppt_funcs;
1565         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1566         smu_table->table_count = TABLE_COUNT;
1567 }